TW483082B

TW483082B - Test structure of integrated circuit and its testing method

Info

Publication number: TW483082B
Application number: TW90100916A
Authority: TW
Inventors: Yi-Yu Dung; Jie-Yan Jeng; Ching-Shiang Shiu
Original assignee: Taiwan Semiconductor Mfg
Priority date: 2001-01-16
Filing date: 2001-01-16
Publication date: 2002-04-11

Abstract

The present invention provides a kind of frame structure and method for testing integrated circuits, in which the invention can be used in the fabrication process of a conducting layer and interconnects so as to obtain a complete test and a method for testing and tracing defects. Defects can be located and positioned before the analysis of substantial errors, in which the obtained defect data can be compared with the data obtained from the examining instruments such that the killer ratio of each layer and yield can be precisely estimated. In order to use the invented testing structure, the tested chip needs to be divided into the sub-chip arrays. The sub-chip arrays are combined with the defect density obtained from the production line. The areas on the sub-chip arrays can be perfectly monitored so as to assure that the probability of defect occurred twice on the same sub-chip is decreased to a much lower value.

Description

483082 6l26twf1.doc/009 A7 B7 經濟部智慧財產局員工消費合作社印製五、發明說明（/ ) 本發明是有關一種積體電路測試結構及其測試方法’ 特別是有關於一種運用類似矩陣路徑（Matnx-Hke Routing) 之積體電路測試結構及其測試方法，係將整個測試結構$ 晶片（Test Structure Οπρ)分成子晶片矩陣（Sub-clnp Matrix)，可不需使用任何電路元件（Active Circuit)良卩可兀成測試積體電路在製造過程中所產生的缺陷(Defect) ° 隨著半導體技術的發展，半導體製程整合的困難度急^ 速增加。因此，測試結構在製程中監測控制和追蹤缺陷來源上扮演了相當重要的角色。隨著半導體元件尺寸縮小化的過程中，類似晶片（dnp-like)的測試結構也隨著設計與製造。測試結構的尺寸大小係需要符合實際的產品，例如導線（擴散、複晶及金屬）的長度分布、接點/接觸窗 (Contact/Via)的總數、晶片面積大小、圖案的密度等等。因此，當晶片的尺寸增加或是缺陷密度的降低等，都會使缺陷隔離（Defect Isolation)比以往需要更多的時間與困難度。因爲有這樣的壓力，所以設計這樣的測試鍵(Test Key) 將顯得特別重要，其可監控製程與有時間性地追蹤降低缺陷來源與機制。底下係揭露四種習知的測試結構（電梳（Comb)/彎曲線 (Meandering Lines))，以量測導電層的阻値。基於這樣的電阻資料，此缺陷可定義爲導電或非導電。此四種習知的測試架構皆係棋盤式（Checkerboard)的測試架構。第一種測試架構如第1圖所示，其中，此測試架構係用以監控導電層與接點/接觸窗鏈（C〇ntact/Via Chain)的阻 (請先閱讀背面之注意事項再填寫本頁) -裝 • ϋ emmm ϋ n I n ϋ 1 ϋ φ 本紙張尺度適用中國國家標準（CNS)A.l規格（210 x 297公釐） 483082 A7 B7 '126twfl . doc/009 五、發明說明（> ) 値。第l(a.l)圖係導電層的分布（Layout)圖。第l(a.2)圖係接點/接觸窗鏈的分布圖。第1(b)圖係其配置與路徑 (Placement and Routing)，而第1(c)圖係其幾何圖形。其中，實線代表導通的元件。第二種測試架構如第2圖所示，其中，此測試架構係用以監控接點/接觸窗鏈（Contact/Via Chain)與缺陷導致短路之電路(Defect Induced Short Circuit)的阻値。第 2(a)圖係接點/接觸窗鏈的分布（Layout)圖。第2(b)圖係其配置與路徑（Placement and Routing)，而第2(c)圖係其幾何圖形。其中，實線代表導通的元件，而虛線代表所可能產生漏電流的路徑(Leakage Path)。第三種測試架構如第3圖所示之測試結構及其幾何圖形。其中，實線代表導通的元件，而虛線代表所可能產生漏電流的路徑（Leakage Path)。標號代表是節點（Nodes)，而用虛線框起來的標號代表爲內部節點(Internal Nodes)。第四種測試架構，請參照H.Sayah，Μ· Buehler， Proceedings IEEE 1990 Inti. Conf. On Microelectronic Test Structures，Vol· 3, pp. 87-92, March 1990· 〇 Buehler 等人提出一種2-by-N接觸墊（Contact Pad)測試結構，其在電性上相互之間有所差異。此用以偵測短路（Short-chxmt)的測試結構係使用電梳(Comb)與彎曲線（Meandering Lines)，而一連串的負載電壓（Vms)及節點以偵測斷路（〇pen-circult)的情形。每一測試結構僅覆蓋一小晶片面積，以確認沒有超過一個以上的缺陷產生。這樣設計的原則係避免複數個錯 4 本纸張尺度適用中國國家標準（CNS)A·丨規格（21〇 X 297公髮) ------------裝 i_!!·訂-丨！ _ (請先閱讀背面之注意事項再填寫本頁) 考經濟部智慧財產局員工消費合作社印製 483082 Λ7 B7 6126twfl.doc/009 五、發明說明（)）誤產生。然而，超過一半以上的測試晶片面積將會被此2-by-N接觸墊本身所覆蓋，而非缺陷感測測試結構（Defect Sensitive Test Structure)。因此，需要很多的測試晶片以成功地偵測隨機的錯誤。爲了這樣的理由，此2-by-N接觸墊所組織的測試晶片將主要僅用在偵測有系統化的錯誤 (Systematic Faults)。此架構將因爲其浪費龐大的晶片面積，而無法用來偵測任何隨機所產生的問題。另外，請參照 C. Hess，A. Strole，IEEE Transactions on Semiconductor Manufacturing, pp. 284-292，Vol. 7，No· 3, 1994。Hess等人提出棋盤式（Checkerboard)的測試架構，用以測試內部或外部導電層以及接點/接觸窗（Contact/Via) 的短路（Short-cirxmt)現象。在此他們嘗試著解決在測試結構中的單一或是多重錯誤（Single & Multi faults)，其方法係計算與比較在較大測試結構分布區域中，可能缺陷位置的機率。然而，這樣的架構在缺陷密度過高的情形下，仍然無法明確地解決多重錯誤的問題。如上所述習知的測試結構，存在有許多的問題與困難需要克服，例如下列的問題： 1.浪費太多的時間在大面積中定位錯誤的位置（Locate Failure Sites) ·· 當缺陷密度越來越小時，則將會針對較大的面積作缺陷的偵測，以掌握有系統或是隨機的缺陷產生。從錯誤分析的觀點來看，越大的面積將會增加錯誤分係的錯誤隔離 (Failure Isolation)的時間與複雜度，例如液晶熱點偵測 5 本紙張尺度適用中國國家標準（CNS)Al規格（210 x 297公髮） (請先閱讀背面之注意事項再填寫本頁) -ϋ ϋ aMmm ί Βϋ 1 n · I mm— ϋ imm 經濟部智慧財產局員工消費合作社印製經濟部智慧財產局員工消費合作社印製 483082 6126twfl.doc/009 ____B7________ 五、發明說明（今） (Liquid Crystal Hot Spot Detection)、光子/熱放射偵測 (Photo/Thermal Emission Detection)、掃描式電子顯微鏡檢查（Scanning Electron Microscope Inspection)等等。 2.經由電性測試（Electrically Testing)的資料與經由光學檢查（Optical Inspection)的資料不符： •對於良率模型（Yield Modeling)與預測（Prediction)，基於電性測試爲主資料之良率的損失，如果在一測試晶片上超過一個以上的缺陷時將無法解決。如第4圖所示，在第 4(a)圖中係經由光學檢查機器所得到的缺陷資料地圖 (Detect Data Map)，而第4(b)圖係顯示單一晶片缺陷地圖 (Single Chip Defect Map)。在電性測試的資料中，顯示只有一個缺陷，然而，在經由光學檢查的資料卻顯示有四個缺陷，因而產生資料不符的情形。而若是要達到一致性，則必須將整個測試結構分成許多的小測試結構（Subchip) ，如第 4(c) 圖所示。然而卻必須浪費很多的時間，完成所增加的小測試結構。 3 ·檢查機器（Inspection Machine)所面對的缺陷特定的污染（Defect Particulate Contamination)或是類似粒子的缺陷（Particle_like Defects) 在生產線上的檢查機器，不是以光學散射爲主，就是由影像爲主之類型。此檢查的敏感性係必定取決於底層的外觀。此偵測的類型，不是缺陷特定的污染（Defect Particulate Contamination)京尤是類似粒子的缺陷（Particle-Hke Defects)，意指製程上的差異，例如關鍵尺寸（Cntwal 本纸張尺度適用中國國家標準（CNS)A.l規格（210 X 297公釐） -----------费------ —訂--------- ΜΨ (請先閱讀背面之注意事項再填寫本頁) 483082 A7 B7 126twfl-doc/〇〇9 五、發明說明（b )483082 6l26twf1.doc / 009 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the Invention (/) This invention relates to an integrated circuit test structure and its test method. Matnx-Hke Routing's integrated circuit test structure and test method are based on dividing the entire test structure (Chip Structure (Test Structure 0πρ) into Sub-clnp Matrix) without using any circuit components (Active Circuit). Defects that can be generated during the manufacturing process of the test integrated circuit. With the development of semiconductor technology, the difficulty of semiconductor process integration has increased rapidly. Therefore, the test structure plays a very important role in monitoring and controlling the source of defects in the process. As the size of semiconductor devices is shrinking, dnp-like test structures are also being designed and manufactured. The size of the test structure needs to be consistent with the actual product, such as the length distribution of the wires (diffusion, polycrystalline and metal), the total number of contacts / contact windows (Contact / Via), the size of the wafer area, the density of the pattern, and so on. Therefore, when the size of the wafer increases or the defect density decreases, the defect isolation (Defect Isolation) requires more time and difficulty than before. Because of this pressure, it is especially important to design such a test key, which can monitor the process and timely track the source and mechanism of defects. Underneath, four conventional test structures (Comb / Meandering Lines) are exposed to measure the resistance of the conductive layer. Based on such resistance data, this defect can be defined as conductive or non-conductive. These four known test architectures are checkerboard test architectures. The first test architecture is shown in Figure 1. Among them, this test architecture is used to monitor the resistance of the conductive layer and the contact / contact window chain (Conntact / Via Chain) (please read the precautions on the back before filling in (This page)-installed • • emmm ϋ n I n ϋ 1 ϋ φ This paper size is applicable to China National Standard (CNS) Al specification (210 x 297 mm) 483082 A7 B7 '126twfl. Doc / 009 V. Description of the invention (> ) value. Figure l (a.l) is the layout of the conductive layer. Figure l (a.2) is the distribution of contact / contact window chains. Figure 1 (b) shows its placement and routing, and Figure 1 (c) shows its geometry. Among them, the solid line represents a conducting element. The second test architecture is shown in Figure 2. Among them, this test architecture is used to monitor the resistance of the Contact / Via Chain and Defect Induced Short Circuit. Figure 2 (a) is the layout of the contact / contact window chain. Figure 2 (b) shows its placement and routing, and Figure 2 (c) shows its geometry. Among them, the solid line represents the components that are conducting, and the dashed line represents the possible leakage path (Leakage Path). The third test structure is the test structure and its geometry shown in Figure 3. Among them, the solid line represents the conducting element, and the dashed line represents the leakage path (Leakage Path) that may occur. The labels represent nodes, and the labels enclosed by dashed lines represent internal nodes. For the fourth test architecture, please refer to H. Sayah, M. Buehler, Proceedings IEEE 1990 Inti. Conf. On Microelectronic Test Structures, Vol · 3, pp. 87-92, March 1990 · Buehler et al. -N Contact Pad test structure, which is electrically different from each other. This test structure used to detect short-chxmt uses combs and meandering lines, and a series of load voltages (Vms) and nodes to detect open-circult situation. Each test structure covers only a small wafer area to confirm that no more than one defect has occurred. The principle of this design is to avoid multiple mistakes. 4 The paper size is applicable to the Chinese National Standard (CNS) A · 丨 specifications (21〇X 297). ------------ Install i _ !! · Order- 丨! _ (Please read the notes on the back before filling out this page) Examination Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 483082 Λ7 B7 6126twfl.doc / 009 V. Description of Invention ()) Mistakes. However, more than half of the test wafer area will be covered by the 2-by-N contact pad itself, rather than the Defect Sensitive Test Structure. Therefore, many test chips are needed to successfully detect random errors. For this reason, the test chip organized by this 2-by-N contact pad will mainly be used only to detect systemic faults. This architecture will not be used to detect any randomly generated problems because it wastes a large amount of chip area. In addition, please refer to C. Hess, A. Strole, IEEE Transactions on Semiconductor Manufacturing, pp. 284-292, Vol. 7, No. 3, 1994. Hess et al. Proposed a checkerboard test architecture to test the short-cirxmt phenomenon of internal or external conductive layers and Contact / Via. Here they try to solve single or multiple faults in the test structure. The method is to calculate and compare the probability of possible defect locations in a large test structure distribution area. However, such an architecture still cannot explicitly solve the problem of multiple errors when the defect density is too high. As mentioned above, there are many problems and difficulties to be overcome in the conventional test structure, such as the following problems: 1. Waste too much time to locate the wrong locations in a large area (Locate Failure Sites). As the hours get smaller, defects will be detected for a larger area to grasp the systematic or random defect generation. From the perspective of error analysis, a larger area will increase the time and complexity of Failure Isolation of the error system, such as liquid crystal hotspot detection. 5 This paper size applies the Chinese National Standard (CNS) Al specification ( 210 x 297) (Please read the precautions on the back before filling out this page) -ϋ ϋ aMmm ί Βϋ 1 n · I mm— ϋ imm Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs Consumer Cooperatives Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the cooperative 483082 6126twfl.doc / 009 ____B7________ 5. Description of the invention (today) (Liquid Crystal Hot Spot Detection), Photon / Thermal Emission Detection (Scanning Electron Microscope Inspection) and many more. 2. The data through Electrically Testing does not match the data through Optical Inspection: • For Yield Modeling and Prediction, based on the yield of the main data based on the electrical test Losses cannot be resolved if more than one defect is present on a test wafer. As shown in Figure 4, in Figure 4 (a) is a defect data map (Detect Data Map) obtained through an optical inspection machine, and in Figure 4 (b) is a Single Chip Defect Map ). In the electrical test data, there is only one defect. However, in the data through optical inspection, there are four defects, which results in discrepancy. To achieve consistency, the entire test structure must be divided into many small test structures (Subchip), as shown in Figure 4 (c). However, a lot of time must be wasted to complete the added small test structure. 3 · Inspection machine (Defect Particulate Contamination) or particle-like defects (Particle_like Defects) Inspection machines on the production line are either optical scattering or image-based Its type. The sensitivity of this inspection must depend on the appearance of the underlying layer. The type of detection is not Defect Particulate Contamination. Particle-Hke Defects are similar, meaning process differences, such as key dimensions (Cntwal. This paper applies Chinese national standards.) (CNS) Al Specifications (210 X 297 mm) ----------- Fees -------- Order --------- ΜΨ (Please read the notes on the back first (Fill in this page again) 483082 A7 B7 126twfl-doc / 〇〇9 V. Description of the invention (b)

Dimension)或是薄膜的厚度等，皆可能無法由此機器來檢查。 (請先閱讀背面之注意事項再填寫本頁) 有鑑於此’本發明之目的即提供一種積體電路測試結構及其測試方法，其係一完整的缺陷分析方法，提供半導體製程硏發與製造時，作爲監控缺陷與良率改善的依據。 ’本發明之目的即提供一種積體電路測試結構及其測試方法’其係運用類似矩陣路徑(Matrix_like Routing)之積體電路測試結構，係將整個測試結構之晶片（Test Structure Chip)分成子晶片矩陣（Sub-chip Matrix)，可不需使用任何電路元件（Active Circuit)即可完成測試積體電路在製造過程中所產生的缺陷（Defect)。本發明之目的即提供一種積體電路測試結構及其測試方法’其可量測在每一個子晶片（Sub-chip)中，導電層與接點/接觸窗鏈（Contact/Via Chain)的阻値，而藉由電性量測I的方法，可將隨機的缺陷導致的短路電路定位。經濟部智慧財產局員工消費合作社印製 ¥發明之目的即提供一種積體電路測試結構及其測試方法’其可將有缺陷之錯誤位置(Failure Sites)群聚（Cluster) 成+同的群組，而不同類型之定位缺陷的技術係可基於本發明之電性測示結果來完成。本:發明之目的即提供一種積體電路測試結構及其測試力其根據相當正確之測試結構的電性缺陷密度，與在製程步驟與缺陷的錯誤型態（Process Steps & Defective Failure Mode)用語中的相當正確之每一層刪除比率（Kniei* rado of each layer)，可即時地追蹤並降低缺陷的產生。 7 本紙張尺度適用中园標準（CNS)A·丨規格（210x297公釐) 經濟部智慧財產局員工消費合作社印製 483082 五、發明說明（U ) 爲達上述之目的，本發明提供一種積體電路測試結構，包括N個測試節點，係代表具有導電分布目標之複數個導體單元的量測點；以及複數個導線，用以將該些測試節點以一二維陣列方式排列相互連接在一起。上述的積體電路測試結構，其中該些該些測試結構單元的數目爲Ν(Ν-1)/2。上述的積體電路測試結構，其中該二維陣列方式係包括一第一配置矩陣與一第二配置矩陣，其中該第一配置矩陣係按照該些測試節點之個別節點排列，而該第二配置矩陣係按照該些測試節點彼此之間的關係排列。爲達上述之目的，本發明提供一種積體電路測試方法，包括提供一測試結構，其中該結構包括複數個N個測試節點，係用以量測複數個導體單元；對該些N個測試節點以一二維可置換程序連接該些測試節點；對該些N個測試節點進行一短路檢測與一斷路檢測，並得到一測試結果；以及根據該結果，計算在該積體電路所發生的缺陷。上述的積體電路測試方法，其中該些該些測試結構單元的數目爲Ν(Ν-1)/2。上述的積體電路測試方法，其中，該二維可置換程序係係使用一二維陣列方式。上述的積體電路測試方法，其中該二維陣列方式係包括一第一配置矩陣與一第二配置矩陣，其中該第一配置矩陣係按照該些測試節點之個別節點排列，而該第二配置矩陣係按照該些測試節點彼此之間的關係排列。 8 -----------裝--------訂--------- (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 483082 經濟部智慧財產局員工消費合作社印製 6l26twfl.doc/009 五、發明說明（、爲達1述之目的’本發明提供〜種積體電路測試方法，係適用於一積體電路結構，該方法包括進行一缺陷群組化之程序’進行一‘單一^錯誤辨識之程序，進行一*多重錯誤辨識之程序，進行一末端節點錯誤位置辨識之程序，進行一非迴圏錯誤位置辨識之程序；以及進行一迴圏錯誤位置辨識之程序，藉以使得根據進行該些程序後之結果，計算在該積體電路結構所發生的缺陷數量。由上所述之積體電路測試架構與方法，提供了在一導電層與內連線製程中，完整的測試結構，與測試及缺陷追蹤的方法。缺陷可在實體錯誤分析之前找出和定位，所得到的缺陷數據將可與經由檢測儀器所得的數據做比較，而能非常準確的刪除比率(Killer ratio of each layer)和良率的估計。爲適用本發明之測試結構，測試晶片需要分割成次晶片陣列。次晶片與由生產線所得的缺陷密度結合，次晶片的區域上可以被完美的監視而確信同時在同一次晶片上出現兩次缺陷的機率降得很低。本發明提供以系統化的缺陷追蹤和電性自動缺陷位置辨認，對半導體製程的發展和製造良率的監視是有相當的幫助。同時可以用來校正檢測儀器所得的數據。爲讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉較佳實施例，並配合所附圖示，作詳細的說明。圖式之簡單說明：第Ua.l)圖係繪示第一種傳統的測試結構&導電層的本紙張尺度適用中國國家標準（CNS)A.l規格（210 x 297公釐） -----------41^裝i_丨丨-—訂·—丨丨丨 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 483082 五、發明說明（¾ ) 分布（Layout)圖；第Ua.2)圖係繪示第一種傳統的測試結構之接點/接胤窗鏈的分布圖；第1(b)圖係繪示第一種傳統的測試結構之配置與路徑 (Placement and Routing)； •第1(c)圖係繪示第一種傳統的測試結構之幾何圖形；第2(a)圖係繪示第二種傳統的測試結構之接點/接觸覲鏈的分布(Layout)圖；第2(b)圖係繪示第二種傳統的測試結構之配置與路徑 (Placement and Routing)；第2(c)圖係繪示第二彳重傳統的測試結構之幾何圖形；第3圖係繪示第三種傳統的測試結構及其幾何圖形；第4(a)圖中係繪示經由光學檢查機器所得到的缺陷資料地圖（Detect Data Map); 第4(b)圖係顯示單一晶片缺陷地圖（Single Chip Defect Map); . 第4(c)係顯示在第4(a)與4(b)圖中的缺陷而若是要達到一致性，則必須將整個測試結構分成許多的小測試結構 (Sub-chip); 第5圖係繪示根據本發明較佳實施例之具有八節點（8-node)之測試結構之圖示；第6圖係繪示根據本發明較佳實施例之八節點測試結構之安置陣列及其內部各相鄰測試單元間之關係；第7圖係繪示根據本發明較佳實施例之以檢查者儀板 10 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） -----丨！丨丨•丨丨丨！丨—訂·！丨— ! (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 483082 五、發明說明（°| ) 測試結構來表現八節點測試結構之示意圖；第8圖係繪示一測試結構之安置及標準程序，其中黑線係代表和晶片的接觸位置；第9圖係繪示每一個測試單元的設計及剖面圖；第10圖係顯示根據本發明較佳實施例之測試結構之串聯電阻模組；第11圖係顯示根據本發明較佳實施例之一短路模型及一量測電路組態之示意圖；第12圖係顯示用以發展本發明較佳實施例之測試結構之方法流程圖。第π圖係繪示根據本發明較佳實施例之一短路 (Short-circuit)模型之示意圖；第14圖係繪示根據本發明較佳實施例之適用於樹型 (Tree-type)多重錯誤（a-b)、迴路型(Loop-type)多重錯誤（c， f)及混合型（Mixed-type)多重錯誤（d，e，g)之節點組態幾何示意圖，其中第14(a)(b)圖即代表樹型多重錯誤，第14(c) 圖即代表迴路型多重錯誤，第14(d)(e)(g)圖即代表混合型多重錯誤，第14(f)圖即代表迴路型多重錯誤；第15圖係繪示根據本發明所提供之測試結構的橋接錯誤偵測之流程圖及演算法；第16圖係繪示根據本發明較佳實施例之節點組態之幾何示意圖；以及第17圖係繪示節點間漏電流之三維表面圖。圖號之說明 11 -----------裝--------訂--------- (請先閱讀背面之注意事項再填寫本頁) 本纸張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐） 483082 6126twfl.doc/〇〇9 ______B7___ 五、發明說明（VQ ) 本發明較佳實施例之說明 (請先閱讀背面之注意事項再填寫本頁) 本發明之目的即提供一種積體電路測試結構及其測試方法，其係一完整的缺陷分析方法，提供半導體製程硏發與製造時，作爲監控缺陷與良率改善的依據。在本發明之較佳實施例中，係運用類似矩陣路徑（Matdx-like Routing) 之積體電路測試結構，係將整個測試結構之晶片（Test Structure Chip)分成子晶片矩陣（Sub-chip Matrix)，可不需使用任何電路元件（Active Circuit)即可完成測試積體電路在製造過程中所產生的缺陷(Defect)。在本實施例之積體電路測試結構及其測試方法，其可量測在每一個子晶片（Sub-chip)中，導電層與接點/接觸窗鏈（Contact/Via Chain)的阻値，而藉由電性量測的方法，可將隨機的缺陷導致的短路電路定位。並可將有缺陷之錯誤位置（Failure Sites)群聚（Cluster)成不同的群組，而不同類型之定位缺陷的技術係可基於本發明之電性測示結果來完成。經濟部智慧財產局員工消費合作社印製而根據本實施例所提供相當正確之測試結構的電性缺陷密度，與在製程步驟與缺陷的錯誤模組(Process Steps & Defective Failure Mode)用語中的相當正確之每一層刪除比率（Killer ratio of each layer)，可即時地追蹤並降低缺陷的產生。傳統上，靜態隨機存取記憶體（Static Random Access Momory，底下稱爲SRAM)通常用來作爲大量製造之生產 12 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱) 483082 A7 B7 6126twfl.doc/009 五、發明說明（u ) 線的邏輯製程開發與良率分析時測試的工具，其係因爲 SRAM具有較高的密度與可用以定位。藉由軟體的協助，此光學檢查缺陷資料係映射到錯誤位元地圖（Failure Bit Map，底下稱爲FBM)。藉由對FBM的分類，錯誤模式將可特徵化（Characterized)，而具有缺陷的製程步驟也可確認。·接著，正確的錯誤位置分析將可進行，以追蹤與降低缺陷產生的原因。此在SRAM測試工具的系統化錯誤分析將可運用到不同類型的記憶體，以及場效可程式閘極陣列 (Field Programmable Gate Array，FPGA)。因此，將測試結構分割成爲類似記憶體(Memory-like)結構，將會是有效的方法，以快速地確認缺陷的種類，並且追蹤在持續增加的晶片尺寸與降低缺陷密度時，所產生具有缺陷的製程步驟。底下之內容將描述此用在接點/接觸窗（Ccmtact/Via)、以及導電層製程中的類似記憶體(Memory-like)結構。此圖形幾何的模組將可用以代表節點之間的空間上與量測上的關係。基於此模組，此測試結構的配置與路徑，及其相關的測試方法結構，將在底下描述。爲方便描述，將使用幾何學上的專門用語來模擬測試結構內部配置物件之幾何結構。N個節點（Ndn^r^h·· •·，ηΝ})代表具有導電分布目標（Conductive Layout Object) 之導體單元（Conductive Unit，CU)的量測點，例如電梳 (Comb)或彎曲線（Meandering Lines)。此線（L)係描述兩量測墊間的量測，包括短路檢測（Short Cnxmt Check)或斷路本紙張尺度適用中國國家標準（CNS)Al規格（210 X 297公釐） -----------裝！----訂·-------- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製經濟部智慧財產局員工消費合作社印製 483082 6126twfl.d〇c/〇〇9 五、發明說明（VV) 檢測（Open Circuit Check)。Dimension) or film thickness, etc., may not be inspected by this machine. (Please read the notes on the back before filling this page) In view of this, the purpose of the present invention is to provide an integrated circuit test structure and test method, which is a complete defect analysis method to provide semiconductor process development and manufacturing. Time, as a basis for monitoring defects and improving yield. 'The purpose of the present invention is to provide an integrated circuit test structure and a test method thereof', which is an integrated circuit test structure using Matrix_like Routing, and divides the entire test structure chip (Test Structure Chip) into sub-chips. Matrix (Sub-chip Matrix), can be used without any circuit components (Active Circuit) can complete the test of the integrated circuit in the manufacturing process (Defect) generated (Defect). The object of the present invention is to provide an integrated circuit test structure and a test method thereof, which can measure the resistance of a conductive layer and a contact / Via chain in each sub-chip. Alas, and by the method of electrical measurement I, the short circuit caused by random defects can be located. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs ¥ The purpose of the invention is to provide an integrated circuit test structure and test method 'which can cluster defective sites into a same group However, different types of defect locating techniques can be completed based on the electrical measurement results of the present invention. The purpose of the invention is to provide an integrated circuit test structure and its test force based on the electrical defect density of a fairly accurate test structure, and the term "Process Steps & Defective Failure Mode" The fairly correct Kniei * rado of each layer in this can track and reduce the occurrence of defects in real time. 7 This paper size applies to the China Garden Standard (CNS) A · 丨 specifications (210x297 mm) printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 483082 V. Description of the invention (U) In order to achieve the above purpose, the present invention provides a product The circuit test structure includes N test nodes, which are measurement points representing a plurality of conductor units with a conductive distribution target; and a plurality of wires, which are used to arrange and connect the test nodes in a two-dimensional array. In the above integrated circuit test structure, the number of the test structure units is N (N-1) / 2. In the above integrated circuit test structure, the two-dimensional array method includes a first configuration matrix and a second configuration matrix, wherein the first configuration matrix is arranged according to individual nodes of the test nodes, and the second configuration The matrix is arranged according to the relationship between the test nodes. To achieve the above object, the present invention provides a method for testing integrated circuits, including providing a test structure, wherein the structure includes a plurality of N test nodes for measuring a plurality of conductor units; and for the N test nodes A two-dimensional replaceable program is used to connect the test nodes; a short-circuit test and an open-circuit test are performed on the N test nodes, and a test result is obtained; and a defect occurring in the integrated circuit is calculated according to the result . In the above integrated circuit test method, the number of the test structural units is N (N-1) / 2. In the above integrated circuit testing method, the two-dimensional replaceable program system uses a two-dimensional array method. In the above integrated circuit test method, the two-dimensional array method includes a first configuration matrix and a second configuration matrix, wherein the first configuration matrix is arranged according to individual nodes of the test nodes, and the second configuration The matrix is arranged according to the relationship between the test nodes. 8 ----------- Installation -------- Order --------- (Please read the notes on the back before filling this page) This paper size is applicable to China Standard (CNS) A4 specification (210 X 297 mm) 483082 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 6l26twfl.doc / 009 V. Description of the invention (for the purpose of 1) 'The present invention provides ~ a kind of integrated circuit The test method is applicable to an integrated circuit structure. The method includes a procedure for grouping defects, a procedure for single error identification, a procedure for multiple error identification, and an error node identification for end nodes. A procedure to perform a non-returning error position identification procedure; and a procedure to perform the non-returning error position identification procedure, so that the number of defects occurring in the integrated circuit structure is calculated according to the results after performing these procedures. The integrated circuit test architecture and method described above provide a complete test structure, testing and defect tracking methods in a conductive layer and interconnect process. Defects can be found and located before physical error analysis. Obtained The trap data can be compared with the data obtained through the testing instrument, and the estimation of the killer ratio of each layer and the yield can be very accurately. In order to apply the test structure of the present invention, the test wafer needs to be divided into sub-wafer arrays. Combining the sub-wafer with the defect density obtained from the production line, the area of the sub-wafer can be perfectly monitored to make sure that the probability of two defects occurring on the same wafer at the same time is very low. Electrical automatic defect location identification is quite helpful for the development of semiconductor processes and the monitoring of manufacturing yield. At the same time, it can be used to correct the data obtained by the testing instrument. It is more obvious and easy to understand, and the following describes the preferred embodiment and the accompanying drawings for detailed description. Brief description of the drawings: Figure Ua.l) shows the first traditional test structure & conductive The paper size of this layer is in accordance with the Chinese National Standard (CNS) Al specification (210 x 297 mm) ----------- 41 ^ 装 i_ 丨丨 -—Order · — 丨丨丨 (Please Read the notes on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 483082 V. Description of the invention (¾) Layout diagram; Figure Ua.2) shows the first traditional test Distribution diagram of the structure's contacts / connection window chains; Figure 1 (b) shows the placement and routing of the first traditional test structure; • Figure 1 (c) shows the first The geometric figure of a traditional test structure; Figure 2 (a) shows the layout of the contact / contact chain of the second traditional test structure; Figure 2 (b) shows the first Placement and Routing of Two Traditional Test Structures; Figure 2 (c) shows the geometry of the second traditional test structure; Figure 3 shows the third traditional test structure And its geometry; Figure 4 (a) shows a defect data map (Detect Data Map) obtained through an optical inspection machine; Figure 4 (b) shows a single chip defect map (Single Chip Defect Map); Section 4 (c) is the defect shown in Figures 4 (a) and 4 (b) and if consistency is required, it must be The entire test structure is divided into a number of small test structures (Sub-chip); FIG. 5 is a diagram showing a test structure with an 8-node according to a preferred embodiment of the present invention; FIG. 6 is a diagram showing The arrangement of the eight-node test structure according to the preferred embodiment of the present invention and the relationship between the adjacent test units; FIG. 7 is a diagram showing the paper sheet of the inspector according to the preferred embodiment of the present invention. Applicable to China National Standard (CNS) A4 specification (210 X 297 public love) ----- 丨!丨丨 • 丨丨丨!丨 —Order ·!丨 —! (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed 483082 V. Description of the invention (° |) The test structure is a schematic diagram showing the eight-node test structure; Figure 8 is Shows the placement and standard procedure of a test structure, where black lines represent the contact positions with the wafer; Figure 9 shows the design and cross-sectional view of each test unit; Figure 10 shows the preferred embodiment according to the present invention The test structure of the series resistance module; Figure 11 is a schematic diagram showing a short circuit model and a measurement circuit configuration according to a preferred embodiment of the present invention; Figure 12 is a diagram for developing a preferred embodiment of the present invention Flow chart of method for testing structure. FIG. Π is a schematic diagram showing a short-circuit model according to one of the preferred embodiments of the present invention; FIG. 14 is a diagram illustrating a tree-type multiple error according to the preferred embodiment of the present invention (Ab), Loop-type multiple errors (c, f) and Mixed-type multiple errors (d, e, g) node configuration geometric diagram, where 14 (a) (b ) Graph represents tree multiple errors, Figure 14 (c) represents loop multiple errors, Figure 14 (d) (e) (g) represents mixed multiple errors, and Figure 14 (f) represents circuits Fig. 15 is a flowchart and algorithm for bridging error detection of a test structure provided by the present invention; Fig. 16 is a geometrical schematic diagram of a node configuration according to a preferred embodiment of the present invention ; And FIG. 17 is a three-dimensional surface diagram showing leakage current between nodes. Explanation of drawing number 11 ----------- Installation -------- Order --------- (Please read the precautions on the back before filling this page) Zhang scale is applicable to China National Standard (CNS) A4 specification (210 x 297 mm) 483082 6126twfl.doc / 〇〇9 ______B7___ V. Description of the invention (VQ) The description of the preferred embodiment of the present invention (please read the precautions on the back first) (Fill in this page again.) The purpose of the present invention is to provide an integrated circuit test structure and test method, which is a complete defect analysis method, which provides a basis for monitoring defects and yield improvement during semiconductor process development and manufacturing. In a preferred embodiment of the present invention, an integrated circuit test structure using a Matdx-like Routing is used, and the entire test structure chip is divided into sub-chip matrices. , Can be used without the need for any circuit components (Active Circuit) to complete the testing of integrated circuit defects in the manufacturing process (Defect). In the integrated circuit test structure and test method of this embodiment, the resistance of the conductive layer and the contact / Via Chain in each sub-chip can be measured. The electrical measurement method can locate the short circuit caused by random defects. Clusters of defective fault sites can be clustered into different groups, and different types of fault location techniques can be completed based on the electrical measurement results of the present invention. The electrical defect density printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs and provided according to this embodiment is quite accurate, and it is in the term of Process Steps & Defective Failure Mode. The fairly accurate Killer ratio of each layer can track and reduce the occurrence of defects in real time. Traditionally, Static Random Access Momory (hereinafter referred to as SRAM) is usually used as a mass-produced product. 12 The paper size is applicable to China National Standard (CNS) A4 (210 X 297 public love) 483082 A7. B7 6126twfl.doc / 009 V. The invention is a tool for testing (u) line logic process development and yield analysis. It is because SRAM has higher density and can be used for positioning. With the assistance of software, this optical inspection defect data is mapped to a Failure Bit Map (hereinafter referred to as FBM). By categorizing FBM, error patterns can be characterized, and defective process steps can be identified. • Next, correct error location analysis will be performed to trace and reduce the cause of defects. This systematic error analysis in SRAM test tools will be applied to different types of memory, as well as Field Programmable Gate Arrays (FPGAs). Therefore, segmenting the test structure into a memory-like structure will be an effective method to quickly identify the types of defects and track the defects that occur as the wafer size continues to increase and the defect density decreases. Process steps. The content below will describe the memory-like structure used in the contact / contact window (Ccmtact / Via) and conductive layer processes. This graph geometry module will be used to represent the spatial and measurement relationships between nodes. Based on this module, the configuration and path of this test structure and its related test method structure will be described below. For the convenience of description, the geometric terminology will be used to simulate the geometry of the objects inside the test structure. N nodes (Ndn ^ r ^ h ····, ηN) represent measurement points of a conductive unit (CU) with a conductive layout object, such as a comb or a curved line (Meandering Lines). This line (L) describes the measurement between two measurement pads, including short-circuit detection (Short Cnxmt Check) or open circuit. The paper size is applicable to China National Standard (CNS) Al specification (210 X 297 mm) ----- ------ Install! ---- Order · -------- (Please read the notes on the back before filling out this page) Printed by the Employees 'Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs printed 483082 6126twfl. d〇c / 〇〇9 V. Open Circuit Check.

LHj，U = l，2,3----，N (a) 若，則h表示短路檢測單元（sccu); (b) 若I=j，則表示斷路檢測單元（0CCu)}。整個測試結構以G=(N，L)來表示。因此，爲達成明確的指認出測試晶片的缺陷，意味著要存取每一個節點，並辨認出所有的錯誤。因爲有測試結構上的限制，若是節點的數量爲N，則較佳的解決方案係爲此測試結構包括了 Νχ(Ν-1)/2條線用以作爲短路檢測（Short Circuit Check)或N條線作爲斷路檢測（Open Circuit Check) 〇在則述習知的第1、2與3圖中的左手邊係顯示傳統的測試結構，而右手邊則顯示其幾何圖形。而節點則定義爲探針墊(Probe Pads)和測試結構的結合，而位於內部無法存取的節點稱之爲內部節點（Internal Nodes)。第5圖係顯示若是爲8節點的測試結構，其較佳的解決方法的示意圖。如圖中所示，此測試結構應該包括28(Νχ(Ν-1)/2)條線適用於短路檢測及8(Ν)條線適用於斷路檢測。測試結構設計 1.標準程序和安置爲元成此測目式結構配置與路徑（Placement and Routing) 的較佳實施例，一種二維可置換程序（2-D Permutation Procedure)係運用來放置測試結構的單元。第6圖係分別繪示所有導體單元（Conductive Unit，底下簡稱CU)，及彼 14 本紙張尺度適用中國國家標準（CNS)Al規格（210x 297公爱） -----------#裝--------訂 (請先閱讀背面之注意事項再填寫本頁) S! 483082 A7 137 6126twfl.doc/009 五、發明說明（\、）此之間的關係，在此僅提出具有8個節點的測試結構爲例，然並非用以限制本發明之範圍，習知此技藝者皆知，本發明之精神係可運用到具有複數個節點的測試結構。如圖所不’此係運用類似矩陣路徑（Matrix_like Routing)之積體電路測§式結構’其中上半邰的矩陣T係代表此8節點之配置矩陣，而下半部的矩陣Tn「係顯示在此8節點測試結構之測試單元彼此之間的關係，例如(2,3)即代表第2節點與第 3節點之間的關係。而底下之程式碼1係用以完成此二維可置換程序的程式碼，其係運用在Matlab™ 5·1之軟體中。 <程式碼1>LHj, U = 1, 2, 3 ----, N (a) If, then h represents the short circuit detection unit (sccu); (b) If I = j, it represents the open circuit detection unit (0CCu)}. The entire test structure is represented by G = (N, L). Therefore, in order to reach a clear identification of the defects of the test wafer, it means accessing every node and identifying all errors. Because of the limitation on the test structure, if the number of nodes is N, the better solution is to include χ (Ν-1) / 2 lines for the test structure as a short circuit check or N. A line is used as an open circuit check. In the conventional figures 1, 2, and 3, the left-hand side shows the traditional test structure, and the right-hand side shows its geometry. Nodes are defined as the combination of probe pads and test structures. Nodes that are inaccessible internally are called internal nodes. Fig. 5 is a schematic diagram showing a preferred solution for an 8-node test structure. As shown in the figure, this test structure should include 28 (Nχ (Ν-1) / 2) lines for short circuit detection and 8 (N) lines for open circuit detection. Design of test structure 1. Standard procedure and placement is the preferred embodiment of Yuancheng's eyepiece structure configuration and routing. A 2-D Permutation Procedure is used to place the test structure. The unit. Figure 6 shows all the Conductive Units (CU for short) and the 14 paper sizes applicable to the Chinese National Standard (CNS) Al specification (210x 297 public love) ---------- -# 装 -------- Order (please read the notes on the back before filling this page) S! 483082 A7 137 6126twfl.doc / 009 5. Description of the invention (\,) The relationship between this, This example only provides a test structure with 8 nodes as an example, but it is not intended to limit the scope of the present invention. As those skilled in the art know, the spirit of the present invention can be applied to a test structure with multiple nodes. As shown in the figure, 'This is a §-type structure using a matrix circuit like Matrix_like Routing'. The matrix T in the upper half represents the 8-node configuration matrix, and the matrix Tn in the lower half is shown. The relationship between the test units of the 8-node test structure, for example, (2,3) represents the relationship between the 2nd node and the 3rd node. The code 1 below is used to complete this two-dimensional replaceable The program code is used in Matlab ™ 5.1 software. &Lt; Code 1 >

Clear all K=4; Ν=2*Κ T=zeros(Z，N); T=(l，:)=1 :Ν;Clear all K = 4; Ν = 2 * Κ T = zeros (Z, N); T = (l,:) = 1: Ν;

ForΙ=2:Κ Τ(1，1)=丁 (Ι_1，2); Τ(1，Ν)=丁 (Ι-1，Ν-1);ForI = 2: Κ Τ (1,1) = Ding (Ι_1,2); Τ (1, N) = Ding (Ι-1, N-1);

For J=1:K-1 T(I，2*JKT(I十2*(J+1)); T(I52*J+1)=T(M52*J-1)；For J = 1: K-1 T (I, 2 * JKT (I ten 2 * (J + 1)); T (I52 * J + 1) = T (M52 * J-1);

End; -----------裝--------訂--------- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製End; ----------- install -------- order --------- (Please read the notes on the back before filling this page) Intellectual Property Bureau of the Ministry of Economic Affairs Printed by Employee Consumer Cooperative

End;End;

483082 6126twfl. :/009 A7 B7 五、發明說明（v^v) 第7圖係繪示此8節點測試結構之較佳的配置與路徑 (Placement and Routing)，以及顯示出每一導體單元之獨特唯一之相鄰關係。此係如上所述之棋盤式（Checkerboard) 的測試架構。，2.實施此測試結構可設計成監測高密度且隔離之接點/堆疊接觸窗。第8圖係繪示本發明所揭露之測試結構之配置與路徑及其對應的記憶胞單元。而其相對應之測試單元胞的設計係繪不於第9圖。此測試單元胞設計來監視堆邊」1 層窗-主動區（Stack-Via-Active)模組化製程。在此繪示出來標準的一層多晶矽三層金屬層（Single Poly Three Metal’ 1P3M)的邏輯製程。當然，其也可運用較先進的製程’例如一層多晶矽五層金屬層（1P5M)所完成。而其係依照最^ 設計規則(Minimum Design Rule，MDR)來設計的。爲確^ 由測試單兀胞之內連線（Interconnection)的最小良率、 (Yield Loss)，測試單元胞之內連線的寬度和間隔戔少係二最少設計規則MDR的至少2倍大。節點l和節點12間的阻値係顯示高密度導電層的整合。而節點I和節點J的漏電流可用來偵測短路之情形。錯誤形成之樽型這些由單元胞(Umt Cell)與缺陷（RSmi)所組成的_ 構，係模擬成電阻。爲模擬與測試這樣的假設，缺險位^ 係由隨機的產生器所產生，而電流係由內部的軟體在®節本纸張尺度適用中國國家標準（CNS)A·丨規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本真> ------- —訂---------；經濟部智慧財產局員工消費合作社印製 483082 經濟部智慧財產局員工消費合作社印製 6126twfl.doc/〇〇9 ^ ----- 五、發明說明（b ) 點之間所重測出$。請參照帛10目，係顯示此測試結構之串聯電阻模組。每個導電單元皆模組化颇N/2的次電阻（若有N個節點）。請參照第u圖，係顯示一短路模型及:量測電_態之示_〜、代表量測系統_電流。因短路而造成的缺陷Μ以RSm」代表，節點！和節點】的 ^値分別以標示〜他一和心他^來表^請參照第12圖，係顯示用以發展本發明較佳實施例之測試結構之方法流程圖。而節點與其他m個節點則被模擬成m+1個電阻。其模擬之配置如第13圖所示，此係爲具有多重錯誤之模組。而如第14圖所示，係顯示各種不同的節點設計圖。而其所代表的即爲節點之間的虛擬連接關係。例如，第14(a)(b) 圖即代表樹型多重錯誤，第14(c)圖即代表迴路型多重錯誤，第14(d)(e)(g)圖即代表混合型多重錯誤，第14(f)圖即代表迴路型多重錯誤。錯誤偵測的樽擬偵測到缺陷的測試結構模擬成一電阻結構體系 (Resistor Network)。阻値是無缺陷之標準元件（G〇lden483082 6126twfl.: / 009 A7 B7 V. Description of the Invention (v ^ v) Figure 7 shows the better placement and routing of this 8-node test structure, and shows the uniqueness of each conductor unit. The only adjacent relationship. This is a checkerboard test architecture as described above. 2. Implementation This test structure can be designed to monitor high density and isolated contacts / stacked contact windows. FIG. 8 shows the configuration and path of the test structure and the corresponding memory cell unit disclosed in the present invention. The design of the corresponding test cell is not shown in Figure 9. This test cell is designed to monitor the stack edge "1 layer window-active area (Stack-Via-Active) modular process. The logic process of a standard Single Poly Three Metal ’1P3M is shown here. Of course, it can also be accomplished using more advanced processes, such as a polycrystalline silicon five metal layer (1P5M). It is designed according to the Minimum Design Rule (MDR). In order to determine the minimum yield of the interconnection of the test cell, (Yield Loss), the width and interval of the inner connection of the test cell should be at least 2 times the minimum design rule MDR. The resistance system between nodes 1 and 12 shows the integration of a high-density conductive layer. The leakage currents at nodes I and J can be used to detect short circuits. Incorrectly formed bottle types These structures consisting of Umt Cells and Defects (RSmi) are modeled as resistors. In order to simulate and test such hypotheses, the danger level ^ is generated by a random generator, and the current is generated by the internal software at the Chinese paper standard (CNS) A · 丨 specification (210 X 297) (Mm) (Please read the notes on the back before filling in the authenticity > ------- —Order ---------; Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 483082 Wisdom of the Ministry of Economic Affairs Printed by the Consumer Cooperative of the Property Bureau 6126twfl.doc / 〇〇9 ^ ----- V. The re-measurement of $ between the points of the invention description (b). Please refer to 目 10 head, which shows the series resistance of this test structure Module. Each conductive unit is modularized with N / 2 secondary resistance (if there are N nodes). Please refer to the figure u, which shows a short-circuit model and: Measured electricity Measurement system_current. Defects caused by short-circuits are represented by RSm ", node! And node" ^^ are marked with ~~ and ^^^ Please refer to Figure 12, which is shown for development A flowchart of a method for testing a structure according to a preferred embodiment of the present invention, and the nodes and other m nodes are simulated as m + 1 resistors. The configuration of the simulation is shown in Figure 13, which is a module with multiple errors. As shown in Figure 14, it shows a variety of different node design diagrams. The virtual connection between the nodes is represented by For example, graph 14 (a) (b) represents tree multiple errors, graph 14 (c) represents loop multiple errors, and graph 14 (d) (e) (g) represents mixed multiple errors Error, Figure 14 (f) represents multiple errors of the loop type. The test structure for error detection is to simulate a resistance structure system (Resistor Network). Resistance is a standard component without defects (Gollden).

Device)的電子測試量測分佈的統計値。缺陷的阻値模型化成一常態分佈’平均値（μ)等於電子測試量測平均値的一半’而標準差（σ)等於電子測試量測値的標準差。使用 Matlab™ 5.1之軟體中的一個程式，來解出節點電位和元件的電流。在任一節點量測阻値的同時，在未量測阻値之任卽點上里測_位。儲存結果並離線進彳了電子分析。缺 17 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 χ 297公楚） ----丨—丨ί ·!丨丨丨1訂·丨丨！丨！ (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 483082 五、發明說明（\b ) 陷的偵測分爲兩個部分··缺陷的群組及單一 /多重錯誤的位置辨識。測試的細節及缺陷位置篩選流程請參照第15 圖。在第1 5圖中，包括了六個程序，係以底下適用於 Matlab™ 5」軟體之程式詳述如下： 1. 關·於缺陷群組化（Defect Grouping)之程序：有施以偏壓的節點2Vf接地GND;，其中 iVi係爲提供第一迴圈之電壓、2Vi係爲提供第二迴圈之電壓Device) electronic test measurement statistics. The impediment of the defect is modeled as a normal distribution 'average 値 (μ) equal to half of the average 电子 of the electronic test measurement and the standard deviation (σ) is equal to the standard deviation of the electronic test measurement 値. Use a program in Matlab ™ 5.1 software to solve the node potential and component current. While measuring the resistance at any node, measure the _ bit at any point where resistance is not measured. The results were stored and electronically analyzed offline. Missing 17 This paper size is applicable to China National Standard (CNS) A4 specification (21 × 297 Gongchu) ---- 丨 — 丨 ί ·! 丨丨 1 Order · 丨丨!丨! (Please read the precautions on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed by 483082 V. Invention Description (\ b) The detection of traps is divided into two groups: Defect groups and single / Multiple false position identification. Please refer to Figure 15 for test details and defect location screening process. In Figure 15, there are six procedures, which are detailed below for the Matlab ™ 5 "software: 1. Procedures related to Defect Grouping: bias applied The node 2Vf is grounded to GND; where iVi is the voltage that provides the first loop and 2Vi is the voltage that provides the second loop

For i=l〜N; j，IFor i = l ~ N; j, I

For j = l〜N & j矣I; VVJ! and VJ2 are measuredFor j = l ~ N & j 矣 I; VVJ! And VJ2 are measured

If then J is defined as same as I group. G^{Node1? Node25 ....}；缺陷群組化係針對每一個節點。 2. 關於單一錯誤辨識（Single Fault Identification)之程序：有施以偏壓的節點1V1=Vdd& 2Vf接地GND ;If then J is defined as same as I group. G ^ {Node1? Node25 ....}; Defect grouping is for each node. 2. Single Fault Identification (Single Fault Identification) procedures: Biased node 1V1 = Vdd & 2Vf ground GND;

For i=l〜N;For i = l ~ N;

If and Only If，彐(exit)Nodei5 Nodei eG! i Gf係代表單一錯誤群組 3. 關於多重錯誤辨識（Multi Fault Identification)之程序·· 有施以偏壓的節點乂=乂〇1(1& 2ν^妾地GND For i=l〜N;If and Only If, ex (exit) Nodei5 Nodei eG! I Gf represents a single error group 3. About the procedure of Multi Fault Identification (Multi Fault Identification) ·· There is a biased node 乂 = 乂〇1 (1 & 2ν ^ 妾地 GND For i = l ~ N;

If and Only If，彐（exit) number of Node} eG! is more than three 18 本紙張尺度適用中國國家標準（CNS)A·丨規恪（210 X 297公釐） -----------裝--------訂------1 — (請先閱讀背面之注意事項再填寫本頁) 483082 A7 137 6126twfl . doc/009 五、發明說明) 1 Gf係代表多重錯誤群組 4. 關於末端節點錯誤位置辨識（Ended-node Fault Sites Identification)之程序：有施以偏壓的節點2V,=接地GND For i=l〜Μ;If and Only If, ex (exit) number of Node} eG! Is more than three 18 This paper size applies Chinese National Standard (CNS) A · 丨 Compliant (210 X 297 mm) -------- --- Installation -------- Order ------ 1 — (Please read the precautions on the back before filling this page) 483082 A7 137 6126twfl .doc / 009 V. Description of the invention 1 Gf series Represents multiple error groups 4. About the procedure of Ended-node Fault Sites Identification: There is a biased node 2V, = ground GND For i = l ~ M;

If and Only If，彐（exit) Nodei eGiIf and Only If, 彐（exit) Nodei eGi

Vi=V2=... VMVi = V2 = ... VM

Nodei末端節點Nodei end node

Min.(Rij){V〇=1VJ=2Vj =!Vk =2Vk =iVL=2VL.......} 〇缺陷定位於Nodei與Node』。 5. 關於非迴圈錯誤位置辨識（Nonloop Fault Sites Identification)之程序：有施以偏壓的節點2Vf接地GND For i=l〜Μ; (Μ是在群組Groi^的數量）Min. (Rij) {V〇 = 1VJ = 2Vj =! Vk = 2Vk = iVL = 2VL .......} The defect is located at Nodei and Node. 5. Procedures for Nonloop Fault Sites Identification: There is a biased node 2Vf ground GND For i = l ~ M; (M is the number of Groi ^ in the group)

If and Only If，.·.（alpNodei eGj &&...(all) &&α}ν! 2VkIf and Only If, ... (alpNodei eGj & & ... (all) & & α} ν! 2Vk

For j，k=l〜M&&j，kH; => 1^0(161係非迴圈錯誤。For j, k = l ~ M & & j, kH; = > 1 ^ 0 (161 is a non-loop error.

Min.(Rij){V1-1VJ-2VJ =2Vk ...…·} 々缺陷定位於Node;與Node』。Min. (Rij) {V1-1VJ-2VJ = 2Vk ......} 々The defect is located at Node; and Node ”.

Mm/RUMV^Vj二2Vj 二iVk =2Vk ^VL=2VL} =>缺陷定位於Node;與Node』。 6. 關於迴圈錯誤位置辨識（Loop Fault Sites Identification)之 19 本纸張尺度適用中國國家標準（CNS)Al規格（21〇χ 297公釐） I t· --訂--------- φ, (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 483082 A7 B7 6126twfl.doc/009 五、發明說明（1¾ ) 程序：有施以偏壓的節點1Vi=Vdd& 妾地GND For i=l〜Μ; (Μ是在群組Group!的數量）Mm / RUMV ^ Vj 2 2Vj 2 iVk = 2Vk ^ VL = 2VL} = > The defect is located at Node; and Node ". 6. Regarding Loop Fault Sites Identification (19) This paper size applies the Chinese National Standard (CNS) Al specification (21〇χ 297 mm) I t · --Order ------- -φ, (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 483082 A7 B7 6126twfl.doc / 009 V. Description of the invention (1¾) Procedure: Node 1Vi = Vdd & Ground GND For i = 1 ~ Μ; (Μ is the number in the group Group!)

If and Only (al^Node, eG, &&3(exit) 1VJ-2VJ &&(exit) ^Vk，1V1 关2乂1，iVi^Vi ......If and Only (al ^ Node, eG, & & 3 (exit) 1VJ-2VJ & & (exit) ^ Vk, 1V1 off 2 乂 1, iVi ^ Vi ......

For j，k=l〜M&&j，k#i; => Nodej Nodek Node!.....係迴圏錯誤。結果爲了確認結果，將模擬一具有80個節點的測試結構。在下列的第1表中給予預先設定缺陷，而其序號係重新映射(Re_mapped)，而在設定的序號。第1表 1，2 11,12 12,20 13,14 13,15 13,17 14,15 14,16 15,16 16,17 16,18 17,20 18,19 2,3 2,9 20,21 21,22 21,23 21,24 21,25 22,23 22,24 22,25 23,24 23,25 24,25 4,5 4,8 5,6 7,8 8,12 8,9 9,10 而第16圖係顯示這些節點之間的幾何連接關係。在此一倂說明。在第16圖中，節點1、3、6、7、10、11與 19 係爲末端節點（Ended Nodes)。節點 2、4、5、8、9、12、 18與20係爲非迴圈節點（Non-loop Nodes)。節點13、14、 15、16 與 17 係爲迴圈節點（Loop Nodes)。節點 21、22、23、 24與25係爲另一迴圈節點（Loop Nodes)。其中，提供第一迴圈之電壓1乂！與提供第二迴圈之電壓2VI値不同。在第2表中說明根據本發明實施例之演算法則所據以 20 本紙張尺度適用中國國家標準（CNS)/\·丨規格（210 x 297公釐） -----------裝--------訂---------^^1 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 483082 6126twf1.doc/009 A7 B7 五、發明說明（Θ ) 實施之缺陷位置確認的結果，如下所示，底線部分係代表：第2表末端節點 1，2 11,12 18,19 2,3 5,6 7,8 9,10 ----—- 非迴圈節點 12,20 16,18 17,20 2,9 20,21 4,5 4,8 8,12 第一迴圈節點 21,22 21,23 21,24 21,25 22,23 22,24 22,25 23,24 23,25 24,25 第二迴圈節點 13,14 13,15 13r16 13,17 14,15 14,16 14r17 15,16 15,17 16,17 經濟部智慧財產局員工消費合作社印製第16圖係繪示節點間漏電流之幾何示意圖，表現出所有的缺陷位置（節點i至節點j，j，I=l〜K，i#j)且包括錯誤缺陷產生的量測。表1顯示位置辨識的結果。和Hess，C. 等人在 IEEE Transactions on Semiconductor Manufacturing， pp. 284-292，Vol· 7，No. 3，1994·及在 Proceedings IEEE 1990 Inti. Conf. On Microelectronic Test Structures, Vol. 115 pp· 141-146, March 1998.所展示的模型相較，本發明可以提供正確的缺陷位置，但不能解出迴路型的缺陷。第17 圖係顯示三維（3-D)表面圖示，說明在節點之間的漏電流，可顯示所有缺陷之位置（節點i到j，i=1〜K，i#j， 300=25*(25-1)/2=Κ*(Κ-1)/2)，包括由量測結果所知的錯誤缺陷。結論本發明提供了在一導電層與內連線製程中，完整的測試結構，與測試及缺陷追蹤的方法。缺陷可在實體錯誤分析之前找出和定位’所得到的缺陷數據將可與經由檢測儀器所得的數據做比較，而能非常準確的刪除比率（Killer 21 -----------·裝--------訂 (請先閱讀背面之注意事項再填寫本頁)For j, k = l ~ M & & j, k # i; = > Nodej Nodek Node! ..... It is an error. Results To confirm the results, a test structure with 80 nodes will be simulated. Defects are given in the first table below, and their numbers are re-mapped, and the numbers are set. Table 1, 2, 11, 12, 12, 20 13,14 13,15 13,17 14,15 14,16 15,16 16,17 16,18 17,20 18,19 2,3 2,9 20, 21 21,22 21,23 21,24 21,25 22,23 22,24 22,25 23,24 23,25 24,25 4,5 4,8 5,6 7,8 8,12 8,9 9 10 and Figure 16 shows the geometric connection between these nodes. I will explain here. In Fig. 16, nodes 1, 3, 6, 7, 10, 11 and 19 are end nodes. Nodes 2, 4, 5, 8, 9, 12, 18, and 20 are non-loop nodes. Nodes 13, 14, 15, 16, and 17 are loop nodes. Nodes 21, 22, 23, 24, and 25 are another Loop Nodes. Among them, the voltage of the first loop is provided 1 乂! It is different from the voltage 2VI 値 which provides the second loop. Table 2 shows that the algorithm according to the embodiment of the present invention is based on the 20 paper standards applicable to the Chinese National Standard (CNS) / \ · 丨 specifications (210 x 297 mm) ---------- -Install -------- Order --------- ^^ 1 (Please read the precautions on the back before filling out this page) Printed by the Employee Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 483082 6126twf1.doc / 009 A7 B7 V. The results of the defect location confirmation of the description of the invention (Θ), as shown below, the bottom line represents: End node of table 2 1, 2 11, 12 18, 19 2, 3 5, 6 7, 8 9,10 -------- Non-loop nodes 12,20 16,18 17,20 2,9 20,21 4,5 4,8 8,12 First loop nodes 21,22 21,23 21 , 24 21,25 22,23 22,24 22,25 23,24 23,25 24,25 Second loop node 13,14 13,15 13r16 13,17 14,15 14,16 14r17 15,16 15, 17 16,17 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Figure 16 is a geometric diagram showing the leakage current between nodes, showing all the defect locations (node i to node j, j, I = l ~ K, i #j) and includes measurements of erroneous defects. Table 1 shows the results of position recognition. And Hess, C. et al. In IEEE Transactions on Semiconductor Manufacturing, pp. 284-292, Vol · 7, No. 3, 1994 · and Proceedings IEEE 1990 Inti. Conf. On Microelectronic Test Structures, Vol. 115 pp · 141 -146, March 1998. Compared with the model shown, the present invention can provide the correct defect location, but cannot solve the loop-type defect. Figure 17 shows a three-dimensional (3-D) surface diagram showing the leakage current between the nodes, showing the location of all defects (nodes i to j, i = 1 ~ K, i # j, 300 = 25 * (25-1) / 2 = κ * (Κ-1) / 2), including false defects known from the measurement results. Conclusion The present invention provides a complete test structure, a method for testing and defect tracking in a conductive layer and interconnect process. Defects can be found and located before physical error analysis. The obtained defect data will be compared with the data obtained through testing equipment, and the deletion ratio can be very accurate (Killer 21 ----------- · Install -------- Order (Please read the precautions on the back before filling this page)

本紙張尺度適用中國國家標準（CNS)A4規格（21〇 297公釐） 483082 6l26twfl.doc/009 A7 B7 五、發明說明（>◦) ratio of each layer)和良率的估計。爲適用本發明之測試結構，測試晶片需要分割成次晶片陣列。次晶片與由生產線所得的缺陷密度結合，次晶片的區域上可以被完美的監視而確信同時在同一次晶片上出現兩次缺陷的機率降得很低。 •本發明提供以系統化的缺陷追蹤和電性自動缺陷位置辨認，對半導體製程的發展和製造良率的監視是有相當的幫助。同時可以用來校正檢測儀器所得的數據。雖然本發明已以一較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者爲準。 -----------裝--------訂·--------^9— (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 22 本紙張尺度適用中國國家標準（CNS)A〗規格（210 x 297公釐)This paper size applies the Chinese National Standard (CNS) A4 specification (21〇 297 mm) 483082 6l26twfl.doc / 009 A7 B7 5. Description of the invention (> ◦) ratio of each layer and yield estimation. In order to apply the test structure of the present invention, the test wafer needs to be divided into sub-wafer arrays. Combining the sub-wafer with the defect density obtained from the production line, the area of the sub-wafer can be perfectly monitored to ensure that the probability of two defects occurring on the same sub-wafer at the same time is very low. • The present invention provides systematic defect tracking and electrical automatic defect location identification, which is quite helpful for the development of semiconductor processes and the monitoring of manufacturing yield. It can also be used to calibrate the data obtained by the testing instrument. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. ----------- Installation -------- Order · -------- ^ 9— (Please read the precautions on the back before filling this page) Intellectual Property of the Ministry of Economic Affairs Printed by the Bureau's Consumer Cooperatives 22 This paper size applies to China National Standard (CNS) A〗 (210 x 297 mm)

Claims

經齊郎智慧財產局員工消費合作社印說 483082 AS R8 C8 Γ)8 _6126twfl.doc/〇〇9____ 六、申請專利範圍 1. 一種積體電路測試結構，包括： N個測試節點，係代表具有導電分布目標之複數個導體單元的量測點；以及複數個導線，用以將該些測試節點以一二維陣列方式排列相互連接在一起。 2. 如申請專利範圍第1項所述之積體電路測試結構，其中該些該些測試結構單元的數目爲Ν(Ν-1)/2。 3. 如申請專利範圍第1項所述之積體雷路測試結構，其中該二維陣列方式係包括一第一配置矩陣與一第二配置矩陣，其中該第一配置矩陣係按照該些測試節點之個別節點排列，而該第二配置矩陣係按照該些測試節點彼此之間的關係排列。 4. 一種積體電路測試方法，包括：提供一測試結構，其中該結構包括複數個N個測試節點，係用以量測複數個導體單元；對該些N個測試節點以一二維可置換程序連接該些測試節點；對該些N個測試節點進行一短路檢測與一斷路檢測，並得到一測試結果；以及根據該結果，計算在該積體電路所發生的缺陷。 5. 如申請專利範圍篥4項所述之積體電路測試方法，其中該些該些測試結構單元的數目爲Ν(Ν-1)/2。 6. 如申請專利範圍第4項所述之積體電路測試方法，其中，該二維可置換程序係係使用一二維陣列方式。 __23__ 本紙張尺度適用中國國家標準（CNS)A4規格（2】〇χ297公坌） (請先閱讀背面之注意事項再填寫本頁) # I I I I I I ! «ΙΙΙΙΙΙΙ — · 經濟部中央標準局員工消費合作社印製 483082 A8 6126twfl.doc/009 ^ D8 六、申請專利範圍 7. 如申請專利範圍第6項所述之稽體雷路測試方法，其中該二維陣列方式係包括一第一配置矩陣與一第二配置矩陣，其中該第一配置矩陣係按照該些測試節點之個別節點排列，而該第二配置矩陣係按照該些測試節點彼此之間的關係排列。 8. 如申請專利範圍第5項所述之積體電路測試方法，其中該二維可置換程序之程式碼運用在Matlab™ 5.1之軟體爲： . Clear all K=4; Ν=2*Κ T=zeros(Z，N); Τ=(1，:)=1:Ν; For l=2:K T(1，1):T(I-1，2); Τ(1，Ν)二 T(I-1，N-1); For J=1:K-1 T(I，2*J)=T(I-1，2*(J+1)); T(I，2*J+1)=T(I-1，2*J-1); End; End ； o 9. 一種積體電路測試方法，係適用於一積體電路結構，該方法包括下列步驟： 24 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公楚:) _ ---：-----0^ —---.——tr----- (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標隼局員工消費合作社印製 483082 六、申請專利範圍進行一缺陷群組化（Defect Grouping)之程序；進行一單一錯誤辨識（Single Fault Identification)之程序；進行一多重錯誤辨識（Multi Fault Identification)之程序；進行一末端節點錯誤位置辨識(Ended-n〇de Fauit Sites Identification)之程序；進行一非迴圏錯誤位置辨識（Nonloop . Fault Shes Identification)之程序；以及進行一迴圈錯誤位置.辨識（Loop Fault Sites Identification)之程序，藉以使得根據進行該些程序後之結果，計算在該積體電路結構所發生的缺陷數量。 10.如申請專利範圍第9項所述之積體電路測試方法，其中該缺陷群組化之程序包括：施以一偏壓的節點iVfVdd，以及2V,=接地，其中iVj 係爲提供一第一迴圈之電壓、2Vi係爲提供一第二迴圈之電壓；以及提供一程式碼，運用在MatlabTM 5.!之軟體，該程式碼如下： For i=l〜N; j弇I For j = l〜N & j矣I; VVJ! and VJ2 are measured If Vj关0, then J is defined as same as I group. G={Nodel5Node2，缺陷群組化係針對每一個節點。 25 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ---1-----ΦΊ^—---.--tr-----•線 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 483082 六、申請專利範圍 11. 如申請專利範圍第9項所沭之穑體電路測試方$，其中該單一錯誤辨識之程序包括：施以一偏壓的節點iV^vdd，以及2ν^接地，其中iVi 係爲提供一第一迴圈之電壓、2VI係爲提供一第二迴圈之電壓；以及提供一程式碼，運用在Matlab™ 5·1之軟體，該程式碼如下： For i=l〜Ν; • · C二、· If and Only If，彐（exit)Nod今匕 Mpdei eGi 3 Gf係代表一單一錯誤 12. 如申請專利範圍第9項所述;電路測試方法，其中該多重錯誤辨識（Multi Fault Id^^^cation)之程序包括· 施以一偏壓的節點JfVdd，以及2Vr接地，其中lVl 係爲提供一第一迴圏之電壓、2Vi係爲提供一第二迴圈之電壓；以及提供一程式碼，運用在Matlab™ 5.1之軟體，該程式碼如下： For i=l〜N; If and Only If，彐（exit) number of Nodei eGi is more than three 係代表一多重錯誤群組。 13. 如申請專利範圍第9項所述之積體電路測試方法，其中該末端節點錯誤位置辨識（Ended-node Fault Sites Identification)之程序包括： 26 本紙ϋ度適用中國國家樣隼(CNS ) Α4規格（210Χ297公釐） -----------：——tr-----雙 (請先閲讀背面之注意事項再填寫本頁) 483082 A8 B8 C8 D8 6126twfl·doc/009 六、申請專利範圍施以一偏壓的節點iVfVdd，以及2Vf接地，其中iVi 係爲提供一第一迴圏之電壓、2乂！係爲提供一第二迴圈之電壓；以及提供一程式碼’運用在MatlabTM 5.1之軟體，該程式碼如下： For i=l〜M; If and Only If，彐（exit) Nodei eG! .V 1=V2=---^M Nodei末端節點 Min.(Rij){V〇=1VJ=2VJ -,Υ, =2Vk ·..····} 二缺陷定位於Nodei與Node/。 14.如申請專#」L範圍第9項所述之積體電路測試方法，其中該非迴圈錯誤位置辨識（Nonloop Fault Sites Identification)之程序包括：施以一偏壓的節點JfVdd，以及2Vi=接地，其中1¼ 係爲提供一第一迴圈之電壓、'V!係爲提供一第二迴圈之電壓；以及提供一程式碼，運用在MatlabTM 5.1之軟體，該程式碼如下： For i=l〜Μ; (M是在群組Group!的數量） If and Only If，…（all)Nodei eG! &&...(all) iVj^Vj &&α}ν! 2Vk , For j，k=l〜M&&5'，㈣； => Nodq係非迴圏―筹A ------------.--訂----- (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合柞According to Qilang Intellectual Property Bureau's employee consumer cooperative, 483082 AS R8 C8 Γ) 8 _6126twfl.doc / 〇〇9 ____ VI. Application for patent scope 1. An integrated circuit test structure, including: N test nodes, which are representative of conductive The measurement points of the plurality of conductor units of the distribution target; and the plurality of wires for connecting the test nodes in a two-dimensional array. 2. The integrated circuit test structure described in item 1 of the scope of patent application, wherein the number of these test structure units is N (N-1) / 2. 3. The integrated lightning test structure described in item 1 of the scope of the patent application, wherein the two-dimensional array method includes a first configuration matrix and a second configuration matrix, and the first configuration matrix is based on the tests. The individual nodes of the nodes are arranged, and the second configuration matrix is arranged according to the relationship between the test nodes. 4. A method for testing integrated circuits, comprising: providing a test structure, wherein the structure includes a plurality of N test nodes for measuring a plurality of conductor units; and a two-dimensional replaceability is applied to the N test nodes. The program connects the test nodes; performs a short-circuit detection and an open-circuit detection on the N test nodes, and obtains a test result; and calculates a defect occurring in the integrated circuit according to the result. 5. The integrated circuit test method described in item 4 of the scope of patent application, wherein the number of these test structural units is N (N-1) / 2. 6. The integrated circuit test method as described in item 4 of the scope of patent application, wherein the two-dimensional replaceable program uses a two-dimensional array method. __23__ This paper size is in accordance with Chinese National Standard (CNS) A4 (2) 0297 mm (Please read the precautions on the back before filling out this page) # IIIIII! System 483082 A8 6126twfl.doc / 009 ^ D8 VI. Application for patent scope 7. The test method for body lightning as described in item 6 of the scope of patent application, wherein the two-dimensional array method includes a first configuration matrix and a second configuration Matrix, wherein the first configuration matrix is arranged according to the individual nodes of the test nodes, and the second configuration matrix is arranged according to the relationship between the test nodes. 8. The integrated circuit test method described in item 5 of the scope of patent application, wherein the code of the two-dimensional replaceable program used in Matlab ™ 5.1 software is:. Clear all K = 4; Ν = 2 * Κ T = zeros (Z, N); Τ = (1,:) = 1: N; For l = 2: KT (1,1): T (I-1,2); Τ (1, N) = T ( I-1, N-1); For J = 1: K-1 T (I, 2 * J) = T (I-1,2 * (J + 1)); T (I, 2 * J + 1 ) = T (I-1, 2 * J-1); End; End; o 9. An integrated circuit test method, which is applicable to an integrated circuit structure, the method includes the following steps: 24 This paper size is applicable to China National Standard (CNS) A4 Specification (210X297): _ ---: ----- 0 ^ -----.-- tr ----- (Please read the precautions on the back before filling this page ) Printed by the Employees' Cooperative of the Central Bureau of Standards, Ministry of Economic Affairs, Consumer Cooperative 483082 6. Apply for a defect grouping (Defect Grouping) procedure; Perform a single fault identification (Single Fault Identification) procedure; Perform a multiple error identification (Multi Fault Identification) procedure; End-node Fauit Sites Iden tification) procedure; a non-loop fault location identification (Nonloop. Fault Shes Identification) procedure; and a loop fault site identification identification (Loop Fault Sites Identification) procedure, so that after performing these procedures according to As a result, the number of defects occurring in the integrated circuit structure is calculated. 10. The integrated circuit test method according to item 9 of the scope of the patent application, wherein the defect grouping procedure includes: a biased node iVfVdd, and 2V, = ground, where iVj is to provide a first The voltage of one loop, 2Vi is to provide the voltage of a second loop; and to provide a code, which is used in the software of MatlabTM 5.!, The code is as follows: For i = l ~ N; j 弇 I For j = l ~ N & j 矣 I; VVJ! and VJ2 are measured If Vj off 0, then J is defined as same as I group. G = {Nodel5Node2, defect grouping is for each node. 25 This paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm) --- 1 ----- ΦΊ ^ -----.-- tr ----- • line (Please read the Please fill in this page again for attention) Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 483082 6. Scope of patent application 11. For example, the circuit tester for the body circuit in item 9 of the scope of patent application, where the single error identification procedure includes : A biased node iV ^ vdd, and 2ν ^ ground, where iVi is to provide a voltage for a first loop, 2VI is to provide a voltage for a second loop; and a code is provided for use in For Matlab ™ 5.1 software, the code is as follows: For i = l ~ N; • C 2. If and Only If, (Exit) Nod today Mpdei eGi 3 Gf represents a single error 12. Such as The method of circuit test described in item 9 of the patent application; wherein the procedure of the Multi Fault Id ^^ cation includes: a node JfVdd with a bias voltage, and 2Vr ground, where lVl is a The voltage of the first loop, 2Vi is the voltage to provide a second loop; and Provide a code for Matlab ™ 5.1 software. The code is as follows: For i = l ~ N; If and Only If, (exit) number of Nodei eGi is more than three represents a multiple error group . 13. The integrated circuit test method described in item 9 of the scope of the patent application, wherein the procedures of the Ended-node Fault Sites Identification include: 26 This paper is applicable to China National Samples (CNS) Α4 Specifications (210 × 297 mm) -----------: —— tr ----- Double (Please read the precautions on the back before filling this page) 483082 A8 B8 C8 D8 6126twfl · doc / 009 6. The scope of the patent application applies a biased node iVfVdd, and 2Vf ground. Among them, iVi is to provide a first loop voltage, 2 °! To provide a second loop voltage; and to provide a code 'used in MatlabTM 5.1 software, the code is as follows: For i = l ~ M; If and Only If, ex (exit) Nodei eG! .V 1 = V2 = --- ^ M Nodei end node Min. (Rij) {V〇 = 1VJ = 2VJ-, Υ, = 2Vk · .. ····} Two defects are located at Nodei and Node /. 14. The integrated circuit test method as described in item 9 of the application scope, wherein the non-loop fault site identification (Nonloop Fault Sites Identification) procedure includes: a node JfVdd that is biased, and 2Vi = Grounding, where 1¼ is to provide a voltage of a first loop, 'V! Is to provide a voltage of a second loop; and a code is provided for use in MatlabTM 5.1 software, the code is as follows: For i = l ~ Μ; (M is the number of Group!) If and Only If, ... (all) Nodei eG! & & ... (all) iVj ^ Vj & & α} ν! 2Vk, For j, k = l ~ M & & 5 ', ㈣; = > Nodq is non-returning-raise A ------------.-- order ----- (please (Please read the notes on the back before filling out this page.)

2Ί L適用中國國家標準（CNS ) A4規格（210X297公釐） 483082 6126twfl.doc/009 A8 B8 C8 D8 六、申請專利範圍 Min/RijMVhVhVj =iV「2Vk =iVL 二 2VL ·..···.} 3缺陷定位於Nodei與Node』。 Μιη._{ν2，ν产2Vj 二％ =2Vk =^八···.…} 缺陷定位於Nodei與Node』。 15.如里請專利範園第9項所沭夕精體雷路試卞法，其中該迴圏錯誤位置辨識（Loop Fault Sites Identification) 之程序包括：施以一偏壓的節點JfVdd，以及2Vi=接地，其中^ 係爲提供一第一迴圈之電壓、2Vi係爲提供一第二迴圈之電壓；以及提供一程式碼，運用在Matla.b™ 5.1之軟體，該程式碼如下： For 〜Μ; (M是在群組GrouPl的數量） If and Only If”·.（all)Nodei 叫 &&3(exit) iVjiVj &&(exit) i Vk 矣 2Vk 5lVi 矣 ^i V〆 2Vi··· ··· For j，k=l〜M&&j，k矣i; ==^ Node； Nodek Nodej 係一'迴圈錯誤。 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 28 本紙張尺度適用中國國家榡準（CNS ) A4規格（210 X 297公釐）2Ί L Applicable to China National Standard (CNS) A4 specification (210X297 mm) 483082 6126twfl.doc / 009 A8 B8 C8 D8 VI. Patent application scope Min / RijMVhVhVj = iV 「2Vk = iVL 2 2VL · .. ···.} 3 Defects are located in Nodei and Node ". Μιη ._ {ν2, ν produced 2Vj 2% = 2Vk = ^ ............ Defects are located in Nodei and Node" 15. Please request the 9th place in the patent garden The test method of the seizure thunderbolt method, wherein the loop fault site identification procedure includes: a node JfVdd with a bias voltage, and 2Vi = ground, where ^ is to provide a first The voltage of the loop, 2Vi is to provide the voltage of the second loop; and to provide a code, which is used in the software of Matla.b ™ 5.1, the code is as follows: For ~ M; (M is in the group GrouPl (Quantity) If and Only If ”.. (all) Nodei is called & & 3 (exit) iVjiVj & & (exit) i Vk 矣 2Vk 5lVi 矣 ^ i V〆2Vi ····· For j, k = l ~ M & & j, k 矣 i; == ^ Node; Nodek Nodej is a loop error. (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Central Bureau of Standards, Ministry of Economic Affairs 28 This paper is sized for China National Standard (CNS) A4 (210 X 297 mm)