TW480653B

TW480653B - Manufacturing method for both landing via and strip contact of embedded memory

Info

Publication number: TW480653B
Application number: TW90104931A
Authority: TW
Inventors: Sun-Chieh Chien; Chien-Li Kuo
Original assignee: United Microelectronics Corp
Priority date: 2001-03-02
Filing date: 2001-03-02
Publication date: 2002-03-21

Abstract

The present invention provides a manufacturing method integrating the landing via and the strip contact of the embedded memory, which includes the following steps: defining a memory array region and a periphery circuits region on the surface of the semiconductor chip; next, forming a plurality of gates and lightly doped drains on the memory array region and the periphery circuits region, respectively; then, covering a silicon nitride layer on the surface of each gate in the memory array region and forming the spacer at the periphery of each gate on the periphery circuits region; forming a dielectric layer on the surface of the semiconductor chip; forming a plurality of landing via holes and strip contact holes in the memory array region and in the dielectric layer on the periphery circuits region, respectively; finally, filling up a conductive layer in each of the holes to simultaneously form each landing via and each strip contact.

Description

480653 五、發明說明（1) --~--- 發明之領域接觸ί ί:提供一種整合嵌入式記憶體以及轉接介層與帶 ^.作方法’尤指一種可減少帶接觸在記憶體元件中所佔據的空間的方法。仟中背景說明、隨著$程積集度的不斷提昇，現今製作半導體積體電，趨勢是將記憶元陣列（memory cell array)與高速邏 ° 電路元件（high-speed logic circuit elements)進行整:二同時製作在一個晶片（ch i p )上，形成一種同時結合了記憶體陣列以及邏輯電路（logic circuits )的嵌入式記憶，’以大幅節省面積並加快訊號的處理速度。而為了避免肷入式記憶體中的各種元件發生短路，每一個元件與電路之間均覆蓋有一絕緣層，然後再利用黃光暨蝕刻製程 (photo-etching-process, PEP)，於絕緣層中會形成複數個接觸洞（c ο n t a c t h ο 1 e )，並於接觸洞中填滿導電層，以達到内部電連接（electrical interc〇nnecti〇n)各金屬氧化物半導體電晶體以及電路的目的。清參考圖一至圖Ί--，圖一至圖十一為習知於一半導體晶片1 0上製作一嵌入式記憶體之金屬氧化物半導體 (M0S)電晶體以及各轉接介層與區域内連線（local480653 V. Description of the invention (1)-~ --- Contact in the field of invention ί ί: Provide an integrated embedded memory and transfer interposer and tape ^. Method of operation 'especially a method to reduce the contact of the tape in the memory A method of space occupied in a component. Langzhong background note, with the continuous increase of the degree of accumulation, the current production of semiconductor integrated circuits, the trend is to integrate memory cell array and high-speed logic circuit elements (high-speed logic circuit elements) : Two are fabricated on a chip (ch ip) at the same time to form an embedded memory that combines a memory array and logic circuits at the same time, 'to greatly save area and speed up signal processing speed. In order to avoid short circuit of various components in the embedded memory, an insulation layer is covered between each component and the circuit, and then a yellow light-etching-process (PEP) is used in the insulation layer. A plurality of contact holes (c ο ntacth ο 1 e) will be formed, and the conductive layer will be filled in the contact holes to achieve the purpose of internal metal oxide semiconductor transistors and circuits. Refer to Figures 1 to Ί--, Figures 1 to 11 are the metal oxide semiconductor (M0S) transistors that are conventionally used to fabricate an embedded memory on a semiconductor wafer 10, and each of the interposers and regions are interconnected. Line

480653 五、發明說明（2) interconnect ion)的方法示意圖。如圖一所示，半導體晶片1 0之石夕基底1 2表面已定義有一記憶陣列區丨4以及一週邊電路區1 6，且記憶陣列區丨4中包含有一單胞井（ce i i we 11)18’而週邊電路區16中包含有至少一 n型井2 〇以及至少一 Ρ型井2 2，各區域以數個淺溝隔離2 3分隔。習知方法是先於半導體晶片丨〇表面依序形成一閘極氧化層21 #夕日日石夕層24、一多晶石夕化金屬層（p〇iyCide)26 以及由^化石夕所形成的頂保護層（c a ρ 1 a y e r ) 2 8。然後 ί圖，7不:於頂保護層2 8上方形成光阻層3 〇，並利用一黃光製程（lithography)以於光阻層30中同時定義出記憶陣列區1 4以及週邊電路區丨6之閘極位置的圖案 (pattern)。隨後再利用圖案化之光阻層3〇作為一罩幕層 (mask layer) ’進行一蝕刻製程，以去除頂保護層28、多晶石夕化金，層2 6以及多晶矽層2 4，直至閘極氧化層2 1表面’以於冗憶陣列區丨4之單胞井丨8上方形成複數個閘極 3 2 ’並同時於週邊電路區1 6之n型井2 〇和ρ型井2 2上方形成複數個閘極3 4。如圖f所示，接著完全去除頂保護層28上方之光阻層 30 ’並進行一離子佈值製程（i〇n implantat i〇n)，以於閘極32、34兩側之矽基底12表面形成一摻雜區（未顯示），隨後再利用一快速熱處理製程（rapid thermal processing, RTP)使違摻雜區中之摻質（d〇pant)趨入矽基底12，形成各480653 V. Description of the invention (2) Method of interconnect ion). As shown in FIG. 1, a memory array area 丨 4 and a peripheral circuit area 16 have been defined on the surface of the stone eve substrate 12 of the semiconductor wafer 10, and the memory array area 丨 4 includes a single cell well (ce ii we 11 18 ', and the peripheral circuit area 16 includes at least one n-type well 20 and at least one P-type well 22, and each area is separated by several shallow trench isolations 2 3. A conventional method is to form a gate oxide layer 21 in sequence on the surface of the semiconductor wafer. The evening sun stone evening layer 24, a polycrystalline silicon metal layer (p〇iCide) 26, and a ^ fossil evening Top protective layer (ca ρ 1 ayer) 2 8. Then, as shown in FIG. 7, a photoresist layer 3 is formed on the top protective layer 28, and a yellow light process (lithography) is used to simultaneously define the memory array region 14 and the peripheral circuit region in the photoresist layer 30. Pattern of gate position of 6. Subsequently, the patterned photoresist layer 30 is used as a mask layer to perform an etching process to remove the top protective layer 28, polycrystalline gold, layers 26, and polycrystalline silicon layer 24 until The gate oxide layer 2 1 has a plurality of gate electrodes 3 2 ′ formed on the surface of the gate array layer 4 and a single cell well 8 in the redundant array area 丨 4 and simultaneously in the n-type well 2 〇 and ρ-type well 2 in the peripheral circuit area 16 A plurality of gates 3 4 are formed above 2. As shown in FIG. F, the photoresist layer 30 ′ above the top protective layer 28 is completely removed and an ion implantation process is performed to the silicon substrate 12 on both sides of the gate electrodes 32 and 34. A doped region (not shown) is formed on the surface, and then a rapid thermal processing (RTP) process is used to make the dopant in the doped region into the silicon substrate 12 to form each

第6頁 480653 五、發明說明（3) Μ0S電晶體之輕摻雜汲極（Hghtiy doped drain, LDD) 36〇如_圖四所示，隨後在半導體晶片丨〇表面沉積一氮矽層 (未顯示）’並利用一非等向性蝕刻製程來回蝕刻部分之氮石夕層，以於記憶陣列區1 4以及週邊電路區丨6之閘極3 2、3 4 周圍形成一側壁子3 8。然後再進行一離子佈值製程，以形成週邊電路區16之各M0S電晶體的源極（S0Urce )與汲極 (d r a 1 η )。亦即先利用一光阻層完全覆蓋記憶陣列區丨4以及N型井2 0之閘極3 2、3 4，然後利用一賭摻質對p型井2 2 ^面進行換雜以形成一摻雜區42，隨後去除該光阻層，接著再形成另一光阻層使其完全覆蓋記憶陣列區丨4以及p型井2 2上方之問極3 4，並利用一 p型摻質以對週邊電路區1 6 之N型井2 0中進行摻雜’形成摻雜區4 〇，隨後再配合另一快速熱處理製程使各摻雜區4 〇、4 2之摻質趨入矽基底1 2，以形成週邊電路區1 6之各M〇s電晶體之源極與汲極。人嵐^圖五所不，在記憶陣列區1 4之石夕基底1 2表面形成一 φ & t 5 2 阻擔層（Sal icide block，SAB) 44，再於週邊電，區· 16中進行一自行對準金屬矽化物（self-aligned iC1de)製程，以於各源極汲極表面形成一自行對準金道1 46 ’即完成習知嵌入式記憶體之金屬氧化物半導體（M0S)電晶體的製作。Page 6 480653 V. Description of the invention (3) Lightly doped drain (LDD) of MOS transistor 36. As shown in Fig. 4, a silicon nitride layer (not shown) is then deposited on the surface of the semiconductor wafer. (Shown) 'and an anisotropic etching process is used to etch part of the nitrogen stone layer back and forth to form a sidewall 3 8 around the gates 3 2, 3 4 of the memory array region 14 and the peripheral circuit region 6. Then, an ion layout process is performed to form a source (SOrce) and a drain (d r a 1 η) of each MOS transistor in the peripheral circuit region 16. That is, a photoresist layer is used to completely cover the memory array area 4 and the gates 3 2 and 3 4 of the N-type well 20, and then a dopant is used to dope the 2 2 ^ plane of the p-type well 2 to form a The photoresist layer is doped, and then the photoresist layer is removed, and then another photoresist layer is formed so as to completely cover the memory array region 4 and the gate electrode 3 4 above the p-type well 22, and a p-type dopant is used to Doping the N-type well 20 of the peripheral circuit region 16 to form a doped region 4 0, and then cooperated with another rapid heat treatment process to make the dopants of the doped regions 4 0 and 4 2 into the silicon substrate 1 2. To form the source and the drain of each Mos transistor in the peripheral circuit region 16. Ren Lan ^ Figure 5 shows that a φ & t 5 2 salicide block (SAB) 44 is formed on the surface of the Shi Xi substrate 1 2 in the memory array region 14, and then performed in the peripheral circuit, region 16. A self-aligned metal silicide (self-aligned iC1de) process to form a self-aligned gold channel 1 46 'on each source-drain surface to complete the conventional metal-oxide-semiconductor (MOS) circuit of embedded memory. Making of crystals.

第7頁 480653 五、發明說明（4) 蝴的2 =人式5憶體之金屬氧化物半導體（_)電晶 ί之轉接入ί ό=於半導體晶片10上製作該欲入式記憶 f ί :ΐ 連線。如圖六所示，先於半導體晶 :一 ί:Ϊ ’例如一二氧化矽層。然後再利 ^ 丁%ΪΛ程於介電層48中定義轉接介層洞（landi^ & ^〇16)50及接觸洞（(：〇111^0：1;1：1〇16)513、5113，如圖七所示 '其中接觸洞51a是連接M0S電晶體34之閘極/而接觸洞 5 1 b是連接另一 M0S電晶體之源極或汲極，因此兩者並不位於同一垂直剖面而是前後交錯的。Page 7 480653 V. Description of the invention (4) Butterfly 2 = human-type 5 memory body metal-oxide semiconductor (_) electric crystal ί transfer access ί = making the desired memory on the semiconductor wafer 10 f ί: ΐ Connect. As shown in FIG. 6, before the semiconductor crystal: a: 例如 For example, a silicon dioxide layer. Then, ^ %% ΪΛ 程 is defined in the dielectric layer 48 to define a via hole (landi ^ & ^ 〇16) 50 and a contact hole ((: 〇111 ^ 0: 1; 1: 1: 110)) 513 , 5113, as shown in Figure 7. 'Where the contact hole 51a is the gate / connected to the M0S transistor 34 and the contact hole 5 1b is connected to the source or the drain of another M0S transistor, so the two are not located in the same The vertical profile is staggered back and forth.

如圖八所示，於矽基底12上依序形成_黏著層（glue layer)或阻障層（barrier layer)5 2和一金屬層54，並填入轉接介層洞5 0及接觸洞5 1 a、5 1 b。其中黏著層或阻障層 5 2和金屬層5 4可分別由鈦或氮鈦層以及鎢金屬層所構成: 隨後如圖九所示，利用介電層4 8作為蝕刻停止層來對金屬層5 4進行一平坦化製程，以分別形成一轉接介層5 5及接觸插塞56a、56b。接著如圖十所示，於半導體晶片1〇表面形成一金屬導線層5 7，隨後於金屬導線層5 7表面形成一圖案化之光阻層5 8以定義出各金屬導線圖案。其中金屬導線層 5 7是由鋁、銅或鋁銅合金所構成。最後如圖十一所示，進行一#刻製程以去除未被光阻層58覆蓋之金屬導線層57，以形成分別與轉接介層55以及接觸插塞56a、56b連接之金屬導線5 9 a、5 9 b。其中金屬導線5 9 b可電連接Μ 0 S電晶體3 4 之閘極以及另一 M0S電晶體之源極或汲極，並與接觸插塞As shown in FIG. 8, a glue layer or a barrier layer 5 2 and a metal layer 54 are sequentially formed on the silicon substrate 12, and the via hole 50 and the contact hole are filled in. 5 1 a, 5 1 b. The adhesion layer or the barrier layer 52 and the metal layer 54 can be composed of a titanium or nitrogen-titanium layer and a tungsten metal layer, respectively. Subsequently, as shown in FIG. 9, the metal layer is made of the dielectric layer 48 as an etch stop layer. A flattening process is performed to form a transfer interposer 55 and contact plugs 56a and 56b, respectively. Next, as shown in FIG. 10, a metal wire layer 57 is formed on the surface of the semiconductor wafer 10, and then a patterned photoresist layer 58 is formed on the surface of the metal wire layer 57 to define each metal wire pattern. The metal wire layer 57 is composed of aluminum, copper, or an aluminum-copper alloy. Finally, as shown in FIG. 11, a # engraving process is performed to remove the metal wire layer 57 not covered by the photoresist layer 58, so as to form metal wires 59 that are respectively connected to the via 55 and the contact plugs 56 a and 56 b. a, 5 9 b. The metal wire 5 9 b can be electrically connected to the gate of the M 0 S transistor 3 4 and the source or sink of another M0S transistor, and contact the plug.

第8頁 480653 五、發明說明（5) 56a、56b共同組成〆區域内連線。然而，在上述所揭露之習知製作嵌入式記憶體方法中’為了同時形成週邊電路區與記憶陣列區之閘極，並兼顧週邊電路區之電性要求，因此必須使多晶矽化金屬層直接沉積在摻雜多晶矽層上方，以降低週邊電路區之閘極結構的電阻，並利用一自行對準金屬矽化物（s a丨i c i d e )製程’於各源極、汲極表面形成一自行對準矽化物層，以降低其上之接觸介面電阻。一般而言，利用沉積方式形成的多晶矽化金屬層具有較自行對準金屬矽化物層更大的電阻值（resistivity)，因此，該週邊電路區中由多晶矽化金屬層與頂保遵層構成之閘極結構，其電性行為與標準週邊電路區中由自行對準矽化物層構成之閘極結構有所差異，導致邏輯電路所建立之資料庫（cell library)無法適用。其次，在以習知技術完成嵌入式記憶體之金屬氧化物半導體（M0S)電晶體的製作之後，該嵌入式記憶體之轉接介層與區域内連線必須分別製作，因此習知製程至少需要使曰用四次光軍，不但使製程變得較為複雜而且亦較耗費成本。發明概述 >5 Μ ^明之主要目的在於提供一種整合嵌入式記憶體以 f接；I層與帶接觸的製作方法，以簡化製程的複雜，盥 ’並能有效減少帶接觸在記憶體中佔據空間，=二 J 運而縮Page 8 480653 V. Description of the invention (5) 56a and 56b together form a connection within the area. However, in the conventional method for manufacturing embedded memory disclosed above, 'in order to form the gates of the peripheral circuit area and the memory array area at the same time and take into account the electrical requirements of the peripheral circuit area, it is necessary to directly deposit a polycrystalline silicon silicide layer. Above the doped polycrystalline silicon layer to reduce the resistance of the gate structure of the peripheral circuit region, and a self-aligned metal silicide (sa 丨 icide) process is used to form a self-aligned silicide on the surface of each source and drain. Layer to reduce the contact interface resistance thereon. Generally speaking, the polysilicon metallization layer formed by the deposition method has a greater resistance than the self-aligned metal silicide layer. Therefore, the peripheral circuit region is composed of the polysilicon metallization layer and the top protection compliance layer. The electrical structure of the gate structure is different from that of a gate structure composed of a self-aligned silicide layer in a standard peripheral circuit area, which makes the cell library created by the logic circuit unsuitable. Secondly, after the fabrication of the metal oxide semiconductor (MOS) transistor of the embedded memory is completed by the conventional technology, the interposer of the embedded memory and the interconnects in the area must be made separately, so the conventional manufacturing process is at least The need to use four light troops not only complicates the process but also costs more. SUMMARY OF THE INVENTION The main purpose of the 5M is to provide a manufacturing method that integrates the embedded memory to connect the I layer and the tape to simplify the complexity of the process, and can effectively reduce the occupation of the tape in the memory. Space, = two J shrink

480653 五、發明說明（6) 小單位記憶體的體積。本發明係提供一種整合嵌入式記憶體（embedded memory)以及轉接介層（landing via)與帶接觸（strip contact)的製作方法。該方法是先該半導體晶片表面定義出一記憶陣列（memory array)區以及一週邊電路 (periphery Circuits )區，接著於該記憶陣列區以及該週邊電路區上分別形成複數個閘極（ga t e )以及輕摻雜没極 (LDD)。隨後於該記憶陣列區之各該閘極表面覆/蓋'一/ 層’並於該週邊電路區上之各該閘極周圍形成側壁子 (spacer)，然後於該半導體晶片表面形成一介電$，並該記憶陣列區以及該週邊電路區上方之介電層中八來複數個轉接介層洞（landing via hole)以及帶接觸、、同 (strip contact hole)，最後於各該洞中填滿一，以同時形成各該轉接介層以及各該帶接觸。 ^ 本發明是將巍入式記憶體製程與後續形成轉人帶接觸製程進行整合，因此可大幅簡化製程的複雜二二本。而且，本發明係將週邊電路區的帶接觸中連拯^= 源極或汲極的部分，合併成為一條導線，因此可以=^ ς 小帶接觸佔據的空間，提高積極度（integrati〇n)。穴^細發明之詳細說明480653 V. Description of the invention (6) Volume of small unit memory. The invention provides a method for manufacturing an integrated embedded memory, a landing via, and a strip contact. In the method, a memory array region and a peripheral circuit region are defined on the surface of the semiconductor wafer, and then a plurality of gates (ga te) are formed on the memory array region and the peripheral circuit region, respectively. And lightly doped diode (LDD). Subsequently, each gate surface of the memory array area is covered / covered with a layer, and a spacer is formed around each gate on the peripheral circuit area, and then a dielectric is formed on the surface of the semiconductor wafer. $, And there are several land via holes and strip contact holes in the dielectric layer above the memory array area and the dielectric layer above the peripheral circuit area, and finally in each of the holes Fill one to form each of the interposer and each of the tape contacts simultaneously. ^ The present invention integrates the in-memory memory system process and the subsequent formation of the transfer belt contact process, which can greatly simplify the complexity of the process. In addition, the present invention combines the parts of the belt contact of the peripheral circuit area with the source or the drain, and merges them into a single wire, so that the space occupied by the small band contact can increase the positiveness (integrati) . Acupoint ^ Detailed description of the invention

第10頁 480653 五、發明說明（7) 請參考圖十二至圖二十六，圖十二至圖二十六為本發明於一半導體晶片60上同時製作嵌入式記憶體（embedded memory)之轉接介層（ianding via)與帶接觸（strip con tact)的方法。如圖十二所示，半導體晶片60之矽基底 7 2表面已定義有一記憶陣列區6 2以及一週邊電路區6 4，且 3己憶陣列區62中包含有一單胞井66，而週邊電路區64中包含有一 N型井6 8以及一 p型井7 0，各區域以數個淺溝隔離6 i 分隔。本發明方法疋先於半導體晶片6 0表面依序形成一介電層 7 4: —未摻雜多晶矽層76以及一介電層78。然後如圖^三所示，在週邊電路區64上方形成一罩幕層8〇，並對記憶^ 列區6 2上方之未摻雜多晶矽層7 6進行一 N型離子佈植製程，以使記憶陣列區6 2上方之未摻雜多晶石夕層7 6形成 N摻雜多晶矽層82。恥馬接著如圖十 .匕陣：區62上方之…78’並向下飯刻摻雜多晶石夕r己 2 直至原未推雜多晶石夕層7 6之她厘/¾:沾 ψ.,, _〇埃如圖十五；；厂: = 〜 6 4上方的罩幕層8 〇之後，接著 *凡k邊電路區成-金屬石夕化物層84以降低摻餘ί ^體晶片60表面依序形阻，一氮氧化矽層8 6作為抗反^ = Β曰矽層8 2的接觸介面電層以及一光阻層90。 w續、一氮石夕層88作為保護 480653 、發明說明（幻然後進行一黃光製程，以於記憶陣列區6 2之單胞井6 6 ^方的光阻層90中定義出複數個閘極91的圖案，隨後利用，阻層9 〇的圖案當作硬罩幕，以蝕刻記憶陣列區6 2上方之氮石夕層8 8、氮氧化矽層8 6、金屬矽化物層8 4以及摻雜多晶碎層+81 ’直至介電層7 4表面，以於記憶陣列區6 2上形成各 Μ 〇 S% a曰體之閘極9 1。同時（i n _ s i t u )钱刻週邊電路區w上方之氮石夕層8 8、氮氧化矽層8 6以及金屬矽化物層8 4，直至介電層78表面，如圖十六所示。隨後如圖十七所示，進行一離子佈植製程，以形成記憶陣列區62中之各M0S電晶體的輕摻雜汲極（LDD) 92，並去除光1^且層9 0。隨後如圖十八所示，在去除完光阻層9 〇之後’接著去除週邊電路區6 4上方之介電層78，並於^導體晶1 60表面形成一光阻層94以及一氮氧化矽層（未顯示）二為抗反射層。然後如圖十九所示，進行一黃光製程，以於週邊電路區64之N型井68以及P型井70上方的光2 中，、分別定義出複數個閘極的圖案。之後利用光阻層ga4的圖案當作硬罩幕來姓刻週邊電路區6 4上方之未摻雜多晶石夕層 76’直至介電層74表面，以於週邊電路區64上形成 &個 MOS電晶體之閘極93、95。接著如圖二十所示，進行一離子佈植製程，形成週邊電路區64中之各MOS電晶體之輕摻雜汲極（LDD) 92，隨後如圖二十一所示，在去除完光阻層94之後，於半導體= 曰曰片Page 10 480653 V. Description of the invention (7) Please refer to FIG. 12 to FIG. 26. FIG. 12 to FIG. 26 are examples of the invention for simultaneously manufacturing embedded memory on a semiconductor wafer 60. Method for transferring vias and strip con tact. As shown in FIG. 12, a surface of the silicon substrate 7 2 of the semiconductor wafer 60 has a memory array region 62 and a peripheral circuit region 64 defined therein, and the memory array region 62 includes a single cell well 66 and peripheral circuits. The area 64 includes an N-type well 68 and a p-type well 70, and each area is separated by several shallow trench isolations 6i. The method of the present invention first sequentially forms a dielectric layer 7 4 before the surface of the semiconductor wafer 60: an undoped polycrystalline silicon layer 76 and a dielectric layer 78. Then, as shown in FIG. 3, a mask layer 80 is formed over the peripheral circuit region 64, and an N-type ion implantation process is performed on the undoped polycrystalline silicon layer 76 above the memory region 62, so that An undoped polycrystalline silicon layer 76 above the memory array region 62 forms an N-doped polycrystalline silicon layer 82. The shame horse is then as shown in Figure 10. The dagger array: ... 78 'above the area 62 and downwardly doped with polycrystalline spheroids r 2 until the original polycrystalline spheric layer 7 6 is not pushed. / ¾: ψψ . ,, _〇Angle as shown in Figure 15; Factory: = ~ 6 4 After the mask layer 8 0, then * Where the k-side circuit area is formed into a metal oxide layer 84 to reduce the doped bulk wafer The 60 surface is sequentially shaped, and a silicon oxynitride layer 86 is used as an anti-reflection layer ^ = B, which is a contact interface electrical layer of the silicon layer 82 and a photoresist layer 90. Continuing, a azite layer 88 is used as protection 480653. Description of the invention (Then, a yellow light process is performed to define a plurality of gates in the photoresist layer 90 of the single cell well 6 6 ^ square in the memory array area 62. The pattern of the pole 91 is subsequently used, and the pattern of the resist layer 90 is used as a hard mask to etch the nitrogen stone layer 8 8, the silicon oxynitride layer 8 6, the metal silicide layer 8 4 above the memory array region 62, and Doped polycrystalline debris layer +81 'to the surface of the dielectric layer 74, so as to form each MOS gate electrode 91 on the memory array region 62. At the same time (in situ) the peripheral circuit is engraved with money Nitrogen oxide layer 88, silicon oxynitride layer 86, and metal silicide layer 84 above region w, up to the surface of dielectric layer 78, as shown in FIG. 16. Subsequently, as shown in FIG. 17, an ion is performed. The implantation process is performed to form a lightly doped drain (LDD) 92 of each MOS transistor in the memory array region 62, and remove light 1 ^ and layer 90. Then, as shown in FIG. 18, the photoresist is removed. After layer 90, the dielectric layer 78 above the peripheral circuit area 64 is removed, and a photoresist layer 94 and a silicon oxynitride layer are formed on the surface of the conductor crystal 160. (Shown) 2 is an anti-reflection layer. Then, as shown in FIG. 19, a yellow light process is performed to define a plurality of light beams 2 in the peripheral circuit area 64 of the N-type well 68 and the P-type well 70 respectively The gate pattern. The pattern of the photoresist layer ga4 is then used as a hard cover to engrave the undoped polycrystalline silicon layer 76 'above the peripheral circuit area 64 to the surface of the dielectric layer 74 to the peripheral circuit area. Gates 93 and 95 of & MOS transistors are formed on 64. Then, as shown in FIG. 20, an ion implantation process is performed to form a lightly doped drain (LDD) of each MOS transistor in the peripheral circuit area 64. ) 92, as shown in FIG. 21, after the photoresist layer 94 is removed, the semiconductor =

第12頁 480653 五、發明說明（9) 6 0表面形成一氮矽層9 7，並覆蓋於各閘極9 3、9 5表面。然後如圖'一十一所示’利用一光阻層（未顯示）以及一黃光程來定義罩幕圖案（mask pattern)，以餘刻週邊電路區上方各閘極9卜9 3、9 5周圍的氮矽層9 7，形成一側壁子 9 6。隨後並進行一離子佈植製程，以形成週邊電路區6 4上之各Μ 0 S電晶體的源極9 8與沒極1 0 0。在形成完週邊電路區上6 4之各M0S電晶體的源極98與汲極1 0 0之後，接著如圖二十三所示，於半導體晶片6 〇表面形成一由始（Co)所構成金屬層（未顯示），且該金屬層係覆蓋於週邊電路區6 4上之各源極9 8、汲極1 0 0以及閘極 9 3、9 5表面之上。隨後進行一溫度範圍為4 〇 0°c〜6 〇〇°c且加熱時間為1 0〜5 0秒之第一快速熱處理（rtP )製程，以使週邊電路區6 4上之各源極9 8、汲極1 0 0以及閘極9 3、9 5表面形成一自行對準矽化物層1 〇 2。然後利用一濕蝕刻來去除於半導體晶片60表面未反應之該金屬層。最後再進行一溫度範圍為6 0 0°C〜8 0 〇°C且加熱時間為1 〇〜5 0秒之第二快速熱處理（RTP)製程，以將自行對準矽化物層1 〇2中的 Co θί以及CoS反應成電阻較低的c〇S i 2。其中該鈷（Co)金屬層亦可取代為一鈦（Ti)、鎳（Ni)或鉬（Mo)等的金屬層。如圖二十四所示，於半導體晶片60表面依序形成一介電層1 0 4以及一光阻層1 〇 6。然後進行一黃光製程，以於光阻層1 0 6中定義出複數個轉接介層以及複數個帶接觸的圖Page 12 480653 V. Description of the invention (9) 60 A nitrogen silicon layer 9 7 is formed on the surface and covers the surface of each gate electrode 9 3, 9 5. Then as shown in '11', a photoresist layer (not shown) and a yellow light path are used to define the mask pattern, so that the gates around the peripheral circuit area are around 9 and 9 3, 9 5 The silicon nitride layer 9 7 forms a sidewall member 9 6. Subsequently, an ion implantation process is performed to form a source 98 and a source 100 of each M 0 S transistor on the peripheral circuit area 64. After forming the source 98 and the drain 100 of each M0S transistor on the peripheral circuit area 64, then as shown in FIG. 23, a semiconductor substrate 60 is formed with a co (Co) surface. A metal layer (not shown), and the metal layer covers the surface of each of the source electrode 98, the drain electrode 100, and the gate electrode 9 3, 9 5 on the peripheral circuit area 64. Subsequently, a first rapid thermal processing (rtP) process is performed in a temperature range of 4,000 ° C to 600 ° C and a heating time of 10 to 50 seconds, so that each source electrode 9 on the peripheral circuit region 64 is 8. The surface of the drain electrode 100 and the gate electrode 9 3, 9 5 forms a self-aligned silicide layer 102. A wet etching is then used to remove the unreacted metal layer on the surface of the semiconductor wafer 60. Finally, a second rapid thermal processing (RTP) process is performed in a temperature range of 600 ° C to 800 ° C and a heating time of 100 to 50 seconds to align the self-alignment in the silicide layer 102. Co θί and CoS react to a lower resistance coS i 2. The cobalt (Co) metal layer may be replaced with a metal layer such as titanium (Ti), nickel (Ni), or molybdenum (Mo). As shown in FIG. 24, a dielectric layer 104 and a photoresist layer 106 are sequentially formed on the surface of the semiconductor wafer 60. Then, a yellow light process is performed to define a plurality of transfer vias and a plurality of contact patterns in the photoresist layer 106.

第13頁 480653 五案 104 接發明說明〇〇) 接著利用光阻層1 0 6的圖案以於記憶陣列區6 2上方之 …介層洞（landing via hole) 64上方之介電層1〇4中形成複數 contact hole) 110，如圖二十連接閘極95與另一 M0S電晶體之洞1 1 0與閘極9 5是位於不同的垂六所示，於各轉接介層洞1 〇 8以導電層1 1 2，以同時形成各轉接 1 16〇當作硬罩幕來蝕刻介電層介電層104中形成複數個轉 108，並同時於週邊電路區個帶接觸洞（strip 五所示。由於帶接觸係電源極或汲極，因此帶接觸直剖面上。最後如圖二十及各帶接觸洞1 1 〇中填滿一介層1 1 4以及各帶接觸相較於習知製作嵌入式記憶體之轉接介盥 j :本發明整合了喪入式記憶體以及轉接介層製私，因此可以同時形成各轉接介層與帶接觸，之，簡化製程的複雜度與成本，而且本發明戶二大 ^以一導線來連接相鄰的閘極與源極或汲 ▼接觸 =縮”接觸佔據的空間，…減少大積，提南積極度（integration)。几件的體 I α ^ i所述僅為本發明之較佳實施例，凡依本称ΒΒ + 圍所做之均等變化與修飾，皆月申請盍乾圍。知月專利之涵Page 13 480653 Five cases 104 followed the description of the invention 〇〇) Then use the pattern of the photoresist layer 10 6 on the memory array region 6 2 above ... dielectric via (landing via hole) 64 dielectric layer 104 A plurality of contact holes 110 are formed in FIG. 20, as shown in FIG. 20. The hole 1 1 0 and the gate 9 5 connecting the gate 95 and another M0S transistor are located in different vertical six, and are shown in each of the via holes 1 〇 8 The conductive layer 1 12 is used to simultaneously form each transition 116 as a hard mask to etch the dielectric layer 104 into the dielectric layer 104 to form a plurality of revolutions 108, and simultaneously to make contact holes in the peripheral circuit area. Figure 5. Because the belt contact is the power or drain electrode, the belt contact is on a straight section. Finally, as shown in Fig. 20, a contact layer 1 1 4 is filled with a dielectric layer 1 1 4 and each belt contact is compared with the conventional one. Knowing the transition interface for making embedded memory: The present invention integrates funnel-type memory and transition interface to make private, so it is possible to form each transition interface and belt contact at the same time, which simplifies the complexity of the process And cost, and the present invention uses two wires to connect the adjacent gate and source or sink The contact occupies the space occupied by the contact,… reduces the large product and raises the integration. The several pieces of body I α ^ i are only the preferred embodiments of the present invention. All equal changes and modifications have been made, and all have applied for Qianganwei every month.

第14頁 480653 圖式簡單說明圖示之簡單說明圖一至圖十一為習知製作嵌入式記憶體以及轉接介層與帶接觸的方法示意圖圖十二至圖二十六為本發明製作嵌入式記憶體之轉接介層與帶接觸的方法示意圖圖示之符號說明 10 半導體晶片 12 ^夕基底 14 記憶陣列區 16 週邊電路區 18 單胞井 20 N型井 21 閘極氧化層 22 P型井 23 淺溝隔離 24 多晶矽層 26 多晶石夕化金屬層 28 頂蓋層 30 > 58 光阻層 32> 34 閘極 36 輕摻雜汲極 38 40 44 46 42 側壁子摻雜區金屬石夕化物阻擋層自行對準金屬石夕化物層Page 14 480653 Schematic illustrations of the diagrams Brief description of the diagrams Figures 1 to 11 are schematic diagrams of the conventional methods for making embedded memory and the contact between the interposer and the tape. Figures 12 to 26 are made according to the present invention. Of the method of contacting the interposer and the tape of the memory with a schematic illustration of the symbols 10 semiconductor wafer 12 substrate 14 memory array area 16 peripheral circuit area 18 cell well 20 N-type well 21 gate oxide layer 22 P-type Well 23 Shallow trench isolation 24 Polycrystalline silicon layer 26 Polycrystalline metallized layer 28 Top cap layer 30 > 58 Photoresist layer 32 > 34 Gate 36 Lightly doped drain 38 40 44 46 42 Side wall doped region metal stone The metal oxide barrier layer is self-aligned to the metal stone metal oxide layer

48 介電層 50 轉接介層洞 51a、 51b 接觸洞 52 阻障層 54 金屬層 55 轉接介層第15頁 480653 圖式簡單說明 5 6a、 •56b 接觸插塞 57 金屬導線層 5 9a、 •59b 金属導線 60 半導體晶片 62 記憶陣列區 64 週邊電路區 72 矽基底 66 單胞井 68 N型井 70 P型井 96 側壁子 9卜 93^ 95 閘極 92 輕摻雜汲極 98 源極 100 汲極 74' 78 ^ 104 介電層 76 未摻雜多晶 ί夕層 80 罩幕層 82 摻雜多晶矽層 84 金屬矽化物層 86 氮氧化矽層 88 > 97 氮矽層 9 0> 94> 106 光阻層 102 動對準矽化物層 108 轉接介層洞 110 帶接觸洞 112 金屬層 114 轉接介層 116 帶接觸48 Dielectric layer 50 Via via 51a, 51b Contact via 52 Barrier layer 54 Metal layer 55 Via via page 15 480653 Simple illustration 5 6a, 56b Contact plug 57 Metal wire layer 5 9a, • 59b metal wire 60 semiconductor wafer 62 memory array area 64 peripheral circuit area 72 silicon substrate 66 cell well 68 N-type well 70 P-type well 96 sidewall 9b 93 ^ 95 gate 92 lightly doped drain 98 source 100 Drain 74 '78 ^ 104 Dielectric layer 76 Undoped polycrystalline layer 80 Mask layer 82 Doped polycrystalline silicon layer 84 Metal silicide layer 86 Silicon oxynitride layer 88 > 97 Nitrogen silicon layer 9 0 > 94 > 106 Photoresist layer 102 Dynamically aligned silicide layer 108 Via via 110 With contact hole 112 Metal layer 114 Via 116 With contact

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Claims

480653 六、申請專利範圍、 1· 一種同時製作散入式記憶體（embedded memory)之轉接介層（landing via)與帶接觸（strip contact)的方法，該製作方法包含有下列步驟： k供一半導體晶片’且该半導體晶片之秒基底 (si 1 icon substrate )表面已定義有一記憶陣列區（mem〇ry array area)以及一週邊電路區（periphery circuits region)；於該記憶陣列區以及該週邊電路區上分別形成複數個閘極（gate)，且各該閘極周圍均形成有一輕摻雜汲極 (lightly doped drain, LDD)；於該半導體晶片表面形成一氮矽層，並覆蓋於各該閘極表面；進行一第一蝕刻製程，去除該週邊電路區上之部份的該氮石夕層，以於該週邊電路區中之各該閘極周圍形成一側壁子(spacer)；於該半導體晶片表面依序形成一第一介電層以及一第一光阻層；進行一第一黃光製程，以於該第一光阻層中定義出複數個轉接介層以及複數個帶接觸的圖案（pattern); 利用該第一光阻層的圖案當作硬罩幕（hard mask)，蝕刻該第一介電層，以於該記憶陣列區上方之第一介電層中幵y成複數個轉接介層洞（landing via hole)，並同時於 ”亥週邊電路區上方之第一介電層中形成複數個帶接觸洞 (strip contact hole)；以及480653 VI. Scope of patent application 1. A method for simultaneously manufacturing a landing via and a strip contact of an embedded memory. The manufacturing method includes the following steps: A semiconductor wafer 'and the surface of the semiconductor wafer's si 1 icon substrate has a memory array area and a peripheral circuits region defined on the surface of the semiconductor wafer; the memory array area and the periphery A plurality of gates are formed on the circuit area, and a lightly doped drain (LDD) is formed around each of the gates; a silicon nitrogen layer is formed on the surface of the semiconductor wafer and covers each A surface of the gate; performing a first etching process to remove a part of the nitrogen stone layer on the peripheral circuit region so as to form a spacer around each of the gates in the peripheral circuit region; A first dielectric layer and a first photoresist layer are sequentially formed on the surface of the semiconductor wafer; a first yellow light process is performed to define a plurality of revolutions in the first photoresist layer. A dielectric layer and a plurality of contact patterns; using the pattern of the first photoresist layer as a hard mask, the first dielectric layer is etched so as to be first on the memory array region;幵 y is formed in the dielectric layer into a plurality of via vias, and at the same time a plurality of strip contact holes are formed in the first dielectric layer above the peripheral circuit region; and

480653 六、申請專利範圍於各該轉接介層洞以及各該帶接觸洞中填滿一導電層，以同時形成各該轉接介層以及各該帶接觸。 2. 如申請專利範圍第1項之方法，其中於該記憶陣列區以及該週邊電路區上形成各該閘極，且各該閘極周圍均形成有一輕摻雜汲極（LDD)的方法係包含有下列步驟：於該半導體晶片表面依序形成一第二介電層、一未摻雜多晶石夕（undoped polysilicon)層以及一第三介電層；對該記憶陣列區上方之該未摻雜多晶矽層進行一第一離子佈植製程，以使該記憶陣列區上方之該未摻雜多晶矽層形成為一摻雜多晶矽層；進行一第二蝕刻製程，以完全去除該記憶陣列區上方之該第三介電層，並蝕刻該摻雜多晶矽層至一預定深度；於該半導體晶片表面依序形成一金屬矽化物（s i 1 i c i de ) 層、一保護層以及一第二光阻層；進行一第二黃光製程，以於該記憶陣列區上方之該第二光阻層中定義出複數個閘極的圖案；利用該第二光阻層的圖案當作硬罩幕，以蝕刻該記憶陣列區上方之該保護層、該金屬矽化物層以及該摻雜多晶矽層，直至該第二介電層表面，並同時蝕刻該週邊電路區上方之該保護層以及該金屬矽化物層，直至該第三介電層表面；進行一第二離子佈植製程，以於該記憶陣列區中之各該閘極周圍形成一輕摻雜汲極（LDD);480653 6. Scope of patent application Fill each conductive via hole and each tape contact hole with a conductive layer to form each of the via layer and each tape contact at the same time. 2. The method according to item 1 of the scope of patent application, wherein each gate is formed on the memory array region and the peripheral circuit region, and a lightly doped drain (LDD) is formed around each gate. The method comprises the following steps: sequentially forming a second dielectric layer, an undoped polysilicon layer, and a third dielectric layer on the surface of the semiconductor wafer; The doped polycrystalline silicon layer is subjected to a first ion implantation process so that the undoped polycrystalline silicon layer above the memory array region is formed as a doped polycrystalline silicon layer; a second etching process is performed to completely remove the memory array region. The third dielectric layer, and etching the doped polycrystalline silicon layer to a predetermined depth; sequentially forming a si 1 ici de layer, a protective layer, and a second photoresist layer on the surface of the semiconductor wafer Performing a second yellow light process to define a plurality of gate patterns in the second photoresist layer above the memory array region; using the pattern of the second photoresist layer as a hard mask to etch The The protective layer, the metal silicide layer, and the doped polycrystalline silicon layer over the array region are recalled to the surface of the second dielectric layer, and the protective layer and the metal silicide layer above the peripheral circuit region are simultaneously etched until A surface of the third dielectric layer; performing a second ion implantation process to form a lightly doped drain (LDD) around each of the gates in the memory array region;

第18頁 480653 六、申請專利範圍去除該第二光阻層以及該週邊電路區上方之該第三介電層；於該半導體晶片表面形成一第三光阻層；進行一第三黃光製程，以於該週邊電路區上方之該第三光阻層中定義出複數個閘極的圖案；利用該第三光阻層的圖案當作硬罩幕，蝕刻該週邊電路區上方之該未摻雜多晶矽層直至該第二介電層表面，以於該週邊電路區上形成各該閘極；進行一第三離子佈植製程，以於該週邊電路區中之各該閘極周圍形成一輕摻雜汲極（LDD);以及去除該第三光阻層。 3. 如申請專利範圍第2項之方法，其中該第二介電層係由二氧化石夕（silicon dioxide， SiO 2)所構成，用來作為各該閘極的閘極氧化層。 4. 如申請專利範圍第2項之方法，其中該預定深度約略為該未摻雜多晶矽層之總厚度的一半。 5. 如申請專利範圍第2項之方法，其中該保護層係由一氣石夕化合物所構成，且該保護層與該金屬石夕化物層之間另包含有一氮氧化石夕（silicon-oxy-nitride， SiOxN y)層，用來做為一抗反射層（anti-reflection coating, ARC)。Page 18 480653 VI. Patent application scope Remove the second photoresist layer and the third dielectric layer above the peripheral circuit area; form a third photoresist layer on the surface of the semiconductor wafer; perform a third yellow light process A pattern of a plurality of gates is defined in the third photoresist layer above the peripheral circuit area; using the pattern of the third photoresist layer as a hard mask, the non-doped layer above the peripheral circuit area is etched A heteropolysilicon layer up to the surface of the second dielectric layer to form each of the gates on the peripheral circuit area; a third ion implantation process is performed to form a light around each of the gates in the peripheral circuit area Doping the drain (LDD); and removing the third photoresist layer. 3. The method according to item 2 of the patent application, wherein the second dielectric layer is composed of silicon dioxide (SiO 2) and is used as a gate oxide layer of each gate. 4. The method according to item 2 of the patent application, wherein the predetermined depth is approximately half the total thickness of the undoped polycrystalline silicon layer. 5. The method according to item 2 of the patent application, wherein the protective layer is composed of a gas-stone compound, and a silicon-oxy-silicon oxide (silicon-oxy- The nitride (SiOxNy) layer is used as an anti-reflection coating (ARC).

第19頁 480653 六、申請專利範圍 6. 如申請專利範圍第2項之方法，其中在該半導體晶片表面形成該第三光阻層之前’另可先於該半導體晶片表面形成一氮氧化矽（Si 0xNy)層當作抗反射層（ARC)。 7. 如申請專利範圍第6項之方法，其中在去除該第三光阻層之後，亦須去除形成於該第三光阻層下方之該氮氧化 ί夕層。 8. 如申請專利範圍第1項之方法，其中在該週邊電路區中之各該閘極的周圍形成各該側壁子之後，該方法另須進行一第四離子佈植製程，以於該週邊電路區中之各該閘極周圍形成一源極（s 〇 u r c e )與沒極（drain)。 9. 如申請專利範圍第8項之方法，其中在形成完各該源極與汲極之後，該方法另包含有下列步驟：於該半導體晶片表面形成一金屬層，且該金屬層覆蓋於該週邊電路區上之各該源極、汲極以及閘極表面之上；進行一第一快速熱處理（rapid thermal process, RTP)製程；去除於該半導體晶片表面未反應之該金屬層；以及進行一第二快速熱處理（RTP)製程。 1 0.如申請專利範圍第9項之方法，其中該金屬層係由鈷 (cobalt，Co)、鈦（titanium，Ti)、錄（nickel, Ni)或钥Page 19, 480653 6. Application for Patent Scope 6. If the method of Patent Application Scope 2 is applied, before the third photoresist layer is formed on the surface of the semiconductor wafer, a silicon oxynitride may be formed before the surface of the semiconductor wafer ( The Si 0xNy) layer is used as an anti-reflection layer (ARC). 7. If the method of claim 6 is applied, after the third photoresist layer is removed, the oxynitride layer formed under the third photoresist layer must also be removed. 8. If the method of applying for the first item of the patent scope, wherein after forming the sidewalls around each of the gate electrodes in the peripheral circuit area, the method must further perform a fourth ion implantation process on the periphery A source (source) and a drain (drain) are formed around each of the gates in the circuit area. 9. The method according to item 8 of the patent application, wherein after forming each of the source and drain electrodes, the method further comprises the following steps: forming a metal layer on the surface of the semiconductor wafer, and the metal layer covering the Performing a first rapid thermal process (RTP) on each of the source, drain, and gate surfaces on the peripheral circuit area; removing the unreacted metal layer on the surface of the semiconductor wafer; and performing a The second rapid thermal processing (RTP) process. 10. The method according to item 9 of the scope of patent application, wherein the metal layer is made of cobalt (Co), titanium (Ti), nickel (Ni) or nickel

第20頁 480653 六、申請專利範圍 (molybdenum，Mo)所構成 1 1. 一種同法，該製作提供一義有一記憶包含有至少含有至少一間極極表該氣壁子於該記，且各於該半面；進行一矽層，時製作嵌入式記憶體之轉接介層與帶接觸的方方法包含有下列步驟：半導體晶片，該半導體晶片之矽基底表面已定陣列區以及一週邊電路區’且該記憶陣列區中一單胞井（cell_well)’而該週邊電路區中包 N型井（N-well)以及至少一 P型井（P-well); 憶陣列區以及該週邊電路區上分別形成複數個該閘極周圍均形成有一輕摻雜汲極（LDD); 導體晶片表面形成一氮矽層，並覆蓋於各該閘第一蝕刻製程，去除該週邊電路區上之部份的以於該週邊電路區中之各該閘極周圍形成一側於該半導體晶片表面依序形成一第一介電層以及一第光阻層；進行一第一黃光製程，以於該第一光阻層中定義出複層以及複數個帶接觸的圖案；第一光阻層的圖案當作硬罩幕，蝕刻該第一介該記憶陣列區上方之第一介電層中形成複數個，並同時於該週邊電路區上方之第一介電層中帶接觸洞；以及轉接介層洞以及各該帶接觸洞中填滿一導電數個轉接介利用該電層，以於轉接介層洞形成複數個於各該 ΦPage 20 480653 VI. Composition of patent application scope (molybdenum, Mo) 1 1. An identical method, the production provides a meaning and a memory containing at least one pole table, the air wall in the record, and each in the record Half surface; a method for making a silicon layer, and making an interposer and an interposer of an embedded memory includes the following steps: a semiconductor wafer, the silicon substrate surface of which has an array region and a peripheral circuit region '; A cell_well in the memory array region and an N-well and at least one P-well in the peripheral circuit region; the memory array region and the peripheral circuit region are respectively A lightly doped drain (LDD) is formed around a plurality of gates; a silicon nitride layer is formed on the surface of the conductor wafer and covers the first etching process of each gate to remove parts of the peripheral circuit area. A side is formed around each of the gate electrodes in the peripheral circuit area to sequentially form a first dielectric layer and a first photoresist layer on the surface of the semiconductor wafer; a first yellow light process is performed for the first light The resist layer defines a multiple layer and a plurality of patterns with contact; the pattern of the first photoresist layer serves as a hard mask, and a plurality of first dielectric layers above the memory array region are etched to form a plurality of layers, and At the same time, a contact hole is provided in the first dielectric layer above the peripheral circuit area; and the via hole and each of the contact holes are filled with a plurality of conductive vias, and the electric layer is used for the via layer. Layer holes form a plurality of holes

第21頁 480653 六、申請專利範圍層，以同時形成各該轉接介層以及各該帶接觸 1 2 .如申請專以及該週邊電成有一輕摻雜導體晶於該半晶矽層對該記佈植製成為一進行一第三介於該半以及一進行一該第二利用該區上方層，直方之該面；以及一憶陣列程，以摻雜多第二蝕電層，導體晶第二光第二黃光阻層第二光之該保至該第保護層利範圍第1項之方法，其中於該記憶陣列區路區上形成各該閘極，且各該閘極周圍均形汲極（LDD)的方法係包含有下列步驟：片表面依序形成一第二介電層、一未摻雜多第三介電層；區上方之該未摻雜多晶石夕層進行一第一離子使該記憶陣列區上方之該未摻雜多晶矽層形晶矽層；刻製程，以完全去除該記憶陣列區上方之該並蝕刻該摻雜多晶矽層至一預定深度；片表面依序形成一金屬石夕化物層、一保護層阻層；光製程，以於該記憶陣列區之單胞井上方之中定義出複數個閘極的圖案；阻層的圖案當作硬罩幕，以蝕刻該記憶陣列護層、該金屬石夕化物層以及該換雜多晶石夕二介電層表面，並同時蝕刻該週邊電路區上以及該金屬矽化物層，直至該第三介電層表去除該第二光阻層；進行一第二離子佈植製程，以於該記憶陣列區中之各該閘極周圍形成一輕摻雜汲極（LDD);Page 21 480653 6. Apply for a patent scope layer to simultaneously form each of the transition interposer and each of the tape contacts 1 2. If the application and the periphery are electrically formed with a lightly doped conductor crystal on the semi-crystalline silicon layer, The recording is made as a first intermediary between the half and a second intermediary to use the layer above the area, the straight side of the area; and an array process to dope multiple second etch layers, the conductor crystal The method for protecting the second light from the second light to the second yellow photoresist layer to the first protection layer, wherein each of the gates is formed on the memory array area and the gates are uniformly shaped around the gates. The method of LDD includes the following steps: a second dielectric layer and an undoped multiple third dielectric layer are sequentially formed on the surface of the chip; the undoped polycrystalline layer above the region is subjected to a first step; An ion causes the undoped polycrystalline silicon layer-shaped crystalline silicon layer above the memory array region; a etch process to completely remove the crystalline silicon layer above the memory array region and etch the doped polycrystalline silicon layer to a predetermined depth; a sheet surface is sequentially formed Metallixide Layer, a protective layer resist layer; a light process to define a plurality of gate patterns in a single cell well above the memory array area; the pattern of the resist layer is used as a hard mask to etch the memory array cover layer , The metal oxide layer and the surface of the doped polycrystalline silicon second dielectric layer, and simultaneously etch the peripheral circuit region and the metal silicide layer until the second photoresist is removed from the third dielectric layer surface Layer; performing a second ion implantation process to form a lightly doped drain (LDD) around each of the gates in the memory array region;

第22頁 480653 六、申請專利範圍去除該週邊電路區上方之該第三介電層；於該半導體晶片表面形成一第三光阻層；進行一第三黃光製程，以於該週邊電路區之N型井以及P型井上方的該第三光阻層中，定義出複數個閘極的圖案；利用該第三光阻層的圖案當作硬罩幕，蝕刻該週邊電路區上方之該未摻雜多晶石夕層直至該第二介電層表面，以於該週邊電路區上形成各該閘極；去除該第三光阻層；以及進行一第三離子佈植製程，以於該週邊電路區中之各該閘極周圍形成一輕摻雜汲極（LDD)。 1 3.如申請專利範圍第1 2項之方法，其中該第二介電層係由二氧化矽（S i 0 2)所構成，用來作為各該閘極的閘極氧化〇 1 4.如申請專利範圍第1 2項之方法，其中該預定深度約略為該未摻雜多晶矽層之總厚度的一半。 1 5.如申請專利範圍第1 2項之方法，其中該保護層係由一氮石夕化合物所構成，且該保護層與該該金屬石夕化物層之間另包含有一氮氧化石夕（SiOxN y)層，用來做為一抗反射層 (ARC)。 1 6 .如申請專利範圍第1 2項之方法，其中在該半導體晶片Page 22 480653 VI. Patent application scope Remove the third dielectric layer above the peripheral circuit area; form a third photoresist layer on the surface of the semiconductor wafer; perform a third yellow light process to the peripheral circuit area A pattern of a plurality of gates is defined in the N-type well and the third photoresist layer above the P-type well; the pattern of the third photoresist layer is used as a hard mask to etch the above the peripheral circuit area. Undoped polycrystalline silicon layer up to the surface of the second dielectric layer to form each of the gates on the peripheral circuit region; removing the third photoresist layer; and performing a third ion implantation process to A lightly doped drain (LDD) is formed around each of the gates in the peripheral circuit region. 1 3. The method according to item 12 of the scope of patent application, wherein the second dielectric layer is composed of silicon dioxide (S i 0 2), and is used as the gate oxide of each gate. For example, the method of claim 12 in the patent application range, wherein the predetermined depth is approximately half of the total thickness of the undoped polycrystalline silicon layer. 15. The method according to item 12 of the scope of patent application, wherein the protective layer is composed of a nitrogen oxide compound, and a nitrogen oxynitride is further included between the protective layer and the metal oxide layer ( SiOxN y) layer is used as an anti-reflection layer (ARC). 16. The method according to item 12 of the patent application range, wherein the semiconductor wafer is

第23頁區含路包電另邊法週方該該在，中後其之，子法壁方側之該項各 11成第形圍圍範周利的專極請閘申該如各 .之 8 1 中路電邊週該於別分以程製植佈子 0 五第及 :以驟四步第列一下行有進源 - 成形圍周極閘該各之方上井該及以井型 Ρ 0 該極之汲中與區極 480653 六、申請專利範圍表面形成該第三光阻層之前，另可先於該半導體晶片表面形成一氮氧化矽（Si 0xNy)層當作抗反射層（ARC)。 1 7 ·如申請專利範圍第1 6項之方法，其中在去除該第三光阻層之後，亦須去除形成於該第三光阻層下方之該氮氧化石夕層0 1 9 .如申請專利範圍第1 8項之方法，其中在形成完各該源極與汲極之後，該方法另包含有下列步驟：於該半導體晶片表面形成一金屬層，且該金屬層覆蓋於該週邊電路區上之各該源極、汲極以及閘極表面之上；進行一第一快速熱處理（RTP)製程；去除於該半導體晶片表面未反應之該金屬層；以及進行一第二快速熱處理（RTP)製程。 2 0 .如申請專利範圍第1 9項之方法，其中該金屬層係由鈷 (Co)、鈦（Ti)、鎳（Ni)或鉬（Mo)所構成。On the 23rd page, including the road and the electricity, the other side should be present, and the middle and the second, the sub-farm side should have 11% of the encirclement of Fan Zhouli's special poles, and please apply for it. No. 8 1 The middle side of the electric circuit should be planted in a separate process. 0 Fifth and: In four steps, the first row has the source-forming the perimeter pole gate, each side of the well, and the well type P 0 the Before the third photoresist layer is formed on the surface of the patent application area, a silicon oxynitride (Si 0xNy) layer may be formed on the surface of the semiconductor wafer as an anti-reflective layer (ARC). 1 7 · The method according to item 16 of the scope of patent application, wherein after removing the third photoresist layer, the oxynitride layer formed under the third photoresist layer must also be removed. 0 1 9 The method of claim 18, wherein after forming each of the source and drain electrodes, the method further includes the following steps: forming a metal layer on the surface of the semiconductor wafer, and the metal layer covering the peripheral circuit area Performing a first rapid thermal processing (RTP) process on the source, drain and gate surfaces; removing the unreacted metal layer on the surface of the semiconductor wafer; and performing a second rapid thermal processing (RTP) Process. 20. The method of claim 19, wherein the metal layer is composed of cobalt (Co), titanium (Ti), nickel (Ni), or molybdenum (Mo).

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