TW478183B - Method for manufacturing electronic semiconductor elements - Google Patents

Method for manufacturing electronic semiconductor elements Download PDF

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Publication number
TW478183B
TW478183B TW089126662A TW89126662A TW478183B TW 478183 B TW478183 B TW 478183B TW 089126662 A TW089126662 A TW 089126662A TW 89126662 A TW89126662 A TW 89126662A TW 478183 B TW478183 B TW 478183B
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Taiwan
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manufacturing
patent application
scope
substrate
semiconductor
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TW089126662A
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Chinese (zh)
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Peter Muhleck
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Vishay Semiconductor Gmbh
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    • H—ELECTRICITY
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    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/483—Containers
    • H01L33/486—Containers adapted for surface mounting
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
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    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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  • Engineering & Computer Science (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Led Device Packages (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

1.Method for manufacturing electronic semiconductor elements 2.1. Known methods of manufacture have the disadvantage whereby the electronic semiconductor elements made by it have relatively large dimensions, a structured printed circuit board is needed, and bondings must be taken from the bottom side of the printed circuit board to its top side. 2.2. Method for manufacturing electronic semiconductor elements for surface mounting, characterised by the following process steps: (a) provision of a conductive substrate; (b) fixing of a semiconductor chip on a first surface side of the substrate; (c) establishing of electrical connections from the semiconductor chip to the first surface side of the substrate; (d) production of a housing body by encapsulating the semiconductor body and the electrical connections with an insulating material; and (e) production of terminal areas (5, 5.1, 5.2) that are electrically insulated from each other by dividing the substrate (1; 11) from a second side (1.2) opposite to the first surface side. 2.3 The invention is sultable for the manufacture of light-emitting components of minimum size used as light sources in display panels, as background lighting for liquid-crystal displays and in light switches, and also for active and passive electronic components such as diodes, transistors and integrated circuits.

Description

478183 五、發明說明（1) 本發明係關於申請專利範圍第1項前序句中所載表面 安裝用電子半導體元件之製法。 此種技術上已知製法，例如載於德國專利公開公報DE 1 9 5 44 9 8 0 A 1。在此製法中，發光組件製法是在絕緣基 體的底側形成電氣終端，結合到頂側，利用焊劑等導電連 接媒體，連接至LED晶片之η側和p側電極。絕緣基體上的 LED晶片和導電連接媒體則利用半透明樹脂加以密封。 然而，此製法之缺點是，由此製成的發光組件尺寸較 大，需要結構化印刷電路板，且必須有在印刷電路板的下 側和頂側之間建立接觸的精緻機構。 本發明之目的，在於設計申請專利範圍第1項前序句 之方法’使得具有很小尺寸的電子半導體元件’可以低成 本和簡單方式量產。 此目的是以具有申請專利範圍第1項專屬特點之方法 解決。 按照申請專利範圍第1項方法製成之電子半導體元件 的優點是，可以簡單而低廉成本生產，而組件之接觸表面 不受到封閉材料的污染。此外，設計上可供充分除去半導 體本體產生的熱。 本發明適於製造最小尺寸的發光組件，用做顯示面板 内之光源、液晶顯示器和光開關内之背景亮光，以及用做 有源和無源電子組件’諸如二極體、電晶體和積體電路。 申請專利範圍第1項方法之有利發展列於申請專利範 圍附屬項。478183 V. Description of the invention (1) The present invention relates to a method for manufacturing an electronic semiconductor component for surface mounting as described in the preamble of the first item of the scope of patent application. Such a method is known in the art, for example, in German Patent Publication DE 1 5 44 9 8 0 A1. In this manufacturing method, a light-emitting component manufacturing method is to form an electrical terminal on the bottom side of an insulating substrate, bond to the top side, and use a conductive connection medium such as a solder to connect to the n-side and p-side electrodes of the LED chip. The LED chip and the conductive connection medium on the insulating substrate are sealed with a translucent resin. However, the disadvantage of this method is that the light-emitting component thus produced is relatively large in size, requires a structured printed circuit board, and must have a delicate mechanism for establishing contact between the underside and the top side of the printed circuit board. The object of the present invention is to design the method 'preamble 1 of the scope of patent application' so that an electronic semiconductor component having a small size can be mass-produced in a low cost and in a simple manner. This objective is solved by a method that has the exclusive features of the first scope of patent application. The advantage of the electronic semiconductor device manufactured according to the method of the first patent application range is that it can be produced simply and inexpensively, and the contact surface of the component is not contaminated by the sealing material. In addition, it is designed to sufficiently remove the heat generated by the semiconductor body. The invention is suitable for manufacturing light-emitting components of the smallest size, used as light sources in display panels, background light in liquid crystal displays and light switches, and as active and passive electronic components such as diodes, transistors and integrated circuits . The advantageous development of the first method of patent application scope is listed in the appendix of patent application scope.

第7頁 478183 五、發明說明（2) ，發明兹藉圖式具體例加以說明。附圖有 你世ίΐ圖為透視圖，說明本發明製法第一式之各種 ^ 、以基體上所安裝發光半導體元件為例； 之透ί 2圖圖為以本發明成型法所製成若干發光半導體元件 之透^ ^圖；為仍然結合在一起的若干成型發光半導體元件 第4圖為本發明方法所製成拆開的發光半 側透視圖，具有鍍錫電氣終端； .70仵底 外側㈣本發明方法所製成I導體元件透視圖，標示 第5b圖為本發明方法所製成半導體元件之側視圖，標 示内側尺寸； 第5c至5e圖為本發明方法所製成若干半導體元件之透 視圖’有光學耦合和脫耦元件整合在殼 第6圖為本發明製法第二式各種二體二，以及 八合檀作業步驟之說明圖， 以安裝在縱向載體長條上的發光半導體元件為例。 第la圖至第Id圖為本發明製法第一式各 說 明圖技/示Λ裝在導電基體1上的發*半導體元件1〇例（微 SMD發光一極體）。 表示導9電基體1，以頂側為第-表面側1.1，底 側Λ/Λ二其二角1.3為所謂安全特點，以免基體 1疋向不正碟。導電基體i使用例如鋼纟長 方形金屬載板。發光半導體元件以規則方<，例如成列成 1 478183 五、發明說明（3) 方式，配置在基體1的頂側1 · 1上。要製造的半導 行之矩陣且 ^ /ISZ- * -V，八 叫丄· - -— >s 取 tJV 干 體元件之電接面積（終端、電極）5，稍後在底側1 · 2構成。 基體1大小約等於核對卡格式，但視上面所要安裝的半導 體元件10數，和所用生產設備之尺寸而定；基體厚度約 1 2 5 // m，設有傳送孔8，以供傳送和定位於製造設備。 第一步驟是把例如發光半導體本體2附在基體1之第一 頂側1 · 1。基體1特別用做發光半導體本體或半導體晶片2 之載體，如第lb圖所示。各發光半導體晶片2宜利用機械 方式安裝於基體1的頂側丨·丨，以便附設在基體1。同 立從半導體本體2至基體丨第一表面側1；1之電接，使Page 7 478183 V. Description of the Invention (2) The invention will be described by specific examples of the drawings. The attached picture is a perspective view illustrating various aspects of the first method of the manufacturing method of the present invention, taking a light-emitting semiconductor element mounted on a substrate as an example; the figure 2 shows a number of light-emitting devices made by the molding method of the present invention. ^^ Figure of a semiconductor element; several shaped light-emitting semiconductor elements still combined together. Figure 4 is a perspective view of a disassembled light-emitting half-side made by the method of the present invention, with tin-plated electrical terminals; .70 (bottom outside) A perspective view of an I-conductor element made by the method of the present invention is shown in FIG. 5b, which is a side view of a semiconductor element made by the method of the present invention, showing the inside dimensions; FIGS. 5c to 5e are perspective views of several semiconductor elements made by the method of the present invention. Figure 'There are optical coupling and decoupling components integrated in the shell. Figure 6 is an explanatory diagram of the second type of two-body two and eight-piece step manufacturing process of the present invention. The light-emitting semiconductor components mounted on the longitudinal carrier strip are example. Figures la to Id are the first illustrations of the manufacturing method of the present invention / showing 10 examples of semiconductor devices (micro SMD light emitting monopoles) mounted on a conductive substrate 1. It indicates that the conductive substrate 1 is electrically conductive, and the top side is the first surface side 1.1, and the bottom side Λ / Λ and its two corners 1.3 are so-called safety features, so that the substrate 1 does not face the dish. As the conductive substrate i, for example, a steel reed rectangular metal carrier is used. The light-emitting semiconductor elements are arranged on the top side 1 · 1 of the substrate 1 in a regular manner < for example, 1 478183 V. Description of the invention (3). The semi-conducting matrix to be manufactured and ^ / ISZ- * -V, eight calls 丄 ·--— > s Take the electrical connection area (terminal, electrode) of tJV dry body element 5, and later on the bottom side 1 · 2 frames. The size of the substrate 1 is approximately equal to the format of the verification card, but it depends on the number of semiconductor components to be installed above and the size of the production equipment used; the thickness of the substrate is about 1 2 5 // m, and there are transmission holes 8 for transmission and positioning For manufacturing equipment. The first step is to attach, for example, a light-emitting semiconductor body 2 to the first top side 1 · 1 of the base body 1. The substrate 1 is particularly used as a carrier for a light-emitting semiconductor body or a semiconductor wafer 2 as shown in FIG. 1b. Each light-emitting semiconductor wafer 2 should be mechanically mounted on the top side of the substrate 1 so as to be attached to the substrate 1. The electrical connection from the semiconductor body 2 to the substrate 丨 the first surface side 1;

I 體晶片2的朝下背側接點，利用銀導電粘膠等導電粘膠 Γ導電方式連接於頂側h1第'終端點。惟需 、S的旁側接點，半導體晶 用晶片熱枯或以其他方式接觸。 員側1.1，利 再建立從各發来主道«λ » 第二電接，也是把曰至基體^第-頂側I」的 的前側接點，利用金或 體曰曰片2之第一接點，朝上 1.1第二終端點’離第車之姑枯結線3.1枯合於基體1頂側 枯結後，附設於V體 點不遠。 各發光半導體晶片2，包人Λ又體。為此，附於頂側1. 1的 法、接、生 Α 包含其粘結線3 · 1和3 9 ，綸&、射出成型或若干1他習知生H2，利用成型 式’用絕緣材料包膠，# ：”生產手段，以已知方 中也指定為成型物胃，係例如C:::材：緣材料在成型法 第9頁 478183 五、發明說明（4) 製造殼體4之第一選項，是在成型時使用成型模且之 個別腔部，使全部發光半導體元件1〇之殼體4可同時^ :由於成型模具内做成溝道，可使成型物質流過， 禱模洗口，故在成型法當中，於配置成列或成行體 元件1 0之殼體4間，即產生橋6。 + ¥體 通常在脫模，即製成零件從成型模具取出後，The contacts on the backside of the I-body wafer 2 facing downward are connected to the top terminal h1 'terminal point using a conductive adhesive such as silver conductive adhesive Γ conductively. However, the side contact of S is necessary, and the semiconductor wafer is thermally dried or otherwise contacted. On the staff side 1.1, Lee then establishes the second electrical connection from each main road «λ», which is also the front side contact to the base ^--top side I ", using gold or body first 2 The contact point is up 1.1 and the second terminal point is not far from the V-body point after the dry knot line 3.1 of the car is closed on the top side of the base body 1. Each of the light-emitting semiconductor wafers 2 is enclosed by a semiconductor. To this end, the method attached to the top side 1.1 includes its bonding wires 3 · 1 and 3 9, nylon & injection molding or a number of other known raw H2, which are packaged with insulating materials. Glue, #: "Production means, also known as the molded stomach in the known method, such as C :::: material: edge material in the molding method, page 9 478183 V. Description of the invention (4) Manufacturing of the shell 4 One option is to use a molding die and individual cavities during molding, so that the shells 4 of all the light-emitting semiconductor elements 10 can be simultaneously ^: Because the channel is formed in the molding die, the molding material can flow through, and the mold is washed Therefore, in the molding method, the bridge 6 is generated between the shells 4 of the row 10 or row body elements 10. + The body is usually demoulded, that is, after the finished part is taken out from the molding mold,

用折斷、裁切或其他手段除去橋6。在本案 "J 立刻除去橋6為宜，故有些半導體元件會 J而= 殼體4結合。 ⑨专崎保留以其 一方面在製法中可大為簡化運送， 起的半導體元件可同時一次送至後使、，％合在一 半：：元件10定向於同一方向，故例保 極性不會改變。 鱼逼乳功能時 製造殼體4之第二選項，县田y 材=成型整個頂側11，使半導體元件的熱塑性 如第一選項，故在製法中比半導-刀^且結合在一起 開的情形更容易運送。半導體元件丨〇稍=1 0立個逐一分 :P 土為單個。α此選項也是可以很好檢如加以鋸開， 、、且δ，一起時的電氣功能。 +導體元件1 〇還 弟1 d圖表示已沒備結構，即終 底，1· 2。結構是利用雷射、蝕刻或鋸· 1和5· 2的基體 。利用蝕刻除去材料之前，义肩，除去材 以光罩，而篡胁, π田 用先钱法（即在戶斤♦占式塗 而基體1必須再浸於酸浴，使不 j而處曝光）加 需要的材料利 第10頁 478183 五、發明說明（5) 用化學手段，於特定溫度在特定時間之後除去。 基體1側邊或傳送孔8，連同切角1 · 3，可使要製造的 結構定向。 在底側1. 2製造結構時，在時序上亦有不同選項。第 一選項是在殼體4下方的部份區域，同時沿電氣終端面積5 、5. 1和5. 2的輪廓，例如利用蝕刻，把基體1完全分離。 電氣終端面積5、5. 1和5. 2再彼此一次完全分開，即告絕 緣，而半導體元件1 0即脫離基體。配置成列的半導體元件 1 0，再僅利用橋6結合在一起，並以此型式（如第3圖所示） 送至隨後之製造步驟。 另一選項是只把殼體4下方在接點5. 1和5. 2間之部份 面積，例如利用餘刻分開。在此情況下，所得電氣終端面 積（終端）5. 1和5 · 2稍後鍍錫，而最後安裝的半導體元件1 0 在分離操作（裁切、鋸開、模鍛等）形成單個。終端面積 5. 1和5. 2之鍍錫，亦可在分成單個後例如利用鍍筒式鍍錫 為之。 第三選項是蝕刻穿過殼體下方在終端面積5.1和5. 2間 之部份面積，只是沿殼體4的輪廓輕微蝕刻到基體1。以此 方式，沿殼體4的輪廓具有界定斷裂點，以便在鍍錫後， 稍後把最後安裝半導體元件1 0，沿此界定斷裂點，例如利 用折斷而形成單個。 以上述所有選項，光蝕和蝕刻貫穿基體1基本上亦可 在Μ錫後為之。 利用本發明方法製成的若干發光半導體元件10，如第The bridge 6 is removed by breaking, cutting or other means. In this case " J, it is advisable to remove the bridge 6 immediately, so some semiconductor elements will be J and = case 4 combined. ⑨Specialty reserves that on the one hand, it can greatly simplify the transportation in the manufacturing method. The semiconductor components can be sent at the same time, and the% is half .: The component 10 is oriented in the same direction, so the polarity is not changed. . The second option for manufacturing the shell 4 when the fish is milking function, the county field material = molding the entire top side 11 to make the semiconductor component as thermoplastic as the first option, so in the manufacturing method, it is better than semiconductor-knife ^ and combined together. Situation is easier to ship. Semiconductor element 丨 〇 Slightly = 10 points one by one: P soil is a single. α This option can also be used to check the electrical function when sawing,,, and δ together. The + conductor element 1 0 and 1 d show that the structure is not ready, that is, the end, 1.2. The structure is laser, etched or sawed · 1 and 5 · 2 matrix. Before removing the material by etching, remove the material with a mask and remove the material to threaten it. Πfield uses the first method (that is, the household paint is applied and the substrate 1 must be immersed in the acid bath to expose it without j. ) Add the required materials. Page 10 478183 V. Description of the invention (5) Use chemical means to remove at a specific temperature after a specific time. The sides of the base body 1 or the transfer holes 8 together with the chamfers 1 · 3 can orient the structure to be manufactured. When manufacturing the structure on the bottom side 1.2, there are also different options in timing. The first option is to partially separate the base body 1 along the contour of the electrical terminal areas 5, 5.1 and 5.2 at the same time, for example by etching. The electrical terminal areas 5, 5.1 and 5.2 are completely separated from each other again, that is, they are insulated, and the semiconductor element 10 is separated from the substrate. The semiconductor elements 10 arranged in a row are combined together only by the bridge 6 and sent to the subsequent manufacturing steps in this type (as shown in FIG. 3). Another option is to only part of the area under the housing 4 between the contacts 5.1 and 5.2, for example, using the leftover to separate. In this case, the resulting electrical terminal areas (terminals) 5.1 and 5 · 2 are later tin-plated, and the semiconductor device 10 mounted last is formed into a single body during a separation operation (cutting, sawing, swaging, etc.). The tin areas of the terminal areas 5.1 and 5.2 can also be divided into individual pieces, for example, using a tin-plated barrel plating. The third option is to etch through the area under the housing between the terminal areas 5.1 and 5.2, but only slightly etch the substrate 1 along the outline of the housing 4. In this way, there are defined break points along the outline of the casing 4 so that after tinning, the semiconductor element 10 is mounted last, and the break points are defined along this, for example, by breaking to form a single. With all of the above options, photoetching and etching through the substrate 1 can also be done basically after M tin. Several light-emitting semiconductor elements 10 made by the method of the present invention are

第11頁 478183 2圖所示。在此情況下，使用單腔部製成殼體4。成型物質 壓經成型模具之進料管（圖上未示），故在脫模後，業已製 成的單元（包括若干相連的半導體元件10和橋6)有相當厚 的橋9存在，而前述橋4是在殼體4之間。 為使製成的半導體元件10在後繼製造步驟中容易運送 起見，在所製成包括若千相連半導體元件10和橋6的單元 各端，宜留豎洗道7·1和7.2。為免運送不正確，配置在一 側的全部豎澆道7 · 2宜具有小凹部7 · 3或若干其他特殊形狀 ，以確保運送安全可靠。 借助於起先未除去的豎澆道7.1和7.2，製成的單元$ 例如在成型後從模具取出，不會接觸到半導體元件和可能 造成損壞。此外，製成的單元與基體1分開時，可夾持於 此等豎洗道7 · 1和7 · 2，再浸入電鍍浴，將電氣終端5錢锡 (第3圖）。 第3圖表示本發明方法所製成的三個發光半導體元件 1 0，在以電鍍法鍍錫於電氣終端5之前，仍然利用橋6連接 在一起。各半導體元件1〇除半導體本體2(圖上未示）外， 有透明殼體4，以及包括陽極5·ι和陰極的電氣終端5。 在電鍍法中，利用橋6相連的半導體元件1〇經鍍錫，即連 同電氣終端放入液體錫浴内，直到銅合金製的終端5完全 浸沒入錫浴内。 把仍然相連在一起的半導體元件丨〇從錫浴拉出後，終 端5塗上層錫’加以保護免受氧化。電氣終端5鍍錫後， 例如利用鋸開、裁切、模鍛、折斷等，把橋6除去，因而Page 11 478183 2 Pictured. In this case, the case 4 is made using a single cavity portion. The molding material is pressed through the feeding tube (not shown in the figure) of the molding die, so after demolding, the unit (including several connected semiconductor elements 10 and bridges 6) has a relatively thick bridge 9 and the aforementioned The bridge 4 is between the shells 4. In order to make the manufactured semiconductor element 10 easy to be transported in subsequent manufacturing steps, vertical washing channels 7.1 and 7.2 should be left at each end of the manufactured unit including the Wakazaki connected semiconductor element 10 and the bridge 6. In order to avoid incorrect transportation, all vertical runners 7 · 2 arranged on one side should have small recesses 7 · 3 or some other special shapes to ensure safe and reliable transportation. By means of the runners 7.1 and 7.2 which were not removed before, the finished unit $, for example, is removed from the mold after molding, and does not come into contact with the semiconductor elements and may cause damage. In addition, when the completed unit is separated from the base body 1, it can be clamped in these vertical washing channels 7 · 1 and 7 · 2 and then immersed in a plating bath to place the electrical terminal 5 tin (Figure 3). Fig. 3 shows that the three light-emitting semiconductor elements 10 manufactured by the method of the present invention are still connected by a bridge 6 before being tin-plated on the electrical terminal 5 by electroplating. In addition to the semiconductor body 2 (not shown), each semiconductor element 10 includes a transparent case 4 and an electrical terminal 5 including an anode 5 · m and a cathode. In the electroplating method, the semiconductor elements 10 connected by the bridge 6 are tinned, that is, they are placed in a liquid tin bath together with the electrical terminals until the terminal 5 made of copper alloy is completely immersed in the tin bath. After the semiconductor elements still connected together are pulled out of the tin bath, the terminal 5 is coated with a layer of tin 'to protect it from oxidation. After the electrical terminal 5 is tinned, the bridge 6 is removed by, for example, sawing, cutting, die forging, breaking, etc.

五、發明說明（7) --—-------- 半導體元件1 〇即成單。 或夕Ϊ氣ί端5利用電鍍法鍍錫，可在底側丨·2結構化之前 相連半導?元件1〇成單之前或之後，甚至在利用橋6 起的_若干半導體元件10從基體1脫離後進行。 釦S 圖表示本發明方法所製成具有終端面積5· 1(陽極） 矛5义2(障極）的成單發光半導體元件1〇之底側，可以看到 =已脫開橋6之遺料6 ·丨。最後半導體元件之底側，與不 、r子#在的基體1之底側1 · 2 一致。因半導體晶片2 (在此未示 糸接結合於較大面積的電氣終端52，故半導體晶片2 内產生的熱可毫無困難地除去。V. Description of the invention (7) -------------- The semiconductor element 10 is ready. Or the terminal 5 is tin-plated by electroplating, and the semiconductor device 10 can be connected to the bottom side before or after the structure 10, or even after the semiconductor device 10 is formed from the substrate. 1 After detaching. Figure S shows the bottom side of a single light-emitting semiconductor element 10 with a terminal area of 5 · 1 (anode) and a spear 5 and 2 (barrier) made by the method of the present invention. It can be seen that the bridge 6 has been removed.料 6 · 丨. Finally, the bottom side of the semiconductor element coincides with the bottom side 1 · 2 of the substrate 1 where the sub-element # is located. Since the semiconductor wafer 2 (not shown here) is bonded to a large-area electrical terminal 52, the heat generated in the semiconductor wafer 2 can be removed without difficulty.

第5a圖表不本發明方法所製成半導體元件1〇之透視圖 坐呈微SMD發光二極體之形式，具有電氣終端5· 1和5· 2、 半導體晶片2和粘結線3，以及透明殼體4。半導體元件1〇 的外側尺寸寬約〇· 8inm，長約丨· 7mm，高約〇· 6mm。 第5b圖表不半導體元件1〇又一尺寸，各電氣終端 =5· 2的寬為〇· 7mm，其間距離〇· 3mm。在此發光LED晶片例 ，半導體晶片2呈立方形，幾近立方體形狀，其尺寸約 U· 3mmx 〇· 3mmx 〇· 25mm 〇 若粘結線3. 1並非曲線，而是在 間彎成大約直肖，則可得更小尺寸。如此可 =元件1〇,高度約50”。若陽極51縮短，而與陰極5 2 ，之距離減小，則半導體元件1〇長度L 可縮短至少 〇.5mm。縮短的陽極5.丨亦可容易與陰極5 2分辨。 第5C圖至第56圖為本發明方法所製成若干半導體元件Figure 5a is a perspective view of a semiconductor element 10 made by the method of the present invention in the form of a micro-SMD light-emitting diode, with electrical terminals 5.1 · 5 · 2, a semiconductor wafer 2 and a bonding wire 3, and a transparent shell. Body 4. The semiconductor device 10 has an outer dimension of about 0.8 inm in width, a length of about 7 mm, and a height of about 0.6 mm. Fig. 5b shows another dimension of the semiconductor device 10. The width of each electrical terminal = 5.2 is 0.7 mm, and the distance between them is 0.3 mm. In this example of a light-emitting LED wafer, the semiconductor wafer 2 has a cuboid shape and a nearly cubic shape, and its size is about U · 3mmx 〇 · 3mmx 〇 · 25mm 〇 If the bonding line 3.1 is not curved, it is bent into an approximately straight shape between , You can get a smaller size. This can be equal to the element 10, and the height is about 50 ”. If the anode 51 is shortened, and the distance from the cathode 5 2 is reduced, the length L of the semiconductor element 10 can be shortened by at least 0.5 mm. The shortened anode 5. 丨 can also be Easy to distinguish from cathode 52. Figures 5C to 56 are a number of semiconductor elements made by the method of the present invention.

478183 五、發明說明（8) _____ 10之透視圖，有光學耦合和 ' --- 5c圖所示半導體元件1〇，有=耦兀件整合於殼體4内。第 體4内。可以較低成本製造並X敕形或非球形透鏡丨8整合於殼 内之圓筒形透鏡19，如第Μ i合-於半導體元件1〇的殼體4 有開口 21之插座2 〇。開口 21㈤所不。在第5 e圖内可見到具 此開口 21内，而與先纖耗人 各，了例如利用光鐵*** 他透鏡形狀和光學輕合元 表光一極體領域内已知的其 第6圖為本發明方、’亦可毫無困難製成。 也是使用發光半導體元件丨一式各種作業步驟之透視圖， ，但士次是呈金屬栽體長條“形式。疋成列安裝在基體上 η上二一式’大多數情形在要安裝於基體 ^ (.·! ^ Λ Λ V Λ ^ ^81 Fa1 ^ ^ ^ ^ ^ t # 器，亦可並列進行°各種作% J而諸K殊設計的生產機 晶片2後’緊接著例如線：二驟諸如在枯著附設半導體 特定=按:;Γ導圖雷半導體晶片2是在第-作業站12,於 於載體長條乂之頂：粘膠降利用焊劑或晶片熱粘結，粘結 設計之背1 ’各情況下’半導體晶片2均有適當 體I片2:‘ 。在此項操作後’在第二作業站13,半導 面，再於第列三側作觸董點利用粘結線3· 1結合於載體長條11之表 包膠於透明Γ站14，把半導體晶片2連同粘結線3·1， ，載體長條才料之殼體4内，此時即製成橋6;稍後 體元件1 0之雷A =則在第四作業站15結構化。最後，半導 υ之電乳終端5在第五作業站16鍍錫。 478183 五、發明說明（9) 在進一步作業站，幾乎完成的半導體元件1 〇利用測試 探針1 7測試適當功能，除去橋6。接著可有各種其他作業 步驟，諸如清洗和包裝。 在二式中以發光半導體元件（微SMD發光二極體）為例 、 所述方法，亦適於製造極小尺寸之其他表面安裝電子半導 體元件，諸如多色發光二極體、二極體、電晶體、積體電 ~ 路，在許多情況下，宜用不透明成型物質。若半導體元件 需要二電氣終端以上，一如多色發光二極體、電晶體，尤 其是積體電路，自當採取基體（載體板或載體長條）之結構 化；然而，對有經驗的專家而言，這不是問題。前述製法 之優點完全適用，即使此種修飾亦無妨。 彳,478183 V. Description of the invention (8) A perspective view of _____ 10, including optical coupling and the semiconductor element 10 shown in FIG. 5c, and a coupling element integrated in the housing 4. Body 4 inside. The cylindrical lens 19, which can be manufactured at a lower cost and is integrated into the housing, such as an X-shaped or aspherical lens, such as a M i-a housing 4 of the semiconductor element 10 has a socket 21 with an opening 21. Opening 21 doesn't help. It can be seen in FIG. 5e that the opening 21 is provided, which is different from the first fiber. For example, the use of light iron to insert other lens shapes and optical light-emitting elements, and the light-polar body is known in the sixth image. The present invention, 'can also be made without difficulty. It is also a perspective view of various operating steps using light-emitting semiconductor elements, but it is in the form of a long strip of metal implants. 安装 Installed in rows on the substrate η. In most cases, it is to be installed on the substrate ^ (. ·! ^ Λ Λ V Λ ^ ^ 81 Fa1 ^ ^ ^ ^ ^ t t For example, when attaching a semiconductor with a specific designation = by :; Γ, the guide wafer semiconductor wafer 2 is at the first operation station 12, on top of the carrier strip: the adhesive is lowered by solder or wafer thermal bonding, and the bonding design is Back 1 'In each case' the semiconductor wafer 2 has a proper body I sheet 2: '. After this operation,' at the second work station 13, the semiconducting surface, and then the contact points on the three sides of the first row to use the bonding line 3 · 1 is combined with the carrier strip 11 to cover the transparent Γ station 14, the semiconductor wafer 2 together with the bonding wire 3 · 1, the carrier strip is expected to be inside the case 4, and the bridge 6 is made at this time; Later, the lightning element A of the body element 10 is structured at the fourth station 15. Finally, the semiconducting electric milk terminal 5 is tinned at the fifth station 16. 478183 V. Description of the invention (9) At the further operation station, the almost completed semiconductor element 10 is tested for proper function using the test probe 17 and the bridge 6 is removed. Then there can be various other operation steps, such as cleaning and packaging. Taking the light-emitting semiconductor element (micro SMD light-emitting diode) as an example, the method is also suitable for manufacturing other surface-mounted electronic semiconductor elements such as multi-color light-emitting diodes, diodes, transistors, and integrated circuits. In many cases, opaque molding materials should be used. If a semiconductor device requires more than two electrical terminals, it is like a multi-color light-emitting diode, a transistor, and especially a integrated circuit. Carrier strips); however, this is not a problem for experienced experts. The advantages of the aforementioned method are fully applicable, even if such modifications are possible. 彳,

第15頁 478183 圖式簡單說明 -------— 作孝：^圖3至」為透視圖，說明本發明製法第—式之各 作業J驟，以基體上所安裳發光半導體元：之各種 $ 2 ® 4以本發明成型法糾剩a# t技止、卜似 筮9闰丛 一从〜丁〒·胆〜,,π例，· 之透視圖V 發明成型法所製成若干發光半導體元件 之透ΐ3圖圖為仍然結合在一起的若干成型發光半導體元件 ίι圖為且本古發明方法所製成拆開的發光半導體元件底 視圖，具有鍍錫電氣終 ^ 側透視圖，具有鍍錫電氣終端成 第5 a圖為本發明方法 4，目® ，福 外側尺寸； 斤製成半導體元件透祝ΰ 一 第5b圖為本發明方法 w说圖， 示内側尺寸； 製成半導體元件之侧 弟5c至5e圖為本發明方 彳件 視圖，“學麵合和脫轉：：所製成若干，導體2 第6圖為本發明製法第_牛整合在殼體内；以、圖 以安裂在縱向載體長條上式各種作業步驟之訛 的發光半導體元件為例。 明 1 基材 1 ·2基材1的底側 2 半導體晶片 3 ·2導電粘膠，焊劑 襟 透 1 · 1基材1的頂側 1 ·3安全特點 3 ·1粘結線 4 彀體 發光半導體元件1〇之 殼體 終端面積5 (陽極）之終端面積 第一接點 第16 478183Page 478183 Brief description of the drawings ---------- Filial Piety: ^ Figures 3 to "" are perspective views illustrating steps J of the first method of the manufacturing method of the present invention, using light emitting semiconductor elements mounted on the substrate : Various kinds of $ 2 ® 4 using the method of the present invention to correct the remaining a # t technology, Bu Si 筮 9 闰 Cong Yi ~ ~ 〒 胆 biliary ~ ,, π example, · perspective view V made by the invention molding method 3 photos of light-emitting semiconductor components. The figure shows a number of shaped light-emitting semiconductor components that are still combined. The bottom view is a light-emitting semiconductor component disassembled and made by the method of the ancient invention. It has a tin-plated electrical end view. The tinned electrical terminal is shown in Figure 5a, which is the method 4 of the present invention, and the outer dimensions of the fuse; the semiconductor device is made into a transparent layer. Figure 5b is the method of the invention, which is the inner dimension; The side pictures 5c to 5e are views of the side pieces of the invention, "Study on and off: make several, conductor 2 Figure 6 shows the first method of the invention _ cattle integrated in the shell; Light-emitting semiconductor in which various operation steps are carried out on a vertical carrier strip by mounting Components as an example: Ming 1 Base material 1 · 2 Bottom side of base material 2 Semiconductor wafer 3 · 2 Conductive adhesive, flux penetration 1 · 1 Top side of base material 1 · 3 Security features 3 · 1 Bonding line 4 Terminal body area 5 of the body light-emitting semiconductor device 10 (terminal area of the anode) The first contact No. 16 478183

第17頁Page 17

Claims (1)

478183 修正 曰 案號 89126662 六、申請專利範圍 ―一J；Tj7 ι· 一種表面安裝用電子半導體元件之製法，其 ’包括下列製法步驟： … (a) 提供導電基體（1 ; 11); (b) 把半導體晶片（2)固定於基體（1;11)之第一表& 側（1 · 1 ); 面 包膠 (c) 建立從半導體晶片（2)至基體的第一表而 (d )以絕緣材料把半莫執 區隔 製成殼體（4);以I導體本體（2)和電接（3」，3.2) (e)把基體（1;11)盥坌_ 製成彼此電氣絕緣、之終一@表面側對面的第二側（1. 2) 2 ·如申請專利範圍第i 、面積（5，5. 1，5. 2 )者。 (2)的第一接點與第一表面=製法，其中在半導體本體 立第一電接（3· 2)者。 ·丨）之間，利用導電粘膠建 3·如申請專利範圍第1 (2)的第一接點與第一表 $製法，其中在半導體本體 —電接（3. 2)者。 训（1.〇之間，利用焊劑建立第 4·如申請專利範圍第1 (2)的第一接點與第一表面 ，其中在半導體本體 建立第一電接（3 · 2 )者。 · 1 )之間，利用晶片熱粘結 5 ·如申請專利範圍第 (2)的第二接點與第一表面側法，其中在半導體本體 第二電接（3 · 1 )者。 （1 · 1)之間，利用钻結線建立 6 ·如申請專利範圍第1 項之製法，其中殻體（4 )係利用 478183 案號 89126662 年月曰 修正 六、申請專利範圍 成型法製成者。 其中絕緣材料為熱 7·如申請專利範圍第1項之製法， 塑性材料者。 8·如申請專利範圍第1項之製法，其中在基體（1· 上固定若干半導體本體（2)者。 ’ 3 、9.如申請專利範圍第8項之製法，其中半導體本體（2) 是以正規方式配置在基體上者。 a 10·如申請專利範圍第8項之製法，其中半導體本體（2) 是成列配置在基體（〗；丨丨）上者。 日U·如申請專利範圍第8項之製法，其中半導體本體（2) 是成列又成行配置在基體（丨；丨丨）上者。 12·如申請專利範圍第1項之製法，其中固定在基體（工丨 U)上之各半導體本體（2)具有其本身殼體（2)者。 ’ 13·如申請專利範圍第1項之製法，其中全部半導體本 體（2)的殼體係同時一次製成者。 1 4·如申請專利範圍第1 〇項之製法，其中成列又成行配 ΐ部半導體元件（1〇)之殼體（4)，在製成後利用橋（6) 保留結合在一起者。 人15·如申請專利範圍第14項之製法，其中利用橋（6)結 ^ 起的半導體元件（10)各端保留豎澆道（7.1，7·2) 者。 ^6·如申請專利範圍第1項之製法，其中在製作終端面 阳^ ’ 5 ·/和5 · 2 )時，基體（1 ; 1 1 )是在殼體（4)下方的部份 區或’並沿殼體（4 )輪廓双双分開者。478183 Amendment No. 89126662 6. Scope of Patent Application-One J; Tj7 · A method for manufacturing electronic semiconductor components for surface mounting, which includes the following manufacturing steps:… (a) providing a conductive substrate (1; 11); (b ) Fix the semiconductor wafer (2) to the first table & side (1 · 1) of the substrate (1; 11); Glue (c) Create the first table from the semiconductor wafer (2) to the substrate and (d) The shell (4) is separated from the semi-moisture by insulating material; the base body (1; 11) is made of each other with I conductor body (2) and electrical connection (3 ", 3.2) (e) Insulation, the first one @ 面面 Opposite the second side (1. 2) 2 · If the scope of patent application i, area (5,5. 1,5. 2). (2) The first contact and the first surface = manufacturing method, in which the first electrical connection (3.2) is established in the semiconductor body. · 丨), using conductive adhesive to build 3. If the first contact of the patent application scope 1 (2) and the first table $ manufacturing method, in which the semiconductor body-electrical connection (3.2). Training (between 1.0), the first contact and the first surface, such as the first application (1) (2) in the scope of the patent application, using the flux to establish the first electrical connection (3 · 2) in the semiconductor body. 1), the wafer is thermally bonded 5) The second contact and the first surface side method of the patent application scope (2), wherein the second electrical connection (3 · 1) of the semiconductor body. (1 · 1), the use of drill knot line to establish 6 · If the patent application scope of the first method, the shell (4) is the use of 478183 case number 89126662, said the amendments, patent application scope molding method made by . Among them, the insulation material is heat. 7. If the manufacturing method of item 1 of the scope of patent application, plastic material. 8. The manufacturing method of item 1 in the scope of patent application, in which a number of semiconductor bodies (2) are fixed on the substrate (1.). 3, 9. The manufacturing method of item 8 in the scope of patent application, wherein the semiconductor body (2) is Those arranged on the substrate in a regular way. A 10 · As in the manufacturing method of item 8 of the scope of patent application, in which the semiconductor body (2) is arranged in a row on the substrate (〗; 丨 丨). The manufacturing method of item 8, in which the semiconductor body (2) is arranged in rows and rows on the substrate (丨; 丨 丨). 12. As in the manufacturing method of the scope of patent application item 1, it is fixed on the substrate (tool). Each of the semiconductor bodies (2) above has its own case (2). '13. As in the manufacturing method of item 1 of the patent application scope, wherein all the cases of the semiconductor body (2) are made at the same time. 1 4 · For example, the method of applying for the scope of patent application No. 10, in which the casings (4) of the semiconductor elements (10) are arranged in rows and rows, and the bridges (6) are used to keep the joints after they are made. People 15 · For example, the application method of the scope of patent application No. 14 in which the bridge (6) knot is used ^ The vertical runners (7.1, 7 · 2) are reserved at each end of the semiconductor device (10). ^ 6 · If the method of applying for the scope of the first patent application method, wherein the terminal surface is manufactured ^ '5 · / and 5 · 2), the base body (1; 1 1) is a part of the area below the shell (4) or separated along the outline of the shell (4). 第19頁 2002.01.03.019 891^rrr9 申請專利範圍 d7 I 專利範圍第1項之製法，其中在製作終端面 區域分門，祐2L) f，基體（1 ; U)是在殼體（4)下方的部份 L A刀開，並沿殼體（4)輪 18·如申請專利範 製成界疋斷裂點者。 沿界定斷裂點斷開，以便使车=製法，其中基體（1 ; 1 1 )係 19·如申請專利範圍吏^導體元件（1〇)成單者。、 利用光蝕法加以光罩者。項之製法，其中基體（丨·〗】 2〇·如申請專利範圍繁] n係 分開是利用雷射進行者。項之製法 2 1 ·如申請專利範圚 分開是利用裁切、剪開弟1項之製法〃、，少w 22.如申請專利範^笛模锻、或鋸開進行者。 用金屬載體板者。 、之製法，其中基體（1 23·如申請專利範 用金屬載體長條者。弟1項之製法， 24·如申請專利範 由銅合金製成者。国第1項之製法， 25·如申請專利範圍馆 5·1和5.2)經鍍錫者。 4項之製法 2 6 ·如申請專利範圍 導體元件（10)者。 之製法， 2 7 ·如申請專利範圍 t晶體和藉體雷製法 積 曰 修正 其中基體（1;11)的 其中基體（1;11)的 1)使 1)使 1)係 其中終蠕面積（5 應用於製造發光半 其中基體（1 其中基體（1 電晶體和積體電路孳 、之製法，應用於製造— 寺有源和無源半導體元件者。一極 體Page 19: 2002.01.03.019 891 ^ rrr9 Patent application scope d7 I Patent scope item 1 manufacturing method, in which the gate is divided in the production of the terminal area, you 2L) f, the base (1; U) is under the shell (4) Part of the LA knife is opened, and along the shell (4) wheel 18, such as those who apply for a patent application to make a boundary break point. Disconnect along the defined break point to make the vehicle = manufacturing method, where the base body (1; 1 1) is 19. As described in the patent application, the conductor element (10) is single. 1. Use photolithography to mask. The manufacturing method of the item, in which the matrix (丨 ·〗) 2〇 · If the scope of the patent application is complicated] n is separated by the use of laser. The manufacturing method of the item 2 1 · If the patent application is separated, it is cut or cut The manufacturing method of item 1 is less, 22. If you are applying for a patent 笛 flute die forging, or sawing. For those who use a metal carrier plate. The manufacturing method, where the substrate (1 23. If the patent application uses a metal carrier, Article 1. The manufacturing method of item 1, 24. If the patent application is made of copper alloys. The manufacturing method of item 1 of the country, 25. If the patent application scope is 5.1.1 and 5.2) tinned. 4 Manufacturing method 2 6 · For those who apply for the patent scope of the conductor element (10). Manufacturing method, 2 7 · For the patent scope of t and crystal lightning, the product method is to modify the matrix (1; 11) in which the matrix (1; 11) 1) make 1) make 1) is a system in which the final creep area (5 is used to manufacture the light-emitting half of the substrate (1 where the substrate (1 the transistor and the integrated circuit), the method of manufacturing, applied to manufacturing — Temple active and passive Semiconductor components. A polar body
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