TW476993B - Silicon on insulator circuit structure with buried semiconductor interconnect structure and method for forming same - Google Patents
Silicon on insulator circuit structure with buried semiconductor interconnect structure and method for forming same Download PDFInfo
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- TW476993B TW476993B TW89126335A TW89126335A TW476993B TW 476993 B TW476993 B TW 476993B TW 89126335 A TW89126335 A TW 89126335A TW 89126335 A TW89126335 A TW 89126335A TW 476993 B TW476993 B TW 476993B
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- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 83
- 239000010703 silicon Substances 0.000 title claims abstract description 83
- 239000012212 insulator Substances 0.000 title claims abstract description 38
- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 238000000034 method Methods 0.000 title claims abstract description 34
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 81
- 239000000758 substrate Substances 0.000 claims abstract description 45
- 230000008878 coupling Effects 0.000 claims abstract description 3
- 238000010168 coupling process Methods 0.000 claims abstract description 3
- 238000005859 coupling reaction Methods 0.000 claims abstract description 3
- 238000004519 manufacturing process Methods 0.000 claims description 21
- 230000005669 field effect Effects 0.000 claims description 12
- 230000000694 effects Effects 0.000 claims description 10
- 230000008569 process Effects 0.000 claims description 7
- 238000009413 insulation Methods 0.000 claims description 6
- 239000004575 stone Substances 0.000 claims description 6
- 238000005381 potential energy Methods 0.000 claims description 4
- 230000002079 cooperative effect Effects 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 2
- 230000006378 damage Effects 0.000 claims description 2
- 238000005530 etching Methods 0.000 claims description 2
- 230000000873 masking effect Effects 0.000 claims description 2
- 235000012431 wafers Nutrition 0.000 claims 4
- 238000005520 cutting process Methods 0.000 claims 1
- 238000005498 polishing Methods 0.000 claims 1
- 239000010409 thin film Substances 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 11
- 238000005516 engineering process Methods 0.000 description 10
- 229920002120 photoresistant polymer Polymers 0.000 description 10
- 238000007667 floating Methods 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 235000012239 silicon dioxide Nutrition 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- CPELXLSAUQHCOX-UHFFFAOYSA-N Hydrogen bromide Chemical compound Br CPELXLSAUQHCOX-UHFFFAOYSA-N 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000012937 correction Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000007499 fusion processing Methods 0.000 description 2
- 150000002500 ions Chemical group 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 241000790917 Dioxys <bee> Species 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000000875 corresponding effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012943 hotmelt Substances 0.000 description 1
- 229910000042 hydrogen bromide Inorganic materials 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000005424 photoluminescence Methods 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Thin Film Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
476993 A7 B7 # 經濟部智慧时產咼員I-消費合阼Fi印製 五、發明說明( [發明背景] [發明領域] 廣義來說’本發明係關於碎位於絕緣體上(silicon on insulator,SOI)電路結構製造技術,詳言之,係關於具有埋 置半導體互連結構之SOI基底結構。 [相關技術之說明] 傳統或者體積式半導體電晶體是在半導體基底内藉著 埋置一個P-形式或N-形式導電矽的阱而長成,該導電矽係 埋置在與其具有相反導電性的矽基底晶圓内,其上再加一 層場氧化層以防止表面反轉(surface inversion)現象發生。 閘極.和源/汲極的擴散即利用一般常見的製程方式而長 成。這類所形成的元件即所謂的金屬氧化半導體(metal_476993 A7 B7 # Printed by the Ministry of Economic Affairs I-consumer I-consumption Fi Fi. 5. Description of the invention ([Background of the Invention] [Field of the Invention] In a broad sense, the present invention is about silicon on insulator (SOI ) Circuit structure manufacturing technology, in detail, is about an SOI substrate structure with a buried semiconductor interconnect structure. [Explanation of the related technology] Traditional or bulk semiconductor transistors are embedded in a semiconductor substrate by a P-form Or N-formed conductive silicon wells. The conductive silicon is embedded in a silicon-based wafer with the opposite conductivity, and a field oxide layer is added to prevent surface inversion. The gate and source / drain diffusions are grown using common process methods. The components formed by this type are called metal oxide semiconductors (metal_
oxide-semiconductor,MOS)場效電晶體(FETs)。每一個 FET 都必須在電性上和其它的FET相隔離,以避免電路的短路 發生。這些FET典型上經由在體積基底上金屬層彼此互 連,以此形成邏輯電路。基本上,這些互連的結構是要根 據互補金屬氧化半導體(complimentary metal-oxide-semiconductor,CMOS)的技術而連結P-通道和N-通道的 FET,以將能量消耗減至最小。 體積半導體邏輯電路先天上有一個問題,即需要大塊 的表面積以將不同的FET做電性上的隔離,而這種隔離的 方式事實上對目前縮小尺寸的產業目標而言,是不合宜 的。除此之外,位於源極/汲極和體積基底之間的接面電容 會降低使用此類電晶體元件的操作速度。 -------I --------^ (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 1 91693 476993 A7 B7 五、發明說明( 為了要解決接面電容問題和縮小尺寸,砍位於絕緣體 上(silicon on insulator,SOI)技術愈來愈受到重視而風行。 於形成一個SOI晶圓的方法中,有一種是利用傳統的氧化 植入(oxygen implantation)技術,在體積晶圓表面下預先規 劃的深度,產生絕緣埋置氧化層。該植入的氧氣會將石夕氧 化成絕緣砍氧化物’而其氧化物以高斯(gaussian)分佈形式 的方式分佈,高斯分佈的中心乃在預先規劃的深度上,以 形成絕緣埋置之氧化層。第二種形成SOI晶圓的方法是在 第一個晶圓的表面上沈積一層絕緣的二氧化矽,然後利用 熱溶製程的方式將該晶圓和第二片晶圓連接在一起。 利用SOI技術,一個SOIFET包括源極區域,和第一 半導體形態的汲極區域,而該汲極區域係在具有相反電性 半導體形態的通道區域的另一側。SOI FET藉由在薄半導 體層内’沿著如島狀區域的周圍而姓刻出一道溝渠做為隔 離的方式,肖薄半導體層係纟S0Ia曰曰Β内絕緣埋置氧化層 之上。在該島上恰當的部位摻雜可以形成所要的源極、汲 極和通導區域。在此等技術當中,可以瞭解的,s〇ifet 在基底上會佔據比較少的表面積’這是因為它和矽基底的 隔離方式是藉由絕緣溝渠和絕緣埋置氧化層而達成,而且 和一個等效的體積半導體FET比較起來,a u a 士 ^ 巧取’它也會有比較低 的接面電容。種種這些提供了可以蔣μ 】」以將比較大的邏輯電路放 置在比較少的面積上的能力,而且可 J M更快的時脈速度操 作其電路。 (請先閱讀背面之注意事項再填寫本頁) 裝oxide-semiconductor (MOS) field effect transistors (FETs). Each FET must be electrically isolated from other FETs to avoid short circuits in the circuit. These FETs are typically interconnected via metal layers on a volume substrate to form logic circuits. Basically, these interconnect structures are based on complementary metal-oxide-semiconductor (CMOS) technology to connect P-channel and N-channel FETs to minimize energy consumption. A problem inherent in volume semiconductor logic circuits is that a large surface area is required to electrically isolate different FETs, and this isolation method is actually inappropriate for the current industry goal of reducing size. . In addition, the junction capacitance between the source / drain and the volume substrate will slow down the operation speed using such transistor components. ------- I -------- ^ (Please read the notes on the back before filling out this page) This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) 1 91693 476993 A7 B7 V. Description of the Invention (In order to solve the problem of junction capacitance and reduce the size, the technology of silicon on insulator (SOI) is becoming more and more important and popular. In the method of forming an SOI wafer, One is the use of traditional oxygen implantation technology to generate a buried insulation oxide layer under a predetermined depth under the surface of the volume wafer. The implanted oxygen will oxidize the stone oxidized into an insulating oxide. The oxide is distributed in the form of a Gaussian distribution. The center of the Gaussian distribution is at a pre-planned depth to form an insulating buried oxide layer. The second method of forming an SOI wafer is to use the first crystal A layer of insulating silicon dioxide is deposited on the round surface, and then the wafer and the second wafer are connected together by means of a hot melt process. Using SOI technology, an SOIFET includes a source region and a first semiconductor shape. The drain region is on the other side of the channel region with the opposite electrical semiconductor shape. The SOI FET is inscribed in a thin semiconductor layer along the periphery of an island-like region. The trench is used as an isolation method, and the thin semiconductor layer is S0Ia or B, which is buried on top of the buried oxide layer. Doping on the appropriate part of the island can form the desired source, drain, and conduction regions. Here Among other technologies, it can be understood that soifet will occupy a relatively small surface area on the substrate. This is because its isolation from the silicon substrate is achieved by insulating trenches and buried oxide layers, and it is equivalent to a Compared with the volume semiconductor FET, aua ^ should take it that it will also have a relatively low junction capacitance. All of these provide the ability to place larger logic circuits on a smaller area. And JM can operate its circuit at a faster clock speed. (Please read the precautions on the back before filling this page)
n n n ·ϋ -ϋ 一一口、I ϋ I I n ϋ n I 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製n n n ϋ -ϋ One sip, printed by I ϋ I I n ϋ n I Printed by the Intellectual Property Agency of the Ministry of Economic Affairs
91693 476993 A7 五、發明說明( 效應(floating body effect)。此浮動體效應的發生是因為埋 置氧化層將電晶體的通道或者個體從固定位能石夕基底中隔 離出來,因此該個體係根據電晶體最近的操作而存置電 荷。該浮動體效應會引起電晶體的電流對電壓曲線變形 (distort)或者扭結(kink),此變形或扭結依序使得操作電晶 體之門限電壓浮動。對用在如動態隨機存取記憶(dynamic random access memory,DRAM)中之類元件的通道元件,浮 動體效應的問題更加顯著,於此類元件中,臨限電壓保持 定值的要求是相當嚴格的,因此電晶體會保持在”關,,的位 置,以避免從儲存電容中發生電荷流失。 因此’於SOI電路結構中,尋求一種可以生成其結構 的方法是很迫切須要的,於該方法中,包括具有低接面電 容特性的SOI FET的優點,而又不具浮動體位能的缺點。 [發明概述與目的] ^ 本發明的首要目的係提供一種矽位於絕緣體上電路, 消 此電路包含矽位於絕緣體上基底,而該基底中包括一層將 矽元件從基座基底分隔的絕緣層。在矽元件層内長有第一 石夕元件’而在絕緣層内嵌有矽互連結構,此結構係竊合至 第一石夕元件。該矽互連結構可能會將第一矽元件竊合至在 矽元件層中形成的第二矽元件。第二矽元件可能是一個接 觸點,用來將第一矽元件藕合至其它電路,而矽互連結構 的功能是保護第一矽元件,免受位於接觸點上高esd位能 的破壞。另一方式為,第一矽元件可以是一個場效電晶體,b 而第二電晶體藕合至一個固定的位能上,因此該互連結構 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公髮) 3 91693 476993 部 智 員 印 A7 五、發明說明(4 ) 的功能是將場效電晶體的通道區域的位能竊 上,例如地線。 U疋位月匕 本發明的第二目的是提供一種製造石夕 ::方法,此方法包括:⑷在第1基底的第、=: 罩出-個半導體互連結構,·(_刻第一表面,以使半= 互連結構向上推擠形成;(c)用絕緣體覆蓋第— 上推擠的半導體互連結構上形表面,在向 平面式表面溶合至㈡基底的平及⑷將該 為,第,底的平面式表面是二氧::面在;=況 ==膜的步驟中,可能包括利用化學氣相沈積製程的: 是咖和T刚中的—種,施加於第_石夕表面上 位於第一表面的相對側是第一基底的第二表面,可 拋光以形成矽元件層,而此石夕元件 構晚鄰。 ㈣和絕緣體以及互連 ::明的第三目的為提供一種製造矽位於絕緣體上, =方法,此方法包括··⑷在第-石夕基底的第一表面」 =罩出-個半導體互連結構;(b)钱刻第一表面,以使钓 互連結構向上推擠形成;⑷用絕緣體覆蓋第—表面 2上推擠的半導體互連結構上形成平面式表面⑷將該 -Si面第二梦基底的平面式表面’·以及⑷在, 二 出至少一個的矽元件層和-個矽元件,而 ΓΓ件層和絕緣體以及半導體互連結構晚鄰。再者,可 一個效場電晶體在石夕元件層内生成,而該效場電晶 G張尺度適i?ii·家標準(CNS)A4規格__ 曰曰 4 91693 (請先閱讀背面之注意事項再填寫本頁) 476993 經 濟 部 智 慧 財 產 局 消 費 合 作 社 印 製 A7 __B7五、發明說明(5 / 體包括通道區域、源極區域和汲極區域。較佳的情況是, 通道區域藕合至半導體互連結構,與此同時,源極區域和 沒極區域與半導體互連結構在電性上是隔離的。半導體互 連、’Ό構可能會將通道區域藕合至固定的位能,譬如地線。 另個方式為’半導體互連結構可能會將場效電晶體藕合 至第二電路,而且保護該場效電晶體不受位於第二電路上 ESD位能的影響。 [圖式之簡單說明] 第1圖是根據本發明之實施例之剖視圖,其所顯示的 是一個矽位於絕緣體上電路的部份切除圖,· 第2圖是根據本發明之實施例中,石夕位於絕緣體上電 路的製造方法流程圖; 弟3 (a)圖是根據本發明之實施例中 緣體上晶圓第一步驟的截面圖; ^ 第3 (b)圖是根據本發明之實施例中 緣體上晶圓第二步驟的載面圖; 第3 (c)圖是根據本發明之實施例中 緣體上晶圓第三步驟的截面圖; 第4(a)圖是根據本發明之實施例中 緣體上晶圓第四步驟的截面圖; 第4(b)圖是根據本發明之實施例中 緣體上晶圓第五步驟的截面圖; 第5(a)圖是根據本發明之實施例中 上晶圓上製造矽元件之一步驟的截面圖 訂 於製造矽位於絕 於製造矽位於絕 線 於製造矽位於絕 於製造矽位於絕 於製造矽位於絕 於矽位於絕緣體 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 5 91693 476993 A7 五、發明說明(6 , 第5 (b)圖疋根據本發明之實施例中,於珍位於絕緣體 上晶圓上製造矽元件另一步驟的截面圖; [元件符號說明] 10 12 14 16(a) 18 20 22 24 26 30 32 34 36 38 40 41 42 44 48 54 64 16(b) 28 46 74 66 68 70 電路 場效電晶體 碎元件層 元件 絕緣溝渠 通道區域 源極區域 汲極區域 接面 上表面 氧化層 基極基底 閘極氧化層 多晶碎閘極 矽互連結構 凹處 晶圓 光罩 矽基底 N-形態摻子 氧化矽(氧化物) (請先閱讀背面之注意事項再填寫本頁) 裝 訂--- 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 制 [實施本發明之最佳模式] 關於本發明的新功能,而能做為本發明特徵之說明 延至增列之專利保護範圍令闡述。然而,本發明的本身 其較佳的使用狀態,以及其更進一步的目的和優點等, 會參考以下實施例之詳細說明,並配合所附之圖式,以 獲得最佳方式之瞭解。圖中的參考數字也同樣用來參考 中對應的元素組件。91693 476993 A7 V. Description of the invention (floating body effect. This floating body effect occurs because the buried oxide layer isolates the channel or individual of the transistor from the fixed potential energy substrate, so the system is based on The recent operation of the transistor results in the storage of charge. The floating body effect will cause the current of the transistor to distort or kink in the voltage curve, which in turn causes the threshold voltage of the operating transistor to float. For channel elements such as dynamic random access memory (DRAM), the problem of floating body effects is even more significant. In such devices, the requirement for the threshold voltage to remain constant is quite strict, so The transistor will remain in the off position to avoid charge loss from the storage capacitor. Therefore, in the SOI circuit structure, it is urgent to find a method that can generate its structure. In this method, including The advantages of SOI FETs with low junction capacitance, but without the disadvantages of floating body energy. [Summary and Purpose of the Invention] ^ A primary object of the present invention is to provide a silicon-on-insulator circuit. This circuit includes a silicon-on-insulator substrate, and the substrate includes an insulating layer that separates the silicon element from the base substrate. There is a silicon element layer in the silicon element layer. The first silicon element is embedded with a silicon interconnect structure in the insulating layer. This structure is coupled to the first silicon element. This silicon interconnect structure may steal the first silicon element into the silicon element layer. The second silicon element formed. The second silicon element may be a contact point for coupling the first silicon element to other circuits, and the function of the silicon interconnect structure is to protect the first silicon element from being located on the contact point. Destruction of high esd potential. Another way is that the first silicon element can be a field effect transistor, b and the second transistor is coupled to a fixed potential, so the interconnect structure is suitable for China on this paper scale. National Standard (CNS) A4 specification (210 X 297 issued) 3 91693 476993 Ministry of Intellectual Seal A7 V. Description of the invention (4) The function is to steal the bit energy of the channel area of the field effect transistor, such as the ground wire. U 月 月 dagger A second object of the present invention is to provide a method for manufacturing a stone slab :: This method includes: ⑷ on a first substrate, =: masking out a semiconductor interconnect structure, · (_ engraving the first surface so that half = The interconnect structure is pushed up to form; (c) the top surface of the semiconductor interconnect structure pushed on the first-is covered with an insulator. The flat surface is dioxy :: surface in; = condition == film step, which may include the use of chemical vapor deposition process: is one of the coffee and T Gang, applied to the surface The opposite side of a surface is the second surface of the first substrate, which can be polished to form a silicon element layer, and the stone element structure is adjacent. ㈣ and insulators and interconnects :: The third purpose of Ming is to provide a method for manufacturing silicon on insulators. This method includes: ⑷ on the first surface of the first-Shi Xi substrate "= cover out a semiconductor interconnect Structure; (b) engraving the first surface to push the fishing interconnect structure upwards; 覆盖 covering the semiconductor interconnect structure pushed on the first surface 2 with an insulator to form a planar surface; The planar surface of the two dream substrates and the two are at least one silicon element layer and one silicon element, and the ΓΓ component layer and the insulator and the semiconductor interconnection structure are adjacent to each other. In addition, an effect field transistor can be generated in the element layer of Shixi, and the G field size of the effect field transistor is suitable for i? Ii · Home Standard (CNS) A4 specification __ Yue 4 91693 (Please read the back Note: Please fill in this page again) 476993 Printed by A7 __B7, Consumer Cooperatives, Bureau of Intellectual Property, Ministry of Economic Affairs V. Invention Description (5 / Body includes channel area, source area, and drain area. It is better that the channel area is combined to The semiconductor interconnect structure, meanwhile, the source region and the non-electrode region are electrically isolated from the semiconductor interconnect structure. The semiconductor interconnect and the structure may combine the channel region to a fixed potential, such as Ground. Another way is that the 'semiconductor interconnect structure may couple the field effect transistor to the second circuit, and protect the field effect transistor from the ESD potential on the second circuit. [Schematic of Brief Description] Figure 1 is a cross-sectional view of an embodiment according to the present invention, which shows a partially cutaway view of a circuit where silicon is located on an insulator, and Figure 2 is an embodiment according to the present invention, where Shi Xi is located on an insulator On the circuit Manufacturing method flowchart; Figure 3 (a) is a cross-sectional view of the first step of the wafer on the edge body according to the embodiment of the present invention; ^ Figure 3 (b) is a crystal on the edge body of the embodiment according to the present invention Figure 3 (c) is a cross-sectional view of the third step of the wafer on the edge body according to the embodiment of the present invention; Figure 4 (a) is a middle side view of the wafer according to the embodiment of the present invention Cross-sectional view of the fourth step of the wafer on the body; FIG. 4 (b) is a cross-sectional view of the fifth step of the wafer on the edge body according to the embodiment of the present invention; FIG. 5 (a) is an embodiment of the present invention A cross-sectional view of one of the steps for manufacturing silicon components on a middle-upper wafer. The manufacturing silicon is located at the manufacturing silicon. The manufacturing silicon is located at the manufacturing line. The manufacturing silicon is located at the manufacturing silicon. National Standard (CNS) A4 specification (210 X 297 mm) 5 91693 476993 A7 V. Description of the invention (6, 5 (b) Figure 疋 In the embodiment of the present invention, silicon is fabricated on a wafer located on an insulator Sectional view of another step of the component; [Explanation of component symbols] 10 12 14 16 (a) 18 20 22 24 26 30 3 2 34 36 38 40 41 42 44 48 54 64 16 (b) 28 46 74 66 68 70 circuit field effect transistor broken element layer element insulation trench channel region source region drain region junction surface oxide base base gate Polar oxide layer polycrystalline silicon gate interconnect structure recessed wafer mask silicon substrate N-type doped silicon oxide (oxide) (Please read the precautions on the back before filling this page) Binding --- Ministry of Economic Affairs Wisdom Printed by the Consumer Cooperative of the Property Bureau [Best Mode for Implementing the Invention] Regarding the new functions of the present invention, the description of the features of the present invention can be extended to the added patent protection scope order. However, the present invention in its preferred use state, as well as its further purposes and advantages, will refer to the detailed description of the following embodiments and the accompanying drawings to obtain the best way to understand. The reference numbers in the figure are also used to refer to the corresponding element components in.
476993 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 A7 B7 五、發明說明(7 ) 包括場效電晶體(FET)12,而該場效電晶體係在矽 疋件層14内生成,而且藉著絕緣溝渠18和在矽元件層14 内生成的其它元件16(a)和16(b)相隔離。FET 12包括閘極 氧化層3 6和多矽晶閘極3 8,該多矽晶閘極3 8係用來定義 一塊中央通道區域20,FET 12也包括源極區域22和位於 中央通道區域20另一側的汲極區域24。於本發明的示範 實施例中,通道區域20最好是p-導電性矽,而源極區域 22和汲極區域24均是义導電性矽,如此而形成兩個半導 體接面26和28。然而,根據已知的矽技術,當源極區域 22和汲極區域24均是導電性矽時,通道區域2〇也可能 是N-導電性矽。絕緣溝渠18從s〇I電路1〇的上表面3〇 延伸至絕緣埋置氧化層32。該埋置氧化層32位於基極基 底4的上面。該埋置氧化層32包括埋置的碎互連結構 40,而在本示範性實施例中,該互連結構和擁有矽元件16(匕 f的FET U的通道區域2〇互連。應該可以認知的,矽元件 16(b)可以是另一個FET、一個將贿12本體竊合至盆它 位於S〇I電路10上之金屬層(未於圖中顯示)内電路的管道 (ν^、—個可以將FET12通道區域2〇以於固定位能以 降低浮動體效應的@定位能排流n(sink)、—個連接至晶片 針頭接觸以隔離和保護FET 12免受其它元件16(^上湖 位能影響的連結體、或者是其它任何的矽元件。 參考第2圖之流程圖和第3⑷、3⑻和3⑷圖的結構 圖八有埋置石夕互連結構4〇的石夕位於絕緣體上晶 是藉著步驟50由,产梦,^ ^ y Λ ^第一矽基底48的上表面46上施以光 本紙張尺度適財_ i^^Js)A4規格⑵G χ撕公爱) 7 91693 ^--------^---------線 (請先閱讀背面之注意事項再填寫本頁) 476993 經濟部智慧財產局員工消費合作社印製476993 Printed by A7 B7, Consumer Cooperative of Intellectual Property Bureau, Ministry of Economic Affairs 5. Description of the Invention (7) Includes field effect transistor (FET) 12, and the field effect transistor system is generated in silicon layer 14 and is insulated by insulation The trench 18 is isolated from other elements 16 (a) and 16 (b) generated in the silicon element layer 14. The FET 12 includes a gate oxide layer 36 and a polysilicon gate 38. The polysilicon gate 38 is used to define a central channel region 20. The FET 12 also includes a source region 22 and a central channel region 20. The drain region 24 on the other side. In the exemplary embodiment of the present invention, the channel region 20 is preferably p-conductive silicon, and the source region 22 and the drain region 24 are both conductive silicon. Thus, two semiconductor junctions 26 and 28 are formed. However, according to known silicon technology, when the source region 22 and the drain region 24 are both conductive silicon, the channel region 20 may also be N-conductive silicon. The insulating trench 18 extends from the upper surface 30 of the SOI circuit 10 to the insulating buried oxide layer 32. The buried oxide layer 32 is located on the base substrate 4. The buried oxide layer 32 includes a buried broken interconnect structure 40, and in this exemplary embodiment, the interconnect structure is interconnected with the channel region 20 of the FET U having a silicon element 16 (a FET U. It should be possible to Cognitively, the silicon element 16 (b) can be another FET, a pipe that steals the body of the bridging 12 to the circuit (ν ^, -One can fix the FET12 channel area 20 to a fixed position to reduce the floating body effect @Positive energy drain n (sink),-Connected to the chip needle contact to isolate and protect the FET 12 from other components 16 (^ The connected body that can be affected by the upper lake position, or any other silicon device. Refer to the flowchart in Figure 2 and the structure in Figures 3, 3, and 3. Figure 8 Shi Xi with the embedded Shi Xi interconnect structure 40 is located on the insulator The crystal is produced by step 50, and the dream is produced, ^ ^ y Λ ^ is applied on the upper surface 46 of the first silicon substrate 48. The paper size is suitable for _ i ^^ Js) A4 size ⑵G χ tear public love) 7 91693 ^ -------- ^ --------- line (please read the notes on the back before filling this page) 476993 Printed cooperatives
A7 ------g7 _五、發明說明(8 ) 罩44,然後刻劃出互連結構4〇的方式而達成,就如第3(句 圖所示。更仔細地說,1)有一層uv感光阻液化合物加到 第一矽基底48的上表面46上;2)透過光罩(reticle),uv 光用來在光阻液上形成影像圖案;和3)當UV光溶解光阻 液時,顯影溶劑會將光阻液未曝光的區域硬化,而且清除 曝光區域的光阻液,最後留下如光罩44所定義的未曝光區 域。 · 於步驟52,一種使用如溴化氫(hydr〇gen,Hbr)蝕刻化 a物的乾餘刻法用來將曝光的石夕腐餘’所侵餘的深度約是 500至1〇〇〇埃(Angstr〇m),由此在如第3(b)圖所突出的互 連結構40的周圍形成一個凹處41。然後,移開光阻罩4扣 於步驟54中,絕緣二氧化矽64沈積在晶圓上,填滿 凹處41,而且完全覆蓋在互連結構4〇之上,而絕緣二氧 化矽46’的上表面的平面結果如第3(c)圖所示。在最佳的 實施例中,二氧化矽是藉由化學氧相沈積(CVD)製程的方 式而形成’所使用的氣體為SIH4或TEOS,至於平面化的 方式疋藉由化學機械撖光(chemicai mechanicai p〇Hsh, CMP)而達成。 參考第4(a)圖,第二矽基底66包括薄層而具有平面上 表面70的二氧化矽68。第一矽基底48會翻轉至背面,因 此平面表面46,會面對第二矽基底66的平面表面7〇,然後 平面表面46’會熔合至平面表面70,如第4(b)圖的步驟56 所示。應當可以認知的,將第一矽基底48熔合至第二矽基 底66,其所形成的S0I晶圓42,以第二基底66變成s〇I 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐)A7 ------ g7 _V. Description of the invention (8) The cover 44 is then achieved by scoring the interconnection structure 40, as shown in Figure 3 (sentence diagram. To be more specific, 1) A layer of UV photoresist compound is added to the upper surface 46 of the first silicon substrate 48; 2) through the reticle, UV light is used to form an image pattern on the photoresist liquid; and 3) when UV light dissolves the light When the liquid is blocked, the developing solvent will harden the unexposed areas of the photoresist, and clear the photoresist in the exposed areas, leaving the unexposed areas defined by the mask 44 at the end. · In step 52, a dry residual etching method such as hydrogen bromide (Hdrogen, Hbr) is used to etch the exposed Shi Xiyu residue 'to a depth of about 500 to 1,000. Angstrom (Angstrom), thereby forming a recess 41 around the interconnection structure 40 as shown in FIG. 3 (b). Then, the photoresist cover 4 is removed and buckled in step 54. Insulating silicon dioxide 64 is deposited on the wafer, fills the recess 41, and completely covers the interconnect structure 40, and the insulating silicon dioxide 46 ' The planar result of the upper surface of is shown in Figure 3 (c). In the preferred embodiment, silicon dioxide is formed by a chemical oxygen phase deposition (CVD) process. The gas used is SIH4 or TEOS. As for the planarization method, chemical mechanical photoluminescence (chemicai) is used. mechanicai p〇Hsh, CMP). Referring to FIG. 4 (a), the second silicon substrate 66 includes a thin layer of silicon dioxide 68 having a planar upper surface 70. The first silicon substrate 48 will be flipped to the back, so the planar surface 46 will face the planar surface 70 of the second silicon substrate 66, and then the planar surface 46 'will be fused to the planar surface 70, as shown in step 4 (b). 56 shown. It should be recognized that the first silicon substrate 48 is fused to the second silicon substrate 66, and the SOI wafer 42 formed by the first silicon substrate 48 is changed to the soi by the second substrate 66. This paper standard is applicable to the Chinese National Standard (CNS) A4 specification ( 210 X 297 mm)
裝 _ -n n n n ϋ滅 (請先閱讀背面之注咅?事項再填寫本頁)_ _ -N n n n annihilation (Please read the note on the back? Matters before filling out this page)
8 91693 ^/6993 A7 _B7 五、發明說明( 晶圓42的基極基底34。第一矽基底48會變成矽元件層 14 ’而氧化物64會變成埋置的氧化層32。熔合過程通常 是一個熱熔合的程序,包括將基底加熱至1〇00至11〇〇。(:, 藉此將兩個基底結合在一起。應當可以認知的,第一石夕美 底48的厚度可能會比矽元件層14所預期的厚度厚,如果 是這樣的情況,可以將SOI晶圓42的上表面30拋光,得 出所預期的矽元件層14厚度,而於本最佳實施例中,所預 期的厚度大約是1000至2000埃,且和步驟58中埋置的氧 化層3 2相鄰。 在步驟60中,用來定義絕緣溝渠18形狀的氮化矽光 罩74在石夕元件層14的上表面3〇上形成,而且和如第5(心 圖中的互連結構40對齊。其中的一個示例性過程包括在矽 元件層14的上表面30上生成大約15〇至2〇〇埃厚的薄氧 化層因此也生成了一個氮化$夕光罩74。該光罩74覆蓋 在矽元件層14上,而且保護住FET 12和矽元件16〇))所 要生成的面積,留置要曝光而形成絕緣溝渠18的面積。氮 化矽光罩74可藉沈積一層氮化矽而形成,其厚度約15〇〇 至2000埃厚,而且位於氧化層的上表面上,然後利用傳統 的光學微影(photolithography)技術將氮化矽侵蝕,形成線 路,在光學微影技術中,”有一層的旧感光光阻化合物 塗在氮化矽的表面上;2)利用一個uv光源和光罩聚光, 對光阻液曝光和形成線路;3)當…光溶解光阻液時,顯 影溶劑會將光阻液未曝光的區域硬化,而且清除曝光區域 的光阻1,最後留下如氮切的表面光罩所定義的未曝光 本紙張尺度適用中關家標準(CNS)A4規格(21G χ 297公髮) 9 91693 A78 91693 ^ / 6993 A7 _B7 V. Description of the invention (Base substrate 34 of wafer 42. The first silicon substrate 48 will become a silicon element layer 14 'and the oxide 64 will become a buried oxide layer 32. The fusion process is usually A thermal fusion process, including heating the substrate to 10,000 to 1100. (:, to join the two substrates together. It should be recognized that the thickness of the first stone Ximei bottom 48 may be thicker than that of a silicon element The thickness of the layer 14 is expected to be thick. If this is the case, the upper surface 30 of the SOI wafer 42 may be polished to obtain the expected thickness of the silicon element layer 14. In this preferred embodiment, the expected thickness is approximately It is 1000 to 2000 angstroms, and is adjacent to the oxide layer 3 2 buried in step 58. In step 60, a silicon nitride mask 74 used to define the shape of the insulation trench 18 is formed on the upper surface 3 of the stone evening element layer 14. Is formed on the surface of the silicon element layer 14 and is aligned with the interconnect structure 40 as shown in FIG. 5 (cardiogram). One exemplary process includes generating a thin oxide layer on the upper surface 30 of the silicon element layer 14 to a thickness of about 150 to 200 Angstroms. The layer thus also creates a nitride mask 74. The mask 74 covers On the silicon element layer 14, and to protect the area to be generated by the FET 12 and the silicon element 16)), leave the area to be exposed to form the insulating trench 18. The silicon nitride mask 74 can be formed by depositing a layer of silicon nitride, Its thickness is about 15,000 to 2000 Angstroms thick, and it is located on the upper surface of the oxide layer, and then the silicon nitride is etched using traditional photolithography technology to form a circuit. In the optical lithography technology, "there is a layer Old photoresist compound is coated on the surface of silicon nitride; 2) using a UV light source and a mask to condense light to expose the photoresist and form lines; 3) when the photoresist is dissolved by the light, the developing solvent will The unexposed area of the photoresist is hardened, and the photoresist 1 in the exposed area is cleared, leaving the unexposed as defined by a nitrogen-cut surface mask. This paper size applies the CNS A4 specification (21G x 297 male). Hair) 9 91693 A7
4/69934/6993
五、發明說明(u ^ 雜的方法即疋一般常知的摻雜技術,如使用離子植入法 (jon lmplantati〇n),其中的離子形態為n形態摻子μ,像 (請先閱讀背面之注意事項再填寫本頁) 疋砷’其在電場中被加速至高速狀態,然後撞擊目標晶圓。 因為離子不能穿透多矽晶閘極38,因此多矽晶閘極38可 以有政地操作為一個光罩,只有曝露的源極區域和汲極區 域才能被摻雜。 { 應該可以認知的’前面所述及的製造具有埋置矽互連 、:構的SOI電路’其可以在⑦元件層内形成的元件之間, 提供一個具有高電阻的互連路徑。例如,該高電阻的互連 路徑可以用來將一個FET的通道區域竊合至第二個元件或 者其它位於矽元件層内的元件。舉例而言,該第二元件或 者電路可為:υ-個固定於固定位能以降低FET浮動體效 應的電路;2) -個連接至晶片針頭接觸以高電阻互連神 隔離和保護FET免受ESD位能影響的電路。 經 部 智 慧 財 產 局 員 工 消 費 合 社 印 製 、本段之前有關本發明實施例的述敘主要是為了闡釋和 說明之目的,並非限制本發明已表明的確實形式。藉助於 以上的說明,許多在細部上做明顯的更正或修飾是可能 的。所選用的實施例及其說明是為了提供本發明原理 佳言全釋表達方式,而其中的應用實例,是為了讓在本行技 般程度的人士 ’也能應用本發明而完成他們具有 明:求的不同實施例。所有的更正或修飾都未脫離本發 月所揭不之精神下所保護之範圍,而這些範圍將在下文中 2釋’且擁有專利保護所賦予之公平、公正與法律上的權 巧張尺度義fgiii^_CNS)A4規格( χ挪公爱) 11 91693V. Description of the invention (U ^ heterogeneous methods are commonly known doping techniques, such as the use of ion implantation (jon lmplantati), where the ion form is n-type dopant μ, like (please read the back first (Please note this page and fill in this page again)) Arsenic 'is accelerated to a high speed in an electric field and then hits the target wafer. Because ions cannot penetrate the polysilicon gate 38, the polysilicon gate 38 can be politically Operate as a photomask, and only the exposed source and drain regions can be doped. {It should be recognized that 'manufactured SOI circuits with embedded silicon interconnects as described above' can be used in A high-resistance interconnect path is provided between the elements formed in the element layer. For example, the high-resistance interconnect path can be used to snag the channel area of a FET to a second element or other silicon element layer For example, the second component or circuit may be: υ- a circuit fixed to a fixed position to reduce the FET floating body effect; 2)-a chip connected to the chip contact to isolate the high-resistance interconnect And protect the FET from The ESD bit can affect the circuit. Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Affairs, the description of the embodiments of the present invention before this paragraph is mainly for the purpose of illustration and description, and does not limit the exact form that the present invention has shown. With the above explanation, many obvious corrections or modifications in the details are possible. The selected embodiments and their descriptions are intended to provide a full explanation of the principles of the present invention, and the application examples are intended to enable people of ordinary skill in the industry to also apply the present invention and complete their understanding: Seeking different embodiments. All corrections or modifications have not deviated from the scope protected under the spirit not disclosed in this month, and these scopes will be explained below and have the fairness, justice and legal rights granted by patent protection. fgiii ^ _CNS) A4 specifications (χ Norwegian public love) 11 91693
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