TW475260B - Formation method of bit line contact area in the CUB DRAM manufacturing process - Google Patents

Abstract

There is provided a formation method of bit line contact area, particularly between crown capacitors, in the capacitor under bit line (CUB) DRAM manufacturing process, which comprises the following steps. First, there is provided a semiconductor substrate formed thereon a transistor structure and a crown capacitor structure. The capacitor structure is respectively formed on a plug connected to the drain of the transistor. In addition, there are plugs connected to the sources of the plurality of transistors. The structure is formed in a first dielectric layer. Besides, the crown capacitor structure is protruded out of the first dielectric layer. The cap electrodes are extended out of the crown capacitor and connected by the edge of the cap. Next, a photoresist pattern is formed on the cap electrode, and the connection of the cap edge is cut off by etching. Then, a wet etching is performed to etch off the top electrode of the cap edge portion under the photoresist layer by using the capacitor dielectric layer as the stop layer. Subsequently, the photoresist pattern is removed. A second dielectric layer is formed and the manufacture of the bit line contact hole is completed by the photolithography and etching technique.

Description

475260 五、發明說明（1) 發明領域： 本發明係有關於記憶元件製程，特別是指一種提高製 程容忍度於電容在位元線下方（CUB )DRAM製程中位元線接 觸區形成方法。 ' 發明背景： 電腦和電子工業不僅要求增加其整體之性能表現並且 也在乎製造整體積體電路之成本的降低。就電腦而言，無 疑的DRAM佔有一決定性的角色。因為DRAM不只是大量使 用，且也關係著電腦之輸出入的速度表現。且由於DRAM使 用量大，競爭者眾，因此，業者需不斷追求成本之降低， 及其高速的表現，而最為關鍵的是DRAM的微小化製程。那 _ 怕只是減少一微影步驟，可以創造相同之密度，都是DRAM 製程工程師必須追求的目標之一。 "475260 V. Description of the invention (1) Field of the invention: The present invention relates to the process of manufacturing memory elements, and more particularly to a method for forming a bit line contact area in a DRAM process in which a capacitor is located below a bit line (CUB) to increase process tolerance. '' BACKGROUND OF THE INVENTION: The computer and electronics industries not only demand an increase in their overall performance, but also a reduction in the cost of manufacturing integrated circuits. As far as computers are concerned, unquestionable DRAM plays a decisive role. Because DRAM is not only used in large quantities, but also related to the speed performance of computer input and output. In addition, due to the large amount of DRAM and competitors, the industry must continue to pursue cost reduction and high-speed performance, and the most critical is the miniaturization process of DRAM. That _ I am afraid that just reducing a lithography step can create the same density, which is one of the goals that DRAM process engineers must pursue. "

D R A Μ—般可以以製程上電容和位元線相對位置而可以 分為電容在位元線下方的CUB或者上方的C0B兩種。不管那 一類型DRAM，在相同佔用矽平面的面積而言，電容愈大愈 好。就相同的再新時間（r e f r e s h )而言，較大的電容可以 提供更可靠的資料保存性，但為使得電容增大，將面臨更 高的製程的挑戰性。本發明將先探討電容在位元線下方的 CUB之製程傳統上的問題，以了解本發明之動機。D R A M-generally can be divided into two types: CUB below the bit line or COB above the bit. Regardless of the type of DRAM, the larger the capacitance, the better the area occupied by the silicon plane. In terms of the same renewal time (r e f r e s h), a larger capacitor can provide more reliable data retention, but in order to increase the capacitance, it will face a higher process challenge. The present invention will first explore the traditional problems of the process of making a CUB with a capacitor below a bit line to understand the motivation of the present invention.

第5頁 475260 五、發明說明（2) * 傳統之CUB在尚未進行位元線接觸區製程前的典型製 程，如圖一所示。包含複數個複晶閘極1 0，形成於一半導 體基板5上，複晶閘極1 0除了具有氮化矽間隙壁層外並有 · 一氮化矽襯裡層1 5覆蓋在複晶閘極1 0及半導體基板5上。 - 一厚的第一内連線介電層2 0則再覆蓋在氮化矽襯裡層1 5上 以提供一平坦的表面。利用氮化矽間隙壁及複晶矽閘極上 的氮化矽覆蓋層為自對準插塞3 0的蝕刻終止層。 圖一中的自對準插塞3 0其中之兩個係做為電容4 0連接之節 點，另一自對準插塞3 0，則用以連接位元線。電容4 0包含 4 一底部電極（具半球狀晶粒的表面以增加表面積）4 0 A、 N/0(nitride/oxide)介電層40B及一填滿電容溝渠並包覆 底部電極的頂部電極4 0 C。電容4 0的形成係先沉積一節點 氧化層3 5，然後利用微影及蝕刻技術蝕刻出電容溝渠。接 _ 著，全面沉積第一導體層以做為底部電極4 0 A。再回填光 阻（未圖示），以進行化學/機械式研磨製程，用以去除電 · 容溝渠外的導體層，隨後，再回蝕刻節點氧化層3 5，以降 低電容溝渠外的節點氧化層3 5高度，用以得到額外電容面 積的冠形電容。接著去光阻後，再均勻一致性沉積電容介 電層4 0 B與最後回填另一導電層4 0 C以做為頂部電極即成圖 | 一之結構體.。此時電容結構已完成。 傳統上為使位元線接觸區可以精確的形成於兩個電容 之間，最安全的方式是上一層UV光阻，這種光阻具有較佳Page 5 475260 V. Description of the invention (2) * The typical process of the traditional CUB before the bit line contact area process is performed, as shown in Figure 1. Contains a plurality of complex gates 10 formed on a semiconductor substrate 5. The complex gates 10 have a silicon nitride spacer layer and a silicon nitride liner layer 15 covering the complex gates. 10 and the semiconductor substrate 5. -A thick first interconnect dielectric layer 20 is then overlaid on the silicon nitride liner layer 15 to provide a flat surface. The silicon nitride spacer and the silicon nitride capping layer on the polysilicon gate are used as the etch stop layer for the self-aligned plug 30. Two of the self-aligned plugs 30 in FIG. 1 serve as nodes connected by the capacitor 40, and the other self-aligned plug 30 is used to connect bit lines. The capacitor 40 includes 4 a bottom electrode (a surface with hemispherical grains to increase surface area) 4 0 A, a N / 0 (nitride / oxide) dielectric layer 40B, and a top electrode that fills the capacitor trench and covers the bottom electrode 4 0 C. The capacitor 40 is formed by first depositing a node oxide layer 35, and then etching the capacitor trench using lithography and etching techniques. Then, the first conductor layer is deposited as the bottom electrode 40 A in a comprehensive manner. Photoresist (not shown) is backfilled to perform a chemical / mechanical polishing process to remove the conductive layer outside the capacitor trench. Subsequently, the node oxide layer 35 is etched back to reduce the node oxidation outside the capacitor trench. Layer 35 height for a crown capacitor with extra capacitance area. After removing the photoresist, the capacitor dielectric layer 40B is uniformly and uniformly deposited, and finally another conductive layer 40C is backfilled as the top electrode to form a structure of the pattern. The capacitor structure is now complete. Traditionally, in order for the bit line contact area to be accurately formed between two capacitors, the safest way is to use an upper layer of UV photoresist. This photoresist has better

第6頁 475260 五、發明說明（3) 的均勻一致性，解析度高，以便可以在切斷電容之間相連 接的複晶矽層時可爭取更多的電容之間的空間以提高定義 位元線接觸洞的製程容忍度。不過，這種光阻價格高，較 不具競爭性，且仍有疊對誤差的問題，但若形成一般 I - 1 i ne光阻，其解析度較差，欲爭取更高的空間以提供定 義位元線接觸洞就會增加難度。但若兩電容之間的空間， 已因I - 1 i n e光阻微影一次而縮小，將進一步因此促使位元 線接觸洞的製程深寬比值的提高而增加了蝕刻的難度與因 位元線接觸區縮小而提高阻值等問題。 本發明的目的，因此，係為提高上述的製程誤差容忍 度的最大限度。 發明目的及概述： 本發明之一目的係提供一種DRAM記憶體位元線接觸洞的製 造方法。 本發明之另一目的係為解決習知CUB位元線接觸洞的 微影困難度，利用本發明的方法，可以提供更多的疊對誤 差邊限，且因製程的微影技術不再是非常關鍵，因此，可 以使用價格較低廉的I - 1 i n e光阻即可。 本發明揭露一種種電容在位元線下方CUB之DR AM製程 475260 五、發明說明（4) 中位元線接觸 本發明之方法 基板已形成電 結構’電容結 此外並有連接 係形成於第一 第一介 電容外 光阻圖 後施以 極，以 二介電 技術定 再予進 塞步驟 電層之 而以帽 案於頂 以濕式 電容介 層以提 義位元 行化學 區之形成方法，電容特別是指皇冠形電容。 至少包含以下步驟：首先供一半導體基板， 晶體結構與皇冠狀電容（crown capacitor) 構則分別形成於連接電晶體汲極之插塞上， 上述複數個電晶體之源極之插塞。上述結構 介電層中，此外，皇冠狀電容結構並突出於 上，頂部電極並自皇冠狀電容延伸至皇冠狀 簷將複數個皇冠狀電容相連接。接著，形成 部電極上，再以#刻切斷構帽詹之連接；之 蝕刻，以蝕刻該光阻下的帽簷部分之頂部電 電層為停止層；隨後再去光阻圖案；形成第 供一大致平坦的表面。再以光阻圖案及蝕刻 線接觸洞。最後回填金屬於位元線接觸洞， /機械式研磨製程以完成位元線接觸洞之填 發明詳細說明： 有鑑於如發明背景所述，習知技術之CUB製程中，為 得到額外電容面積，就得回钱刻節點氧化層，若以價格較 高的UV光阻，定義位元線接觸洞，對蝕刻而言會變得較容 易，而只剩下疊對誤差容忍度的問題。然而若以一般光阻 定義，則又因電容高度及電容溝渠外的導體層之限制，而 不但疊對誤差容忍度縮小，同時又增加了深寬比值Page 6 475260 V. Description of the invention (3) Uniform consistency and high resolution, so that when the polycrystalline silicon layer connected between the capacitors is cut, more space between the capacitors can be obtained to improve the definition Process tolerance of bit line contact holes. However, this type of photoresist is expensive, less competitive, and still has the problem of overlapping errors. However, if a general I-1 in ne photoresist is formed, its resolution is poor, and it is necessary to strive for more space to provide definition bits. Yuan line contact holes will increase the difficulty. However, if the space between the two capacitors has been reduced due to the photolithography of the I-1 ine photoresist once, it will further increase the process aspect ratio of the bit line contact hole and increase the difficulty of etching and the bit line. The contact area is reduced and the resistance is increased. The object of the present invention is therefore to maximize the tolerance of the above-mentioned process errors. Object and Summary of the Invention: One object of the present invention is to provide a method for manufacturing a bit line contact hole of a DRAM memory. Another object of the present invention is to solve the lithography difficulty of the conventional CUB bit line contact hole. By using the method of the present invention, more overlap error margin can be provided, and the lithography technology due to the manufacturing process is no longer It's very important, so you can use the cheaper I-1 ine photoresist. The present invention discloses a DR AM manufacturing process of CUB with capacitors under bit lines 475260. 5. Description of the invention (4) The method of the invention in which the bit lines contact the substrate has formed an electrical structure. The capacitor junction has a connection system formed in the first A method for forming a chemical region by applying a pole after the external photoresistance pattern of the first dielectric capacitor, and using a two-dielectric technique to determine the electric layer, and capping the wet capacitor dielectric layer to improve the bit-line chemical region. Capacitance, in particular, means a crown-shaped capacitor. At least the following steps are provided: first, a semiconductor substrate is provided, and a crystal structure and a crown capacitor structure are respectively formed on the plugs connected to the drain of the transistor, and the plugs of the source of the plurality of transistors are respectively formed. In the dielectric layer of the above-mentioned structure, in addition, the crown-shaped capacitor structure does not protrude above, and the top electrode extends from the crown-shaped capacitor to the crown-shaped eaves to connect a plurality of crown-shaped capacitors. Next, the electrodes on the part are formed, and then the connection of the cap is cut off with # engraving; the etching is to etch the top electrical layer of the brim part under the photoresist as the stop layer; then the photoresist pattern is removed; Roughly flat surface. Then contact the hole with a photoresist pattern and an etching line. Finally, backfill metal into the bit line contact hole. / Mechanical polishing process to complete the filling of the bit line contact hole. Detailed description of the invention: In view of the background of the invention, in the conventional CUB process, in order to obtain additional capacitance area, It is necessary to return the money to etch the node oxide layer. If a higher-priced UV photoresist is used to define the bit line contact hole, it will become easier for etching, and only the problem of stacking error tolerance will be left. However, if it is defined by general photoresistance, it is also limited by the height of the capacitor and the conductive layer outside the capacitor trench. Not only the tolerance of the stacking error is reduced, but the aspect ratio is also increased.

第8頁 475260 五、發明說明（5) (aspect ratio)，而提高了位元線接觸洞的製程誤差的風 波。 將清楚闡述，本發明問何解決習知 以下圖示及說明 技術的困境。 首先仍請參考圖一，圖中由複晶矽層所構成的頂部電 極4 0 C仍然互相連接，位元線接觸洞要形成，得先以光阻 圖案及蝕刻技術切斷皇冠狀電容結構之互為連接之帽簷 4 2，接著，去光阻後再回填内連線介電層，再利用兩電容 之間的空間，更正確的說是上述光阻圖案及蝕刻技術切斷 其連接後的空間才可以形成位元線接觸洞的區域。位元線 接觸洞偏向任一側，都有可能造成位元線接觸洞與頂部電 極4 0 C之間短路。因此，若能只犧牲一小部分的頂部電極 面積，例如將帽簷42清除，而換取更大的製程容忍度，應 屬值得。本發明的主要觀念，即在使兩電容間連接的帽簷 4 2 (複晶矽層），盡可能去除乾淨以爭取製程疊對誤差的容 忍度。 請請參考圖二所示的橫截面不意圖’形成一光阻圖案 5 0以裸露兩電容間連接的部分複晶矽層，再將裸露的複晶 矽層4 0 C去除。請注意本發明此一步驟的特色是不需使用 價格特別高的UV光阻，只要使用適用於I - 1 i ne的光阻即 可。如此便可以降低成本。此外，本步驟的光阻圖案的微Page 8 475260 V. Description of the invention (5) (aspect ratio), which improves the process error of the bit line contact hole. It will be clearly explained how the present invention solves the conventional problems and illustrates the technical difficulties. First, please refer to FIG. 1. In the figure, the top electrode 40 C composed of a polycrystalline silicon layer is still connected to each other. To form a bit line contact hole, the crown-shaped capacitor structure must be cut by photoresist patterns and etching techniques. The eaves 42 are connected to each other. Then, after the photoresist is removed, the interconnecting dielectric layer is backfilled, and the space between the two capacitors is used. More precisely, the above photoresist pattern and etching technology cut off the connection. Space can form the area where the bit line contacts the hole. The bit line contact hole is biased to either side, which may cause a short circuit between the bit line contact hole and the top electrode 40 C. Therefore, it is worthwhile to sacrifice only a small portion of the top electrode area, such as removing the brim 42 in exchange for greater process tolerance. The main idea of the present invention is that the brim 4 2 (polycrystalline silicon layer) connecting the two capacitors is removed as much as possible in order to strive for tolerance of errors in the process stack. Please refer to the cross section shown in FIG. 2 for the purpose of forming a photoresist pattern 50 to expose a part of the polycrystalline silicon layer connected between the two capacitors, and then remove the exposed polycrystalline silicon layer 40C. Please note that the feature of this step of the present invention is that there is no need to use a particularly expensive UV photoresist, as long as a photoresist suitable for I-1 in is used. This reduces costs. In addition, the photoresist pattern

第9頁 475260 五、發明說明（6) 影技術，由於並不需要克意在本步驟中就將兩電容之間連 接的複晶矽層一次清除，因此，疊對誤差的困難度降低。Page 9 475260 V. Description of the invention (6) Since the shadow technology does not need to remove the polycrystalline silicon layer connected between the two capacitors at one time in this step, the difficulty of stacking error is reduced.

請參考圖三所示的橫截面示意圖，圖二步驟，由於去 除的複晶矽層所產生的空間未克意提高，因此，本步驟可 以解決這個難題。本步驟係使用濕式蝕刻的方法回蝕刻， 以電容介電層為蝕刻終止層，蝕刻光阻圖案5 0下的複晶矽 層，以增加額外的空間4 0 D。為防止電容介電層被過度蝕 刻，本步驟可以選擇ΝΗ40Η或HN03/HF其中之一，或其組 合，做為蝕刻複晶矽層的濕式蝕刻溶液。當然上述之頂部 電極材料並不限定是複晶矽層，以金屬材料也可以，例如 I呂銅、Ti/ TiN。若是上述金屬材料，可以以銨水和過氧 化氫為主之APM溶液或硫酸和銨水為主之HPM其中之一，或 其組合做為蝕刻液。 接著去除光阻圖案，請參考圖四所示的橫截面示意 圖，再全面沉積内連線介電層6 0。内連線介電層6 0係氧化 矽層或S0G層或TE0S層其中之一。圖示中的40D便是提高疊 對誤差容忍度的量。Please refer to the schematic diagram of the cross section shown in Fig. 3. In the step of Fig. 2, because the space generated by the removed polycrystalline silicon layer is not improved, this step can solve this problem. In this step, wet etching is used to etch back, using the capacitor dielectric layer as an etch stop layer, and etching the polycrystalline silicon layer under the photoresist pattern 50 to increase the extra space 40 D. In order to prevent the capacitor dielectric layer from being over-etched, one of NΗ40Η or HN03 / HF, or a combination thereof can be selected as a wet etching solution for etching the polycrystalline silicon layer in this step. Of course, the above-mentioned top electrode material is not limited to a polycrystalline silicon layer, and a metal material may also be used, such as copper and Ti / TiN. For the above-mentioned metal materials, one of the APM solution mainly composed of ammonium water and hydrogen peroxide, or the HPM mainly composed of sulfuric acid and ammonium water, or a combination thereof can be used as the etching solution. Next, the photoresist pattern is removed. Please refer to the schematic cross-sectional view shown in FIG. The interconnect dielectric layer 60 is one of a silicon oxide layer, a SOG layer, or a TE0S layer. The 40D in the figure is the amount to increase the tolerance of the overlap error.

請參考圖五，接著，再利用光阻圖案形成於内連線介 電層6 0上以定義位元線接觸洞的位置。並以光阻圖案為罩 幕，施以姓刻内連線介電層6 0的步驟及回填金屬7 0，以形 成位元線接觸區等步驟，一如一般習知技術，再此因此不 475260 五、發明說明（7) · 再贅述。 因此，應用本發明的方法具有以下優點： (1 )製程簡單，比傳統方法幾乎只只多了一道濕式回 蝕刻步驟，就可以有效增加疊對誤差的製程容忍度。 - (2 )切斷電容間相連接的複晶矽層時，光阻圖案可以 允許使用較低廉的I - 1 i ne光阻，代替成本相對高的UV光 阻。因此提高了競爭力。 以上所述僅為本發明之較佳實施例而已，並非用以限 定本發明之申請專利範圍；凡其它未脫離本發明所揭示之 精神下所完成之等效改變或修飾，均應包含在下述之申請 專利範圍内。Please refer to FIG. 5. Then, a photoresist pattern is formed on the interconnect dielectric layer 60 to define the position of the bit line contact hole. The photoresist pattern is used as a mask, and the steps of inscribing the dielectric layer 60 and the backfilling of the metal 70 to form the bit line contact area are performed as usual. 475260 V. Description of Invention (7) · Repeated description. Therefore, applying the method of the present invention has the following advantages: (1) The process is simple, and there is only one wet etch-back step compared with the traditional method, which can effectively increase the tolerance of the process of overlapping errors. -(2) When the polycrystalline silicon layer connected between the capacitors is cut, the photoresist pattern can allow the use of a less expensive I-1 in ne photoresistor instead of a relatively high cost UV photoresistor. This increases competitiveness. The above are merely preferred embodiments of the present invention, and are not intended to limit the scope of patent application for the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention shall be included in the following Within the scope of patent application.

第11頁 475260 圖式簡單說明 本發明的較佳實施例將於往後之說明文字中輔以下列 圖形做更詳細的闡述： 圖一顯示用以進行cum立元線接觸洞準備之橫截面 圖，其中cub中之電容係帽簷相連接之皇冠形電容。 圖 二 顯 示 形 成 光阻 圖 案 及 姓 刻 技 術 以切斷 上述相連 接 之 帽 簷 部 分 J 圖 二 顯 示 施 以 濕式 刻 光 阻 圖 案 下 之複晶 石夕層以增 加 疊 對 誤 差 之 容 忍 度 之橫 截 面 示 意 圖 〇 圖 四 顯 示 在 去 除光 阻 圖 案 後 再 形 成 内連線 介電層後 的 橫 截 面 示 意 圖 〇 圖 五 顯 示 位 元 線接 觸 洞 形 成 並 回 填 金屬後 的橫截面 意 圖 0 圖 號 對 昭 表 ·· 半 導 體 基 板 5 複 晶 閘 極 結 構 10 氮 化 矽 襯 裡 層 15 第 一 内 連 線 介 電 層 20 對 準 插 塞 30 々/Γ 即 點 氧 化 層 35 底 部 電 極 40A 電 容 介 電 層 40B 頂 部 電 極 40C 帽 簷 42 光 阻 圖 案 50 内 連 線 介 電 層 60 金 屬 層 70Page 475260 Schematic illustration of the preferred embodiment of the present invention will be explained in more detail in the following explanatory text with the following figures: Figure 1 shows a cross-sectional view of the preparation of the cum Li line contact hole The capacitor in the cub is a crown-shaped capacitor connected to the brim. Figure 2 shows the cross-section of forming a photoresist pattern and engraving technique to cut off the connected brim part J Figure 2 shows a polycrystalline stone layer under a wet-etched photoresist pattern to increase the tolerance of overlapping errors Schematic diagram. Figure 4 shows the cross-section diagram after the photoresist pattern is removed and then the interconnect dielectric layer is formed. Figure 5 shows the cross-section intent after the bit line contact hole is formed and the metal is backfilled. Semiconductor substrate 5 Compound gate structure 10 Silicon nitride liner 15 First interconnect dielectric layer 20 Alignment plug 30 々 / Γ Point oxide layer 35 Bottom electrode 40A Capacitor dielectric layer 40B Top electrode 40C Cap eaves 42 Photoresist pattern 50 Interconnect dielectric layer 60 Metal layer 70

第12頁Page 12

Claims (1)

475260 六、申請專利範圍 1. 一種電容在位元線下方之D R A Μ製程中位元線接觸區之 形成方法，該方法至少包含以下步驟： 提供一半導體基板，該半導體基板已形成複數個電晶 體結構與複數個皇冠狀電容（c r 〇 w n c a p a c i t 〇 r )結構，該 複數個皇冠狀電容結構分別形成於連接上述複數個電晶體 之汲極上，此外並有連接上述複數個電晶體之源極之插 塞，該複數個電晶體結構、上述之所有插塞、該複數個皇 冠狀電容結構係形成於第一介電層之中，此外，該複數個 皇冠狀電容結構並突出於該第一介電層之上，該頂部電極 /電容介電層底部電極除形成電容外，並形成於該複數個 皇冠狀電容結構之外部側壁及帽簷，而使得該複數個皇冠 狀電容結構互為連接之； 形成第一光阻圖案於該頂部電極上，用以切斷該皇冠 狀電容結構帽簷之連接； 施以蝕刻技術，蝕刻該頂部電極，以該光阻圖案為罩 幕； 施以濕式蝕刻，以蝕刻該第一光阻下的帽簷部分之頂 部電極，以該電容介電層為停止層； 去除該第一光阻圖案； 形成第二介電層於所有區域； 形成第二光阻圖案於該第二介電層上，用以定義位元 線接觸洞，該位元線接觸洞係用以連接上述複數個電晶體 之源極連接插塞； 施以蝕刻技術，以蝕刻該第一介電層及該第二介電475260 VI. Application Patent Scope 1. A method for forming a bit line contact area in a DRA M process in which a capacitor is below a bit line. The method includes at least the following steps: A semiconductor substrate is provided, and the semiconductor substrate has formed a plurality of transistors. Structure and a plurality of crown-shaped capacitor structures (cr 〇wncapacit 〇r) structure, the plurality of crown-shaped capacitor structures are respectively formed on the drain electrodes connected to the plurality of transistors, in addition to the source electrodes connected to the plurality of transistors Plugs, the plurality of transistor structures, all the plugs described above, and the plurality of crown-shaped capacitor structures are formed in the first dielectric layer. In addition, the plurality of crown-shaped capacitor structures do not protrude from the first dielectric layer. Above the layer, the top electrode / capacitive dielectric layer bottom electrode, in addition to forming a capacitor, is formed on the outer side walls and brims of the plurality of crown-shaped capacitor structures, so that the plurality of crown-shaped capacitor structures are connected to each other; A first photoresist pattern on the top electrode to cut off the connection of the crown-shaped capacitor structure brim; applying an etching technique , Etching the top electrode, using the photoresist pattern as a mask; applying wet etching to etch the top electrode of the brim portion under the first photoresist, and using the capacitor dielectric layer as a stop layer; removing the first Photoresist pattern; forming a second dielectric layer on all regions; forming a second photoresist pattern on the second dielectric layer to define a bit line contact hole, the bit line contact hole is used to connect the above-mentioned plural A source connection plug of a transistor; an etching technique is applied to etch the first dielectric layer and the second dielectric 第13頁 475260 六、申請專利範圍 層：及 回填金屬層以形成位元線接觸。 2 ·如申請專利範圍第1項之方法，其中上述之第一介電 層、及第二介電層係氧化矽層或S0G層或TE0S層其中之 3. 如申請專利範圍第1項之方法，其中上述之第一介電層 更包含一節點氧化層。 4. 如申請專利範圍第1項之方法，其中上述之頂部電極係 選自複晶^夕層。 5. 如申請專利範圍第4項之方法，其中上述之濕式蝕刻係 以ΝΗ40Η或HN03/HF其中之一，或其組合，做為蝕刻複晶矽 層的濕式#刻溶液。 6. 如申請專利範圍第1項之方法，其中上述之頂部電極係 選自金屬材料。 7. 如申請專利範圍第6項之方法，其中上述之之濕式蝕刻 係以銨水和過氧化氫為主之APM溶液或硫酸和銨水為主之 HP Μ其中之一，或其組合，以做為姓刻金屬材料的濕式餘 刻溶液。Page 13 475260 6. Scope of patent application Layer: and backfill metal layer to form bit line contact. 2 · The method according to item 1 of the patent application, wherein the first dielectric layer and the second dielectric layer are a silicon oxide layer or a SOG layer or a TE0S layer. 3. The method according to item 1 of the patent application The first dielectric layer further includes a node oxide layer. 4. The method according to item 1 of the patent application range, wherein the top electrode is selected from a polycrystalline layer. 5. The method according to item 4 of the patent application, wherein the above-mentioned wet etching is one of NΗ40Η or HN03 / HF, or a combination thereof, as a wet #etching solution for etching the polycrystalline silicon layer. 6. The method according to item 1 of the patent application, wherein the top electrode is selected from metal materials. 7. The method according to item 6 of the patent application, wherein the above-mentioned wet etching is one of an APM solution based on ammonium water and hydrogen peroxide or HP MH based on sulfuric acid and ammonium water, or a combination thereof, It is used as a wet afterglow solution for engraving metal materials. 第14頁 475260 六、申請專利範圍 8.如申請專利範圍第1項之方法，其中上述之電容介電層 係選自與該頂部電極有蝕刻選擇比之材質。Page 14 475260 6. Scope of patent application 8. The method of the first scope of patent application, wherein the above-mentioned capacitor dielectric layer is selected from materials having an etching selection ratio with the top electrode. 第15頁Page 15