473909 案號 89113118 五、發明說明（1) 本發明係關於一種在半導體晶圓中形成深溝$ trench)之方法，尤指一種提高半導體積體電路=程;= 關遮蔽層（masking layer )對半導體基底餘刻選擇比有 (s e 1 e c t i v i t y )之蝕刻方法者。 、 在製造積體電路於半導體晶圓中時，如何提曰 面每單位面積之裝置數量，長久以來一直為業界努$片表 標。而隨著半導體積體電路集積度之持續增加趨勢，^I 來因為記憶體積集度急速增加，電容器為保持或加大2 & 量’半導體製造業者多已採用半導體基底中形成深溝準奋 (Deep Trench)的電容器方式，而溝渠之深寬比 ratio )越來越大（亦即溝渠之鉛直尺寸已遠大於水 寸）。不過，伴隨者深寬比之增加，吾人欲取得較大之餘 刻比值’在製程技術上之困難度日益增加。熟習此技藝之 人士都知道一般製造深溝渠式電容器或其他深溝渠式&件 之方法’该等製造方法需對半導體基底（即石夕晶^ )進行 钱刻製程，以形成一溝渠。習知技術如美國專利第4 1 3 9 442號和第4, 211，582號等案業已大量利用電漿（pla^ma )’ 或活性離子（react ive ion)蝕刻技術來形成深溝渠式半導 體元件。在進行溝渠之蝕刻之前，都會先在半導體晶圓表 面形成一層或若干層緊貼晶圓表面之遮蔽層。早期主要皆 以光阻層做為遮蔽層，現業界則已多改用氧化石夕等介電^ 做為遮蔽層。以介電質做為遮蔽層，然後形成深溝渠，其 做法是先於半導體基底表面形成遮蔽層（masking Uyei^' 作為遮蔽罩幕，然後以乾蝕刻製程，例如是電漿蝕刻，對 體基底進行蝕刻製程以形成深溝渠。電漿的形成原理473909 Case No. 89113118 V. Description of the invention (1) The present invention relates to a method for forming a deep trench in a semiconductor wafer, in particular to improve the semiconductor integrated circuit = the process; = the shielding layer (masking layer) to the semiconductor The substrate is selected with an etching method having a ratio of (se 1 ectivity). When manufacturing integrated circuits in semiconductor wafers, how to mention the number of devices per unit area has long been a benchmark for the industry. With the continuous increase in the concentration of semiconductor integrated circuits, ^ I because of the rapid increase in memory volume concentration, capacitors in order to maintain or increase the volume of semiconductor manufacturers have been using semiconductor substrates to form deep trenches. Deep Trench) capacitor, and the ratio of depth to width of the trench is getting larger and larger (that is, the vertical dimension of the trench is much larger than the water inch). However, with the increase of the aspect ratio, it is increasingly difficult for us to obtain a larger value of the remaining ratio 'in terms of process technology. Those who are familiar with this technique know the general method of manufacturing deep trench capacitors or other deep trench & parts. These manufacturing methods require a semiconductor substrate (that is, Shi Xijing ^) to be engraved to form a trench. Conventional technologies such as U.S. Patent Nos. 4 1 9 9 442 and 4, 211, 582 have used a large number of plasma (reactive plasma) etching techniques to form deep trench semiconductors. element. Before the trench is etched, one or more shielding layers are formed on the surface of the semiconductor wafer. In the early days, a photoresist layer was mainly used as a shielding layer, and now the industry has changed to a dielectric layer such as stone oxide as a shielding layer. Dielectrics are used as a shielding layer, and then deep trenches are formed. The method is to form a masking layer (masking Uyei ^ ') as a mask on the surface of the semiconductor substrate, and then use a dry etching process, such as plasma etching, to the bulk substrate. An etching process is performed to form deep trenches. Principles of plasma formation
第4頁 473909 修正 五 口 疋 中 分 深 I虫 漿 是 是 的 間 面 成 除 可 或 應 漿 遮 展 深 量 量 層 須 齒虎89113118_年月 日 發明說明（2) 萄一，處於適當低壓狀態下的氣體被施以電壓時，原本 性的氣體分子會被激發成各種不同之帶 ^ 子或帶負電荷的電子，此即為電裝成 用到二種不同型態的電漿’其—是反應性離子 到（RIE)，用於蝕刻遮蔽層，以定義遮蔽層；其二 用於與半導體基底反應以形成深溝渠。由於電 虱體分子處於崩潰狀態下的一種現象，因此電: 2導體。當對電漿施以電壓時，如果對電漿施以電壓 的電J為陰極時’帶正電核的離子會因為電聚與電極板 ' 差而加速，轟擊置於電極板上的半導體基底表 私電水離子即與遮蔽層進行化學反應’產生揮發性 二:：被真空系統抽離’此藉著結合化學與物理二種去 的㈣方法，即為反應性離子餘刻。同時， 冬^應的氣體解離成對半導體基底具有反應性的原子團 ',、二错著原子團或原子與半導體基底所含的矽進行反 姓列 發性的生成物，而被真空系統抽離，此即為電 蔽二，、習知技術即是採用電漿蝕刻以形成深溝渠，可是 薄：=為反應性離子㈣的緣故，使遮蔽層的厚度 ，爐^ ^半導體記憶裝置尺寸規袼朝微細化技術趨勢發 、、盖泪=在度及記憶容量必須提昇，在0. 1 75微米以下之 =^半導體記憶體製程技術，為增加電容器之電容 :^潭渠的深度勢必越來越深，才可維持應有之電容Page 4 473909 Amendment to the depth of I. larvae in five mouthfuls of maggots. Insect surface can be removed or should be applied to cover the depth of the measuring layer. Tooth tiger 89113118_Invention description (2) Grape, at an appropriate low pressure. When a voltage is applied to the gas in the state, the original gas molecules will be excited into various different bands or negatively charged electrons. This is the electric assembly of two different types of plasma. — Is reactive ion to (RIE), used to etch the masking layer to define the masking layer; the second is used to react with the semiconductor substrate to form deep trenches. Due to the phenomenon that the electrical lice body molecules are in a collapsed state, electricity: 2 conductors. When a voltage is applied to the plasma, if the voltage J applied to the plasma is the cathode, the ions with a positive charge will be accelerated due to the difference between the electroconcentration and the electrode plate, and bombard the semiconductor substrate placed on the electrode plate. The surface ionized water ion chemically reacts with the shielding layer to generate volatility 2 :: It is extracted by the vacuum system. By combining the two methods of chemistry and physics, it is the reactive ion. At the same time, the winter gas is dissociated into atomic groups that are reactive to the semiconductor substrate, and two staggered atomic groups or atoms are formed by the anti-lasting formation of the silicon and the silicon contained in the semiconductor substrate. This is Electro-Shield 2. The conventional technique is to use plasma etching to form deep trenches, but it is thin: = For the sake of reactive ion plutonium, the thickness of the shielding layer, the size of the semiconductor memory device ^ ^ Trends in microfabrication technology, tears and tears = the degree and memory capacity must be improved, below 0.175 microns = ^ semiconductor memory system technology, in order to increase the capacitor's capacitance: ^ Tanqu's depth is bound to become deeper and deeper In order to maintain the proper capacitance
第5頁 對半ϋ ϊ Ϊ #刻,ί ’ ^不增加遮蔽層之厚度，遮蔽 不斷士后土底之蝕刻選擇比將明顯不足，以致遮蔽層必 才可使遮蔽層達到保護基底的目的，然此_ .ΨΛτιιι^ιιι· . 1 __丨" - _ ^ 473909 五、發明說明（3) J9113U8 月 曰 修正 缺失已成為半導體製造技 ^勺 曰在克服前揭缺失 選擇比及低破壞性蝕刻技 本發明主要於半導體 層，然後於形成深溝渠前 ，之圓周邊緣定義一寬度 %可於後續形成深溝渠之 層的電漿離子，不但可降 ^濺擊速率，降低遮蔽層 :導體基底蝕刻選擇比， 曰加遮蔽層的厚度。 術之一大障礙。因此，本發明之 亚突破目前之技術瓶頸，提供高 術予半導體積體電路製程。阿 基底上先形成一介電層作為遮蔽 ，在定義遮蔽層的同時，亦於晶 遠大於深溝渠的導電環，此導電 電漿蝕刻製魟中，捕捉濺擊遮蔽 低其他區威之電聚離子對遮蔽層 之蝕刻率，同時可提开遮蔽層對 因此要形成更深的溝渠可不必再 麵 第 圖至第二圖與第五圖係代表本發明實施例中形成深溝 渠之主要步驟之剖面圖。 第四圖係顯示本發明實施例於晶圓邊緣形成導電環，該導 電環所在的位置。 符號說明 100 〜晶圓； 105 〜基底； 106 〜墊氧化矽層； 108 〜墊氮化矽層； 110 〜遮敝層； 120 〜光阻層； 123 〜導電環； 125 ' 1 3 0〜孔洞； 127 ' 132〜溝渠； 140 ' M2〜深溝渠 實施例 上 請參考第一圖，首先，提供基底1〇5，此基底丨〇5為一半導 體材質，例如：矽或鍺，其形成方式則有磊晶或 有矽等，為方便說明，在此以一 P型矽基底為 、、、豕層 依序於基底1〇5表面以氧化製程形成厚度為3〇 $ °接箸， 墊氧化矽層（pad oxide) 1 06，再由化學某— β〇〇埃Page 5 刻 ϋ 刻 ί # 刻, ί '^ Without increasing the thickness of the shielding layer, the etching selection ratio of the soil bottom after continuous shielding will be significantly insufficient, so that the shielding layer must enable the shielding layer to protect the substrate. However, this _.ΨΛτιιι ^ ιιι ·. 1 __ 丨 "-_ ^ 473909 V. Description of the invention (3) J9113U August said that the lack of correction has become a semiconductor manufacturing technology. ^ The lack of selection ratio and low destructiveness before it is overcome Etching technology The present invention is mainly applied to a semiconductor layer, and then before forming a deep trench, a peripheral edge defines a width% of plasma ions that can be used in the subsequent formation of a deep trench, which can not only reduce the sputtering rate, but also the shielding layer: the conductor substrate The etching selection ratio is the thickness of the shielding layer. One of the major obstacles to surgery. Therefore, the present invention breaks through the current technical bottleneck and provides advanced technology for semiconductor integrated circuit manufacturing processes. A dielectric layer is first formed as a shield on the substrate. While defining the shielding layer, it is also on a conductive ring with a crystal that is much larger than a deep trench. This conductive plasma is used to etch the puppet to capture the splashing and shielding of other regions. The etching rate of the ion pair masking layer, and the masking layer pair can be lifted at the same time. Therefore, it is not necessary to face the trenches to form deeper trenches. Figures 2 to 5 and 5 are cross sections representing the main steps of forming a deep trench in the embodiment of the present invention. Illustration. The fourth figure shows an embodiment of the present invention forming a conductive ring on the edge of the wafer, where the conductive ring is located. 100 ~ wafer; 105 ~ substrate; 106 ~ pad silicon oxide layer; 108 ~ pad silicon nitride layer; 110 ~ mask layer; 120 ~ photoresist layer; 123 ~ conductive ring; 125 '1 3 0 ~ hole 127 '132 ~ ditch; 140' M2 ~ deep ditch. Please refer to the first figure in the embodiment. First, a substrate 105 is provided. This substrate is a semiconductor material, such as silicon or germanium. The formation method is as follows: There are epitaxial or silicon, etc. For the convenience of explanation, a P-type silicon substrate is used as the first, second, and third layers on the 105 surface of the substrate in order to form a thickness of 30 $ through an oxidation process. The silicon oxide is then padd. Layer (pad oxide) 1 06, and then by a chemical — β〇〇angstrom
—— >氣洗積决子之 473909 修正 曰 案號 89113118 圖式簡單說明 厚度為1 6 0 0〜30 0 0埃的墊氮化矽層（pad nitride)108。然 後’形成尽度約8，000至1〇，〇〇〇埃的遮蔽層（masking layer) 110於墊氮化矽層1〇8表面，此遮蔽層11〇可以是由 化學氣相沈積法（CVD)、常壓化學氣相沈積法（APCVD)、次 常壓化學氣相沈積法（SAPCVD)、低壓化學氣相沈積法 (LPCVD)、電漿加強型化學氣相沈積法（pECVD)或高密度電 漿化學氣相沈積法（HDPCVD)等方法同步摻雜硼離子之硼石夕 玻璃（BSG)層所形成。接著，於遮蔽層n〇表面形成光阻層 1 2 0。在本圖中，區域b為晶圓丨〇 〇表面之圓周邊緣區域， 區域A則為晶圓1 〇 〇表面除區域b的其他區域。 請參考第二圖，定義光阻層12〇，在區域A形成寬度^之孔 洞1 25 ’在區域β形成寬度“之溝渠127以露出遮蔽層丨丨〇。 前述孔洞125之寬度h約為1 5 0 0〜250 0埃，溝渠127之寬 ^乙2約為2至3毫米（mm)，因此，寬度l2遠大於寬度l。 明苓考第二圖’以習知之蝕刻製程，依序去除孔洞丨2 5及 溝渠127正下方之遮蔽層11〇、墊氮化矽層1〇8與墊氧化矽 層106 ’在區域a形成孔洞13〇，在區域b形成溝渠132，露 出其下之基底105表面，此區域b曝露出之基底1〇5表面即 形成，電環123，此導電環123於晶圓1〇〇上的相關位置請 f考第四圖。前述之部分遮蔽層110、墊氮化矽層108、墊 氧，矽層丨〇 6之去除，可以是由非等向性之電漿蝕刻製程 所完成。接著，去除光阻層12〇。 請5考第五圖，以遮蔽層110為遮蔽罩幕（mask)，實施蝕 刻製程，例如可以是電漿蝕刻製程，去除孔洞丨3〇與溝渠 方之部分基底105，於區域A形成深溝渠140，於區域—— > 473909 amendment of air wash product deciduous case No. 89113118 Simple illustration of the diagram The thickness of the silicon nitride layer (pad nitride) 108 of 16 0 ~ 30 0 0 angstroms. Then, a masking layer 110 is formed to the extent of about 8,000 to 10,000 angstroms on the surface of the pad silicon nitride layer 108. The masking layer 11 may be formed by a chemical vapor deposition method ( CVD), atmospheric pressure chemical vapor deposition (APCVD), sub-normal pressure chemical vapor deposition (SAPCVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (pECVD) or high Boron borosilicate glass (BSG) layers doped with boron ions simultaneously by methods such as density plasma chemical vapor deposition (HDPCVD). Next, a photoresist layer 12 is formed on the surface of the shielding layer no. In this figure, the area b is the peripheral edge area of the wafer surface, and the area A is the other area of the wafer surface except the area b. Referring to the second figure, the photoresist layer 12 is defined, and a hole 1 of width ^ is formed in area A 25 'a trench 127 of width' is formed in area β to expose the shielding layer. The width h of the aforementioned hole 125 is approximately 1 50 ~ 250 0 Angstroms, the width of the trench 127 ^ 2 is about 2 to 3 millimeters (mm), so the width 12 is much larger than the width 1. The second picture of Mingling's test is sequentially removed by the conventional etching process. Holes 丨 25 and the shielding layer 110, directly under the trench 127, the silicon nitride layer 108, and the silicon oxide layer 106 'form a hole 13 in area a, and a trench 132 in area b, exposing the underlying substrate 105 surface, the exposed surface of the substrate 105 in this area b is formed, and the electric ring 123, the relevant position of the conductive ring 123 on the wafer 100, please refer to the fourth figure. The aforementioned part of the shielding layer 110, the pad The removal of the silicon nitride layer 108, padding oxygen, and silicon layer 106 can be performed by an anisotropic plasma etching process. Then, the photoresist layer 12 is removed. Please refer to the fifth figure for shielding The layer 110 is a mask, and an etching process is performed, for example, a plasma etching process may be performed to remove holes and trenches. 30 A square part of the base 105 forms a deep trench 140 in the area A, and in the area
第8頁 473909 --案號 89113118 --^-3-a_ 圖式簡單說明 B形成深溝渠1 4 2，其中深溝渠1 4 〇係包含孔洞1 3 0，深溝渠 1 4 2係包含溝渠1 3 2，至此即完成深溝渠1 4 0的製作。 在進行前述之電聚#刻製程以形成深溝渠1 4 2時，因電漿 蝕刻製程所產生之分子團或分子撞擊基底1 0 5並產生揮發 性氣體以後，即形成深溝渠140與深溝渠142，遮蔽層110 也同時因為受到電漿所產生其他離子的反應性離子蝕刻， 發生化學反應而導致部分之遮蔽層11 0也被蝕刻移除，此 種遮蔽層11 0被蝕刻移除情形會因為深溝渠1 40之深度的加 深，蝕刻時間越長而更形嚴重。因此，習知技術是以加厚 遮蔽層1 1 0之厚度來克服，才足以抵擋電子的濺擊，以達 到遮蔽的效果，以便保護深溝渠1 4 0周圍的基底1 〇 5。為克 服前述之問題，解決之道厥為增加遮蔽層1 1 0之厚度或降 低該遮蔽層1 1 〇之蝕刻率。前者為目前業界普遍之做法， 但此做法易增加製程時間與生產成本；本發明則採用後者 的方法，利用部分外露之半導體基底1〇5的表面以形成導 電環123捕捉電漿產生之電子，改變電場之分布，使遮蔽 層上方之電場降低，因此可減少電漿離子對遮蔽層之濺擊 速率，降低該遮蔽層110之蝕刻率，進而提高遮蔽層n〇對 基底=5之蝕刻選擇比。導電環123的位置、大小與形狀， 除本實施例所提到之形成於晶圓丨〇 〇圓周邊緣的環狀^以 外丄其功能主要在捕捉濺擊遮蔽層11〇之離子，其位置不 的圓周邊緣，可在晶圓1〇〇表面的任何位置，· …Γ ;大可小，可視實際需要而$ ;其形狀也不-定 疋ί衣狀，可以為其他形狀。 驗，證，實施電漿飯刻形成深溝渠以後，結果如Page 8 473909-Case No. 89113118-^-3-a_ The diagram briefly illustrates that B forms a deep trench 1 4 2, where the deep trench 1 4 0 includes a hole 1 3 0 and the deep trench 1 4 2 includes a trench 1 32, so far, the production of deep trenches 140 is completed. When the aforementioned electro-polymerization # engraving process is performed to form the deep trenches 1 2 4, after the molecular clusters or molecules generated by the plasma etching process hit the substrate 105 and generate volatile gases, deep trenches 140 and deep trenches are formed. 142, the masking layer 110 is also etched by reactive ion etching of other ions generated by the plasma, and a part of the masking layer 110 is also removed by chemical reaction. Such a masking layer 110 may be removed by etching. As the depth of the deep trenches 140 increases, the longer the etching time becomes, the more severe it becomes. Therefore, the conventional technique is to overcome the problem by thickening the thickness of the shielding layer 110, which is enough to resist the splash of the electrons, so as to achieve the shielding effect, so as to protect the substrate 105 around the deep trench 140. In order to overcome the foregoing problems, the solution is to increase the thickness of the shielding layer 110 or reduce the etching rate of the shielding layer 110. The former is a common practice in the industry at present, but this method is easy to increase process time and production cost; the present invention uses the latter method to use a part of the exposed surface of the semiconductor substrate 105 to form a conductive ring 123 to capture the electrons generated by the plasma. Changing the distribution of the electric field reduces the electric field above the shielding layer, so it can reduce the sputtering rate of plasma ions on the shielding layer, reduce the etching rate of the shielding layer 110, and then increase the etching selection ratio of the shielding layer n0 to the substrate = 5 . The position, size, and shape of the conductive ring 123, except for the ring ^ formed on the circumferential edge of the wafer mentioned in this embodiment, its function is mainly to capture the ions of the splash shielding layer 110, and its position is not The circumferential edge can be anywhere on the 100 surface of the wafer,… Γ; large or small, depending on actual needs; its shape is also not fixed-shaped, and can be other shapes. After the inspection, verification, and implementation of plasma engraving to form a deep trench, the results are as follows
ilHi 第9頁 473909 -......89M3U8^_年月日_修正 __ 圖式簡單說明 下： 未於晶圓1 0 0表面形成導電層1 2 3的晶圓，於區域A (晶圓中 間部分）形成深溝渠1 4 0 (深度6 · 8埃）以後，其殘留遮蔽層 11 0之厚度為2 0 3 5埃；於區域B (晶圓邊緣）形成深溝渠 1 4 2 (珠度6. 7埃）以後，其殘留遮蔽層11 0之厚度為1 〇 2 0 埃。 於^圓| 0 0表面形成導電層1 2 3的晶圓，於區域A (晶圓中間 部f)形成深溝渠丨4〇(深度7· 1埃）以後，其殘留遮蔽層110 之厚ί為4 160埃；當於區域16(晶圓邊緣）形成深溝渠 1 4 2 (/木度7 · 1埃）以後，其殘留遮蔽層1 1 0之厚度為5 0 0 0 埃。由此可見，形成深溝渠140與深溝渠142以後，有導電 fni:3曰的m晶圓1〇0，其殘留之遮蔽層110比無導電層123者厚 間部分）〜49〇%(晶圓邊緣）。可見形成導電層 123確貝可減少遮蔽層11〇的厚度。 並非^ I ^發明已以較佳實施例揭露於上揭說明中，然其 明之精神和ΙίΓ月二任何熟習此技藝者，在不脫離本發 之權利範附等效變更與修改。0此本發明 田 灸附之申凊專利範圍中所界定者為準。ilHi Page 9 473909 -... 89M3U8 ^ _year month day_correction__ The diagram is briefly explained: The wafer with no conductive layer 1 2 3 formed on the surface of wafer 1 0 0 is located in area A ( After the deep trench 1 4 0 (depth 6 · 8 angstroms) is formed, the thickness of the remaining shielding layer 110 is 2 0 3 5 angstroms; a deep trench 1 4 2 ( After the sphericity is 6.7 angstroms), the thickness of the remaining shielding layer 110 is 1020 angstroms. A wafer with a conductive layer 1 2 3 is formed on the surface of the circle | 0 0, and a deep trench is formed in the area A (the middle portion of the wafer f). The thickness of the remaining shielding layer 110 is 40. It is 4 160 angstroms; when a deep trench 1 4 2 (/ woodiness 7 · 1 angstrom) is formed in the region 16 (wafer edge), the thickness of the remaining shielding layer 1 1 0 is 50 angstroms. It can be seen that after the deep trench 140 and the deep trench 142 are formed, there are conductive fni: 3 m wafers 100, and the remaining shielding layer 110 is thicker than those without the conductive layer 123) ~ 49% (crystalline Round edges). It can be seen that forming the conductive layer 123 can reduce the thickness of the shielding layer 110. It is not that the invention has been disclosed in the above description with a preferred embodiment, but the spirit of the invention and anyone familiar with the art on the second day of the present invention will be accompanied by equivalent changes and modifications without departing from the scope of rights of the present invention. 0This invention is defined in the scope of patent application attached to Tian Moxibustion.
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