472387 68〇5twf.doc/008 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（f ) 本發明是有關於一種記憶元件的製造法，且特別是有 關於一種靜態隨機存取記憶（Static Random Access Memory，SRAM)元件的製造方法。 靜態隨機存取記憶是半導體記憶體中處理速度非常快 的一種記憶體。依照設計的方式，靜態隨機存取記憶體之 記憶胞可以由四個電晶體與兩個電阻(4T2R)組成，或是由 六個電晶體(6T)所組成。對於目前低功率/低電壓之靜態隨 機存取記憶的需求而言，則以六個電晶體所設計之靜態隨 機存取記憶體具有較高的穩定性。 由六個電晶體（6T)所組成之靜態隨機存取記憶胞，依 照其功能可以區分爲電壓下拉元件（Pull Down Device， PD)、P型電壓負載元件(PMOS Load Device、PL)與傳送 閘元件(Pass Gate Device，PG)，其電路結構如第1圖所示。 由於每一個記憶胞必須使用六個電晶體來形成，因此，其 積集度較低。爲了符合市場輕、薄、短、小的需求，必須 縮小製程尺寸(Dimension)，增加積極度並且降低製造的成 本，以製造更小尺寸的靜態隨機存取記憶體之記憶胞。然 而，元件的通道長度(Channel Length)縮小之後，閘極氧化 層的厚度必須隨之縮小，以避免次起始漏電流(Sub-Through Leakage)的發生。但是，閘極氧化層縮小之後，卻又造成 聞極誘發漏電流（Gate-Induce Drain Leakage ’ GIDL) ’ 使 得待機電流(Stand-By Current)增大而無法符合低功率的需 求（Low Power Requirement)。 請參照第2圖，目前解決閘極誘發漏電流的方法，係 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 請 先 閲 讀 背 意 事 瑣 與 填 % 奮 t 裝472387 68〇5twf.doc / 008 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the Invention (f) The present invention relates to a method for manufacturing a memory element, and more particularly to a static random access memory (Static Random Access Memory, SRAM) device manufacturing method. Static random access memory is a type of memory that has very fast processing speed in semiconductor memory. According to the design, the memory cell of the static random access memory can be composed of four transistors and two resistors (4T2R), or six transistors (6T). For the current low-power / low-voltage static random access memory requirements, the static random access memory designed with six transistors has higher stability. A static random access memory cell composed of six transistors (6T) can be divided into a voltage pull down device (Pull Down Device, PD), a P-type voltage load device (PL), and a transmission gate according to its function. Element (Pass Gate Device, PG), its circuit structure is shown in Figure 1. Since each memory cell must be formed using six transistors, its degree of accumulation is low. In order to meet the market's light, thin, short, and small requirements, it is necessary to reduce the process dimension (Dimension), increase enthusiasm and reduce manufacturing costs, in order to manufacture smaller-sized static random access memory cells. However, after the channel length of the device is reduced, the thickness of the gate oxide layer must be reduced accordingly to avoid the occurrence of sub-Through Leakage. However, after the gate oxide layer shrinks, the gate-induce drain leakage (GIDL) 'causes the standby current (Stand-By Current) to increase and fails to meet the low power requirement (Low Power Requirement). . Please refer to Figure 2 for the current method to solve the gate-induced leakage current. The paper size is in accordance with the Chinese National Standard (CNS) A4 (210 X 297 mm). Please read it carefully and fill in the details.
I I I I Itr • ! I 線 387 387 經濟部智慧財產局員工消費合作社印製 6805twf.doc/008 A7 五、發明說明（π ) 在閘極氧化層202中接近源極區204與汲極區206之處形 成鳥嘴（Bird Beak)狀，以藉由厚度的增加來達到目的。但 是’此方法卻會增加起始電壓値(Vt)，並且降低電壓下拉 元件電流量，使得電壓下拉元件與傳送閘元件之間的胞比 例(Cell Ratio)減小，而影響靜態隨機存取記憶體的穩定性 (Stability)。 因此’本發明的目的就是在提供一種靜態隨機存取記 憶體的製造方法，可以降低閘極誘發汲極漏電流量。 本發明的再一目的是提供一種靜態隨機存取記憶體的 製造方法，可以增加驅動電流，使得低功率/低電壓之靜 態隨機存取記憶體在操作過程中維持電壓下拉元件與傳送 閘元件之間的胞比例，增加靜態隨機存取記憶體的穩定 性。 本發明提出一種靜態隨機存取記憶體的製造方法，此 方法係在基底上形成一具有頂蓋層的堆疊閘，接著，在基 底上形成一罩幕層，以覆蓋部分的堆譽閘表面，使堆疊閘 其汲極側的氧化層裸露出來，其後，進行熱氧化製程，以 使所裸露出來之氧化層的厚度增加，而形成一汲極端厚度 較厚於其他之處的閘氧化層，之後，去除罩幕層與頂蓋層， 再於基底中形成一源極區與一汲極區。 依照本發明的較佳實施例所述，上述之罩幕層具有一 開口，此開口係裸露出電壓下拉元件與電壓負載元件之堆 疊閘其汲極側的氧化層。在進行熱製程之後，因熱氧化而 形成本發明之閘氧化層，此閘極氧化層的汲極端因熱氧化 4 --I I I I-----裝 ------ 訂·！ 線 /、 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 472387 6805twf.doc/008 A7 B7 五、發明說明（》） 而厚度增加呈鳥嘴狀，而其他之處的厚度則維持不變爲/ 厚度均一的氧化層。 本發明之閘極氧化層，其在汲極端的厚度較厚於其他 之處，因此，可以降低閘極誘發汲極漏電流量。 本發明僅在閘極氧化層的汲極端形成厚度較厚的鳥嘴 狀，而汲極端以外之處則爲厚度較薄且均一的閘極氧化 層，因此，不僅可以降低閘極誘發汲極漏電流量，而且可 以降低源極端之淡摻雜源極區的電阻，增加驅動電流’使 得低功率/低電壓之靜態隨機存取記憶體在操作過程中維 持電壓下拉元件與傳送閘元件之間的胞比例’增加靜態隨 機存取記憶體的穩定性。 本發明在閘極導體層上所形成之頂蓋層’可以在形成 罩幕層的蝕刻過程中保護之，使其不會遭受蝕刻的破壞， 因此，在定義罩幕層其開口的位置時，可以具有較大的對 準空間。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 第1圖是習知六個電晶體所組成之靜態隨機存取記憶 體之電路結構圖。 第2圖是習知避免閘極誘發汲極漏電流之靜態隨機存 取記憶體其電晶體的剖面示意圖。 第3A圖至第3D圖係依照本發明較佳實施例所繪示 5 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） I I I I----II--表· I I I I 11 I 訂· I ! ---線 ' (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 472387 經濟部智慧財產局員工消費合作杜印製IIII Itr •! I line 387 387 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 6805twf.doc / 008 A7 V. Description of the invention (π) In the gate oxide layer 202, it is close to the source region 204 and the drain region 206 Form a bird beak (Bird Beak) to achieve the purpose by increasing the thickness. But 'this method will increase the starting voltage 値 (Vt) and reduce the current of the voltage pull-down element, so that the cell ratio between the voltage pull-down element and the transmission gate element is reduced, which affects the static random access memory. Body stability (Stability). Therefore, the object of the present invention is to provide a method for manufacturing a static random access memory, which can reduce the amount of gate-induced drain leakage current. Another object of the present invention is to provide a method for manufacturing a static random access memory, which can increase the driving current, so that the low-power / low-voltage static random access memory maintains the voltage pull-down element and the transmission gate element during operation. Cell ratio, increasing the stability of static random access memory. The invention proposes a method for manufacturing a static random access memory. This method forms a stack gate with a cap layer on a substrate, and then forms a cover layer on the substrate to cover a part of the surface of the stack gate. Exposed the oxide layer on the drain side of the stack gate, and then performed a thermal oxidation process to increase the thickness of the exposed oxide layer to form a gate oxide layer having a thicker drain electrode thickness than elsewhere, After that, the mask layer and the cap layer are removed, and then a source region and a drain region are formed in the substrate. According to a preferred embodiment of the present invention, the above-mentioned cover layer has an opening, and this opening exposes the oxide layer on the drain side of the stack gate of the voltage pull-down element and the voltage load element. After the thermal process is performed, the gate oxide layer of the present invention is formed due to thermal oxidation, and the drain terminal of the gate oxide layer is thermally oxidized. 4 --I I I I ----- install ------ order! Line / 、 (Please read the notes on the back before filling in this page) This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) 472387 6805twf.doc / 008 A7 B7 V. Description of Invention (") The increase in thickness is a bird's beak, while the thickness elsewhere remains the same / uniform thickness of the oxide layer. The gate oxide layer of the present invention is thicker at the drain terminal than at other places, and therefore, the amount of gate-induced drain leakage current can be reduced. The invention only forms a thick bird's beak shape at the drain terminal of the gate oxide layer, and a thin and uniform gate oxide layer outside the drain terminal, so that it can not only reduce gate-induced drain leakage Flow, and can reduce the resistance of the lightly doped source region at the source extreme and increase the driving current, so that the low-power / low-voltage static random access memory maintains the cell between the voltage pull-down element and the transmission gate element during operation. Proportional 'increases the stability of static random access memory. The capping layer formed on the gate conductor layer according to the present invention can protect the capping layer from being damaged by etching during the etching process of forming the capping layer. Therefore, when defining the position of the opening of the capping layer, Can have a larger alignment space. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Brief description of the drawings: FIG. 1 It is a circuit diagram of the static random access memory composed of six transistors. Figure 2 is a schematic cross-sectional view of a transistor in a static random access memory that is conventionally known to avoid gate-induced drain leakage. Figures 3A to 3D are drawn in accordance with a preferred embodiment of the present invention. 5 The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) III I ---- II--Table · IIII 11 I Order · I! --- Line '(Please read the precautions on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 472387 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs
6S05twf.doc/008 Λ/ _B7_五、發明說明（0) 之一種靜態隨機存取記憶體之製造流程的上視圖。 第4A圖至第4D圖係繪示第3A圖至第3D圖其IV-IV 切線之剖面圖。 圖式之標示說明： 202 :閘極氧化層 204、316、318、324、326、332、334 :源極區 206、312、314、320、322、328、330 :汲極區 300 :基底 302 :隔離區 304a、304b、304c、304d :主動區 306、306a、306b、308、308a、308b、310、310a、310b :堆疊閘 336 :氧化層 338 :氮化矽層 340 :罩幕層 342 :開口 344、346、348、350、352、354、356、358 ··金屬層 364 :氧化層 366 :導體層 368 :頂蓋層 360、362 :汲極側實施例 第3A圖至第3D圖，係依照本發明較佳實施例所繪 示之一種靜態隨機存取記憶體之製造流程的上視圖。第4A —-----------&t--------訂----------、 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員X消費合作社印製 472387 6805twf.doc/008 A7 B7 五、發明說明（c) 圖至第4D圖係繪示第3A圖至第3D圖其IV-IV切線之剖 面圖。 請參照第3A圖與第4A圖。在基底300中形成隔離 區302 ’以在基底300界疋出主動區304a、304b、304c與 304d。隔離區302的形成方法例如是淺溝渠隔離法(STI)或 局部區域熱氧化法(LOCOS)。 接著，請參照第3B圖與第4B圖。在基底300上依序 形成堆疊聞306、308與310。堆疊閘306、308與310均 是由氧化層364、導體層366與頂蓋層368所組成。較佳 的氧化層364例如是氧化矽，其係以熱氧化方式所形成者。 導體層366例如是複晶矽或是由複晶矽與矽化金屬層所組 成之複晶矽化金屬層。複晶矽的形成法例如是以低壓化學 氣相沉積法(LPCVD)所形成，其可以摻入摻雜以賦予導電 性。摻雜的形成方法可以在沉積複晶矽的同時（In_Situ)進 行，或是在複晶矽層沉積之後，再經由離子佈植的方式以 形成之。頂蓋層368之材質以不易於氧化者較佳，其材質 例如爲氮化矽’其形成的方法例如是化學氣相沉積法。在 基底300上覆蓋氧化層、複晶矽層、金屬矽化物層與頂蓋 層之後’再以微影與蝕刻技術定義其圖案，以形成由氧化 層364、導體層366與頂蓋層368所組成的堆疊閘306、308 與 310。 堆疊閘306中跨在主動區304a的部分306a爲靜態隨 機存取記憶體其電壓負載元件(PL)，例如是一 P型金氧半 導體(PMOS)的堆疊閘，堆疊閘306a兩側的主動區304a爲 7 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ---ml-----^----!| 訂··---!1-線·. (請先閱讀背面之注意事項再填寫本頁) 472387 6805twf.doc/008 A7 _：___ B7 五、發明說明（6 ) 預定之汲極區312與源極區316。而堆疊閘306中跨在主 動區304c的部分306b爲靜態隨機存取記憶體其電壓下拉 元件(PD)，例如是一 NMOS的堆疊閘，堆疊閘306b兩側 的主動區304c爲預定之汲極區320與源極區324。 堆疊閘308中跨在主動區304b的部分308a爲靜態隨 機存取記憶體其另一個電壓負載元件（PMOS PL)的堆疊 閘，堆疊閘308a兩側的主動區304b爲預定之汲極區314 與源極區318。而堆疊閘308中跨在主動區304d的部分308b 爲靜態隨機存取記憶體其另一個電壓下拉元件的堆疊閘， 堆疊閘308b兩側的主動區304d爲預定之汲極區322與源 極區326。 堆疊閘310中跨在主動區304c的部分310a爲靜態隨 機存取記憶體其傳送閘元件(PG)，例如是一NMOS的堆疊 閘，堆疊閘310a兩側的主動區304c爲預定之汲極區330 與源極區334。而堆疊閘3 10中跨在主動區304d的部分310b 爲靜態隨機存取記憶體其另一傳送閘元件(NMOS PG)的堆 疊閘，堆疊閘310b兩側的主動區304d爲預定之汲極區328 與源極區332。 接著，請參照第3C圖與第4C圖。在基底300上形成 一層罩幕層340 ’以覆蓋電壓負載元件(pl)其預定的源極 區316、318、電壓下拉元件(PD)其預定的源極區324、326、 傳送閘元件(PG)其預定的源極區332、334與汲極區328、 330以及堆疊閘306、308與310的一部份。而罩幕層340 的開口 342則裸露出電壓負載元件以及電壓下拉元件之堆 8 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝--------訂---------線 經濟部智慧財產局員工消費合作社印製 472387 6805twf.doc/008 A7 ____B7 __ 五、發明說明（)） (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 疊閘306、308其汲極側360、362(接近汲極區312、314、 320、322之一側）的氧化層364。罩幕層340之材質以能 阻擋氧氣與水氣之擴散者較佳。較佳的罩幕層340例如是 由氧化矽層336與氮化矽層338所組成者。氧化矽層336 的形成方法例如是以四乙氧基矽甲烷(TEOS)爲反應氣體， 經由電漿增益型化學氣相沉積法(PECVD)所形成者，其厚 度爲1〇〇埃至200埃左右。氮化矽層338的形成方法例如 爲低壓化學氣相沉積法，其厚度爲1000埃至2000埃左右。 當氧化矽層336_與氮化矽層338沉積於基底300上方之後， 經由微影與蝕刻技術將氧化矽層336與氮化矽層338圖案 化，以形成覆蓋部分堆疊閘306、308、310其頂蓋層368 頂部，堆疊閘306、308、310源極側（接近於源極區之一 側)側壁以及覆蓋預定之源極區316、318、324、326、332、 334之基底300表面的罩幕層340。在蝕刻氮化矽層與氧 化矽層以形成罩幕層340的過程中，頂蓋層368可以保護 其下方的導體層366，使其不會遭受蝕刻的破壞，因此， 在定義罩幕層340之開口 342位置時，可以具有較大的對 準空間（Alignment Window)，僅需使所形成之罩幕層334 可以使電壓負載元件以及電壓下拉元件之堆疊閘306、308 其汲極側的氧化層364裸露出來即可。 其後，進行熱製程，以使罩幕層340其開口 342所裸 露來之汲極側360、362的氧化層因氧化而厚度增加並呈 鳥嘴狀，而汲極側以外的氧化層364，則因爲被罩幕層340 所覆蓋，因此，並不會發生氧化，故而，在進行熱製程之 9 ^紙張尺度適用中國國家規格（210 x 297公釐） 472387 A7 B7 6805twf.doc/008 五、發明說明（兄） 後，可以使得所形成的閘氧化層364,其在汲極側360、362 的厚度較其他之處爲厚。熱製程可以熱氧化的方式來施 行，例如是乾式熱氧化法或是濕式熱氧化法，其熱氧化的 溫度在攝氏800度至1〇〇〇度之間。 請參照弟3D圖與弟4D圖。去除罩幕層340與頂蓋 層368，以裸露出堆疊閘306、308、310之導體層366。 去除罩幕層340與頂蓋層368的方法包括濕式蝕刻法。當 罩幕層340係由氮化矽層338與氧化矽層336所組成，而 頂蓋層368係以氮化矽形成時，可以先以磷酸去除罩幕層 340之氮化矽層338，再以氫氟酸溶液去除氧化矽層336， 最後，再以磷酸去除氮化矽頂蓋層368。 之後，在基底300中形成電壓負載元件(PL)的汲極區 312、314與源極區316、318、電壓下拉元件(PD)的汲極 區320、322與源極區324、326以及傳送閘元件(PG)的汲 極區328、330與源極區332、334。源極區316、318、324、 326、332、334 與汲極區 312、314、320、322、328、330 的形成方法例如是在基底300上形成光阻層，之後，以光 阻層作爲植入罩幕，分別進行N型或P型離子之植入步驟 以形成之。接著，於堆疊閘306、308、310之導體層366 上以及源極區3 16、318、324、326、332、334與汲極區312、 314、320、322、328、330的基底300表面上形成自動對 準金屬矽化物（未標示出來），再形成金屬內連線344、346、 348 、 350 、 352 、 354 、 356 、 358 ° 綜合以上本發明實施例所述，本發明具有下列優點： 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 訂---------線.. 經濟部智慧財產局員工消費合作社印製 472387 6805twf.doc/008 A7 五、發明說明（1 ) 1. 本發明之閘極氧化層，其在汲極端的厚度較厚於其 他之處，因此，可以降低閘極誘發汲極漏電流量。 2. 本發明僅在閘極氧化層的汲極端形成厚度較厚的鳥 嘴狀，而汲極端以外之處則爲厚度較薄且均一的閘極氧化 層，因此，不僅可以降低閘極誘發汲極漏電流量，而且可 以降低源極端之淡摻雜源極區的電阻，增加驅動電流，使 得低功率/低電壓之靜態隨機存取記憶體在操作過程中維 持電壓下拉元件與傳送閘元件之間的胞比例，增加靜態隨 機存取記憶體的穩定性。 3. 本發明在閘極導體層上所形成之頂蓋層，可以在形 成罩幕層的蝕刻過程中保護之，使其不會遭受蝕刻的破 壞，因此，在定義罩幕層其開口的位置時，可以具有較大 的對準空間。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作些許之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 S ^1 ϋ I n « I n a— n n I n n n I **^^** {·言 A'·1- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員Η消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）6S05twf.doc / 008 Λ / _B7_ V. Top view of the manufacturing process of static random access memory (0). 4A to 4D are cross-sectional views taken along the line IV-IV of FIGS. 3A to 3D. Description of the diagram: 202: gate oxide layer 204, 316, 318, 324, 326, 332, 334: source region 206, 312, 314, 320, 322, 328, 330: drain region 300: substrate 302 : Isolation area 304a, 304b, 304c, 304d: Active area 306, 306a, 306b, 308, 308a, 308b, 310, 310a, 310b: Stack gate 336: Oxide layer 338: Silicon nitride layer 340: Mask layer 342: Openings 344, 346, 348, 350, 352, 354, 356, 358 ... metal layer 364: oxide layer 366: conductor layer 368: cap layer 360, 362: examples of drain side FIG. 3A to 3D, It is a top view of a manufacturing process of a static random access memory according to a preferred embodiment of the present invention. Section 4A ----------- & t -------- Order ----------, (Please read the notes on the back before filling this page) This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) Printed by the Intellectual Property Bureau of the Ministry of Economy X Consumer Cooperatives 472387 6805twf.doc / 008 A7 B7 V. Description of the invention (c) Figures to 4D 3A to 3D are cross-sectional views taken along the line IV-IV. Please refer to FIGS. 3A and 4A. An isolation region 302 'is formed in the substrate 300 to protrude the active regions 304a, 304b, 304c, and 304d at the boundary of the substrate 300. The method of forming the isolation region 302 is, for example, a shallow trench isolation method (STI) or a local area thermal oxidation method (LOCOS). Next, please refer to FIGS. 3B and 4B. Stacks 306, 308, and 310 are sequentially formed on the substrate 300. The stack gates 306, 308, and 310 are each composed of an oxide layer 364, a conductor layer 366, and a cap layer 368. The preferred oxide layer 364 is, for example, silicon oxide, which is formed by thermal oxidation. The conductive layer 366 is, for example, a polycrystalline silicon or a polycrystalline silicided metal layer composed of a polycrystalline silicon and a silicided metal layer. The method for forming the polycrystalline silicon is, for example, a low pressure chemical vapor deposition (LPCVD) method, which can be doped to impart conductivity. The doping method can be performed while depositing the polycrystalline silicon (In_Situ), or after the polycrystalline silicon layer is deposited, it can be formed by ion implantation. The material of the cap layer 368 is preferably not easily oxidized. The material of the cap layer 368 is, for example, silicon nitride, and the method of forming the cap layer 368 is, for example, a chemical vapor deposition method. After the substrate 300 is covered with an oxide layer, a polycrystalline silicon layer, a metal silicide layer, and a cap layer, the pattern is defined by lithography and etching techniques to form an oxide layer 364, a conductor layer 366, and a cap layer 368. Composed of stack gates 306, 308, and 310. The part 306a of the stack gate 306 that spans the active area 304a is a static random access memory and its voltage load element (PL), such as a P-type metal oxide semiconductor (PMOS) stack gate. The active areas on both sides of the stack gate 306a 304a is 7 paper sizes applicable to China National Standard (CNS) A4 specifications (210 X 297 mm) --- ml ----- ^ ----! | Order ·· ---! 1-line ·. (Please read the notes on the back before filling this page) 472387 6805twf.doc / 008 A7 _: ___ B7 V. Description of the invention (6) The planned drain region 312 and source region 316. The part 306b of the stack gate 306 across the active region 304c is a static random access memory and its voltage pull-down element (PD), for example, is an NMOS stack gate. The active region 304c on both sides of the stack gate 306b is a predetermined drain. Region 320 and source region 324. The part 308a of the stack gate 308 across the active region 304b is a stack gate of another random load memory (PMOS PL) of the static random access memory. The active region 304b on both sides of the stack gate 308a is a predetermined drain region 314 and Source region 318. The part 308b of the stack gate 308 across the active region 304d is a stack gate of another voltage pull-down element of the static random access memory. The active region 304d on both sides of the stack gate 308b is a predetermined drain region 322 and a source region. 326. The part 310a of the stack gate 310 spanning the active region 304c is a static random access memory and its transfer gate element (PG), for example, an NMOS stack gate. The active region 304c on both sides of the stack gate 310a is a predetermined drain region. 330 and source region 334. The part 310b of the stack gate 3 10 spanning the active region 304d is a stack gate of the other random gate memory (NMOS PG) of the static random access memory. The active region 304d on both sides of the stack gate 310b is a predetermined drain region. 328 and source region 332. Next, please refer to FIG. 3C and FIG. 4C. A cover layer 340 'is formed on the substrate 300 to cover the voltage source element (pl) its predetermined source regions 316, 318, the voltage pull-down element (PD) its predetermined source regions 324, 326, and the pass gate element (PG ) Part of its predetermined source regions 332, 334 and drain regions 328, 330 and stacked gates 306, 308 and 310. The opening 342 of the cover layer 340 exposes the stack of voltage load components and voltage pull-down components. 8 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling (This page) -------- Order --------- Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 472387 6805twf.doc / 008 A7 ____B7 __ V. Description of the Invention ()) ( Please read the notes on the back before filling out this page) The employee cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed the stack gates 306 and 308 and their drain sides 360 and 362 (close to one of the drain regions 312, 314, 320, 322) Of the oxide layer 364. The material of the cover layer 340 is preferably one capable of blocking the diffusion of oxygen and water vapor. The preferred mask layer 340 is composed of a silicon oxide layer 336 and a silicon nitride layer 338, for example. The method for forming the silicon oxide layer 336 is, for example, formed by using tetraethoxysilylmethane (TEOS) as a reaction gas and a plasma gain chemical vapor deposition (PECVD) method, and the thickness is 100 to 200 angstroms. about. The method for forming the silicon nitride layer 338 is, for example, a low-pressure chemical vapor deposition method, and its thickness is about 1000 to 2000 angstroms. After the silicon oxide layer 336_ and the silicon nitride layer 338 are deposited over the substrate 300, the silicon oxide layer 336 and the silicon nitride layer 338 are patterned by lithography and etching techniques to form a partial stack gate 306, 308, 310. The top of its capping layer 368, the side walls of the source gate (close to one side of the source region) of the stack gate 306, 308, 310 and the surface of the substrate 300 covering the predetermined source region 316, 318, 324, 326, 332, 334 Of the curtain layer 340. During the process of etching the silicon nitride layer and the silicon oxide layer to form the mask layer 340, the cap layer 368 can protect the conductor layer 366 below it from being damaged by etching. Therefore, the mask layer 340 is defined The position of the opening 342 can have a large alignment window, and only the formed mask layer 334 can oxidize the drain side of the stacked gates 306 and 308 of the voltage load element and the voltage pull-down element. The layer 364 may be exposed. Thereafter, a thermal process is performed to make the oxide layers on the drain side 360 and 362 exposed from the opening 342 of the mask layer 340 increase in thickness and form a bird's beak due to oxidation, and the oxide layer 364 other than the drain side, Because it is covered by the cover layer 340, no oxidation will occur. Therefore, the national standard of China (210 x 297 mm) is applicable to the paper size of thermal process 9 ^ 387387 A7 B7 6805twf.doc / 008 V. Invention After explaining (brother), the gate oxide layer 364 formed can be made thicker on the drain side 360 and 362 than elsewhere. The thermal process can be performed by thermal oxidation, such as dry thermal oxidation or wet thermal oxidation. The temperature of thermal oxidation is between 800 ° C and 1000 ° C. Please refer to Brother 3D and Brother 4D. The cover layer 340 and the top cover layer 368 are removed to expose the conductor layers 366 of the stack gates 306, 308, 310. Methods for removing the cover layer 340 and the cap layer 368 include a wet etching method. When the mask layer 340 is composed of a silicon nitride layer 338 and a silicon oxide layer 336, and the cap layer 368 is formed of silicon nitride, the silicon nitride layer 338 of the mask layer 340 may be removed with phosphoric acid first, and then The silicon oxide layer 336 is removed with a hydrofluoric acid solution. Finally, the silicon nitride cap layer 368 is removed with phosphoric acid. After that, drain regions 312 and 314 and source regions 316 and 318 of the voltage load element (PL), drain regions 320 and 322 and source regions 324 and 326 of the voltage pull-down element (PD) are formed in the substrate 300, and transmission is performed. The gate regions (PG) have drain regions 328, 330 and source regions 332, 334. The formation method of the source region 316, 318, 324, 326, 332, 334 and the drain region 312, 314, 320, 322, 328, 330 is, for example, forming a photoresist layer on the substrate 300, and then using the photoresist layer as a The implantation mask is formed by implanting N-type or P-type ions, respectively. Next, on the conductive layer 366 of the stacked gates 306, 308, and 310, and on the surface of the substrate 300 of the source region 3 16, 318, 324, 326, 332, 334 and the drain region 312, 314, 320, 322, 328, 330 An auto-aligned metal silicide (not shown) is formed thereon, and then metal interconnects 344, 346, 348, 350, 352, 354, 356, and 358 are formed. Based on the foregoing embodiments of the present invention, the present invention has the following advantages: : This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling this page) Order --------- Line: Intellectual Property of the Ministry of Economic Affairs Printed by the Bureau ’s Consumer Cooperatives 472387 6805twf.doc / 008 A7 V. Description of the Invention (1) 1. The gate oxide layer of the present invention is thicker at the drain terminal than elsewhere, so it can reduce the gate induction Drain leakage. 2. The present invention forms a thick bird's beak only at the drain terminal of the gate oxide layer, and the gate oxide layer is thinner and more uniform outside the drain terminal. Therefore, not only can the gate-induced drain be reduced. The amount of leakage current can reduce the resistance of the lightly doped source region at the source extreme and increase the driving current, so that the low-power / low-voltage static random access memory maintains the voltage between the pull-down element and the transmission gate element during operation. The cell ratio increases the stability of static random access memory. 3. The capping layer formed on the gate conductor layer of the present invention can be protected during the etching process of forming the mask layer from being damaged by the etching. Therefore, the position of the opening of the mask layer is defined. In this case, it is possible to have a large alignment space. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. S ^ 1 ϋ I n «I na— nn I nnn I ** ^^ ** {· 言 A '· 1- (Please read the notes on the back before filling this page) The paper size of the paper is applicable to China National Standard (CNS) A4 (210 X 297 mm)