TW471154B - Robust bonding pad structure for integrated circuit chips - Google Patents

Robust bonding pad structure for integrated circuit chips Download PDF

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Publication number
TW471154B
TW471154B TW088118359A TW88118359A TW471154B TW 471154 B TW471154 B TW 471154B TW 088118359 A TW088118359 A TW 088118359A TW 88118359 A TW88118359 A TW 88118359A TW 471154 B TW471154 B TW 471154B
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bonding pad
layer
contact
conductive layer
conductive
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TW088118359A
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Chinese (zh)
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Yoko Horiguchi
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Nippon Electric Co
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H01L2224/05089—Disposition of the additional element
    • H01L2224/05093—Disposition of the additional element of a plurality of vias
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    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
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    • H01L2924/1304—Transistor
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    • H01L2924/14—Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

A bonding pad structure for an integrated circuit is comprised of a semiconductor substrate in which a protection device is formed, a bonding pad for connection of a wire through which a signal is supplied to or delivered from the integrated circuit, an insulating layer formed on the substrate. At least a portion of the insulating layer is covered by the bonding pad. In the insulating layer, a first conductive layer is formed for connection to ground, and a second conductive layer laterally spaced from the first conductive layer, arrays of juxtaposed metallic contacts are used to establish a contact between the second conductive layer and the bonding pad, a contact between a first portion of the protection device and the first conductive layer, and a contact between a second portion of the protection device and the second conductive layer.

Description

471154 五、發明說明（1) 【發明背景】 【發明領域】 本兔明係關於接合墊結構（b〇nding pad structure )之改良’該接合墊結構係用於保護積體電路晶片免於靜 電放電故障’此外也用於配線連接，其中一信號透過該配 線連接而施加於該積體電路，或從該積體電路透過該配線 連接而傳送一信號。 【相關技術之說明】 — 接合塾係作為介於積體電路晶片與外界間之界面。接 二墊經常具有保護裝置，用以保護積體電路免於ES])(靜 電放電，electrostatic discharges)故障。隨著高積集 度之一般發展傾向，一積體電路所具有之接合墊數目隨之 增加，並且接合墊與相關聯的保護裝置所佔據之空間亦變 j。既然保護裝置之尺寸係由相關聯的接合墊之尺寸所決 定，所以藉由嵌入保護裝置於接合墊之下可節省空間。 ^此種配置揭露於^ R· McC〇y等人所獲得之美國專利 =3，6 7 3，4 2 7琥。依據此習知技術，保護裝置藉由植入雜 λ而形成於半導體基板中。保護裝置係受一氧化層所覆 蓋，該氧化層上具有該金屬接合堅。 ，如何’當一配線連接於該塾或一測試探針接觸於 该墊日守’大量的壓力會施加於該塾上，導致下方的保 置雙損。再者，下層傾向使其圖案出現於上層，造成= 墊上之表面不規則，使得當配線被接合時，該接合墊會ς471154 V. Description of the invention (1) [Background of the invention] [Field of the invention] The present invention relates to the improvement of the bonding pad structure (bonding pad structure), which is used to protect the integrated circuit chip from electrostatic discharge Faults are also used for wiring connections, where a signal is applied to the integrated circuit through the wiring connection, or a signal is transmitted from the integrated circuit through the wiring connection. [Explanation of related technology] — Bonding system is used as the interface between the integrated circuit chip and the outside world. The two pads often have protection devices to protect the integrated circuit from ES]) (electrostatic discharges) failures. With the general development tendency of high integration density, the number of bonding pads of an integrated circuit increases, and the space occupied by the bonding pads and associated protection devices also becomes j. Since the size of the protective device is determined by the size of the associated bonding pad, space can be saved by embedding the protective device under the bonding pad. ^ This configuration is disclosed in ^ U.S. patents obtained by R. McCoy et al. = 3, 6 7 3, 4 2 7 Hu. According to this conventional technique, a protection device is formed in a semiconductor substrate by implanting a dopant λ. The protection device is covered by an oxide layer having the metal joint on the oxide layer. How, when a wiring is connected to the cymbal or a test probe is in contact with the pad, the large amount of pressure will be applied to the cymbal, resulting in a double loss of retention. Furthermore, the lower layer tends to have its pattern appear on the upper layer, resulting in an irregular surface on the pad, so that when the wiring is bonded, the bonding pad will

471154471154

五、發明說明（2) 下方的氧化層中抽離。 【發明概述】 因而’本發明之一目的在於，提供一種積體電路晶片 用之堅固接合墊結構，具有抵抗高壓接觸之能力。 ㈤ 依據第一態樣’本發明提供一種積體電路晶片用之接 合墊結構，包含一半導體基板，其具有第一與第二擴散區 域、一輸出/輸入接合墊、一絕緣層，形成於該基板上"， 該絕緣層之至少一部份係由該接合墊所覆蓋、一第一導電 層位於该絕緣層中，用以連接於接地位準導電層、以及 一第=導電層，位於該絕緣層中且橫向分離於該& 一導電 層、複數個並列金屬接觸，位於該絕緣層中，用以建立介 第二導電層與該接合墊間之接觸、以及複數個並列^ 位於該絕緣層巾，用以建立介於該第一擴散區域 ς ^弟一導電層間之接觸，及複數個並列金屬接觸，位於 緣層中，用以建立介於該第二擴散區域與該 層間之接觸。 电 八依據第二態樣，本發明提供一種積體電路晶片用之接 i結構，包含一半導體基板，其具有第一與第二擴散區 二_ 4第一與該第二擴散區域之導電型態相反於該基板、 輸出/輸入接合墊、一絕緣層，形成於該基板上，該絕 ;I=至少一部份係由該接合墊所覆蓋。此接合墊結構更 ^ ^ 一第一導電層，位於該絕緣層十，用以連接於接地位 導電層、一第一複數個並列金屬接觸陣列，位於該絕緣5. Description of the invention (2) Extraction from the oxide layer below. [Summary of the Invention] Therefore, it is an object of the present invention to provide a strong bonding pad structure for an integrated circuit chip, which has the ability to resist high-voltage contact. ㈤ According to the first aspect, the present invention provides a bonding pad structure for an integrated circuit wafer, including a semiconductor substrate having first and second diffusion regions, an output / input bonding pad, and an insulating layer formed on the substrate. On the substrate, at least a part of the insulating layer is covered by the bonding pad, a first conductive layer is located in the insulating layer, and is used to connect to the ground level conductive layer, and a first conductive layer is located at The insulating layer is laterally separated from the & conductive layer, a plurality of side-by-side metal contacts, and is located in the insulating layer to establish a contact between the second conductive layer and the bonding pad, and a plurality of side-by-side ^ An insulating layer towel is used to establish contact between the first diffusion region and a conductive layer, and a plurality of side-by-side metal contacts are located in the edge layer to establish contact between the second diffusion region and the layer. . According to a second aspect, the present invention provides an i-structure for an integrated circuit wafer, which includes a semiconductor substrate having first and second diffusion regions 2-4 and a conductivity type of the first and the second diffusion regions. The state is opposite to the substrate, the output / input bonding pad, and an insulating layer formed on the substrate, and the insulation; I = at least a part is covered by the bonding pad. The bonding pad structure further includes a first conductive layer located on the insulating layer 10 for connection to the ground level, a conductive layer, and a first plurality of parallel metal contact arrays located on the insulation.

第6頁 471154 五、發明說明（3) 層中，用以建立介於該第一擴散區域與該接合墊間之接 觸、一第二複數個並列金屬接觸陣列，位於該絕緣層中， 用以建立介於該第二擴散區域與該第一導電層間之接觸、 以及一第一導電層’位於該絕緣層中，該第二導電層位於 電流路徑之上，該電流路徑係介於該第一與該第二擴散區 域間，該第一與該第二擴散區域係接觸於該第一導電層。 依據第三態樣，本發明提供一種積體電路晶片用之接 合墊結構，包含一半導體基板、一輸出/輸入接合墊、一 絕緣層，形成於該基板上，該絕緣層之至少一部份係由該 接合墊所覆蓋、第一、第二、與第三導電層，彼此橫向分 離，位於該絕緣層中，用以接地。其更包含第一、第二、 與第三擴散區域，形成於該基板中，該第一、第二、與第 三擴散區域具有第一導電型態，該第一導電塑態相反於該 基板之導電型態、第五與第六擴散區域，形成於該基板 中，該第五與第六擴散區域具有第二導電型態’該第二導 電型態相反於該第/導電型態，並且分別鄰近於該第一與 該第三擴散區域、第一與第二複數個並列金屬接觸陣列’ 位於該絕緣層中，用以建立介於該第一和該第三擴散區域 與該接合墊間之接觸、第三與第四複數個並列金屬接觸陣 列’位於該絕緣層中，用以分別建立介於該第五和該第六 擴散區域與該第一和該第三導電層間之接觸、以及一第五 複數個並列金屬接觸，位於該絕緣層中，用以建立介於該 第二擴散區域與該第二導電層間之接觸。第四與第五導電 層’彼此橫向分離，形成於該絕緣層中，該第四導電層位Page 6 471154 V. Description of the invention (3) The layer is used to establish a contact between the first diffusion region and the bonding pad, and a second plurality of parallel metal contact arrays are located in the insulating layer for Establish a contact between the second diffusion region and the first conductive layer, and a first conductive layer is located in the insulating layer, the second conductive layer is located above the current path, and the current path is between the first Between the second diffusion region and the first diffusion region, the first and second diffusion regions are in contact with the first conductive layer. According to a third aspect, the present invention provides a bonding pad structure for an integrated circuit wafer, comprising a semiconductor substrate, an output / input bonding pad, and an insulating layer formed on the substrate, at least a portion of the insulating layer The first, second, and third conductive layers covered by the bonding pad are laterally separated from each other and are located in the insulating layer for grounding. It further includes first, second, and third diffusion regions formed in the substrate. The first, second, and third diffusion regions have a first conductive type, and the first conductive plastic state is opposite to the substrate. The conductive type, the fifth and sixth diffusion regions are formed in the substrate, and the fifth and sixth diffusion regions have a second conductive type 'the second conductive type is opposite to the / conductive type, and Adjacent to the first and the third diffusion regions, the first and the second plurality of parallel metal contact arrays, respectively, are located in the insulating layer, and are used to establish a gap between the first and the third diffusion regions and the bonding pads. The contact, the third and fourth parallel metal contact arrays' are located in the insulating layer, and are used to establish contacts between the fifth and the sixth diffusion regions and the first and the third conductive layers, respectively; and A fifth plurality of side-by-side metal contacts are located in the insulating layer to establish a contact between the second diffusion region and the second conductive layer. The fourth and fifth conductive layers are laterally separated from each other and are formed in the insulating layer. The fourth conductive layer

471154 五、發明說明（4) 於一電流路徑之上，該電流路徑係介於該第一與該第二擴 散區域間，該第一與該第二擴散區域係接觸於該第一導電 層，並且該第五導電層位於一電流路徑之上，該電流路徑 係介於該第二與該第三擴散區域間，該第一與該第二擴散 區域係接觸於該第一導電層。 【圖示之簡單說明】 茲將參照所附圖示，更詳細說明本發明，其中之圖示 為： 圖1係顯示依據本發明第一實施例的積體電路晶片之 接合墊結構的上平面圖； 圖2係沿著圖1之線2-2之剖面圖； 圖3係沿著圖2之線3 _ 3之剖面圖； 圖4係顯示依據本發明第二實施例的積體電路晶片之 接合墊結構的上平面圖； 圖5係沿著圖4之線5 - 5之剖面圖； 圖6係沿著圖5之線6_6之剖面圖； 圖7係顯示依據本發明第三實施例的積體電路晶片之 接合墊結構的上平面圖； 圖8係沿著圖7之線8_8之剖面圖； 圖9係沿著圖7之線9-9之剖面圖； 圖10係沿著圖8之線10-10之剖面圖；以及 圖11係顯示本發明第三實施例之電連接之示意圖。471154 V. Description of the invention (4) On a current path, the current path is between the first and the second diffusion regions, and the first and the second diffusion regions are in contact with the first conductive layer, And the fifth conductive layer is located above a current path, the current path is between the second and the third diffusion region, and the first and the second diffusion region are in contact with the first conductive layer. [Brief description of the drawings] The present invention will be described in more detail with reference to the attached drawings, which are as follows: FIG. 1 is an upper plan view showing a bonding pad structure of a integrated circuit wafer according to a first embodiment of the present invention 2 is a cross-sectional view taken along line 2-2 of FIG. 1; FIG. 3 is a cross-sectional view taken along line 3_3 of FIG. 2; FIG. 4 is a cross-sectional view of a integrated circuit chip according to a second embodiment of the present invention; FIG. 5 is a cross-sectional view taken along line 5-5 of FIG. 4; FIG. 6 is a cross-sectional view taken along line 6-6 of FIG. 5; and FIG. 7 is a cross-sectional view showing a product according to a third embodiment of the present invention. Upper plan view of the bonding pad structure of the bulk circuit wafer; FIG. 8 is a cross-sectional view taken along line 8_8 of FIG. 7; FIG. 9 is a cross-sectional view taken along line 9-9 of FIG. 7; 10-10 is a cross-sectional view; and FIG. 11 is a schematic view showing an electrical connection of a third embodiment of the present invention.

第8頁 471154 五、發明說明（5) ------ 【較佳實施例之詳細說明】 依據本發明第一實施例之積體電路之輸入/輪出電路 用接合墊結構係顯示於圖丨、2、與3中。本發明之接合墊 結構包含積體電路晶片之一P型基板10、一導電接合墊 11、以及一絕緣層12，該絕緣層係介於該基板1〇與該墊Η 間。在接合製程中，一薄配線（未圖示）焊接於該接合墊 11上。 藉由連續沉積絕緣子層12Α與12β，以形成絕緣層12， 俾使導電層13、14、與15嵌入基板1〇與接合墊η間。導電 層13、14、與15彼此橫向分離，並且垂直地分離於基板ι〇 與接合墊11。如圖1所示，導電層14位於導電層13與15 間，並且連接於地面導電層（未圖示），以作為突波 電流（surge current)用之放電路徑。 ' 複數個N+擴散區域1 6、1 7、與1 8形成於基板丨〇之上表 面上。 藉由複數個並列金屬柱或從絕緣子層丨2A (參照圖2 ) 延伸出之”插塞接觸（plug contact ) π 21，使型擴散區 域16接觸於導電層13。以相同之方式，藉由複數個 屬接觸22，使N+擴散區域17接觸於導電層14，並且藉由二 數個並列金屬接觸2 3，使區域1 8接觸於導電尽L。 、 藉由複數個並列金屬接觸24，使接合墊/丨接觸於導電 層1 3，並且藉由複數個並列金屬接觸25，使其更接觸 電層15。 ； 舉例而言’銘係適合作為接合塾11與導電層1 31 4Page 8 471154 V. Description of the invention (5) ------ [Detailed description of the preferred embodiment] The structure of the bonding pad for the input / round-out circuit of the integrated circuit according to the first embodiment of the present invention is shown in Figures 丨, 2, and 3. The bonding pad structure of the present invention includes a P-type substrate 10 of an integrated circuit wafer, a conductive bonding pad 11, and an insulating layer 12, and the insulating layer is interposed between the substrate 10 and the pad Η. In the bonding process, a thin wiring (not shown) is soldered to the bonding pad 11. The insulator layers 12A and 12β are successively deposited to form the insulating layer 12, and the conductive layers 13, 14, and 15 are embedded between the substrate 10 and the bonding pad n. The conductive layers 13, 14, and 15 are laterally separated from each other, and are vertically separated from the substrate ι and the bonding pad 11. As shown in FIG. 1, the conductive layer 14 is located between the conductive layers 13 and 15, and is connected to the ground conductive layer (not shown) to serve as a discharge path for a surge current. 'A plurality of N + diffusion regions 16, 17, and 18 are formed on the surface of the substrate. The type diffusion region 16 is brought into contact with the conductive layer 13 by a plurality of side-by-side metal pillars or a “plug contact” π 21 extending from the insulator layer 2A (see FIG. 2). In the same manner, by The plurality of sub-contacts 22 make the N + diffusion region 17 contact the conductive layer 14 and contact the conductive layer L with two parallel metal contacts 23 and the region 18 with the parallel conductive contact L.. The bonding pad / 丨 is in contact with the conductive layer 1 3, and is made more in contact with the electrical layer 15 by a plurality of side-by-side metal contacts 25. For example, 'Ming is suitable as the bonding layer 11 and the conductive layer 1 31 4

471154 五、發明說明（6) 適合作為金屬接觸21至25之材料係具有高 之至屬，例如鎢與矽化物金屬（metaiiic 接合墊11之表面積約為8 0平方微米至1 2 0平方微米。 中=導電層13、14、與15彼此分離約2.0至5 ,卡 ^係從4.0至10.。微米，㈣觸如之尺寸而十定層戶;4 有玉屬接觸21至25之遮罩尺寸係從〇· 2至〇· 5平方微米。 既然接合墊結構形成雙層結構，下 於接合墊之表面上。此外然所有金屬接觸 藝：及ί周圍材料之物質戶爾，且其水平剖面係 接觸與接合墊間之接觸壓力係大數值。因％，當配線：士 墊或測試探針接觸於接合墊時，金屬接觸24、以可 度上進入較軟的接合墊11，造成塾11堅固地連結 =底、，、》構。所以，本發明之接合墊結構係足夠堅固以 外部壓力，其足以使配線堅固地接合於金屬墊丨i。 藉由此種配置，雙載子接合整電晶體係經㈣區域i6 ::以及P型基板10，而作為第一保護裝置，區域“叫 ^別作為集極與射極’並且P型基板1〇作為基極。同樣 :雙：ΐίΪΪ1:::、與U作為第二保護Μ，形成第 雙載子接ΰ塾電晶體，區域1 7 11 8孫八ή,ι从：^ ώ 極，並且基板作為基極。」8係刀別作為射極與集 此實施例之保護裝置之動作如下。當接合墊u上之正 超，介於r，域'射型基板1〇間之接面的崩潰 電£ (breakdown voltage)時，載子之崩潰產生會發471154 V. Description of the invention (6) Materials suitable for metal contact 21 to 25 are of high standard. For example, the surface area of tungsten and silicide metal (metaiiic bonding pad 11 is about 80 square micrometers to 120 square micrometers). Middle = conductive layers 13, 14, and 15 are separated from each other by about 2.0 to 5; the card ^ is from 4.0 to 10.. Micron, the size of the contact is ten fixed households; 4 there is a mask of jade contact 21 to 25 The size ranges from 0.2 to 0.5 square microns. Since the bonding pad structure forms a double-layer structure, it is placed on the surface of the bonding pad. In addition, all metal contact technology: and the material of the surrounding material, and its horizontal section The contact pressure between the contact and the bonding pad is a large value. Because of the%, when the wiring: the Shi pad or the test probe contacts the bonding pad, the metal contact 24 enters the softer bonding pad 11 to a certain extent, causing 塾 11 Strongly connected = bottom, bottom, bottom, and bottom. Therefore, the bonding pad structure of the present invention is sufficiently strong to apply external pressure, which is sufficient for the wiring to be firmly bonded to the metal pad. With this configuration, the double carrier bonding is completed. Transistor region i6 :: and P-type substrate 10 And as the first protection device, the region “Do n’t be used as the collector and emitter” and the P-type substrate 10 is used as the base. Similarly: double: ΐίΪΪ1 :::, and U as the second protection M, forming the second double load Sub-connected transistor, area 1 7 11 8 Sun Ba price, ι from: ^ free pole, and the substrate as the base. "8 series knife as an emitter and the protection device of this embodiment operates as follows. When When the positive voltage on the bonding pad u is between r and the junction of the field-emitting substrate 10, a breakdown voltage will occur when the breakdown of the carrier occurs.

471154 五、發明說明（7) 生’造成電洞電流穿過基板丨〇。由於此電洞電流，區域基 板處之電位上升，導致介於射極（N+區域17 )與基板1〇間 之接面正偏壓（forward bias)，使電子從區域17注入基 板ίο内’並且聚集於集極（N+區域16與18)。二個雙載子 NpN電晶體皆導通。假若負電靜電電荷聚積於接合墊“ 上’則介於區域16與基板1〇間之接面以及介於區域18與基 板1 0間之接面皆為正偏壓，導致電子注入基板丨〇。因此， 接合墊11與接地位準（gr〇und ievel)導電層（未圖示） 間有電流流經導電層14，其方向視靜電放電之極性而定。 ^ 本發明之另一優點在於，雙層結構允許接合墊下之保 護裝置之佈局圖設計具有較大之自由度，放鬆佈局圖之要 求。不必所有的保護裝置皆受接合墊之覆蓋。部分保護裝 置得位於接合墊之外。符合積體電路之特定需要的^ 置亦可實現。 此等保護裝置之另一種型態顯示於圖4、5、與6中。 此實施例包含一P型基板30，一接合墊31與沉積於Α 之 一絕緣層32。 ~ ^藉由沉積絕緣子層32A與32B，而形成絕緣層32，俾 橫向分離的導電層33與34嵌入絕緣層中。 N型井36形成於P型基板30之上表面上，其中化型 區域37之一部份位於井36内，而其餘部分則位於井外:月 為此種位置，介於γ區域37 (井36之外）與p型基板3〇 之接面具有低崩潰電壓。在Ν型井36中，更形成^擴散^ 域38，其平行於Ν+擴散區域37之一側。此外，ρ擴散"區°域471154 V. Description of the invention (7) The hole current is caused to pass through the substrate. Due to this hole current, the potential at the substrate of the region rises, causing a forward bias at the junction between the emitter (N + region 17) and the substrate 10, so that electrons are injected into the substrate from the region 17 and Gathered at the collector (N + regions 16 and 18). Both bipolar NpN transistors are turned on. If negative electrostatic charges accumulate on the bonding pad "on", the interface between the region 16 and the substrate 10 and the interface between the region 18 and the substrate 10 are positively biased, causing electrons to be injected into the substrate. Therefore, an electric current flows through the conductive layer 14 between the bonding pad 11 and a ground level conductive layer (not shown), the direction of which depends on the polarity of the electrostatic discharge. ^ Another advantage of the present invention is that: The double-layer structure allows the layout design of the protection device under the bonding pad to have a greater degree of freedom, relaxing the requirements of the layout drawing. It is not necessary that all protection devices are covered by the bonding pad. Some protection devices must be located outside the bonding pad. The specific needs of the integrated circuit can also be realized. Another type of these protection devices is shown in Figs. 4, 5, and 6. This embodiment includes a P-type substrate 30, a bonding pad 31 and a layer deposited on A is an insulating layer 32. ~ ^ The insulating layer 32 is formed by depositing the insulating sublayers 32A and 32B, and the laterally separated conductive layers 33 and 34 are embedded in the insulating layer. The N-type well 36 is formed on the P-type substrate 30 On the surface, among the chemically modified regions 37 One part is located inside the well 36, and the other part is located outside the well: the moon is this position, and the junction between the gamma region 37 (outside the well 36) and the p-type substrate 30 has a low breakdown voltage. In the N-type In the well 36, a diffusion region 38 is formed, which is parallel to one side of the N + diffusion region 37. In addition, the ρ diffusion region

第11頁 471154Page 11 471154

其平行於區域 五、發明說明（8) 39與N+擴散區域40皆形成於P型基板30上 37 與38。 藉由金屬接觸41陣列（參照圖6)，使導電層33接觸 於N+區域37，且藉由金屬接觸42陣列，使導電層33接觸於 P+區域39。同樣地，藉由並列金屬接觸43陣列，使導電層 34接觸於P+區域39，且藉由並列金屬接觸44陣列，使導^ 層34接觸於N+區域40。藉由金屬接觸45陣列，使導電層33 接觸於接合墊31，且使導電層34連接於接地位準導電^， 作為靜電電荷之放電路徑（參照圖4 ) 。 θ 藉由此種配置’寄生ΝΡΝ雙載子電晶體係由Ν+區域 37、Ν型井3 6、Ρ型基板30、與Ν+區域40所形成，並且寄生 ΡΝΡ雙載子電晶體係由Ρ區域39、Ρ型基板30、Ν型井36、 與Ρ區域38所形成。既然Ν+區域37係接觸於Ν型井36與}>型 基板30 ’所以ΡΝΡ與ΝΡΝ寄生電晶體組合成寄生ρνρν結構， 或介於接合墊3 1與接地位準導電層間之閘流電晶體 (thyristor) 〇 保護裝置之又一實施例係顯示於圖7、8、9、與1 0 中。在此實施例中，接合墊結構包含p型基板5 〇、接合墊 5 1與沉積於其間之絕緣層5 2 (圖8 )。藉由沉積絕緣子層 52A、52B、與52C而形成絕緣層52，俾使橫向分離的導電 層81、82、與83嵌入基板50與接合墊51間。導電層81、 82、與83錯由接地之積體偶合元件（integral coupling member ) 80而彼此連接。 P+型擴散區域60與複數個N+型擴散區域61、62、63、It is parallel to the region V. Description of the invention (8) 39 and the N + diffusion region 40 are both formed on the P-type substrate 30 37 and 38. The array of metal contacts 41 (see FIG. 6) makes the conductive layer 33 contact the N + region 37, and the array of metal contacts 42 makes the conductive layer 33 contact the P + region 39. Similarly, the conductive layer 34 is brought into contact with the P + region 39 by the parallel metal contact 43 array, and the conductive layer 34 is brought into contact with the N + region 40 by the parallel metal contact 44 array. Through the metal contact 45 array, the conductive layer 33 is brought into contact with the bonding pad 31, and the conductive layer 34 is connected to the ground level to be conductive, as a discharge path for electrostatic charges (see FIG. 4). θ With this configuration, the 'parasitic NPN bipolar transistor system is formed by N + region 37, N-type well 36, P-type substrate 30, and N + region 40, and the parasitic PNP bipolar transistor system consists of A P-region 39, a P-type substrate 30, an N-type well 36, and a P-region 38 are formed. Since the N + region 37 is in contact with the N-type well 36 and the} > type substrate 30 ′, the PNP and NPN parasitic transistors are combined to form a parasitic ρνρν structure, or a thyristor between the bonding pad 31 and the ground level conductive layer. Crystal (thyristor). Another embodiment of the protection device is shown in Figures 7, 8, 9, and 10. In this embodiment, the bonding pad structure includes a p-type substrate 50, a bonding pad 51, and an insulating layer 5 2 deposited therebetween (FIG. 8). The insulating layer 52 is formed by depositing the insulating sublayers 52A, 52B, and 52C, and the laterally separated conductive layers 81, 82, and 83 are embedded between the substrate 50 and the bonding pad 51. The conductive layers 81, 82, and 83 are connected to each other by an integrated coupling member 80 (ground). P + -type diffusion region 60 and a plurality of N + -type diffusion regions 61, 62, 63,

第12頁 471154 五、發明說明（9) 與64形成於P型基板之上表面上。N+盤擴散區域61與62分 別形成第一NMOS場效電晶體之汲極與源極區域，且N+型擴 散區域62與63分別形成第二NM〇s場效電晶體之源極與汲極 區域。同樣地，N+型擴散區域63與64分別形成第三NMOS場 效電晶體之汲極與源極區域。N+型擴散區域64與另一N型 區域（未圖示）形成第四關⑽場效電晶體。舉例言之，此 等場效電晶體之閘電極係由多晶矽導電層71、72、73、與 74所提供。 ’ 如圖9與10中所示，導電層82與83之一端分別形成連 接部分82人與83人，其向側邊延伸至閘極71、72、73、與74 上。金屬接觸90、91、92、與93形成於絕緣層52上，用以 使接地導電層82與83連接於閘電極71、72、73、與74。 藉由並列金屬接觸94，使N+型區域61連接於接合墊 51 ’且藉由並列金屬接觸95，使型區域6 3連接於接合墊 51。另一方面，藉由並列金屬接觸1〇2與1〇3，使…型區域 6 2與64分別連接於中間導電層82與83。藉由並列金屬接觸 101使P+區域60偶合於中間導電層81，以形成由p+型區域60 與相鄰之N+型區域61所形成之二極體。 因而’ NMOS場效電晶體之線形陣列係沿著接合墊5丨之 一侧’作為預定的極性之靜電放電用之保護裝置，而二極 體作為相反極性之充電之保護裝置。 ^ 如圖11中所示，第三實施例之接合墊結構包含一鏈連 績排列之N+汲極與源極區域至65、複數個閘極區域至 74 ’其每一個皆位於相連續之汲極與源極區域間、以及〆Page 12 471154 V. Description of the invention (9) and 64 are formed on the upper surface of the P-type substrate. N + disk diffusion regions 61 and 62 form the drain and source regions of the first NMOS field effect transistor, respectively, and N + type diffusion regions 62 and 63 form the source and drain regions of the second NMOS field effect transistor, respectively. . Similarly, the N + type diffusion regions 63 and 64 form the drain and source regions of the third NMOS field effect transistor, respectively. The N + -type diffusion region 64 and another N-type region (not shown) form a fourth gate field effect transistor. For example, the gate electrodes of these field effect transistors are provided by polycrystalline silicon conductive layers 71, 72, 73, and 74. As shown in FIGS. 9 and 10, one end of each of the conductive layers 82 and 83 forms a connecting portion 82 and 83, respectively, which extends sideways to the gate electrodes 71, 72, 73, and 74. Metal contacts 90, 91, 92, and 93 are formed on the insulating layer 52 for connecting the ground conductive layers 82 and 83 to the gate electrodes 71, 72, 73, and 74. The N + type region 61 is connected to the bonding pad 51 'by the parallel metal contact 94, and the type region 63 is connected to the bonding pad 51 by the parallel metal contact 95. On the other hand, by juxtaposed metal contacts 102 and 103, the ... type regions 62 and 64 are connected to the intermediate conductive layers 82 and 83, respectively. The P + region 60 is coupled to the intermediate conductive layer 81 by the side-by-side metal contact 101 to form a diode formed by the p + type region 60 and the adjacent N + type region 61. Therefore, the 'NMOS field effect transistor linear array is along one side of the bonding pad 5 丨' as a protection device for electrostatic discharge of a predetermined polarity, and the diode is a protection device for charging of an opposite polarity. ^ As shown in FIG. 11, the bonding pad structure of the third embodiment includes a chain of N + drain and source regions to 65 and a plurality of gate regions to 74 ′, each of which is located in a continuous drain. Between source and source regions, and

第13頁 471154 五、發明說明（ίο) --- 對P+區域60與66，丨分別位於N+區域陣列之相#端。藉由 線94、95、與96所代表之金屬接觸，N+區域61、63、與65 連接於墊51，作為汲極電極。藉由金屬接觸1〇2與以及 導電層82與83，使Μ區域6丨與64接地，作為源極電極，所 有T電極71至74以及P區域6〇與66亦皆接地。『區域鏈之 始&與終翊部分係汲極區域6 1與6 5，俾與相鄰之P+區域β 〇 與6 6形成ΡΝ接面二極體，該Ρ區域6〇與66經由金屬接觸 101與104以及導電層81與84而接地。 當由於預定的極性之靜電放電使介於!^+區域6丨與？型 基板50間之接面為正偏壓時，Ν+區域6丨與p+區域6〇會形成 一極體，該ρ+區域β 〇用以釋放能量。假若經由相反極性之 靜電放電使此接面為逆偏壓，則Ν+區域6丨與相鄰的Ν+區域 62形成閘極接地M〇SFET，該Ν+區域62用以釋放能量。Ν+區 域6 6與相鄰的Ν+區域6 5之動作亦相同。 藉由重複相同的没極、閘極、與源極之圖案，可提供 所需的汲極、閘極、與源極鏈之長度。Page 13 471154 V. Description of the invention (ίο) --- For the P + regions 60 and 66, they are located at the phase # ends of the N + region array, respectively. By the lines 94, 95, and the metal contact represented by 96, the N + regions 61, 63, and 65 are connected to the pad 51 as drain electrodes. By the metal contact 102 and the conductive layers 82 and 83, the M regions 6 and 64 are grounded, and as source electrodes, all the T electrodes 71 to 74 and the P regions 60 and 66 are also grounded. "The beginning and end of the regional chain are the drain regions 6 1 and 65, and the adjacent P + regions β 0 and 6 6 form a PN junction diode. The P regions 60 and 66 pass through the metal. The contacts 101 and 104 and the conductive layers 81 and 84 are grounded. When due to the electrostatic discharge of a predetermined polarity, it is between! ^ + Region 6 and? When the interface between the type substrates 50 is positively biased, the N + region 6 丨 and the p + region 60 will form a polar body, and the ρ + region β will release energy. If the junction is reverse biased by electrostatic discharge of opposite polarity, the N + region 6 and the adjacent N + region 62 form a gate-grounded MOSFET, which is used to release energy. The operations of the N + region 65 and the adjacent N + region 65 are the same. By repeating the same pattern of gate, gate, and source, the required length of the drain, gate, and source chains can be provided.

第14頁Page 14

Claims (1)

471154 皇號8811幻59 车 b月曰____ 六、申請專利範圍 1 · 一種積體電路用之接合墊結構，包含·· 一半導體基板（10; 30)，其具有第一與第二擴散區 域（17 、 18 、 36-40 ); 一輪出/輪入接合墊（11;31); —絕緣層（12 ; 32A、32B )，形成於該基板上，該絕 緣層之至少一部份係由該接合墊所覆蓋，· 一弟一導電層（1 4 ; 3 4 )，位於該絕緣層中’用以連 接於接地位準導電層，以及一第二導電層（15，33)，位 於該絕緣層中且橫向分離於該第一導電層； 複數個並列金屬接觸（2 5 ; 4 5 )，位於該絕緣層中， 用以建立介於該第二導電層（1 5 ; 33 )與該接合墊（1 1 ; 31 )間之接觸；以及 複數個並列金屬接觸（22 ; 43、44 )，位於該絕緣層 中’用以建立介於該第一擴散區域（1 7 ; 3 9、4 0 )與該第 —導電層（1 4 ; 3 4 )間之接觸，及複數個並列金屬接觸 (23 ; 41、42 )，位於該絕緣層中，用以建立介於該第二 擴散區域（18 ; 3 6- 38 )與該第二導電層（15 ; 33 )間之 接觸。 2中如申請專利範圍第1項之積體電路用之接合墊結構，其 3所有該金屬接觸之熔點皆高於該金屬墊之熔點。 中^如々申請專利範圍第1項之積體電路用之接合墊結構，其 曰垓第一與該第二擴散區域以及該基板皆包含一雙載子電471154 King No. 8811 magic 59 car b month said ____ VI. Patent application scope 1 · A bonding pad structure for integrated circuits, including a semiconductor substrate (10; 30), which has first and second diffusion regions (17, 18, 36-40); a round-out / round-in bonding pad (11; 31);-an insulating layer (12; 32A, 32B) formed on the substrate, at least a part of the insulating layer is made of Covered by the bonding pad, a conductive layer (1 4; 3 4) is located in the insulating layer 'for connecting to the ground level conductive layer, and a second conductive layer (15, 33) is located in the The insulating layer is laterally separated from the first conductive layer; a plurality of side-by-side metal contacts (2 5; 4 5) are located in the insulating layer to establish a gap between the second conductive layer (1 5; 33) and the Contact between the bonding pads (1 1; 31); and a plurality of side-by-side metal contacts (22; 43, 44) located in the insulating layer 'for establishing between the first diffusion region (1 7; 3 9, 4 0) the contact with the first conductive layer (1 4; 3 4), and a plurality of parallel metal contacts (23; 41, 42), located in the insulation In, for establishing between the second diffusion region (18; 36-38); a contact (3315) between the conductive layer and the second. For example, if the bonding pad structure for integrated circuit in item 1 of the patent application in item 2, the melting point of all the metal contacts is higher than the melting point of the metal pad. The structure of the bonding pad for integrated circuits in item 1 of the scope of patent application of the Chinese patent, the first diffusion region and the second diffusion region, and the substrate both include a double carrier 471154 _案號88118359_1°^厶月曰 修正_ 六、申請專利範圍 中該第一與該第二擴散區域（1 7、1 8 )之導電型態皆相反 於該基板之導電型態。 5. 如申請專利範圍第1項之積體電路用之接合墊結構，更 包含： 一第三導電層（1 3 )，位於該絕緣層中，且橫向分離 於該第一導電層（14); 一第一複數個並列金屬接觸（2 4 )，位於該絕緣層 中，用以建立介於該第三導電層（13)與該金屬墊（11) 間之接觸；以及 一第二複數個並列金屬接觸（2 1 )，位於該絕緣層 中，用以建立介於該基板之該第三擴散區域（1 6 )與該第 三導電層（1 3 )間之接觸。 6. 如申請專利範圍第5項之積體電路用之接合墊結構，其 中該金屬接觸（2 4、2 1 )之熔點皆高於該金屬墊之熔點。 7. 如申請專利範圍第5項之積體電路用之接合墊結構，其 中該基板之該第三擴散區域（1 6 )之導電型態皆相反於該 基板之導電型態。 8. 如申請專利範圍第1項之積體電路用之接合墊結構，其 中該第一與該第二擴散區域（36-4 0 )以及該基板包含一 閘流電晶體（t h y r i s t 〇 r ) ◦ 9. 如申請專利範圍第1項之積體電路用之接合墊結構，其 中該第一擴散區域包含一第一對擴散區域（39、40 )，該 第一對擴散區域具有相反之導電型態，並且其中該第二擴 散區域包含一第二對擴散區域（3 7、3 8 )，該第二對擴散471154 _Case No. 88118359_1 ° ^ Yueyue Yue Amendment_ VI. In the scope of patent application, the conductive types of the first and second diffusion regions (17, 18) are opposite to the conductive type of the substrate. 5. If the bonding pad structure for integrated circuit of item 1 of the patent application scope further includes: a third conductive layer (1 3), which is located in the insulating layer and is laterally separated from the first conductive layer (14) A first plurality of side-by-side metal contacts (2 4), located in the insulating layer, for establishing a contact between the third conductive layer (13) and the metal pad (11); and a second plurality The side-by-side metal contact (2 1) is located in the insulating layer and is used to establish a contact between the third diffusion region (16) of the substrate and the third conductive layer (1 3). 6. If the bonding pad structure for integrated circuit of item 5 of the patent application scope, wherein the melting point of the metal contact (24, 21) is higher than the melting point of the metal pad. 7. For a bonding pad structure for an integrated circuit according to item 5 of the patent application, wherein the conductive type of the third diffusion region (16) of the substrate is opposite to the conductive type of the substrate. 8. The bonding pad structure for an integrated circuit such as the item 1 in the scope of the patent application, wherein the first and the second diffusion regions (36-4 0) and the substrate include a thyristor (thyristor). 9. For example, a bonding pad structure for an integrated circuit of the scope of patent application, wherein the first diffusion region includes a first pair of diffusion regions (39, 40), and the first pair of diffusion regions have opposite conductive types. And wherein the second diffusion region includes a second pair of diffusion regions (37, 3 8), the second pair of diffusion regions 第16頁 471154 案號 88118359 正 修 六、申請專利範圍 區域具有相 導體井之導 二對擴散區 1 0.如申請 其中該第二 (36 )中且 11. 一種積 一半導 (61 ^ 62 ) #能5 體型 導電 半導 一之 及板 以基 ，該 態於 型反 電相 導態 之型 反電 之 中 丨域 38第區 、圍散 37範擴 C利之 域專對 中 井 該 於 成 形 係 半第 士5 士 3 構 結 墊 合 接 之 用 路 體 積 之 項 井 該 入 嵌 分 ΚΓ it口 係 含 構 。 結 外墊 之合 井接 該之 於用 位路 分電 部體 反 域相 區皆 擴型 二電 第導 與之 一域 第區 有散 具擴 其二 ’ 第 }該 50與 (-板第 基該 體， •，出緣由一導一建 二建之二位散 板輸絕係第準第以 第以間第}擴 基一 一份一位一用；一用}一71二 該 部地 ，觸 ，82^第 於 一 接 中接 中C 層該 塾 合 接 入 輸 層 少 至 之 層 緣 絕 該 上 板 基 該 於 成 形 於 接 自c 以 用 中 層 緣 絕 •"5 於 ;位 蓋’ 覆3 所82 墊C 合層 接電 該導 4 /fv 9 C域 觸區 接 散 屬擴 金 一 列第 並該 •，個於 層數介 電複立 之 層間 緣墊 絕合 該接 於該 位與 C域 觸區 接散 屬擴 金二 列第 並該 個於 數介 複立 層 緣 絕 玄 古σ 於 位 層 ^¾ ^Η 導 及71 以C ; 觸電 接導 電 導 二 第 該 中 層 緣 絕 該 於 位 與域 一 區 第散 該擴 於二 介第 係該 徑與 路一 流第 電該 亥 ， 古ΐί ’ 間 上? 之62 徑、 路61 流C 電域 於區Page 16 471154 Case No. 88118359 Amendment VI. The patent application area has two pairs of diffusion zones with phase conductor wells. 10. If the application is in the second (36) and 11. A product half guide (61 ^ 62) # It can be a 5 type conductive semiconducting one and a plate based. This state is in the type of anti-electrical phase conduction state. The domain 38 area, the area of the 37-span expansion Cli domain should be used in the forming system. Taxi 5 Taxi 3 The construction volume of the joints used by the entry wells should be embedded in the κΓ it mouth. The connection of the outer pads and the connection of the anti-phase phase area of the power distribution unit is expanded. The second electric conductance and the first electric field are divergent. The second and the second are the second and the second. The basic body, •, the origin of the two scattered boards lost by one guide, one built, two built, is the first standard, the first, the first, the first, the second, the first, the first, the first, and the first; Touch, 82 ^ The first layer is connected to the middle layer of the C, which is connected to the lowest layer of the transmission layer, and the upper board base should be formed on the connection from c to use the middle layer to be isolated. &Quot; 5 at; Cover 'cover 3, 82 pads, C-layer connection, the conductive 4 / fv 9 C-domain contact area dispersion is the first row of the expansion, and • the number of interlayer edge pads in the dielectric dielectric compound layer must be connected to This bit intersects with the contact area of the C domain, which belongs to the second column of the gold expansion. This one is on the edge of the digital complex layer. It is σ at the bit layer. ^ ¾ ^ Η and 71; C; the electric contact is the second middle layer. The reason should be in place and the first area of the domain should be scattered, the extension should be in the second line, the path and the road, the first line, the electricity, the ancient city. ? The 62-path, 61-stream C electric domain in the district 第17頁 471154 案號 88118359 年 G月 >0曰 修正 層 ^g1 導 1 第 圍該 懷於 矛 參觸 帽接 六係 ，相域 構態區 結型散 墊電擴 合導三 接其第 之，該 用/^ ， 路60態 電丨型 體域電 積區導 之散之 項擴} 1 三 1 一—I - 6 第第丨 圍一域 範含區 \^包散 專更擴 請板 一 申基第 如該該 .中於 2其反 及 以 :中 含 包52 5 更C ， 層 緣 1 邑 6 β C該 域於 區位 散， 擴> 一 1 _ 8 第C 該層 於電 近導 鄰三 係第 ο 一—I 11 οο Γν Γν 觸層 接電 屬導 金三 列第 並該 個於 數介 複立 三建 第以 一 用 中 層 緣 絕 該 於 位 域 區 散 擴 三 第 該 ΠΗ、 ，相 構態 結型 墊電 合導 接其 之， 用3 各 3 Ά 6 ^^/—\ 體域 積區 之散 項擴 11四 第第 圍一 。範含 觸利包 接專更 之請板 間申基 如該 )0中 6 . C 3其 :C域 含觸區 包接散 更屬擴 ,金四 態歹第 型並該 電個於 導數介 之複立 板四建 基第以 該一用 於 ’ 反 中 之 層間 緣墊 絕合 該接 於該 位與 觸 接 層 電 導 四 第- 第 該 於 介 中 層 緣 絕 該 於 位 觸之 接徑 屬路 金流 列電 並一 個於 數位 複} 四72 第C 該層 與電 導 四 第 該 間 第 該 於 介 係 徑 路 流 該 域 區 散 擴 四。 \ly 亥 2 士'口 8 與C 二層 電 導- 第 該 於 觸 接 且 ’熔 構之 結質 墊物 合屬 接金 之該 用， 路質 電物 體屬 積金 之 \ 項含 1 包 Ί1 第皆 圍觸 範接 屬 專金 請該 申有 如所 .中 [4其 構 結 墊 合 接 之 用 路 電 體 積 之 項 ο 2 T· A 點第 溶圍 之範 塾利 合專 接請 該申 人、、 口 高Page 17 471154 Case No. 88118359 G &0; Correction layer ^ g1 Guide 1 This should be connected to the sixth series with the contact cap of the spear, and the junction-type scattered pad electric expansion guide of the phase domain configuration area is the third. In other words, the use of / ^, the expansion of the 60-state electric field-type body area electric product area divergence term} 1 3 1 1-I-6 The first area of the domain range containing area \ ^ Banyi Shenji should do the same. In the middle of the 2 and the reverse: inclusive package 52 5 more C, layer margin 1 yi 6 β C the domain is scattered in the location, expand> 1_ 8th C this layer in The first three lines of electrical proximity are ο I—I 11 οο Γν Γν The contact layer is electrically connected to the third row of the gold guide and the third one is built in the number three complex. The first use of the middle layer should definitely spread in the area. The first ΠΗ, 构, and the phase-structured junction pads are electrically connected to each other, and the 3rd 3 Ά 6 ^^ / — \ bulk area is used to expand the 11th and 4th circumferences. Fan Han touches the package, please refer to the board application.) 6 in 0. C 3 Its: The C domain contains the touch zone. The packet is more expanded. The fourth base of the compound riser is the first one used for the anti-intermediate edge pads, which should be connected to the bit and the contact layer. The fourth conductive layer is the first one, which should be connected to the middle layer. Lu Jinliu is connected to a digital complex} 4 72 The C layer and the conductance of the fourth and the fourth are spread out in the area of the median runoff. \ ly 海 2 士 '口 8 and C two-layer conductance-should be used for contacting and the' melt's junction mat should be used for gold deposits, and the road quality electric objects should be MPF's. 1 item includes 1 bag 1 The contact of Fanjiewei Fan belongs to the special application, please apply for the application. Chinese [4 The item of the volume of the road electricity used for the connection of the structure pads. 2 T · A People, mouth high 第18頁 471154 _案號 88118359_γ年 月 >。曰__ 六、申請專利範圍 其中該第二與該第三複數個並列金屬接觸皆包含一金屬物 質，該金屬物質之熔點高於該接合墊之熔點。 16. 如申請專利範圍第1 3項之積體電路用之接合墊結構， 其中該第四複數個並列金屬接觸皆包含一金屬物質，該金 屬物質之熔點高於該接合墊之熔點。 17. 如申請專利範圍第11項之積體電路用之接合墊結構， 其中該第一與該第二擴散區域（61、62)與該第二導電層 (7 1 )形成一金屬氧化物半導體場效電晶體。 18. 一種積體電路用之接合墊結構，包含： 一半導體基板（50 ); 一輸出/輸入接合墊（51); 一絕緣層（5 2 )，形成於該基板上，該絕緣層之至少 一部份係由該接合墊所覆蓋； 第一、第二、與第三導電層（81、82、84)，彼此橫 向分離，位於該絕緣層中，用以接地； 第一、第二、與第三擴散區域（61、6 2、6 3 )，位於 該基板中，該第一、第二、與第三擴散區域具有第一導電 型態，該第一導電型態相反於該基板之導電型態； 第五與第六擴散區域（6 0、6 6 )，位於該基板中，該 第五與該第六擴散區域具有第二導電型態，該第二導電型 態相反於該第一導電型態，並且分別鄰近於該第一與該第 三擴散區域（6 1、6 3 ); 第一與第二複數個並列金屬接觸（9 4、9 5 )，位於該 絕緣層中，用以建立介於該第一和該第三擴散區域（6 1、Page 18 471154 _Case No. 88118359_Year Month >. __ VI. Scope of patent application Where the second and the third parallel metal contacts each include a metal substance, the melting point of the metal substance is higher than the melting point of the bonding pad. 16. For example, the bonding pad structure for integrated circuits of item 13 in the patent application range, wherein the fourth plurality of parallel metal contacts each include a metal substance, and the melting point of the metal substance is higher than the melting point of the bonding pad. 17. The bonding pad structure for an integrated circuit as claimed in item 11 of the scope of patent application, wherein the first and second diffusion regions (61, 62) and the second conductive layer (7 1) form a metal oxide semiconductor Field effect transistor. 18. A bonding pad structure for an integrated circuit, comprising: a semiconductor substrate (50); an output / input bonding pad (51); an insulating layer (5 2) formed on the substrate, at least the insulating layer A part is covered by the bonding pad; the first, second, and third conductive layers (81, 82, 84) are laterally separated from each other and are located in the insulating layer for grounding; the first, second, and And the third diffusion region (61, 6 2, 6 3) are located in the substrate, and the first, second, and third diffusion regions have a first conductivity type, and the first conductivity type is opposite to that of the substrate Conductivity type; fifth and sixth diffusion regions (60, 6 6), which are located in the substrate, the fifth and sixth diffusion regions have a second conductivity type, and the second conductivity type is opposite to the first conductivity type A conductive type, and adjacent to the first and the third diffusion regions (6 1, 6 3); the first and the second plurality of parallel metal contacts (9 4, 9 5) are located in the insulating layer, For establishing between the first and the third diffusion region (6 1, 第19頁 471154 _案號88118359_年G月U曰 修正_ 六、申請專利範圍 6 3 )與該接合墊間之接觸； 第三與第四複數個並列金屬接觸（1 〇 1、1 〇 4 )，位於 該絕緣層中，用以分別建立介於該第五和該第六擴散區域 (60、66 )與該第一和該第三導電層（81、84 )間之接 觸； 一第五複數個並列金屬接觸（1 0 2 )，位於該絕緣層 中，用以建立介於該第二擴散區域（6 2 )與該第二導電層 (8 2 )間之接觸；以及 第四與第五導電層（71、72 )，彼此橫向分離，位於 該絕緣層中，該第四導電層（71 )位於一電流路徑之上， 該電流路徑係介於該第一與該第二擴散區域（6 1、6 2 ) 間，該第一與該第二擴散區域係接觸於該第一導電層（8 2 )，及該第五導電層（7 2 )位於一電流路徑之上，該電流 路徑係介於該第二與該第三擴散區域（6 1、6 3 )間，該第 一與該第二擴散區域係接觸於該第一導電層（82 )。 19. 如申請專利範圍第1 8項之積體電路用之接合墊結構， 其中該金屬接觸皆包含一金屬物質，該金屬物質之爆點高 於該接合墊之熔點。 20. 如申請專利範圍第1 8項之積體電路用之接合墊結構， 其中該第一與該第二擴散區域（6 1、62 )以及該第四導電 層（7 1 )形成一第一金屬氧化物半導體場效電晶體，並且 該第二與該第三擴散區域（6 2、6 3 )以及該第五導電層 (72 )形成一第二金屬氧化物半導體場效電晶體。 21. 一種積體電路用之靜電放電保護裝置，包含： 一基板（1 0 ; 3 0 );Page 19 471154 _ Case No. 88118359_Amended U__ Sixth, the scope of patent application 6 3) contact with the bonding pad; third and fourth multiple parallel metal contacts (101, 〇4 ), Located in the insulating layer, for establishing contact between the fifth and the sixth diffusion regions (60, 66) and the first and the third conductive layers (81, 84), respectively; a fifth A plurality of side-by-side metal contacts (1 0 2) are located in the insulating layer for establishing a contact between the second diffusion region (6 2) and the second conductive layer (8 2); Five conductive layers (71, 72) are laterally separated from each other, and are located in the insulating layer. The fourth conductive layer (71) is located above a current path, which is between the first and the second diffusion regions ( 6 1, 6 2), the first and the second diffusion regions are in contact with the first conductive layer (8 2), and the fifth conductive layer (7 2) is located above a current path, the current path Is between the second and the third diffusion region (61, 6 3), and the first and the second diffusion region are in contact with the first Layer (82). 19. For example, the bonding pad structure for integrated circuits of item 18 in the scope of patent application, wherein the metal contacts all contain a metal substance, and the explosion point of the metal substance is higher than the melting point of the bonding pad. 20. For example, the bonding pad structure for integrated circuit of item 18 in the scope of patent application, wherein the first and the second diffusion regions (61, 62) and the fourth conductive layer (7 1) form a first A metal oxide semiconductor field effect transistor, and the second and third diffusion regions (62, 63) and the fifth conductive layer (72) form a second metal oxide semiconductor field effect transistor. 21. An electrostatic discharge protection device for integrated circuits, comprising: a substrate (1 0; 3 0); 第2◦頁 --1號 881 六 '申請專概m ^^ —=出/輸入接合替 、—導電層（13、15 CU ; 31 ); 連接於該接合墊（11 )·，藉由複數個接觸（24 士 —保護裝置（16 ，以及 二置之至少一部份藉由；1 8 )，位於該基板中 二5亥保護裝置之至小t個接觸而連接於該第 覆蓋 V ~加>‘、 修正 而 25 5亥保護裝置之至少個接觸而連接於該第一導電 。 ^份係受該輸入/輸出接合墊所 :如申請專利範園第21 二置’其中該複數個接觸：〉積體電路用之靜電放電保護 2壯3·如申請專利範圍第蜀匕έ插塞接觸。 衣置，其中該插塞 1項之積體電路用之靜電放電 ，"請專利範；】高炼點之金屬物質。 、置’其中該保蔑壯 項之積體電路用之靜電放電保護 =·如申請專利範$奸包含一雙載子電晶體。 是置’其中該保護壯弟21項之積體電路用之靜電放電保護 )。 衣置包含一閘流電晶體（thyristor 26· 一種積體電略 —基板（5〇) •之靜電放電保護裝置，包含： 一輪出/輸入拯八# ^ 一保護裝置（6f、 （51 ); 蠖裒置之至少一部八三6 2、6 3 )，形成於該基板中，該保 該接合墊（51 ) 份藉由複數個接觸（94、95 )而連接於 輪出接合墊所覆笔^保護裝置之至少一部份係受該輸入/ -導電層以及 間，該導電層藉由W8 3)，介於該接合墊與該保護裝置 個接觸（102、103 )而連接於該保 蚁炝 丨編TrTT!" ------- 第21頁 471154 _案號88118359_Γ年G月 y日 修正_ 六、申請專利範圍 護裝置。 27.如申請專利範圍第26項之積體電路用之靜電放電保護 裝置，其中該複數個接觸包含插塞接觸。 2 8,如申請專利範圍第2 6項之積體電路用之靜電放電保護 裝置，其中該插塞接觸係高熔點之金屬物質。 2 9.如申請專利範圍第2 6項之積體電路用之靜電放電保護 裝置，其中該保護裝置包含一金屬氧化物半導體電晶體。 30.如申請專利範圍第26項之積體電路用之靜電放電保護 裝置，其中該保護裝置包含一個二極體。Page 2◦-1 No. 881 VI's application profile m ^^ — = out / input bonding, — conductive layer (13, 15 CU; 31); connected to the bonding pad (11), by plural 24 contacts—protective devices (16, and at least a part of the two sets are connected by; 1 8), and at least t contacts of the protective device located in the substrate are connected to the first cover V ~ plus > ', amended and connected to the first conductive by at least one contact of the 25-h protection device. ^ is subject to the input / output bonding pad: such as the application for patent fan garden No. 21 second set' where the plurality of contacts ：> Electrostatic discharge protection for integrated circuits. 2 · If the plug is in contact with the scope of the patent application, please refer to the patent. 】 High-refined metal materials. Set the electrostatic discharge protection of the integrated circuit in which the Zhuangzhuang item is used. If the patent application $ rape contains a double-transistor transistor, it is set in which the Zhuangdi is protected. 21 items of integrated circuit for electrostatic discharge protection). The clothes set contains a thyristor (a type of integrated circuit-substrate (50)), an electrostatic discharge protection device, including: a round out / input Zheng eight # ^ a protection device (6f, (51); At least one set of 853, 6, 2, 3) is formed in the substrate, and the bonding pad (51) is guaranteed to be connected to the wheel-out bonding pad by a plurality of contacts (94, 95). At least a part of the pen ^ protection device is subject to the input / -conductive layer and the conductive layer is connected to the protection device through W8 3), between the contact pads and the protection device (102, 103).炝 丨 edit TrTT! &Quot; ------- Page 21 471154 _ Case No. 88118359 _ amended on G month y of the year _ 6. Applicable patent scope protection device. 27. The electrostatic discharge protection device for an integrated circuit as claimed in claim 26, wherein the plurality of contacts include a plug contact. 28. The electrostatic discharge protection device for integrated circuits as described in item 26 of the patent application scope, wherein the contact of the plug is a metal substance with a high melting point. 2 9. The electrostatic discharge protection device for integrated circuits according to item 26 of the patent application scope, wherein the protection device includes a metal oxide semiconductor transistor. 30. The electrostatic discharge protection device for an integrated circuit as claimed in claim 26, wherein the protection device includes a diode. 第22頁Page 22
TW088118359A 1998-10-23 1999-10-21 Robust bonding pad structure for integrated circuit chips TW471154B (en)

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KR100393220B1 (en) * 2001-03-23 2003-07-31 삼성전자주식회사 Semiconductor devices for ESD protection
JP5033071B2 (en) * 2008-06-24 2012-09-26 ラピスセミコンダクタ株式会社 Manufacturing method of semiconductor device
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KR101975894B1 (en) 2012-12-04 2019-08-28 삼성전자주식회사 Apparatus for protecting electrostatic discharge

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US5149674A (en) * 1991-06-17 1992-09-22 Motorola, Inc. Method for making a planar multi-layer metal bonding pad
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US5652689A (en) * 1994-08-29 1997-07-29 United Microelectronics Corporation ESD protection circuit located under protected bonding pad
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US5700735A (en) * 1996-08-22 1997-12-23 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming bond pad structure for the via plug process
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