TW469506B

TW469506B - Pattern transfer method

Info

Publication number: TW469506B
Application number: TW89120758A
Authority: TW
Inventors: I-Hsiung Huang; Kuei-Shun Chen; Chien-Ming Wang
Original assignee: United Microelectronics Corp
Priority date: 2000-10-05
Filing date: 2000-10-05
Publication date: 2001-12-21

Abstract

A pattern transfer method transfers plural patterns arranged in array on a photo mask onto a semiconductor wafer. The semiconductor wafer consists of a substrate and a photoresist layer disposed on the surface of the substrate. The method comprises providing a light source and a photo mask to expose the photoresist layer, placing the photo mask between the light source and the photoresist layer, installing a dipole aperture having a common axis between the light source and the photo mask, and exposing the photoresist layer off-axis by the light source. During the exposure process by the light source, the dipole aperture causes patterns transferred to the photoresist layer to elongate in size along the direction parallel to the common axis and to shorten in size along the direction perpendicular to the common axis.

Description

46 95 ϋ 〇 ^____________ 五、發明說明（ι) 發明之領域本發明係提供一種光阻圖案的轉移方法，尤指一種將複數個以陣列方式排列之光阻圖案自一光罩轉移至一半導體晶片上的方法。背景說明微影製程（photolithography)是半導體製程中最重要的一個步驟，其可將積體電路（integrated circuits)的佈局（1 ay out)圖案順利地轉移到半導體晶片上。晶圓廠為了在半導體晶片上形成一設計的積體電路，必須先製作一光罩並在光罩上形成一設計的圖案’再藉由微影製程將光罩上的圖案以一定的比例轉移（transfer)到該半導體晶片表面的光阻層上。隨著積體電路的複雜度與積集度（integration)的不斷提昇’光覃上的圖案亦被設計得越來越小。然而在進行圖案轉移時’由於曝光（expo sure)製程所能製作出的圖案的臨界尺寸（critical dimension，CD)會受限於曝光機台 (optical exposure tool)的解析度極限（res〇iuti〇n limit)，因此在對於這些高密度排列的光罩圖案進行曝光製程以形成光阻圖案時，便非常容易產生光學接近效應 (optical proximity effect)，使得形成於光阻層上圖46 95 ϋ 〇 ^ ____________ V. Description of the Invention (ι) Field of the Invention The present invention provides a method for transferring a photoresist pattern, particularly a method for transferring a plurality of photoresist patterns arranged in an array from a photomask to a semiconductor. Method on wafer. Background photolithography is one of the most important steps in semiconductor manufacturing. It can smoothly transfer the integrated circuit's 1 ay out pattern to the semiconductor wafer. In order to form a designed integrated circuit on a semiconductor wafer, a fab must first make a mask and form a designed pattern on the mask. Then the pattern on the mask is transferred by a lithographic process at a certain ratio. To the photoresist layer on the surface of the semiconductor wafer. With the increasing complexity of integrated circuits and integration, the patterns on the light beams are also designed to be smaller and smaller. However, when performing pattern transfer, the critical dimension (CD) of the pattern that can be produced due to the exposure process is limited by the resolution limit (res〇iuti of the optical exposure tool). n limit), so when an exposure process is performed on these high-density mask patterns to form a photoresist pattern, it is very easy to produce an optical proximity effect, so that it is formed on the photoresist layer

46 95 0 6 五、發明說明（2) 案的轉角處（corner)將會因為過度曝光（overexP〇se)或是曝光不足（underexpose)，造成解析度減損（resolution 1 〇 s s )，進而導致所設計圖案之尺寸的縮小化，使得光罩上的圖案與光阻層上的圖案不一致或是發生轉角圓形化效應（corner rounding effect)，隶後造成於光阻層上的圖案會與原始的設計尺寸差異甚遠° 請參考圖一至圖六，圖一至圖六為習知於一半導體晶片10上定義一動態隨機存取記憶體（dynamic random access memory, DRAM)之電容下層健存電極（storage node)的尺寸與位置的示意圖。如圖一所示，半導體晶片 10包含有一基底16，以及一光阻層^設於基底16的表面。基底1 6包含一矽基底1 2，一絕緣層1 3設於矽基底1 2之上，複數個由摻雜多晶矽（doped poly silicon)所構成之接觸電極（node contact) 14設於絕緣層13之中，以及一用來形成該下層儲存電極之非晶矽層1 5設於絕缘層1 3的表面並覆蓋住各接觸電極14。如圖二所示，習知在進行微影製程前，係先依據一設計的積體電路圖案來製作一光罩2L·光罩21包含有一透明的石英基板2 3，以及複數個以矩陣方式排列的不透明之鉻，膜圖案25設於透明基板23的表面。如圖三所示，在完成光罩2 1的製作後，接著將光罩2 1安置於曝光系統3 0之中，並利用曝光系統3 0對半導體晶片1 0進行一曝光製程，然後將46 95 0 6 V. Description of the invention (2) The corner of the proposal (2) will be overexposed (underexposed) or underexposed (underexpose), resulting in resolution loss (resolution 1 〇ss), which will lead to all The reduction of the size of the design pattern makes the pattern on the photomask inconsistent with the pattern on the photoresist layer or a corner rounding effect. The pattern on the photoresist layer will be the same as the original The design dimensions are very different. Please refer to Figures 1 to 6. Figures 1 to 6 are conventional storage node (storage node) capacitors that define a dynamic random access memory (DRAM) on a semiconductor wafer 10. ) Size and location diagram. As shown in FIG. 1, the semiconductor wafer 10 includes a substrate 16 and a photoresist layer disposed on a surface of the substrate 16. The substrate 16 includes a silicon substrate 12, an insulating layer 13 is provided on the silicon substrate 12, and a plurality of node contacts 14 made of doped poly silicon are provided on the insulating layer 13 Among them, an amorphous silicon layer 15 for forming the lower storage electrode is provided on the surface of the insulating layer 13 and covers each contact electrode 14. As shown in Figure 2, before performing the lithography process, it is known to first create a mask 2L according to a designed integrated circuit pattern. The mask 21 includes a transparent quartz substrate 23, and a plurality of matrix methods. The arrayed opaque chromium, and the film pattern 25 is provided on the surface of the transparent substrate 23. As shown in FIG. 3, after the fabrication of the photomask 21 is completed, the photomask 21 is then placed in the exposure system 30, and an exposure process is performed on the semiconductor wafer 10 using the exposure system 30, and then

第5頁 46 95 0 6 五、發明說明（3) 曝光後的半導體晶片1 〇置於一顯影液中’以進行一顯影製程。曝光系統30包含有一光源32’用以曝光半導體晶片10 表面的光阻層1 7，一光源遮板3 3設於光源3 2與半導體晶片 1 0之間，一透鏡3 4設於光源遮板3 3與半導體晶片1 0之間，用以將光源3 2發出的光束聚焦於光罩2 1上，光罩2 1設於透鏡3 4與半導體晶片1 0之間，以及一透鏡3 6設於光罩2 1與半導體晶片1 0之間，用以將通過光罩2 1之光束聚焦於半導體晶片1 0表面的光阻層1 7。如圖四所示，光源遮板3 3包含有一開口 3 5設於光源遮板3 3的中心。如圖五所示，在顯影製程之後，半導體晶片1 0必須再進行數次的清洗製程，以去除顯影液以及被溶解的光阻，而於半導體晶片10表面留下一組光阻圖案19。如圖六所示，隨後進行一蝕刻製程，以光阻圖案1 9為硬罩幕垂直向下去除未被光阻圖案1 9覆蓋的非晶矽層1 5直到絕緣層1 3的表面，形成了動態隨機存取記憶體（DRAM)之電容的下層儲存電極20的輪廓。然而在上述的微影製程中，光學接近效應會造成半導體晶片10上每一個孤立的（isolated)光阻圖案19發生轉角圓形化的現象，亦即光阻圖案1 9的四個頂角係呈現一圓角而非原始設計的直角。這是因為在曝光的過程中，雖然光Page 5 46 95 0 6 V. Description of the invention (3) The exposed semiconductor wafer 10 is placed in a developing solution 'to perform a developing process. The exposure system 30 includes a light source 32 'for exposing the photoresist layer 17 on the surface of the semiconductor wafer 10, a light source shield 3 3 provided between the light source 32 and the semiconductor wafer 10, and a lens 34 provided on the light source shield. 3 3 and the semiconductor wafer 10 are used to focus the light beam emitted by the light source 32 on the mask 21, and the mask 21 is provided between the lens 34 and the semiconductor wafer 10, and a lens 36 is provided. A photoresist layer 17 between the photomask 21 and the semiconductor wafer 10 for focusing the light beam passing through the photomask 21 on the surface of the semiconductor wafer 10. As shown in FIG. 4, the light source shield 33 includes an opening 35 provided at the center of the light source shield 33. As shown in FIG. 5, after the development process, the semiconductor wafer 10 must be cleaned several times to remove the developing solution and the dissolved photoresist, leaving a set of photoresist patterns 19 on the surface of the semiconductor wafer 10. As shown in FIG. 6, an etching process is subsequently performed, and the photoresist pattern 19 is used as a hard mask to vertically remove the amorphous silicon layer 15 not covered by the photoresist pattern 19 until the surface of the insulating layer 13 is formed. The outline of the lower storage electrode 20 of the capacitor of the dynamic random access memory (DRAM). However, in the above-mentioned lithography process, the optical proximity effect will cause the corner rounding of each of the isolated photoresist patterns 19 on the semiconductor wafer 10, that is, the four corner systems of the photoresist pattern 19 Presents a rounded corner instead of a right angle as originally designed. This is because during the exposure, although the light

第6頁 469506 五、發明說明（4) 源的照射能量相同，但是光阻層1 7上各部位的獲得照射能 I 量卻不盡相同。所以在半導體晶片1 0上光阻圖案1 9的轉角處將會因為獲得過多的照射能量，造成過度曝光，使得光阻圖案19的轉角處形成圓形的輪廓。甚至產生更嚴重的光學接近效應，會使得光阻圖案1 9的尺寸縮小化，即光阻圖案1 9的尺寸小於原始的設計尺寸而呈現如島嶼般的形狀。 I 因為光阻圖案1 9的尺寸小於原始的設計圖案（圖五中以虛 I 線表示之圖案），使得後續形成的電容下層儲存電極2 0的 | 尺寸小於原先的設計尺寸，進而降低了電容下層儲存電極丨 2 0所能儲存的電荷容量，影響了積體電路的電性表現。 | 發明概述 t ! 本發明之主要目的在於提供一種光阻圖案的轉移方 | 法，以解決上述問題。 i ] 本發明係提供一種光阻圖案的轉移方法，該方法是用 I來將複數個以陣列方式排列之光阻圖案自一光罩轉移至一 i '1 半導體晶片上，該半導體晶片包含有一基底，以及一光阻 :1 I 層設於該基底表面。該方法係先提供一光源以及一光罩， | 用以曝光該光阻層，接著將該光罩安置於該光源與該光阻 I層之間。然後安置一具有設於一共同軸上之兩個偶極孔的光源遮板於該光源與該光罩之間，使該光源偏軸曝光該光阻層。當該使用該光源進行曝光製程時，該偶極孔光源遮Page 6 469506 V. Description of the invention (4) The source has the same irradiation energy, but the amount of obtained irradiation energy I on the photoresist layer 17 is not the same. Therefore, the corners of the photoresist pattern 19 on the semiconductor wafer 10 will be overexposed because of obtaining too much irradiation energy, so that a round outline will be formed at the corners of the photoresist pattern 19. Even a more serious optical proximity effect will reduce the size of the photoresist pattern 19, that is, the size of the photoresist pattern 19 is smaller than the original design size and presents an island-like shape. I Because the size of the photoresist pattern 19 is smaller than the original design pattern (the pattern indicated by the dashed I line in Figure 5), the size of the subsequent storage capacitor storage layer 20 | is smaller than the original design size, which reduces the capacitance. The storage capacity of the lower storage electrode 20 can affect the electrical performance of the integrated circuit. SUMMARY OF THE INVENTION The main purpose of the present invention is to provide a method for transferring a photoresist pattern to solve the above problems. i] The present invention provides a photoresist pattern transfer method. The method uses I to transfer a plurality of photoresist patterns arranged in an array from a photomask to an i '1 semiconductor wafer. The semiconductor wafer includes a The substrate and a photoresist: 1 I layer are disposed on the surface of the substrate. The method first provides a light source and a photomask for exposing the photoresist layer, and then places the photomask between the light source and the photoresist I layer. Then, a light source shield having two dipole holes provided on a common axis is disposed between the light source and the mask, so that the light source is off-axis to expose the photoresist layer. When the light source is used for the exposure process, the dipole hole light source is shielded.

第7頁 469506 五、發明說明（5) 板將增長轉移至該光阻層之光阻圖案在平行於共同軸方向的尺寸而縮短在垂直共同軸方向的尺寸3 本發明可以縮短呈陣列方式排列之光阻圖案的間隔距離，以符合下一世代半導體製程之設計尺寸的要求。該光源遮板可使該光源偏轴照射於該半導體晶片表面的光阻層上，進而增長轉移至該半導體晶片上之光阻圖案在平行於共同軸方向的尺寸，並縮短該光阻圖案在垂直共同軸方向的尺寸。由於該光源遮板可以縮短該光阻圖案在垂直共同軸方向的尺寸，因此利用本發明可縮短以陣列方式排列之光阻圖案的間隔距離，即本發明可以縮短呈陣列方式排列之電容下層儲存電極、接觸洞或閘極的間隔距離，以符合下一世代半導體製程之設計尺寸的要求。發明之詳細說明請參考圖七至圖十二，圖七至圖十二為應用本發明於於一半導體晶片4 0上形成一動態隨機存取記憶體之電容下層儲存電極的尺寸與位置的示意圖。如圖七所示，半導體晶片40包含有一基底46，以及一光阻層47設於基底4 6的表面。基底46包含一矽基底42，一由矽氧化合物所構成之絕緣層4 3，複數個由摻雜多晶矽所構成之接觸電極4 4設於絕緣層4 3之中，以及一用來形成該下層儲存電極之非晶矽層 4 5設於絕緣層4 3的表面並覆蓋住各接觸電極4 4。其中接觸Page 7 469506 V. Description of the invention (5) The plate transfers the growth of the photoresist pattern of the photoresist layer in a direction parallel to the common axis direction and shortens the size in the vertical common axis direction. The distance between the photoresist patterns can meet the design size requirements of the next generation semiconductor process. The light source shield can make the light source off-axis irradiate the photoresist layer on the surface of the semiconductor wafer, thereby increasing the size of the photoresist pattern transferred to the semiconductor wafer in a direction parallel to the common axis, and shortening the photoresist pattern. Dimensions perpendicular to the common axis. Since the light source shield can shorten the size of the photoresist pattern in the direction of the common axis, the distance between the photoresist patterns arranged in an array can be shortened by using the present invention, that is, the present invention can shorten the storage of capacitors arranged in an array The distance between electrodes, contact holes or gates to meet the design size requirements of the next generation semiconductor process. For a detailed description of the invention, please refer to FIG. 7 to FIG. 12. FIG. 7 to FIG. 12 are schematic diagrams showing the size and position of a storage electrode of a capacitor lower layer of a dynamic random access memory formed on a semiconductor wafer 40 using the present invention . As shown in FIG. 7, the semiconductor wafer 40 includes a substrate 46, and a photoresist layer 47 is provided on the surface of the substrate 46. The substrate 46 includes a silicon substrate 42, an insulating layer 4 3 made of silicon oxide compound, a plurality of contact electrodes 4 4 made of doped polycrystalline silicon are provided in the insulating layer 4 3, and a lower layer is used to form the lower layer. The amorphous silicon layer 45 of the storage electrode is provided on the surface of the insulating layer 43 and covers each contact electrode 44. Which contacts

第8頁Page 8

J 469506 五、發明說明（6) 電極44係用來電連接一設於石夕基底42表面上之M〇S電晶體的汲極（未顯示）以及後續所形成的電容下層儲存電極50。如圖八所示，利用本發明方法來進行微影製程之前’ 必須先依據設計的積體電路圖案製作光草51。光罩51包含有一透明的石英基板53，以及複數個以矩陣方式排列的不透明之鉻膜圖案5 5設於透明基板53的表面。每一個絡膜圖案5 5均相對應並且涵蓋一個欲形成於半導體晶片表面之光阻圖案4 9的位置。如圖九所示’完成光罩51的製作之後，接著將光罩5 1安置於曝光系統6 0之中’並利用一曝光系統 6 0對半導體晶片4 0進行一曝光製程，使光阻層4 7相對應光罩5 1上的光罩圖案5 5進行圖案轉移。曝光系統6 0包含有一光源6 2，用以曝光半導體晶片4 0 表面的光阻層4 7，一光源遮板6 3設於光源6 2與半導體晶片 4 0之間，一透鏡6 4設於光源遮板6 3與半導體晶片4 0之間，用以將光源6 2發出的光束聚焦於光罩5 1上，光罩5 1設於透鏡6 4與半導體晶片4 0之間，以及一透鏡6 6設於光罩5 i與半導體晶片4 0之間，用以將通過光罩5 1之光束聚焦於半導體晶片40表面的光阻層47。請參考圖十，圖十為本發明之光源遮板6 3的俯視圖。光源遮板6 3具有設於一共同軸上的兩個偶極孔65，當以爆光乐統6 0對半導體晶片表面的光阻層47進行曝光製程時，J 469506 V. Description of the invention (6) The electrode 44 is used to electrically connect a drain (not shown) of a MOS transistor provided on the surface of the Shixi substrate 42 and a capacitor storage electrode 50 formed later. As shown in FIG. 8, before using the method of the present invention for the photolithography process, the light grass 51 must be made according to the designed integrated circuit pattern. The photomask 51 includes a transparent quartz substrate 53 and a plurality of opaque chromium film patterns 55 arranged in a matrix manner on the surface of the transparent substrate 53. Each of the pellicle patterns 55 corresponds to and covers a position of a photoresist pattern 49 to be formed on the surface of the semiconductor wafer. As shown in FIG. 9, after the fabrication of the photomask 51 is completed, the photomask 51 is then placed in the exposure system 60 and an exposure system 60 is used to perform an exposure process on the semiconductor wafer 40 to make the photoresist layer. 4 7 corresponds to the mask pattern 5 5 on the mask 5 1 for pattern transfer. The exposure system 60 includes a light source 62 for exposing a photoresist layer 47 on the surface of the semiconductor wafer 40. A light source shield 6 3 is disposed between the light source 62 and the semiconductor wafer 40. A lens 64 is disposed on The light source shield 63 and the semiconductor wafer 40 are used to focus the light beam emitted by the light source 62 on the photomask 51, which is disposed between the lens 64 and the semiconductor wafer 40 and a lens The photoresist layer 47 is provided between the photomask 5 i and the semiconductor wafer 40 to focus the light beam passing through the photomask 51 on the surface of the semiconductor wafer 40. Please refer to FIG. 10, which is a top view of the light source shield 63 of the present invention. The light source shutter 63 has two dipole holes 65 provided on a common axis. When the photoresist layer 47 on the surface of the semiconductor wafer is exposed by the exposure system 60,

第9頁 i 46 95 0 6 五、發明說明（7) 光源遮板6 3上的偶極孔6 5將增長轉移至半導體晶片4 0表面之光阻圖案49在平行於共同軸方向的尺寸’並縮短光阻圖案49在垂直共同轴方向的尺寸。如圖十一所示，在完成曝光製程之後，半導體晶片40 必須放置於一顯影液中以進行一顯影製程。在顯影製裎之後，半導體晶片4 0必須再進行數次的清洗製程，以去除顯影液與被溶解的光阻，而於半導體晶片4 0上形成複數個以陣列方式排列的光阻圖案4 9。如圖十二所示，隨後進行一蝕刻製程，以光阻圖案49為硬幕罩垂直向下去除未被光阻圖案4 9覆蓋的非晶矽層4 5直到絕缘層4 3表面，形成動態隨機存取記憶體之電容下層儲存電極50的輪廓。由於偶極孔光源遮板6 3可使由光源6 2偏軸照射於半導體晶片4 0表面的光阻層4 7上，進而增長轉移至半導體晶片 40上之光阻圖案49在平行於共同軸方向的尺寸，並縮短光阻圖案49在垂直共同轴方向的尺寸，使得最後形成於半導體晶片4 0上的光阻圖案4 9係呈現一橢圖形》也就是說，本發明方法即利用偶極孔光源遮板6 3來縮短光阻圖案4 9在垂直共同韩方向的尺寸，以減小各種以陣·列方式排列之光阻圖案49的間隔距離，進而能於越來越小的半導體製程中精確地定義接觸洞（contact hole)、儲存電極（st〇rage node)或閘極（gate)等呈陣列方式排列元件的尺寸與位置。、Page 9 i 46 95 0 6 V. Description of the invention (7) The dipole holes 6 5 on the light source shield 6 3 will transfer the growth to the surface of the semiconductor wafer 4 0. The size of the photoresist pattern 49 parallel to the common axis direction ' The size of the photoresist pattern 49 in the direction of the common axis is shortened. As shown in FIG. 11, after the exposure process is completed, the semiconductor wafer 40 must be placed in a developing solution to perform a developing process. After the development process, the semiconductor wafer 40 must be cleaned several times to remove the developing solution and the dissolved photoresist, and a plurality of photoresist patterns arranged in an array manner are formed on the semiconductor wafer 40. . As shown in FIG. 12, an etching process is subsequently performed, using the photoresist pattern 49 as a hard curtain cover to remove the amorphous silicon layer 4 5 that is not covered by the photoresist pattern 4 9 vertically to the surface of the insulating layer 4 3 to form a dynamic The outline of the capacitor underlying storage electrode 50 of the random access memory. Since the dipole hole light source shield 63 can make the light source 62 off-axis irradiate the photoresist layer 47 on the surface of the semiconductor wafer 40, the photoresist pattern 49 transferred to the semiconductor wafer 40 is grown parallel to the common axis. And shorten the size of the photoresist pattern 49 in the direction of the vertical common axis, so that the photoresist pattern 49 formed on the semiconductor wafer 40 finally presents an elliptical pattern. That is, the method of the present invention uses a dipole The hole light source shield 6 3 shortens the size of the photoresist pattern 4 9 in the vertical common direction to reduce the distance between various photoresist patterns 49 arranged in an array or array, thereby enabling smaller and smaller semiconductor processes. The dimensions and positions of array elements such as contact holes, storage nodes, or gates are precisely defined in. ,

第10頁 46 95 0 6 五、發明說明（8) 因此即使光學接近效應使得形成於半導體晶片表面的光阻圖案呈現轉角圓形化，導致發生解析度受損以及無法符合下一世代半導體製程之設計尺寸（design rule)要求的情形，但是利用本發明之方法則可突破光學接近效應的影響，而於半導體晶片上形成一具有較小間隔距離且呈陣列方式排列之電容下層儲存電極、接觸洞或閘極的製程上，使得本發明可以符合下一世代半導體製程之設計尺寸的要求。相較於習知技術，本發明可以縮短以陣列方式排列之光阻圖案的間隔距離。由於本發明使用偶極孔光源遮板所形成之橢圓形光阻圖案的間隔距離A大於使用傳統圓孔光源遮板所形之圓形光阻圖案的間隔距離B (如圖十一所示），因此利用本發明可將以陣列方式排列之光阻圖案的間隔距離縮短，即本發明可以縮短呈陣列方式排列之電容下層儲存電極、接觸洞或閘極之間隔距離，以符合下一世代半導體製程之設計尺寸（design rule)的要求β 以上所述僅本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明專利之涵蓋範圍。Page 10 46 95 0 6 V. Description of the invention (8) Therefore, even if the optical proximity effect makes the photoresist pattern formed on the surface of the semiconductor wafer appear rounded, resulting in loss of resolution and failure to comply with the next-generation semiconductor process Design rule requirements, but the method of the present invention can break through the effect of optical proximity effect, and form a capacitor lower storage electrode and contact hole with a small distance and arranged in an array on the semiconductor wafer. Or the gate process makes the invention meet the design size requirements of the next generation semiconductor process. Compared with the conventional technology, the present invention can shorten the distance between the photoresist patterns arranged in an array. Because the interval A of the oval photoresist pattern formed by using the dipole hole light source shield of the present invention is greater than the interval B of the circular photoresist pattern formed by using a conventional circular hole light source shield (as shown in FIG. 11) Therefore, the present invention can shorten the distance between photoresist patterns arranged in an array, that is, the present invention can shorten the distance between storage capacitors, contact holes, or gate electrodes arranged in an array to meet the next generation of semiconductors. Requirements for the design rule of the manufacturing process β The above are only the preferred embodiments of the present invention. Any equal changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the patent of the present invention.

第11頁 469506 圖式簡單說明圖示之簡單說明圖一至圖六為習知於一半導體晶片上形成一動態隨機存取記憶體之電容下層儲存電極的尺寸與位置的示意圖。圖七至圖十二為應用本發明於於一半導體晶片上形成一動態隨機存取記憶體之電容下層儲存電極的尺寸與位置的示意圖。圖示之符號說明 10 半導體晶片 12 矽基底 13 絕緣層 14 接觸電極 15 非晶矽層 16 基底 17 光阻層 19 光阻圖案 20 下層儲存電極 21 光罩 23 透明基板 25 光罩圖案 30 曝光系統 32 光源 33 光源遮板 34 透鏡 35 開〇 36 透鏡 40 半導體晶片 42 矽基底 43 絕緣層 44 接觸電極 45 非晶矽層 46 基底 47 光阻層 49 光阻圖案 50 下層儲存電極 51 光罩Page 11 469506 Brief description of the diagrams Brief description of the diagrams Figures 1 to 6 are schematic diagrams of the size and position of the storage electrode of the capacitor underneath the capacitor used to form a dynamic random access memory on a semiconductor wafer. FIG. 7 to FIG. 12 are schematic diagrams illustrating the size and position of a capacitor lower storage electrode for forming a dynamic random access memory on a semiconductor wafer by applying the present invention. Explanation of reference symbols 10 semiconductor wafer 12 silicon substrate 13 insulating layer 14 contact electrode 15 amorphous silicon layer 16 substrate 17 photoresist layer 19 photoresist pattern 20 lower storage electrode 21 photomask 23 transparent substrate 25 photomask pattern 30 exposure system 32 Light source 33 Light source shield 34 Lens 35 On 03 Lens 40 Semiconductor wafer 42 Silicon substrate 43 Insulating layer 44 Contact electrode 45 Amorphous silicon layer 46 Substrate 47 Photoresist layer 49 Photoresist pattern 50 Lower storage electrode 51 Photomask

第12頁 469506 圖式簡單說明Page 12 469506 Schematic description

53 透明基板 55 光罩圖案 60 曝光系統 62 光源 63 光源遮板 64 透鏡 65 開口 66 透鏡53 Transparent substrate 55 Mask pattern 60 Exposure system 62 Light source 63 Light source shutter 64 Lens 65 Opening 66 Lens

Claims

4 6 9 b U 6 六、申請專利範圍 1. 一種光阻圖案（pat tern)的轉移方法’該方法是用來將複數個以陣列方式排列之光阻圖案自一光罩轉移至一半導體晶片上，該半導體晶片包含有一基底（substrate)’ 一光阻（photo resist)層設於該基底表面，該方法包含有：提供一光源，用以曝光該光阻層；安置該光罩於該光源與該光阻層之間，該光罩包含有一透明基板，以及一光罩圖案（photo mask pattern)設於該透明基板表面，該光罩圖案係由複數個以陣列狀排列的不透明區所構成，且每一不透明區均相對應並涵蓋有一個光阻圖案的相對位置；以及 ~ 安置一偶極孔光源遮板於該光源與該光罩之間，該光源遮板具有設於一共同軸上之兩個偶極孔，使該光源偏轴曝光該光阻層；其中當該使用該光源進行曝光製程時，該偶極孔光源遮板將增長轉移至該光阻層之光阻圖案在平行妓同軸方向的尺寸而縮短在垂直共同轴方向的尺订於/、门軸方 2. 如申請專利範圍第1項之方法，其中該光阻圖案係用以定義接觸洞（contact hole)、儲存電極（st〇rage n〇de) 或閘極（g a t e )之尺寸與位置。 ί申請專利範圍第1項之方法，其中該透明基板係由玻璃或石英（quartz)所構成。4 6 9 b U 6 6. Patent application scope 1. A method for transferring a photoresist pattern (pattern) 'This method is used to transfer a plurality of photoresist patterns arranged in an array from a photomask to a semiconductor wafer The semiconductor wafer includes a substrate 'and a photo resist layer disposed on the surface of the substrate. The method includes: providing a light source for exposing the photoresist layer; placing the photomask on the light source; Between the photoresist layer and the photoresist layer, the photomask includes a transparent substrate, and a photo mask pattern is provided on the surface of the transparent substrate. The photomask pattern is composed of a plurality of opaque areas arranged in an array. And each opaque area corresponds to and covers the relative position of a photoresist pattern; and ~ a dipole hole light source shield is disposed between the light source and the mask, and the light source shield has a common axis The two dipole holes above make the light source off-axis to expose the photoresist layer; wherein when the light source is used for the exposure process, the dipole hole light source shield will grow and transfer to the photoresist pattern of the photoresist layer The size in the parallel coaxial axis direction is shortened in the vertical common axis direction. The rule is set at /, the door axis side. 2. The method of the first item of the patent application, wherein the photoresist pattern is used to define a contact hole. , The size and position of the storage electrode (st〇rage node) or the gate (gate). The method of claim 1 in the patent application range, wherein the transparent substrate is made of glass or quartz.

第14頁 J 46950b 六、申請專利範圍 4. 如申請專利範圍第1項之方法，其中該不透明區係由鉻膜（chromium film)所構成。 5. 一種於一半導體晶片上形成複數個以陣列方式排列之光阻圖案的方法，該半導體晶片包含有一基底，一光阻層設於該基底表面，該方法包含有下列步驟：提供一光源，用以曝光該光阻層；安置一光罩於該光源及該光阻層之間，該光罩包含有一透明基板，以及一光罩圖案設於該透明基板表面，該光罩圖案係由複數個以陣列方式排列之不透明區所構成，且每一不透明區均相對應並涵蓋有一個光阻圖案的相對位置；安置一偶極孔光源遮板於該光源與該光罩之間，該光源遮板具有設於一共同軸上之兩個偶極孔，使該光源偏軸曝光該光阻層；進行一曝光製程，使該光阻層相對應該光罩上之光罩圖案進行圖案轉移；以及進行一顯影（development)製程，於該半導體晶片上形成該複數個以陣列方式排列的光阻圖案；其中在曝光製程中，該偶極孔光源遮板將增長轉移至光阻層之光阻圖案在平行於共同軸方向的尺寸而縮短在垂直共同軸方向的尺寸。Page 14 J 46950b 6. Scope of Patent Application 4. The method of the first scope of patent application, wherein the opaque area is composed of a chromium film. 5. A method for forming a plurality of photoresist patterns arranged in an array on a semiconductor wafer. The semiconductor wafer includes a substrate, and a photoresist layer is provided on the surface of the substrate. The method includes the following steps: providing a light source, For exposing the photoresist layer; placing a photomask between the light source and the photoresist layer, the photomask includes a transparent substrate, and a photomask pattern disposed on the surface of the transparent substrate, the photomask pattern is composed of a plurality of It consists of two opaque areas arranged in an array, and each opaque area corresponds to and covers the relative position of a photoresist pattern; a dipole hole light source shield is placed between the light source and the mask, and the light source The mask has two dipole holes provided on a common axis, so that the light source is off-axis exposed to the photoresist layer; an exposure process is performed to make the photoresist layer corresponding to the mask pattern on the mask for pattern transfer; And performing a development process to form the plurality of photoresist patterns arranged in an array on the semiconductor wafer; wherein in the exposure process, the dipole hole light source The mask shifts the size of the photoresist pattern in the photoresist layer parallel to the common axis direction and shortens the size of the photoresist pattern in the vertical common axis direction.

第15頁 4 6 9 5 .0 6 六、申請專利範圍 6. 如申請專利範圍第5項之方法，其中該光阻圖案係用以定義接觸洞、儲存電極或閘極之尺寸與位置。 7. 如申請專利範圍第5項之方法，其中該透明基板係由玻璃或石英所構成。 8. 如申請專利範圍第5項之方法，其中該不透明區係由鉻膜所構成。Page 15 4 6 9 5 .0 6 6. Scope of Patent Application 6. For the method of the fifth scope of patent application, the photoresist pattern is used to define the size and position of the contact hole, storage electrode or gate. 7. The method of claim 5 in which the transparent substrate is made of glass or quartz. 8. The method of claim 5 in which the opaque area is formed by a chromium film.

第16頁Page 16