TW468250B

TW468250B - An advanced low-leakage architecture for sub-0.18 μm salicided CMOS device

Info

Publication number: TW468250B
Application number: TW89107744A
Authority: TW
Inventors: Eng Hua Lim; Wee Lim Chong; Soh Yun Siah; Kong Hean Lee; Pei Ching Lee
Original assignee: Chartered Semiconductor Mfg
Priority date: 2000-04-25
Filing date: 2000-04-25
Publication date: 2001-12-11

Abstract

A method for forming a stepped shallow trench isolation is described. A pad oxide layer is deposited on the surface of a semiconductor substrate. A first nitride layer is deposited overlying the pad oxide layer. The first nitride layer is etched through where it is not covered by a mask to provide an opening to the pad oxide layer. A first trench is etched through the pad oxide layer within the opening and into the semiconductor substrate. A second nitride layer is deposited overlying the first nitride layer and filling the first trench. Simultaneously, the second nitride layer is anisotropically etched to form nitride spacers on the sidewalls of the first trench and the semiconductor substrate is etched into where it is not covered by the spacers to form a second trench. Ions are implanted into the semiconductor substrate underlying the second trench. The first and second trenches are filled with an oxide layer. Thereafter, the first nitride and pad oxide layers are removed completing the formation of shallow trench isolation in the fabrication of an integrated circuit device. This nitride spacer STI architecture prevents STI corner oxide recess and enables borderless contact formation. This unique process reduces junction leakage and also reduced contact leakage.

Description

4 6 82 5 Ο .奪號五、發明說明（1) 【發明之背景 Ο)發明之領本發明係4 6 82 5 〇. Winning the number V. Description of the invention (1) [Background of the invention 〇) The invention of the invention

是有關方法。 (2)習由以使用烏嘴）別是在缺墊氧化因而造中的淺 2*7於主極3 0係 ’將產於一種知技藝於裝置傳統的所限制超大型而，在物的移成角落溝渠隔動區的以橫剖生尚電域有關於積體電路裝置的製造，並且更特別地在積體電路製造中形成低漏電淺溝渠隔離的之說明技術被縮矽局部氧。淺溝渠積體電路形成淺溝除亦將造凹陷，如離區20具邊緣，其面圖表示場的問題小尺寸至0. 2 5微米或更低尺寸，所化隔離將為更小的通道寬度侵佔（隔離可被使用於消除這些侵佔，特裝置中。渠隔離區中，在溝渠被填充後，襯成淺溝渠隔離區角落區域的移除，第1圖所示。形成於半導體基板1〇有角落凹陷25。其將形成尖銳角落將導致高電場與漏電流。多晶矽閘。當多晶矽閘極超過尖銳角落2 7時。此亦為熟知的_，多晶矽包覆效應" 再者’其將造成次閥凸丘於形成在主動區中的金屬氧化物半導體電晶體中。該次閥凸丘21係為異常的金屬氧化物半導體裝置ID — VG曲線’其係由累積在尖銳淺溝渠隔離角落2 7的高電場所造成，如第2圖所舉例說明。第2圖舉例說明為飽和電流ID之函數的閘極電極電壓t ^高電場將造成以21表示的"VA -krak”現象，其將造成更高的次閥漏電流It's about the method. (2) Xi reason to use Wuzui) In addition to the lack of pad oxidation and thus the shallow 2 * 7 in the main pole 30 series' will be produced by a kind of know-how and the traditional limitations of the device. The illustrated technology, which is moved into a corner trench isolation region in a cross-section, is related to the manufacture of integrated circuit devices, and more specifically, the formation of low leakage shallow trench isolation technology in integrated circuit manufacturing is shrunk by silicon. The formation of shallow trenches in shallow trenches will also cause depressions. If there are 20 edges in the area, the plan view shows the problem of the field. The small size is 0.2 5 microns or less, and the isolation will be a smaller channel. Width encroachment (Isolation can be used to eliminate these encroachments in special devices. In the trench isolation area, after the trench is filled, the corner area of the shallow trench isolation area is lined up, as shown in Figure 1. Formed on the semiconductor substrate 1 〇There are corner recesses 25. It will form sharp corners which will lead to high electric fields and leakage currents. Polycrystalline silicon gates. When polycrystalline silicon gates exceed sharp corners 27. This is also a well-known _, polycrystalline silicon coating effect " The secondary valve hump will be caused in the metal oxide semiconductor transistor formed in the active area. The secondary valve hump 21 is an abnormal metal oxide semiconductor device ID — VG curve 'which is isolated by the accumulation of sharp shallow trenches Corner 2 7 is caused by a high voltage field, as illustrated in Figure 2. Figure 2 illustrates the gate electrode voltage t as a function of the saturation current ID. ^ A high electric field will cause the " VA -krak "phenomenon represented by 21. Which will result in a higher secondary valve leakage current

4 6 82 5 Ο _棄號 89107744 五、發明說明（2) 以及控制閥電壓的困難度。第二個問題係舉例說明於第3圖中。在源極//汲極區 34金屬矽化32後’該凹陷角落25將允許接面漏電35。第三個問題發生於形成無邊際接觸時，如第4圖所示。多晶砂接觸40被形成於淺溝渠隔離區域上，其將造成深入淺溝渠隔離區而產生過量的接觸漏電流41 ^ ' 諸多專利已經提出淺溝渠的形成。美國專利第5, 8 3 4 360號（Tesauro等人）教導蝕刻一溝渠於—基板中，’形成一石夕截刻阻絕層於該溝渠中與氮化矽間隔物於該溝渠壁面上，以及接著將矽氧化形成一個場氧化物區域於該^渠中。美國專利第5, 637, 529號（jang等人）教導形成氮化矽間隔物於一經刻晝氮化矽層壁面，並接著蝕刻溝渠於間隔物之間的基板中》鍺被離子植入於溝渠下，且一個場氧化區域被形成於該溝渠中。美國專利第5, 78〇, 325號（Ue等人）形成一離子植入區於一基板中；形成間隔物於植入區上之絕緣層中的開口壁面上；穿經植入區蝕刻出一溝渠，而使得植入區在溝渠壁面的間隔物下；以及接著填充該溝渠。美國專利第5,795,81 1號（Kim等人）形成間隔物絕緣層中的開口壁面上，以及在間隔物之間蝕刻—溝渠於基板中。一種一階段溝渠填充及回蝕完成該隔離區域。美國專，第5’ 753, 562號（Kim等人）教導一種淺溝渠隔離法，其中厂溝渠係以氮化矽與氧化物層填充。該基板被反轉其中溝渠底部將變成溝渠頂端，以避免角落凹陷。【發明之概要】 4 6 82 5 Ο 案號 89107744 年月五、發明說明（3) 修正因此，本發明的主要目的在於提供一種用於在積體電路製造中形成淺溝渠隔離的製程。 —本發明的另一個目的在於提供一種用於形成避免淺溝渠隔離場邊緣暴露之淺溝渠隔離的製程。本發明的另一個目的在於提供一種用於形成淺溝渠隔離的製程’其中主動區域與隔離區域之間有一平坦的過渡區。本發明的另一個目的在於提供一種用於形成階梯式淺溝渠隔離的製程。本發明的另一個目的在於提供一種用於形成具有縮減氮化物間隔物寬度的階梯式淺溝渠隔離的製程。另一個目的在於提供一種用於形成具有通道場植入以降低隔離漏電階梯式淺溝渠隔離的製程。另一個目的在於提供一種用於形成具有阻絕氮化物間隔物與通道場植入以降低隔離漏電階梯式淺溝渠隔離的製程。另一個目的在於提供一種用於形成作為無邊際接觸形成之蝕刻阻絕層以降低接觸漏電之自行對齊氮化物間隔物的製程。根據本發明之目的，一種用於形成階梯式淺溝渠隔離的方法係被達成。一個襯墊氧化物層被沈積於一半導體基板表面上。一個第一氮化物層被沈積於該襯墊氧化物上。未為遮罩所覆蓋的該第一氮化物層被蝕刻穿經，以提供達該襯墊氧化物層的開口。一個第一溝渠係於開口中被蝕刻 46 825 Ο _案號89107744_年月-曰修正五'發明說明（4) 穿經該槪塾氧化物層，並進入半導體基板中。一個第二氮化層被沈積於該第一氮化物層上並填充該第一溝渠。同時，該第二氮化物層被非等向性银刻，而形成氣化物間隔物於該第一溝渠的壁面上，以及未為該間隔物所覆蓋的半導體基板被蝕入’而形成一第二溝渠。離子被植入該第二溝渠底下的半導體基板中。該第一與第二溝渠係以一個氧化物層填充。其次’該第一氮化物與襯墊氧化物層被移除，而在積體電路裝置的製造中完成淺溝渠隔離的形成。該氮化物間隔物淺溝渠隔離結構可避免淺溝渠角落氧化物凹陷 ’並可使得無邊際接觸形成^該獨特的製程將降低接面漏電流’且亦降低接觸漏電流。【圖式之簡要說明】 10 半導體基板 25 角落凹陷 3 0 多晶碎閑極 34 源極/汲極區 4 0 多晶矽接觸 4 2 襯墊氧化物層 46 溝渠 50 間隔物 56 場植入區 70 閘極電極 74 矽化 78 無邊際接觸 2〇淺溝渠隔離區 27 尖銳角落 32 金屬矽化 35 接面漏電 41 接觸漏電流 44 氮化矽層 4 8 毯覆式氮化石夕 52 溝渠 6〇 .淺溝渠隔離區 7 2 源極與汲極區 7 6 中間介電層4 6 82 5 0 _Abandonment number 89107744 V. Description of the invention (2) and the difficulty of controlling the valve voltage. The second problem is illustrated in Figure 3. After the source / drain region 34 is metallized 32, the recessed corner 25 will allow the interface to leak 35. The third problem occurs when forming borderless contact, as shown in Figure 4. The polycrystalline sand contact 40 is formed on the shallow trench isolation area, which will cause an excessive contact leakage current 41 deep into the shallow trench isolation area. Many patents have proposed the formation of shallow trenches. U.S. Patent No. 5, 8 3 4 360 (Tesauro et al.) Teaches etching a trench in a substrate, 'forming a stone cutting barrier layer in the trench and a silicon nitride spacer on the trench wall surface, and then Silicon is oxidized to form a field oxide region in the trench. U.S. Patent No. 5,637,529 (jang et al.) Teaches the formation of silicon nitride spacers on the surface of the silicon nitride layer over time, and then etching the trenches in the substrate between the spacers. The germanium is implanted ion Below the trench, a field oxidation region is formed in the trench. U.S. Patent No. 5,78,0,325 (Ue et al.) Forms an ion-implanted region in a substrate; forms a spacer on an opening wall surface in an insulating layer on the implanted region; etches through the implanted region A trench such that the implanted area is under a spacer on the wall surface of the trench; and then filling the trench. U.S. Patent No. 5,795,81 1 (Kim et al.) Forms the opening walls in the spacer insulation and etches between the spacers-trenches in the substrate. A one-stage trench filling and etchback complete the isolation area. US Patent No. 5 '753, 562 (Kim et al.) Teaches a shallow trench isolation method in which a factory trench is filled with silicon nitride and an oxide layer. The substrate is inverted where the bottom of the trench becomes the top of the trench to avoid corner depressions. [Summary of the invention] 4 6 82 5 〇 Case No. 89107744 May 5. Description of the invention (3) Amendment Therefore, the main purpose of the present invention is to provide a process for forming shallow trench isolation in the manufacture of integrated circuits. -Another object of the present invention is to provide a process for forming a shallow trench isolation that avoids exposure of the edges of the shallow trench isolation field. Another object of the present invention is to provide a process for forming a shallow trench isolation 'in which there is a flat transition region between the active region and the isolation region. Another object of the present invention is to provide a process for forming a stepped shallow trench isolation. Another object of the present invention is to provide a process for forming a stepped shallow trench isolation having a reduced width of a nitride spacer. Another object is to provide a stepped shallow trench isolation process with a channel field implant to reduce isolation leakage. Another object is to provide a stepped shallow trench isolation process with barrier nitride implantation and channel field implantation to reduce isolation leakage. Another object is to provide a process for forming a self-aligned nitride spacer for forming an etch stop layer formed as a borderless contact to reduce contact leakage. According to the purpose of the present invention, a method for forming a stepped shallow trench isolation is achieved. A pad oxide layer is deposited on the surface of a semiconductor substrate. A first nitride layer is deposited on the pad oxide. The first nitride layer not covered by the mask is etched through to provide an opening to the pad oxide layer. A first trench is etched in the opening. 46 825 Ο _ Case No. 89107744_ Month-Year-Amendment V. Description of the Invention (4) Pass through the hafnium oxide layer and enter the semiconductor substrate. A second nitride layer is deposited on the first nitride layer and fills the first trench. At the same time, the second nitride layer is etched with anisotropic silver to form gaseous spacers on the wall of the first trench, and the semiconductor substrate not covered by the spacers is etched to form a first Second ditch. Ions are implanted into a semiconductor substrate under the second trench. The first and second trenches are filled with an oxide layer. Secondly, the first nitride and the pad oxide layer are removed, and the formation of the shallow trench isolation is completed in the manufacture of the integrated circuit device. The nitride spacer shallow trench isolation structure can avoid oxide depressions in the corners of the shallow trenches and allow the formation of borderless contacts. This unique process will reduce junction leakage current and also reduce contact leakage current. [Brief description of the drawing] 10 semiconductor substrate 25 corner depression 3 0 polycrystalline chip 34 source / drain region 4 0 polycrystalline silicon contact 4 2 pad oxide layer 46 trench 50 spacer 56 field implanted region 70 gate Electrode 74 Silicide 78 Boundaryless contact 2 Shallow trench isolation area 27 Sharp corner 32 Metal silicide 35 Contact leakage 41 Contact leakage current 44 Silicon nitride layer 4 8 Blanket-type nitride nitride 52 Ditch 6 60 Shallow trench isolation area 7 2 Source and drain regions 7 6 Intermediate dielectric layer

第11頁 d6 825 0 __案號89107744__年月日___ 五、發明說明（5) 【較佳實施例之說明】本發明之製程提供一種避免淺溝渠隔離場邊緣暴露， (該暴露將導致高場邊緣接面漏電）的階梯式淺溝渠隔離。一個薄的阻絕氮化物間隔物被使用於本發明的製程中。該間隔物的存在將允許通道場植入降低隔離漏電。在特徵尺寸為0. 1 8微米或更小尺寸的裝置中，此係特別地重要。本發明的製程將參考第5圖至第1 2圖而被說明。現在更特別地參考第5圖，所示為一半導體基板丨〇。一個襯墊氧化物層42被成長於該半導體基板表面上，達約 5 0至20 0埃之間的厚度。一個氮化矽層44被沈積於該襯墊氧化物層12上，達約1〇〇〇至2〇〇〇埃之間的厚度。Page 11 d6 825 0 __Case No. 89107744__Year Month and Day ___ V. Description of the invention (5) [Description of the preferred embodiment] The process of the present invention provides a way to avoid the exposure of shallow trench isolation field edges, (the exposure will be Leading to high field edge junction leakage) stepped shallow trench isolation. A thin barrier nitride spacer is used in the process of the invention. The presence of this spacer will allow channel field implantation to reduce isolation leakage. This is particularly important in devices having a feature size of 0.18 microns or less. The manufacturing process of the present invention will be described with reference to FIGS. 5 to 12. Referring now more particularly to FIG. 5, a semiconductor substrate is shown. A pad oxide layer 42 is grown on the surface of the semiconductor substrate to a thickness between about 50 and 200 Angstroms. A silicon nitride layer 44 is deposited on the pad oxide layer 12 to a thickness between about 1000 and 2000 Angstroms.

一個光阻遮罩（未表示於圖中）被形成於具有一開口的氮化物層表面上’其中該開口為淺溝渠隔離區形成處。使用傳統的光學微影及蝕刻技術，將該氮化物層蝕刻，而留下隔離區形成處的開口。、現在參考第6圖’使用該氮化矽作為一硬式遮罩，該概塾氧化物層與暴露於開口中的半導體基板被蝕刻達約 2000至3500埃的深度，以形成溝渠46。現在參考第7圖’―毯覆式氮化矽48沈積被製作於該土板表面上及溝渠中。該氮化矽層被沈積達約3 〇〇至丨〇〇〇埃的厚度。如第8圖所舉例說明’氮化矽層48被非等向性地蝕刻 ’：留下間隔物50於溝渠46壁面上。該蝕刻步驟亦同時蝕 —更深的溝渠52於未為氮化物間隔物50所覆蓋之溝渠A photoresist mask (not shown) is formed on the surface of the nitride layer having an opening ', where the opening is where the shallow trench isolation area is formed. Using conventional optical lithography and etching techniques, the nitride layer is etched, leaving an opening where the isolation region is formed. Referring now to FIG. 6 ', using the silicon nitride as a hard mask, the oxide layer and the semiconductor substrate exposed in the opening are etched to a depth of about 2000 to 3500 angstroms to form a trench 46. Referring now to Figure 7 '-blanket silicon nitride 48 deposition is made on the surface of the soil plate and in the trench. The silicon nitride layer is deposited to a thickness of about 300 to 100 Angstroms. As illustrated in FIG. 8, 'the silicon nitride layer 48 is anisotropically etched': a spacer 50 is left on the wall surface of the trench 46. This etching step also etches--deeper trenches 52 in trenches that are not covered by nitride spacers 50

第12頁 m 4 6 82 5 0 修正曰案號 89107744 五、發明說明（6) 46下的基板中◊該溝渠52具有約500至25 00埃之間的深度。該氮化矽間隔物具有約3 〇〇至1 〇〇〇埃的寬度。Page 12 m 4 6 82 5 0 Amendment No. 89107744 V. Description of the invention (6) In the substrate under 46, the trench 52 has a depth between about 500 and 2500 Angstroms. The silicon nitride spacer has a width of about 300 to 100 Angstroms.

至此，一相反的NMOS-PMOS場植入遮罩（未表示於圖中 )被形成於該基板上，且離子被植入該深溝渠52下的半導體基板中’以避免漏電。第9圖所示的場植入區56將取決於鄰近的裝置而可為Ν+或Ρ+。例如，一Ν +場植入可包含以約1 X 1011 至1 X l〇i3atoms/cm2 之間的劑量，以3〇至8〇 keV 能量植入的硼或氟化硼離子。—P+場植入可包含以約 10丨1至1 X I〇i3atoms/Cffl2之間的劑量，以3〇至8〇 keV能量植入的鱗或神離子。 —個氧化物層係以化學氣相沈積法而被沈積於該基板表面上並填充該溝渠。該氧化物層可具有約4000至8000埃之間的厚度。該氧化物層係以具有一拋光阻絕物於該氮化物層44的化學機械拋光法拋光。所產生的淺溝渠隔離區6〇被舉例說明於第1 0圖中。至此’氮化矽層4 4係使用電裝回餘移除。因為電槳回 #為有方向性的’所以氮化物間隔物50係為氧化物層6〇所保護且未被移除。其次，襯墊氧化物4 2被移除。此將產生平坦的氮化物間隔物50角落，如第11圖所示。加工係以本技藝的傳統方式繼續進行。例如，如第1 2 圖所舉例說明’ 一閘極氧化物及一多晶矽層被沈積於該基板表面上’並被刻晝而形成閘極電極7 〇。閘極電極7 〇的源極與沒極區72可被形成於隔離區域之間的主動區中，如本技藝的傳統方式。該閘極電極與源極/汲極區可被矽化74So far, an opposite NMOS-PMOS field implantation mask (not shown in the figure) has been formed on the substrate, and ions have been implanted into the semiconductor substrate under the deep trench 52 'to avoid leakage. The field implantation area 56 shown in Fig. 9 will be N + or P + depending on the neighboring devices. For example, an N + field implant may include boron or boron fluoride ions implanted at a dose between about 1 × 1011 to 1 × 10iatoms / cm2 at an energy of 30 to 80 keV. The -P + field implantation may include scales or god ions implanted at a dose of between about 10 and 1 × 10 μs atoms / Cffl2 at an energy of 30 to 80 keV. An oxide layer is deposited on the surface of the substrate by a chemical vapor deposition method and fills the trench. The oxide layer may have a thickness between about 4000 and 8000 angstroms. The oxide layer is polished by a chemical mechanical polishing method having a polishing stopper on the nitride layer 44. The resulting shallow trench isolation area 60 is illustrated in Figure 10 as an example. So far, the silicon nitride layer 4 and 4 have been removed by using electrical equipment. Because the electric paddle return # is directional, the nitride spacer 50 is protected by the oxide layer 60 and has not been removed. Second, the pad oxide 42 is removed. This will produce a flat nitride spacer 50 corner, as shown in Figure 11. Processing continues in the traditional manner of the art. For example, as illustrated in FIG. 12 ', a gate oxide and a polycrystalline silicon layer are deposited on the surface of the substrate' and are etched to form a gate electrode 70. The source of the gate electrode 70 and the non-electrode region 72 may be formed in an active region between the isolation regions, as is conventional in the art. The gate electrode and source / drain regions can be silicided74

第13頁 46 8250 年Page 13 46 8250

__案號 8flin77M 五、發明說明（7) ，如傳統方式。 A在進行本發明之製程的矽化作用後，無接面漏電。如第3圖所示，接面漏電35的發生係起因於淺溝渠隔離區角落凹陷25允許來自底下導電層（未表示於圖中）的電流穿經，而進入基板中的源極/汲極區34。在本發明的製= 中，如第12圖中所示，凹陷65係為氮化矽間隔物5〇所環繞第13圖舉例說明—無邊際接觸78的形成。一般的製程並不允許一無邊際接觸。因為中間介電層76及淺溝渠隔離 60皆$氧化物，所以接觸蝕刻將造成過量的淺溝渠隔離氧化物損失（如第4圖所示）。然而，在本發明的製程中，在淺溝渠一主動區接面的氮化物間隔物5〇係作為一飯刻阻絕，而避免淺溝渠隔離氧化物被挖掘。因此，接觸漏電被降低。本發明的製程將造成階梯式淺溝渠隔離的形成。該淺溝渠隔離場邊緣暴露係為該薄氮化物間隔物的存在所避免。在矽化作用後’其必然可避免高電場邊緣接面漏電。該具有阻絕氮化矽間隔物的階梯式淺溝渠隔離將允許通道場植入，以降低隔離漏電’特別是在特徵尺寸為〇18微米或更小尺寸的裝置中。該無邊際接觸製程完全為本發明的製程所支援。雖然本發明已被特別地表示’並參考其較佳實施例做說明’惟應為熟習本技藝之人士所瞭解地是，各種在形式上及細節上的改變可於不違背本發明之精神與範鳴下為之__ Case No. 8flin77M V. Description of the invention (7), such as the traditional method. A After performing the silicidation of the process of the present invention, there is no leakage at the interface. As shown in Fig. 3, the junction leakage 35 is caused by the recess 25 in the corner of the shallow trench isolation zone, allowing current from the underlying conductive layer (not shown in the figure) to pass through, and into the source / drain in the substrate Area 34. In the manufacturing method of the present invention, as shown in FIG. 12, the recess 65 is surrounded by the silicon nitride spacer 50. FIG. 13 illustrates the formation of the non-border contact 78. The general process does not allow a borderless contact. Because the intermediate dielectric layer 76 and the shallow trench isolation 60 are both oxides, contact etching will cause excessive loss of shallow trench isolation oxides (as shown in Figure 4). However, in the process of the present invention, the nitride spacer 50 at the junction of the active region of the shallow trench is blocked as a meal to prevent the shallow trench isolation oxide from being excavated. Therefore, contact leakage is reduced. The manufacturing process of the present invention will cause the formation of stepped shallow trench isolation. The shallow trench isolation field edge exposure is avoided by the presence of the thin nitride spacer. After silicidation, it will inevitably avoid leakage at the high electric field edge junction. The stepped shallow trench isolation with silicon nitride spacers will allow channel field implantation to reduce isolation leakage ', especially in devices with a feature size of 018 microns or smaller. This borderless contact process is fully supported by the process of the present invention. Although the present invention has been specifically shown 'and explained with reference to its preferred embodiments', it should be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention. Fan Ming

第14頁 d6 8250 __案號89107744_年月曰修正_ 圖式簡單說明第1、3及4圖係為習知技藝之一實施例的橫剖面圖表示。第2圖係為在具有過量角落氧化物凹陷之習知技藝的淺溝渠隔離中的VA-kmk現象的圖式。第5至1 3圖係為本發明之一較佳實施例的橫剖面表示。Page 14 d6 8250 __Case No. 89107744_ Year Month Amendment _ Brief Description of Drawings Figures 1, 3 and 4 are cross-sectional views showing one embodiment of the conventional art. Figure 2 is a diagram of the VA-kmk phenomenon in shallow trench isolation with the conventional art of excessive corner oxide depressions. Figures 5 to 13 are cross-sectional representations of a preferred embodiment of the present invention.

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Claims

46 8250 ---案號 8910774+__革月日__ 六、申請專利範圍 1 · 一種用於在積體電路製造中形成淺溝渠隔離的方法，包含有：一個襯墊氧化物層被沈積於一半導體基板表面上；一個第一氮化物層被沈積於該襯墊氧化物層上；刻晝該第一氮化物層，以提供達該襯墊氧化物層的開 σ ; 一個第一溝渠係於該開口中被蝕刻穿經該襯墊氧化物層’並進入該半導體基板中；一個第二氮化物層被沈積於該第一氮化物層上並填充該第一溝渠； ' 同時’該第二氮化物層被非等向性蝕刻，而形成氮化物間隔物於該第一溝渠的壁面上，以及未為該間隔物所覆蓋的半導體基板被钮入，而形成一第二溝渠離子植入該第二溝渠底下的半導體基板中；该第一與第二溝渠係以一個氧化物層填充；其次，該第一氮化物與襯墊氧化物層被移除，而在該積體電路裝置的該製造令完成該淺溝渠隔離的該= 構。、。如申請專利範圍第1項之方法，其中該襯墊氣化物層具有約50至200埃之間的厚度β θ 氮化物層溝渠具有 3 ·如申請專利範圍第1項之方法，其中該第一被沈積達約1 0 0 0至2000埃之間的厚度。 4.如申請專利範圍第丄項之方法，其$該第一46 8250 --- Case No. 8910774 + __ Leather Month__ VI. Scope of Patent Application1. A method for forming shallow trench isolation in the manufacture of integrated circuits, including: a pad oxide layer is deposited On a semiconductor substrate surface; a first nitride layer is deposited on the pad oxide layer; the first nitride layer is engraved to provide an opening σ to the pad oxide layer; a first trench Is etched through the opening through the pad oxide layer and enters the semiconductor substrate; a second nitride layer is deposited on the first nitride layer and fills the first trench; and at the same time the The second nitride layer is anisotropically etched to form a nitride spacer on the wall of the first trench, and a semiconductor substrate not covered by the spacer is pushed in to form a second trench ion implantation. Into the semiconductor substrate under the second trench; the first and second trenches are filled with an oxide layer; second, the first nitride and pad oxide layer are removed, and the integrated circuit device End of the manufacturing order The STI = the configuration. . For example, the method of claiming a patent scope item 1, wherein the liner gasification layer has a thickness between about 50 and 200 Angstroms. The nitride layer trench has a value of 3. · The method of claim 1, wherein the first It is deposited to a thickness of between about 1000 and 2000 Angstroms. 4. If the method of applying for item (1) of the patent scope,

第16頁Page 16

46 8250 __案號89107744_年月日修正___ 六、申請專利範圍約200 0至3500埃之間的厚度。 5 ·如申請專利範圍第1項之方法，其中該第二氮化物層被沈積達約3 0 0至1 0 0 0埃之間的厚度。 6 ·如申請專利範圍第1項之方法，其中該第二溝渠具有約500至2500埃之間的深度。 7 .如申請專利範圍第1項之方法，其中該間隔物具有約 3 0 0至1 0 0 0埃之間的寬度。 8 ·如申請專利範圍第1項之方法，其中同時非等向性韻刻該·第二氮化物層與該半導體基板的該步驟係使用非等向性電漿蝕刻完成。 9 .如申請專利範圍第1項之方法，其中植入離子的該步驟包含以約1 X 1 011至1 X 1 013 aΐ〇ms/cm2之間的劑量，. 以30至80 keV能量植入的硼或氟化硼離子，而形成一 N+場植入區於該淺溝渠隔離下方。 I 0 ’如申請專利範圍第1項之方法，其中植入離子的該步驟包含以約1 X 10"至1 X 10】3atoms/cra2之間的劑量，以30至80 keV能量植入的磷或砷離子，而形成一p+場植入區於該淺溝渠隔離下方。 II .如申請專利範圍第1項之方法，其中填充該第—與第二溝渠的該步驟，包含有：、以化學氣相沈積法沈積一個氧化物層達約40Q0至8Q〇〇埃之間的厚度；以及使用具有一拋光阻絕物於該第一氮化物層的化學機械拋光法拋光該氧化物層。46 8250 __Case No. 89107744_Year Month Date Amendment ___ Sixth, the scope of patent application is about 200 to 3,500 Angstroms. 5. The method of claim 1 in which the second nitride layer is deposited to a thickness between about 300 and 100 angstroms. 6. The method of claim 1 in which the second trench has a depth between about 500 and 2500 Angstroms. 7. The method of claim 1, wherein the spacer has a width between about 300 and 100 angstroms. 8. The method of claim 1 in the scope of patent application, wherein the step of simultaneously anisotropically carving the second nitride layer and the semiconductor substrate is performed using anisotropic plasma etching. 9. The method of claim 1, wherein the step of implanting ions comprises implanting at a dose between about 1 X 1 011 to 1 X 1 013 a 100 ms / cm2 with an energy of 30 to 80 keV Boron or boron fluoride ions to form an N + field implanted region under the shallow trench isolation. I 0 'As in the method of claim 1, wherein the step of implanting ions includes phosphorous implanted at a dose between about 1 X 10 " and 1 X 10] 3 atoms / cra2 at an energy of 30 to 80 keV Or arsenic ions, and a p + field implanted region is formed under the shallow trench isolation. II. The method of claim 1 in the scope of patent application, wherein the step of filling the first and second trenches comprises: depositing an oxide layer by chemical vapor deposition to between about 40Q0 and 8Q00 Angstroms Thickness; and polishing the oxide layer using a chemical mechanical polishing method having a polishing stopper on the first nitride layer.

46 8250 ------MM 89107744__车月日鉻 π：六、申請專利範園 1 2 ’如申請專利範圍第1項之方法’更包含有在該淺溝渠隔離之間的該半導體基板中及上方製造半導體裝置結構。 i3 •一種用於在積體電路製造中形成淺溝渠隔離的方法，包含有：一個襯墊氧化物層被沈積於一半導體基板表面上；一個第一氮化物層被沈積於該襯墊氧化物層上；刻晝該第一氮化物層’以提供達該襯墊氧化物層的開口；個第一溝渠係於該開口中被餘刻穿經該襯塾氧化物層’並進入該半導體基板t ; '-個第二氮化物層被沈積於該第一氮化物層上並填充該第一溝渠； ' 同時’該第一 II化物層被非等向性飯刻，而形成氣化物間隔物於該第一溝渠的壁面上，以及未為該間隔物所覆.蓋的半導體基板被银入，而形成一第二溝竿離子植入於該第二溝渠底下的半導體基板中，以形成通道場植入；沈積一個氧化物層於該第一氮化物層上，並填充該第一與第二溝渠；、W 使用具有一拋光阻絕物於該第一氮化物層的化學機械抛光法拋光該氧化物層；其次，該第—氮化物與襯墊氧化物層被移除，其中該氮化物間隔物將阻絕漏 46 8250 I號 89107744 六、申請專利範園電穿經該第一與第二溝渠中之該氧化物層的暴露角落’而在該積體電路裝置的該製造中完成該淺溝渠隔離的該結構。 ^ 14 ·如申請專利範圍第13項之方法，其中該襯墊氧化物層具有約50至200埃之間的厚度。曰 15 ·如申請專利範圍第13項之方法，其中該第一氮化物層被沈積達約1000至2000埃之間的厚度。 16 ·如申請專利範圍第13項之方法，其中該第—溝渠具有約2000至3500埃之間的厚度。 1 7 .如申請專利範圍第丨3項之方法，其中該第二氮化物層被沈積達约3 0 0至1 〇〇〇埃之間的厚度。 18 *如申請專利範圍第13項之方法，其中該第二溝渠具有約500至2500埃之間的深度。 1 9 ·如申請專利範圍第丨3項之方法，其中該間隔物具有約 30 0至1 0 0 0埃之間的寬度。 2 0 ·如申請專利範圍第丨3項之方法，其中同時非等向性餘刻該第二氮化物層與該半導體基板的該步驟係使用非等向性電漿蝕刻完成。 21 ·如申請專利範圍第13項之方法，其中植入離子的該步驟包含以約1 X 1 01】至1 X 1 〇13 a t 〇m s / cm2之間的劑量，以30至80 keV能量植入的硼或氟化硼離子，而形成— N+場植入區於該淺溝渠隔離下方。 22 .如申請專利範圍第13項之方法，其中植入離子的該步驟包含以約1 X 1 〇ι 1至1 X 1 〇i3 a七0ms/ cm2之間的劑量，46 8250 ------ MM 89107744__ Car Moon Day Chromium π: VI. Patent Application Park 1 2 'The method of applying for the first item of patent scope' further includes the semiconductor substrate between the shallow trench isolations Middle and upper semiconductor device structures are manufactured. i3 • A method for forming shallow trench isolation in integrated circuit manufacturing, comprising: a pad oxide layer is deposited on a surface of a semiconductor substrate; a first nitride layer is deposited on the pad oxide Layer; engraving the first nitride layer 'to provide an opening to the pad oxide layer; a first trench is etched through the lining oxide layer' in the opening and enters the semiconductor substrate t; '-a second nitride layer is deposited on the first nitride layer and fills the first trench;' at the same time 'the first II compound layer is engraved by an anisotropic meal to form a gas spacer On the wall surface of the first trench, and the semiconductor substrate that is not covered by the spacer. The covered semiconductor substrate is silvered in, and a second trench rod is ion-implanted into the semiconductor substrate under the second trench to form a channel. Field implantation; depositing an oxide layer on the first nitride layer and filling the first and second trenches; and W polishing the chemical mechanical polishing method with a polishing stopper on the first nitride layer Oxide layer; its The first nitride and the pad oxide layer are removed, in which the nitride spacer will prevent leakage 46 8250 I No. 89107744 Sixth, the patent application Fan Yuan electricity passes through the oxidation in the first and second trenches The exposed corner of the physical layer 'completes the structure of the shallow trench isolation in the fabrication of the integrated circuit device. ^ 14 The method of claim 13 in which the pad oxide layer has a thickness between about 50 and 200 angstroms. 15: The method of claim 13 in which the first nitride layer is deposited to a thickness of between about 1000 and 2000 angstroms. 16. The method according to item 13 of the patent application, wherein the first trench has a thickness between about 2000 and 3500 Angstroms. 17. The method of claim 3, wherein the second nitride layer is deposited to a thickness between about 300 and 1000 angstroms. 18 * The method of claim 13 in which the second trench has a depth between about 500 and 2500 Angstroms. 19. The method of claim 3, wherein the spacer has a width between about 300 and 100 angstroms. 2 0. The method of claim 3, wherein the step of simultaneously anisotropically etching the second nitride layer and the semiconductor substrate is performed using anisotropic plasma etching. 21 · The method according to item 13 of the patent application, wherein the step of implanting ions comprises implanting at a dose between about 1 X 1 01] and 1 X 1 〇13 at 〇ms / cm2 with an energy of 30 to 80 keV Implanted boron or boron fluoride ions to form an N + field implanted region below the shallow trench isolation. 22. The method of claim 13 in the scope of patent application, wherein the step of implanting ions comprises a dose between about 1 X 1 〇ι 1 to 1 X 1 〇i3 a 70ms / cm2,

第19頁 46 8250 __案號89107744__本月曰 ι ·τ_ 六、申請專利範圍以30至80 keV能量植入的磷或砷離子，而形成一 ρ+場植入區於該淺溝渠隔離下方。 23 ·如申請專利範圍第13項之方法，更包含有在該淺溝渠隔離之間的該半導體基板中及上方製造半導體裝置結構。 24 · —種用於在積體電路製造中形成淺溝渠隔離的方法，包含有： —個襯墊氧化物層被沈積於一半導體基板表面上；一個第一氮化物層被沈積於該襯墊氧化物層上；刻晝該第一氮化物層，以提供達該襯墊氧化物層的開口；一個第一溝渠係於該開口中被餘刻穿經該襯塾氧化物層’並進入該半導體基板中；一個第二氮化物層被沈積於該第一氮化物層上並填充該第一溝渠；同時’該第二氮化物層被非等向性蝕刻，而形成氮化物間隔物於該第一溝渠的壁面上，以及未為該間隔物所覆蓋的半導體基板被飯入，而形成一第二溝渠 ϊ 離子植入於該第二溝渠底下的半導體基板中，以形成通道場植入；沈積一個氧化物層於該第—氮化物層上，並填充該第一與第二溝渠；、使用具有一拋光阻絕物於該第一氮化物層的化學機械Page 19 46 8250 __Case No. 89107744__ Month of this month τ_ VI. Patent application: Phosphorus or arsenic ions implanted with energy of 30 to 80 keV to form a ρ + field implanted area to isolate the shallow trench Below. 23. The method of claim 13 further includes fabricating a semiconductor device structure in and above the semiconductor substrate between the shallow trench isolations. 24. A method for forming shallow trench isolation in integrated circuit manufacturing, comprising:-a pad oxide layer is deposited on a surface of a semiconductor substrate; a first nitride layer is deposited on the pad On the oxide layer; engraving the first nitride layer to provide an opening to the pad oxide layer; a first trench in the opening is penetrated through the lining oxide layer 'and enters the In a semiconductor substrate; a second nitride layer is deposited on the first nitride layer and fills the first trench; at the same time, the second nitride layer is anisotropically etched to form a nitride spacer on the first nitride layer A second trench is formed on the wall surface of the first trench and the semiconductor substrate not covered by the spacer, and ions are implanted into the semiconductor substrate under the second trench to form a channel field implant; Depositing an oxide layer on the first nitride layer and filling the first and second trenches; using a chemical mechanism having a polishing stopper on the first nitride layer

46 8250 修正曰 ^E 89107744 六、申請專利範圍拋光法拋光該氧化物層；其次’該第一氮化物與襯墊氧化物層被移除，其中該氮化物間隔物將阻絕漏電.穿經該第一與第二溝渠中之該氧化物層的暴露角落，而完成該淺溝渠隔離的該結構；形成閘極電極與相關的源極/汲極區於該淺溝渠隔離之間；以及將該閘極電極與該源極/汲極區矽化，以完成該積體電路裝置的製造。 25 如申請專利範圍第24項之方法，其中該第一與第二溝渠具有約2 5 0 〇至6 0 0 0埃之間的組合深度。 26 如申請專利範圍第24項之方法，其中該間隔物具有約 300至1000埃之間的寬度。46 8250 Amendment ^ E 89107744 6. Polishing the oxide layer with a patent-applied polishing method; Secondly, the first nitride and pad oxide layer are removed, wherein the nitride spacer will prevent leakage. Pass through the The exposed corners of the oxide layer in the first and second trenches complete the structure of the shallow trench isolation; forming a gate electrode and an associated source / drain region between the shallow trench isolations; and The gate electrode is silicified with the source / drain region to complete the fabrication of the integrated circuit device. 25. The method of claim 24, wherein the first and second trenches have a combined depth of between about 2500 and 600 Angstroms. 26. The method of claim 24, wherein the spacer has a width between about 300 and 1000 Angstroms.

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