TW468228B

TW468228B - Method for manufacturing a MOS transistor

Info

Publication number: TW468228B
Application number: TW89100115A
Authority: TW
Inventors: Chih-Hsiang Cheng; Tzung-Han Lee
Original assignee: United Microelectronics Corp
Priority date: 2000-01-05
Filing date: 2000-01-05
Publication date: 2001-12-11

Abstract

The invention provides a method for manufacturing a MOS transistor on a semiconductor chip. The semiconductor chip comprises a substrate, a dielectric layer formed on a predetermined region of the substrate, a conductive layer constructed by tungsten or tungsten silicon formed on the dielectric layer, and a protective layer formed on the conductive layer. An isotropic etching process is performed to etch the sidewall of the dielectric layer and the conductive layer to form a gate electrode. Then, a first ion implantation process is performed with an incidence to form lightly doped drain regions in the substrate at both sides of the gate electrode. A second ion implantation process is performed by using the protective layer as a hard mask to form a source region and a drain region in the substrate at the both sides of the gate electrode. The gate electrode comprises a gate dielectric layer formed by the remaining dielectric layer and a gate conductive layer formed by the remaining conductive layer.

Description

46 822 8 五、發明說明（1) 發明之領域，. 本發明提供一種金屬氧化半導體（raetal-oxide semiconductor, M0S)電晶體的製作方法，尤指一種以金屬做為閘極（gate)之M0S電晶體的製作方法。背景說明 M0S電晶體是積體電路中非常重要的元件，多半用來做為電路中的開關（switch)» M0S電晶體通常利用多晶矽 (poly-silicon)來做為閘極導電層（gate electrode)的材料。為了提高這層多晶矽層的導電性，通常在多晶矽層中摻入一定寧彳量的摻質（dopant)，來降低多晶矽層的）ί電阻 (sh ee t r e s i s t anc e )，以達到半導體電路的電性要求。例如，在邏輯（logic)電路中，已摻雜多晶矽（doped ρ ο 1 y - s i 1 i c ο η )層的片電阻須小於1 〇歐姆/正方（Ω /□)以提供較高的操作速度，而在動態隨機存取記憶體（dynamic random access memory, DRAM)中，已換雜多晶石夕層的片電阻須介於1 6〜1 8Ω /匚]之間。然而，隨著積體電路積集度（integration)的提昇，已摻雜多晶矽層已無法提供更低的片電阻，因此以已摻雜多晶矽層做為閘極的M0S電晶體，已經逐漸不敷積體電路設計者的需求。請參考圖一與圖二，圖一與圖二為習知M0S電晶體1 046 822 8 V. Description of the invention (1) Field of the invention. The present invention provides a method for manufacturing a metal oxide semiconductor (MOS) transistor, especially a MOS using a metal as a gate. Method for making transistor. Background: M0S transistors are very important components in integrated circuits. Most of them are used as switches in the circuit. »M0S transistors usually use poly-silicon as the gate electrode. s material. In order to improve the conductivity of this polycrystalline silicon layer, a certain amount of dopant is usually added to the polycrystalline silicon layer to reduce the resistance of the polycrystalline silicon layer (sh ee tresist anc e) in order to achieve the electrical properties of the semiconductor circuit. Sexual requirements. For example, in a logic circuit, the sheet resistance of a doped polycrystalline silicon (doped ρ ο 1 y-si 1 ic η) layer must be less than 10 ohms / square (Ω / □) to provide higher operating speed. In a dynamic random access memory (DRAM), the chip resistance of the polysilicon layer must be between 16 ~ 18Ω / 6]. However, with the integration of integrated circuits, the doped polycrystalline silicon layer can no longer provide lower sheet resistance. Therefore, the M0S transistor with the doped polycrystalline silicon layer as the gate has gradually become insufficient The needs of integrated circuit designers. Please refer to Fig. 1 and Fig. 2. Fig. 1 and Fig. 2 are conventional M0S transistors 1 0

逢 a 8+2 2:8 五、發明說明（2) 的製程示意圖。習知10S電晶體1 〇是製作在一半導體晶片 12上，而半導體晶片包含有一基底（substrate) 14，一主動區域（active area) 1 6設於基底1 4表面的一預定區域上，以及一場氧化層（f i e 1 d ο X i d e) 1 8設於基底1 4表面並環繞於主動區域1 6。如圖一所示，習知MOS電晶體1 0的製作方法是先在主動區域1 6内形成一閘極20’閘極包含有一閘極氧化層 (gate oxide) 22設於主動區域16内的中央部份’ 一已摻雜多晶矽層2 4設於閘極氧化層2 2之上，以及一矽化鎢 (1；111^3七6113111(^(16,1¥3〇層2 6設於已摻雜多晶石夕層2 4之上，以降低已摻雜多晶矽層2 4與後續導線的接觸電祖 (contact resistance)。在完成閘極20之後，接著在閘極 20上方形k 一由氮化矽（silicon nitride, Si N)所構成的保護層28。然後在進行一離子饰植（ion implantation)製程，以保護層2 8與場氧化層18為一硬罩幕（hard mask)，將摻質（dopant)植入未被硬罩幕所遮蓋的基底14内，以在閘極2 0兩側分別形成一輕微掺雜没極（1 i g h 11 y d ο p e d drain, LDD) 30 ° 〇如圖二所示，在形成LDD 3 0之後，接著在閘極2 0與保護層28的周圍形成一侧壁子（spacer) 32«然後進行一離子佈植製程’以側壁子32、保護層28與場氧化層18為另一硬罩幕，將摻質植入未被硬罩幕所遮蓋的基底14内，並與Every a 8 + 2 2: 8 V. Schematic diagram of the process of invention description (2). The conventional 10S transistor 10 is fabricated on a semiconductor wafer 12, and the semiconductor wafer includes a substrate 14, an active area 16 is provided on a predetermined area on the surface of the substrate 14, and a field An oxide layer (fie 1 d ο X ide) 1 8 is provided on the surface of the substrate 14 and surrounds the active area 16. As shown in FIG. 1, a conventional method for manufacturing a MOS transistor 10 is to first form a gate electrode 20 in the active region 16. The gate electrode includes a gate oxide 22 provided in the active region 16. In the central part, a doped polycrystalline silicon layer 24 is provided on the gate oxide layer 22, and a tungsten silicide (1; 111 ^ 3-76113111 (^ (16,1 ¥ 3〇 layer 2 6 is provided in the The doped polycrystalline silicon layer 24 is used to reduce the contact resistance between the doped polycrystalline silicon layer 24 and subsequent wires. After the gate 20 is completed, a square k is formed on the gate 20 A protective layer 28 composed of silicon nitride (Si N). Then an ion implantation process is performed, with the protective layer 28 and the field oxide layer 18 as a hard mask. A dopant is implanted into the substrate 14 not covered by the hard cover to form a lightly doped drain (LDD) 30 ° on both sides of the gate 20 respectively. As shown in FIG. 2, after forming the LDD 30, a spacer 32 «is formed around the gate 20 and the protective layer 28, and then an ion is generated. Implantation process' to the sub-side wall 32, the protective layer 28 and the field oxide layer 18 is another hard mask, the hard mask is not implanted dopants within a substrate 14 covered by a curtain, and with

第5頁Page 5

4 6 δ 2 2 B 五、發明說明（3) ^ 形成 _ 知M0S電晶體10的製作輕微摻雜汲極3 0的部份區域相重疊’以在閑，極2 〇兩侧分別形成一源極（source) 34與一汲極（drai 6，成習 1 ΠίΑ 4'J iu. 但疋受限於多晶石夕層的飽和摻雜劑量（約然而，目前M0S電晶體1〇的閘極2〇寬度均越做越小， 3 f積體電路的積集度’❿目前的微影技術在0. IS" πι以下之閘極的製作。此外，為了提高丄I度 1 〇的操作速度，已掺雜多晶矽層的片電阻必須 s電晶體低，但是# 於容旦访JS ΑΛ私L— 、步降 /平方公分低無法將已換雜多晶石夕層的片電阻更〇概子左此在製作線寬更小、速度更快的M0S電晶體時''步降體10的製作方法就有其偏限性，而成為目二習導體製程梦展的瓶頸。 ^目前半發明概述明之主要目的在於提供一種以金屬做為閉# 限制，並、*製作方法，破I微影技術最小線窗认限牵並進一步降低閘極的片電阻。寬的斗明提供一種金屬氧化半導體電晶體的製作方、t ma體係製作於-半導體晶片上。該半導體晶片去，4 6 δ 2 2 B V. Description of the invention (3) ^ Formation _ Knowing the fabrication of the M0S transistor 10 Partially doped regions of the drain electrode 30 overlap each other to form a source at both sides of the pole 20 Source 34 and a drain (drai 6, Cheng Xi 1 ΠίΑ 4'J iu. However, 疋 is limited by the saturation doping dose of the polycrystalline silicon layer (approximately, however, the gate of the current MOS transistor 10) 2〇 The width is getting smaller and smaller, the integration degree of the 3 f integrated circuit '❿ the current lithography technology is below 0. IS " gate fabrication below. In addition, in order to improve the operation speed of 丄 I degree 1 〇 , The sheet resistance of the doped polycrystalline silicon layer must be low, but # 于容旦 Visit JS ΑΛprivate L—, low step / cm 2 can not change the sheet resistance of the replaced polycrystalline silicon layer. The method of making the step-down body 10 has a limitation when making M0S transistors with smaller line widths and faster speeds, and it has become the bottleneck of the dream exhibition of the conductor process of the second standard. ^ Overview of the current semi-invention The main purpose of Ming is to provide a metal with a closed # limit, and, * production method, breaking the minimum line window recognition limit of I lithography technology And further reduce the sheet resistance of the gate width of the bucket invention provides producers of metal oxide semiconductor transistors of, t ma system fabricated -.. On a semiconductor wafer to the semiconductor wafer,

3 : 底’一介電層設於該基底表面之一預定區域 L 一 ·或發化鎢所構成的導電層設於該介電層之上， ’ Μ及 Λ6δ22β I—--------正/更正/補充五、發明說明（4) 一保護層設於該導電層之上。本發明製作方法首等向性蝕刻製程’用來敲刻該介電層及該導電層之兩側壁，以形成一開極。然後進行一第一離子佈植製程，以一傾斜之入射角度在該閘極兩側之基底内分別形成二輕微摻雜汲極。最後進行一第二離子佈植製程，利用該保護層做為一硬罩幕，以在該閘極兩側之基底内分別形成一源極與一汲極。該閘極包含有一閘極介電層係由殘餘之該介電層所構成’以及一閘極導電層係由殘餘之該導電層所構成。本發明製作方法所製作的MOS電晶體，其閘極係由鎢或矽化鎢所構成’而且本發明製作方法利用一等向性蝕刻裝程’來突破習知微影技術的限制，以進一步地縮短閘極的寬度’因此本發明MOS電晶體具有較佳的電性表現。同時，本發明製作方法不用製作一側壁子，即可完成該輕微擴散汲極以及該源極與汲極的製作，因此本發明M 〇 s電晶體的製作方法可以較少的製程步驟，來製作線寬更小、速度更快而成本更低的MOS電晶體。圖示之簡單說明圖一與圖二為習知MOS電晶體的製程示意圖。圖三至圖六為本發明MOS電晶體製作方法的製程示意 i 0 圖七與圖八為本發明MOS電晶體製作方法之另一實施 46 8228 五、發明說明（5) 例的製程示意圖。圖示之符號說明 10 Μ 0 S電晶體 12 半導體晶片 14 基底 16 主動區域 18 場氧化層 20 閘極 22 閘極氧化層 24 已摻雜多晶矽層 26 矽化鎢層 28 保護層 30 輕微摻雜汲極 32 側壁子 34 源極 36 汲極 40 MOS電晶體 42 半導體晶 >5 44 基底 46 主動區域 48 淺溝隔離 50 二氧化矽層 52 氮化鈦層 54 導電層 56 保護層 58 氧化石夕層 60 氮氧化矽層 62 氮化矽層 64 閘極 66 輕微摻雜汲極 68 離子植入方向 70 源極 72 汲極 74 離子植入方向 76 離子植入方向 78 離子植入方向發明之詳細說明3: Bottom 'a dielectric layer is provided on a predetermined area of the substrate surface. A conductive layer composed of tungsten or tungsten oxide is provided on the dielectric layer.' M and Λ6δ22β I -------- --Positive / Correct / Supplement V. Explanation of the invention (4) A protective layer is provided on the conductive layer. The first isotropic etching process of the manufacturing method of the present invention is used to etch both sides of the dielectric layer and the conductive layer to form an open electrode. Then, a first ion implantation process is performed to form two slightly doped drain electrodes in the substrate on both sides of the gate electrode at an inclined incident angle. Finally, a second ion implantation process is performed, and the protective layer is used as a hard mask to form a source electrode and a drain electrode in the substrate on both sides of the gate electrode, respectively. The gate includes a gate dielectric layer composed of the remaining dielectric layer 'and a gate conductive layer composed of the remaining conductive layer. The gate electrode of the MOS transistor manufactured by the manufacturing method of the present invention is composed of tungsten or tungsten silicide, and the manufacturing method of the present invention uses an isotropic etching process to break the limitation of the conventional lithography technology to further The gate width is shortened, so the MOS transistor of the present invention has better electrical performance. At the same time, the manufacturing method of the present invention can complete the fabrication of the slightly diffused drain and the source and the drain without making a sidewall. Therefore, the manufacturing method of the MOS transistor of the present invention can be manufactured with fewer process steps. MOS transistors with smaller line width, faster speed and lower cost. Brief description of the diagrams Figures 1 and 2 are schematic diagrams of the manufacturing process of a conventional MOS transistor. Figures 3 to 6 are schematic illustrations of the manufacturing process of the MOS transistor manufacturing method of the present invention i 0 Figures 7 and 8 are another implementation of the manufacturing method of the MOS transistor of the present invention 46 8228 V. Schematic illustration of the example of the invention (5). Symbols shown in the figure 10 MEMS transistor 12 semiconductor wafer 14 substrate 16 active area 18 field oxide layer 20 gate 22 gate oxide layer 24 doped polycrystalline silicon layer 26 tungsten silicide layer 28 protective layer 30 lightly doped drain 32 side wall 34 source 36 drain 40 MOS transistor 42 semiconductor crystal> 5 44 substrate 46 active area 48 shallow trench isolation 50 silicon dioxide layer 52 titanium nitride layer 54 conductive layer 56 protective layer 58 stone oxide layer 60 Silicon oxynitride layer 62 Silicon nitride layer 64 Gate 66 Lightly doped drain 68 Ion implantation direction 70 Source 72 Drain 74 Ion implantation direction 76 Ion implantation direction 78 Ion implantation direction Detailed description of the invention

46 82 ^° 五、發明說明（6) 睛參考圖二至圖六，圖三至圖六為本發明M 〇S電晶_體 4 0製作方法的製程示意圖。本發明為一種金屬氧化半導體 (M0S)電晶體40的製作方法，MOS電晶體40是製作於一半導體晶片42上。半導體晶片42包含有一基底44’ 一主動區域 4 6設於基底4 4表面的·~~預定區域上’以及一淺溝隔離 (shallow trench isolation, STI)-48設於基底 44表面並環繞於主動區域46。如圖三所示，半導體晶片@包含有一二氧化矽 (silicon dioxide，SiO 2)層5 0於主動區域4 6内的一預定區域上，一氮化鈦（titanium nitride, TiN)層52設於二氧化石夕層5 0之上，一由鶴（tungsten, W)金屬或石夕化嫣 (WSi)所構成的導電層54設於氮化鈦層52之上，以及一保護層5 6設於導電層5 4之上。保護層56包含有一氧化矽 (silicon oxide)層5 8設於導電層5 4之上，一氤氡化矽 (silicon-oxy-nitride，SiON)層 60設於氧化石夕層 58之上，以及一氮化矽（S i N)層6 2設於氮氧化矽層6 0之上。氮化鈦層5 2是用來增加導電層5 4對二氧化矽層5 0的附著力，並阻止導電層5 4内的鎢原子穿過（penetration)二氧化矽層50，而影響基底44的電性表現。此外，氮化矽層 6 2用來做為一硬罩幕，而氮氧化矽層'6 0則做為—緩衝式硬罩幕（buffer hard mask)並做為抗反射層 (anti-reflective coating, ARC)，氧化矽層 58則是用來46 82 ^ ° V. Description of the invention (6) Refer to Figures 2 to 6 for reference. Figures 3 to 6 are schematic diagrams of the manufacturing process of the method for manufacturing the MOS transistor 40 of the present invention. The present invention is a method for manufacturing a metal oxide semiconductor (MOS) transistor 40. The MOS transistor 40 is fabricated on a semi-conductive wafer 42. The semiconductor wafer 42 includes a substrate 44 ', an active region 46 disposed on the surface of the substrate 4 4 on a predetermined region', and a shallow trench isolation (STI) -48 disposed on the surface of the substrate 44 and surrounding the active region. Area 46. As shown in FIG. 3, the semiconductor wafer @ includes a silicon dioxide (SiO 2) layer 50 on a predetermined area in the active area 46, and a titanium nitride (TiN) layer 52 is provided. Above the stone dioxide layer 50, a conductive layer 54 composed of a tungsten (W) metal or Shi Xihuayan (WSi) is disposed on the titanium nitride layer 52, and a protective layer 5 6 It is provided on the conductive layer 54. The protective layer 56 includes a silicon oxide layer 58 on the conductive layer 54, a silicon-oxy-nitride (SiON) layer 60 on the stone oxide layer 58, and A silicon nitride (S i N) layer 62 is disposed on the silicon oxynitride layer 60. The titanium nitride layer 52 is used to increase the adhesion of the conductive layer 54 to the silicon dioxide layer 50 and to prevent tungsten atoms in the conductive layer 54 from penetrating the silicon dioxide layer 50 and affect the substrate 44. Electrical performance. In addition, the silicon nitride layer 62 is used as a hard mask, and the silicon oxynitride layer '60 is used as a buffer hard mask and as an anti-reflective coating. , ARC), silicon oxide layer 58 is used

第9頁Page 9

'46 822 8 五、發明說明（7)'46 822 8 V. Description of the invention (7)

做為氮氧化碎層6 0與導電層5 4之間的應壓緩衝層 stress buffer)。 (release 如圖四所示，本發明製作方法首先進行一等向性蝕刻 fa^u〇1；ropic etchmg)製程，以RCA標準清洗溶液，以及 =，^隨〇114，隨3)與雙氧水（117(^〇^111)”〇^(^，112〇2) ，此二溶液，來蝕刻二氧化矽層5 〇、氮化鈦層52、導電層 4與氧化矽層58的兩側壁，以形成—閘極6心閘極64包含閘極介電層（gate dielectric layer)是由殘餘的二矽層50所構成’以及一閘極導電層（gate electr〇de) 疋由殘餘氮化鈦層5 2與導電層5 4所構成Q 如圖五與圖六所示’在完成閘極64的製作後，接著製輕微#雜汲極6 6、一源極與一汲極。如圖五所示，以型（N -1 y p e ) Μ 0 S電晶體的製作為例，首先進行一離子佈植 I程，將砷（arsenic，As)離子以一傾斜之入射角度植入主動區域46内的基底44内，而在閘極64兩側的基底44内分別形成輕微摻雜汲極66。離子佈植製程的入射角度的範圍 f 1 5〜3 0度之間，而所使用的佈植能量為4 〇汗電子伏特 (KeV)，且佈植劑量為！ χ ι〇1雔子/平方公分（i〇n/cm2)。圖五中’箭頭6 8表示形成LDD 6 6時砷離子植入的方向。如圖六所示’然後進行另一離子佈植製程，利用保護 5 6做為硬罩幕’將坤離子與碟（phosphorous，p)離子依As a stress buffer layer between the oxynitride fragment layer 60 and the conductive layer 54. (Release is shown in Figure 4. The manufacturing method of the present invention first performs an isotropic etching process (fa ^ u〇1; ropic etchmg)), a RCA standard cleaning solution, and =, ^ with 〇114, and 3) and hydrogen peroxide ( 117 (^ 〇 ^ 111) ”〇 ^ (^, 112〇2), these two solutions are used to etch the two sidewalls of the silicon dioxide layer 50, the titanium nitride layer 52, the conductive layer 4 and the silicon oxide layer 58 to Formation—Gate 6 and gate 64 include a gate dielectric layer composed of a residual silicon layer 50 ′ and a gate conductive layer 疋 composed of a residual titanium nitride layer Q formed by 5 2 and conductive layer 5 4 is shown in Fig. 5 and Fig. 6 'After the fabrication of gate 64 is completed, a slight #heterode 6 is formed, and a source and a drain are formed. See Fig. 5 As an example, the fabrication of a type (N -1 ype) M 0 S transistor is taken as an example. First, an ion implantation process is performed, and arsenic (As) ions are implanted into the active region 46 at an inclined incident angle. In the substrate 44, slightly doped drain electrodes 66 are formed in the substrate 44 on both sides of the gate 64. The incidence angle of the ion implantation process ranges from f 1 5 to 30 degrees, and The implantation energy used is 40 Khan electron volts (KeV), and the implantation dose is! Χ ι〇1 〇子 / cm2 (Ion / cm2). 'Arrow 6 8 in Figure 5 indicates the formation of LDD 6 The direction of the arsenic ion implantation at 6 o'clock. As shown in Figure 6, 'Then proceed with another ion implantation process, using protection 5 6 as a hard cover'. The Kun ion and the phosphorous (p) ion depend on

II

第10頁 46 8228 — 五、發明說明（8) 序植入未被硬罩幕所遮蓋主動區域46内的基底44内，蓋輕微掺雜没極66的部份區域’以在閘極64兩侧匕分別形成-源極7。與一汲極…最後再完全去：以4 56’以完成本發明M〇s電晶體狂的製作。離子佈植製程植印子時所使用的佈植能量為60 KeV，砷離子的佈植劑 4 X 10。ion/cm2,而在植人磷離子時所使用的佈植鲍，為30 KeV，磷離子的佈植劑量為3 χ 1〇u i〇n/cra2。 Z 3；! f胃74表示形成源極7〇以及沒極72時石申離子與磷雕卞植入的方向。若欲製作P型（p-type)M0S電晶體，僅入離子與操作…在形成二 ϋΪΚΓ2離子，而所使用的佈植能量為且 IS夏…—而在形成源極7〇以及沒斤植入的離子為BFZ離子與蝴（b〇ron，雜早與2 ’圖七與圖八為本發明M0S電晶體例的製程示意圖。本發明製作方法與汲極72,再製作Ud 66。 2之後先製作源極70 體1的另一製作方法是先逸=所示，本發明M〇S電晶層56做為硬罩幕，將摻 =f佈植製^ ,利用保護雜離子植入未被硬罩幕所遮蓋之主 η 第11頁 468228 五、發明說明（9) 動區域46内的基底44内，以在閘極64兩側的基底44内分別形成源極7 0與汲極7 2。圖七中，箭頭7 6表示形成源極7 0以 |及汲極7 2時離子植入的方向。如圖八所示，接著利用熱鱗酸（phosphoric acid，. Η 3P0 4)與雙氧水加水稀釋的蝕刻液，完全去除氮化矽層6 2 |與乳氧化石夕層60。隨後再以含有氫氟酸（hydrofluoric acid, HF)的蝕刻液，來完全去除氧化矽層58。最後進行另一離子佈植製程’以閘極6 4為硬罩幕，將摻雜離子植入 |未被硬罩幕所遮蓋之主動區域4 6的基底44内，以在閘極64 兩侧的基底44内分別形成LDD 66。圖八中，箭頭78表示形 |成LDD 66時離子植入的方向。Page 10 46 8228 — V. Description of the invention (8) Sequenced implantation into the substrate 44 in the active area 46 not covered by the hard mask, covering a part of the doped electrode 66 slightly to cover the gate 64 Side daggers are formed-source electrode 7. And a drain ... and finally go completely: 4 56 'to complete the production of the Mos transistor of the present invention. The implantation energy used in the ion implantation process is 60 KeV, and the arsenic ion implantation agent is 4 X 10. ion / cm2, and the implanted abalone used when implanting phosphorus ions was 30 KeV, and the implantation dose of phosphorus ions was 3 x 10u inon / cra2. Z 3;! F stomach 74 indicates the direction in which Shishen ions and phosphorous ions were implanted when the source 70 was formed and the electrode 72 was formed. If you want to make a p-type M0S transistor, you only need to enter ions and operate ... to form two ϋΪKΓ2 ions, and the planting energy used is and IS summer ...-while forming the source 70 and no planting The ions that are introduced are BFZ ions and butterfly (boron, miscellaneous and 2 ′). Figures 7 and 8 are schematic diagrams of the manufacturing process of the MOS transistor of the present invention. The manufacturing method and drain 72 of the present invention, and then Ud 66. 2 Another method of manufacturing the source electrode 70 is shown in the following. First, as shown in the figure, the MOS transistor layer 56 of the present invention is used as a hard cover, and the doped f is implanted. The master covered by the hard cover Page 11 468228 V. Description of the invention (9) In the substrate 44 in the moving area 46, a source 7 0 and a drain 7 are formed in the substrate 44 on both sides of the gate 64, respectively. 2. In FIG. 7, the arrow 76 indicates the direction of ion implantation when the source 70 and the drain 72 are formed. As shown in FIG. 8, the phosphoric acid (. 3P0 4) and Hydrogen peroxide and water-diluted etching solution completely remove the silicon nitride layer 6 2 | and the lactite layer 60. Subsequently, a hydrofluoric acid (HF) -containing Etching solution to completely remove the silicon oxide layer 58. Finally, another ion implantation process is performed with the gate electrode 6 4 as a hard mask, and doped ions are implanted | the active area 4 6 that is not covered by the hard mask In the substrate 44, LDD 66 is formed in the substrate 44 on both sides of the gate electrode 64. In FIG. 8, the arrow 78 indicates the direction of ion implantation when the LDD 66 is formed.

I 本發明製作方法所製作的M0S電晶體12_，其閘極導電 |層是由鎢或矽化鎢所構成，因此可大幅降低M0S電晶體H 的閘極片電阻’使得閘極電流的傳輸速度加快β同時，本 J發明製作方法利用一等向性蝕刻製程，來進一步地縮短閘極的寬度’使得本發明M0S電晶體的閘極線寬可以不受微影技術的最小線寬所限制。由於閘極電流的傳輸速度加丨快’再加上閘極寬度的縮短使得通道長度（channei length)相對地縮短’因此可大幅提昇本發明M〇s電晶體3〇的操作速度。此外，本發明製作方法.不用製作一側壁子，即可完成LDD 66以及源極70與汲極72的製作，因此本發明製作方法可以較少的製程步驟，來製作線寬更小、速度更I The M0S transistor 12_ produced by the manufacturing method of the present invention has a gate conductive layer made of tungsten or tungsten silicide, so the gate chip resistance of the M0S transistor H can be greatly reduced, and the transmission speed of the gate current is accelerated. β At the same time, the manufacturing method of the J invention uses an isotropic etching process to further shorten the gate width, so that the gate line width of the MOS transistor of the invention can not be limited by the minimum line width of the lithography technology. Because the gate current transmission speed is increased, and the gate width is shortened, the channel length is relatively shortened, so the operating speed of the MOS transistor 30 of the present invention can be greatly improved. In addition, the production method of the present invention can complete the production of LDD 66 and source 70 and drain 72 without making a side wall. Therefore, the production method of the present invention can produce smaller line width and faster speed with fewer process steps.

第12頁 d6 8228Page 12 d6 8228

快而成本更低的MOS電晶體β 相較於習知體4 0是以鶴或石夕 4 0的閘極片電阻本發明製作方法閘極的寬度，使習知的微影技術習知方法先製作極7 0與汲極7 2的法少的製程步驟的M0S電晶體。 M0S電晶體10的製作 .化鶴來做為間極導電方/，/發明嶋晶利用一等向性姓電阻。同時，— 得本發明M0S電晶體的閘進^步地縮短所限制。此外，侧壁子32，就可以直接ί，方法不必如同製=，因此本發明製作方法可以較習知方，來製作線寬更小、速度更快而成本更低以上所述僅本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明專利之涵範圍。Faster and lower cost MOS transistor β is compared with the conventional body 40. It is a gate chip resistor of crane or stone xi 40. The manufacturing method of the present invention is the width of the gate, which makes the conventional lithography technology known. First, an M0S transistor with a few process steps of the pole 70 and the drain 72 is fabricated. Production of M0S transistor 10. To transform the crane as an interpolar conducting square, / to invent the crystal using an isotropic resistor. At the same time, the gate of the MOS transistor of the present invention is further shortened, which is limited. In addition, the side wall 32 can be directly used, and the method does not need to be the same as the manufacturing method. Therefore, the manufacturing method of the present invention can be used to make smaller line widths, faster speeds, and lower costs than conventional methods. In a preferred embodiment, any equivalent changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the patent of the present invention.

第13頁Page 13

Claims

-468228 六、申請專利範圍 1. 一種金属氧化半導體（metal-oxide semiconductor,， M0S)電晶體的製作方法，該M0S電晶體係製作於一半導體晶片上，該半導體晶片包含有一基底，一介電層設於該基底表面之一預定區域上，一導電層設於該介電層之上，以及一保護層設於該導電層之上，該製作方法包含有下列步驟：進行一等向性蝕刻製程，用來蝕刻該介電層及該導電層之兩侧壁，以形成一閘極（g a t e )，該閘極包含有一閘極介電層（gate dielectric layer)係由殘餘之該介電層所構成，以及一閘極導電層（gate electrode)係由殘餘之該導電層所構成；進行一第一離子佈植（ion implantation)製程，以一傾斜之入熨角度在該閘極兩側之基底内分別形成二輕微摻雜沒極（lightly doped drain, LDD);以及進行一第二離子佈植製程，利用該保護層做為一硬罩幕（hard mask)，以在該閘極兩側之基底内分別形成一源極（source)與一沒極（drain)。 2. 如申請專利範圍第1項之製作方法，其中該介電層係為一二氧化珍（silicon dioxide, Si 0 2)層。 3. 如申請專利範圍第1項之製作方法，其中該導電層係為一鎢（tungsten, W)金屬層或一矽化鎢（tungsten silicide, WSix)層。-468228 6. Application Patent Scope 1. A method for manufacturing a metal-oxide semiconductor (MOS) transistor. The MOS transistor system is fabricated on a semiconductor wafer. The semiconductor wafer includes a substrate and a dielectric. A layer is disposed on a predetermined area of the substrate surface, a conductive layer is disposed on the dielectric layer, and a protective layer is disposed on the conductive layer. The manufacturing method includes the following steps: performing an isotropic etching A process for etching the dielectric layer and two side walls of the conductive layer to form a gate, the gate including a gate dielectric layer made of the residual dielectric layer And a gate electrode is composed of the remaining conductive layer; a first ion implantation process is performed, and a sloped ironing angle is formed on both sides of the gate electrode; Two lightly doped drains (LDDs) are formed in the substrate, respectively; and a second ion implantation process is performed, and the protective layer is used as a hard mask to shield the gate Respectively forming a source electrode (source) and a pole not (Drain) on both sides of the substrate. 2. The manufacturing method according to item 1 of the patent application scope, wherein the dielectric layer is a silicon dioxide (Si 02) layer. 3. The manufacturing method according to item 1 of the application, wherein the conductive layer is a tungsten (W) metal layer or a tungsten silicide (WSix) layer.

第14頁 46 8228 六、申請專利範圍 4. 如申請專利範圍第3項之製作方法，其中該導電層與該介電層之間另包含有一氛化鈦（titaniuin nitride, TiN)層’用來增加該鎢金屬層或矽化鎢層對該介電層的附著力’並阻止該鎢金屬層或矽化鎢層内之鎢原子穿過該介電層。 5. 如申請專利範圍第1項之製作方法，其中該保護層包含有：一乳化石夕（silicon oxide)層，設於該導電層之上；一氮氧化發（silicon-oxy-nitride，SiOxNy)層，設於該氧化矽層之上；以及一氣化石夕（silicon nitride, SiNx)層，設於該氣氧化石夕層之上。 6 · 如申請專利範圍第1項之製作方法，其中該傾斜之入射角度的範圍為15〜3 0度。 7. 如申請專利範圍第1項之製作方法，其中該M0S電晶體係為一 N型（N-type)MOS電晶體》 8. 如申請專利範圍第6項之製作方法，其中該第一離子佈植製程係植入珅（arsenic, As)離子，而該第二離子佈植製程係植入神離子與鱗（phosphorous，P)離子。Page 14 46 8228 6. Application scope of patent 4. The production method of the third scope of application for patent, wherein the conductive layer and the dielectric layer further include a titanium titanium nitride (TiN) layer. Increase the adhesion of the tungsten metal layer or tungsten silicide layer to the dielectric layer and prevent tungsten atoms in the tungsten metal layer or tungsten silicide layer from passing through the dielectric layer. 5. The manufacturing method according to item 1 of the scope of patent application, wherein the protective layer includes: a silicon oxide layer provided on the conductive layer; a silicon-oxy-nitride (SiOxNy) ) Layer is disposed on the silicon oxide layer; and a silicon nitride (SiNx) layer is disposed on the silicon oxide layer. 6 · For the method of making the first item in the scope of patent application, wherein the angle of incidence of the inclined range is 15 to 30 degrees. 7. The manufacturing method of item 1 in the scope of patent application, wherein the MOS transistor system is an N-type MOS transistor. 8. The manufacturing method of item 6 in the scope of patent application, wherein the first ion The implantation process implants arsenic (As) ions, and the second ion implantation process implants divine ions and phosphorous (P) ions.

第15頁 46 822 8 六' 申請專利範圍 ——---------------------------一- ^t ί請專利範圍第7項之製作方法，其中該第一離子植劍吾基f使?之佈植能量為40仟電子伏特（KeV)，而佈劑量為lx 101雔子/平方公分（i 〇n/cm2)。 i0插ΐΐΐ專2範圍第7項之製作方法，其令該第二離子 η;離入二離：時所使用之佈植能量為6°仟電子伏特 t離子之佈植劑量為4Χ 1〇|離子/平方公分 P而麟離子時所使用之佈植能量為30仟電于伏^特（K e V ) *麟離耳·夕你始杰丨田& 分（ion/c^)。離子之佈植劑1為3 X 10嘴子/平方公其中該M0S電晶體 U，如申费專利範園第1項之製作方法係為一P型（P-type)M〇s電晶體。 :植umv項；；m其中該第-離子子與硼(二，1>離；該第二離子佈植製程係植入 1 3 如申請專利範圍第！〇項之製佈植製程所使用之佈植能量為丨工，八中該第一離子植劑量為2〜4x 1〇丨雔子;電子伏特（KeV)，而佈卞万公分（i〇n/cm2)。如申請專利範圍第1〇項之製作方法，4中該第二離子Page 15 46 822 8 Six 'scope of patent application --------------------------- 一-^ t ίPlease patent scope No. 7 The manufacturing method of item, wherein the first ion planting sword kiwi f makes the planting energy of 40 仟 electron volts (KeV), and the cloth dose is 1 × 101 雔 / cm² (ion / cm2). The production method of item 7 in the range of i0 insertion 2 is to make the second ion η; the ion implantation energy is 6 °, and the implantation dose of the electron volt t ion is 4 × 1〇 | Ion / cm 2 P, and the implantation energy used by the Lin ion is 30 仟 volts (K e V) * Lin Lier · Xi You Shijie 丨 Field & cent (ion / c ^). The ion implanting agent 1 is 3 X 10 mouthpieces per square centimeter. The M0S transistor U, as described in the first item of the patent application park, is a P-type M0s transistor. : Plant umv term; m where the -ion ion is separated from boron (II, 1 >); the second ion implantation process is implanted 1 3 as used in the patent application scope of the cloth production process! The planting energy is 丨 work, the first ion implantation dose in the eighth is 2 ~ 4x10〇雔子; electron volts (KeV), and the cloth is 10,000 cm (i0n / cm2). Production method of item 〇2, the second ion in 4

第16頁 468228 六、申請專利範圍佈植製程所使用之佈植能量為10仟電子伏特（KeV)，而佈植劑量之範圍為2 X 1 0 4 X 1 0 1灕子/平方公分 (i on/ cm 2) 〇 :15. —種金屬氧化半導體（M0S)電晶體的製作方法，該M0S 電晶體係製作於一半導體晶片上，該半導體晶片包含有一基底，一介電層設於該基底表面之一預定區域上，一導電 |層設於該介電廣之上，以及一保護層設於該導電層之上，該製作方法包含有下列步驟：進行一等向性蝕刻製程，用來蝕刻該介電層及該導電層之兩側壁，以形成一閑極，該閘極包含有一閘極介電層 |係由殘餘之該介電層所構成，以及一閘極導電層係由殘餘之該導電層所構成；進行一第一離子佈植製程，利用該保護層做為一硬罩幕，以在該閘極兩側之基底内分別形成一源極與一汲極；完全去除該保護層，以及進行一第二離子佈植製程，在該閘極兩側之基底内分 i別形成二輕微摻雜汲極（LDD)。 1 6.如申請專利範圍第1 5項之製作方法，其中該介電層係為一二氧化珍（SiO 2)層。Page 16 468228 6. Application scope of patent application The implantation energy used in the implantation process is 10 仟 electron volts (KeV), and the implantation dose range is 2 X 1 0 4 X 1 0 1 Lizi / cm 2 (i on / cm 2) 〇: 15. — A method for manufacturing a metal oxide semiconductor (M0S) transistor, the M0S transistor system is fabricated on a semiconductor wafer, the semiconductor wafer includes a substrate, and a dielectric layer is disposed on the substrate On a predetermined area of the surface, a conductive layer is provided on the dielectric layer, and a protective layer is provided on the conductive layer. The manufacturing method includes the following steps: An isotropic etching process is performed for The dielectric layer and the two sidewalls of the conductive layer are etched to form a free electrode. The gate includes a gate dielectric layer, which is composed of the residual dielectric layer, and a gate conductive layer is composed of the residual The conductive layer is formed; a first ion implantation process is performed, and the protective layer is used as a hard cover to form a source electrode and a drain electrode in the substrate on both sides of the gate electrode; completely removing the A protective layer and a second ion implant In the substrate, two lightly doped drains (LDDs) are formed in the substrate on both sides of the gate. 16. The manufacturing method according to item 15 of the scope of patent application, wherein the dielectric layer is a SiO 2 layer.

第17頁 1 7 .如申請專利範圍第1 5項之製作方法，其中該導電層係 2 為一鶴（W )金屬層或一紗化鶴（WSix)層。 d6 8228Page 17 1 7. The manufacturing method of item 15 in the scope of patent application, wherein the conductive layer 2 is a crane (W) metal layer or a yarn crane (WSix) layer. d6 8228

第18頁 468228 六、申請專利範圍 a (KeV) ’砷離子之佈植劑量為4 X 1 〇 %子八八 (ion/cm2)’而植人碟離子時所使用之佈二，$ 子伏特（KeV)，磷離子之佈植劑量為3 a ^仟電分（ion/cm2)。鱗子/平方公 24·如申請專利範圍第22項之製作方法，佈植製程所使用之佈植能量為40仟電子姓一離子植劑量為1χ 1〇ι雔子/平方公分（ionm/KeV)，而佈 2 5 如申請專利範圍第1 5項之製作方法體係為一 P型（卜type)M0S電晶ΐ 法其中該M〇S電晶 26.如申碛專利範圍第2 5項之製作方法，一佈植製程係植入BF2離子與硼（B)離子，而嗲二製程係植入BF2離子》 μ第一離子佈植 27_如申請專利範圍第26項之製作方法，佈植製程所使用之佈植能量為1 〇件電子伏胜 ' 植劑量之範圍為2x 10^4x 10^m(KeV)’而佈 (i〇n/cm2)« 方公分 V 28.如申請專利範圍第26項之製作方法，佈植製程所使用之佈植能量為10仟電子伏^，該^ 一離子植劑量為2〜4 X HP雔子/平方公分（i〇n/HeV)，而饰 e jj] )〇Page 18 468228 VI. Patent application scope a (KeV) 'The implantation dose of arsenic ions is 4 X 10% sub-88 (ion / cm2)' and the cloth used when implanting dish ions, $ 子 volt (KeV), and the implantation dose of phosphorus ions was 3 a ^ 仟 electric minutes (ion / cm2). Scales / cm2 24. According to the production method of item 22 in the scope of patent application, the implantation energy used in the implantation process is 40. The electronic surname and the ion implantation dose are 1 × 10mm. Per square centimeter (ionm / KeV). ), And the manufacturing method system of cloth 2 5 as in item 15 of the scope of patent application is a P-type M0S transistor. Among them, the M0S transistor 26. As in claim 25 of patent scope Production method, the first production process is implanted with BF2 ions and boron (B) ions, and the second production process is implanted with BF2 ions. Μfirst ion implantation 27 The planting energy used in the process is 10 electronic volts. The range of planting dose is 2x 10 ^ 4x 10 ^ m (KeV) 'and the cloth (i〇n / cm2) «square centimeter V 28. In the production method of item 26, the implantation energy used in the implantation process is 10 仟 electron volts ^, and the ^ one ion implantation dose is 2 to 4 X HP 雔子 / cm2 (イ〇 / HeV), and the decoration is e jj]) 〇