TW468227B - High frequency metal oxide semiconductor field effect transistor structure - Google Patents
High frequency metal oxide semiconductor field effect transistor structure Download PDFInfo
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d6Q227____ 五、發明說明（1) 發明領域 本發明係有關於一種積體電路（integrated circuits ;ICs)製程技術，特別是肴關於一種能夠提高元 件性能之高頻（high frequency)金氧半場效電晶體（metal oxide semiconductor field effect transistor ； MOSFET)及其製造方法。 相關技術之描述 近年來高頻金氧半場效電晶體已經被快速發屐並且應 用於行動通訊產品（例如行動電話），此高頻金氧半場效電 晶體被要求具有高增益（high gain)與高效率（high efficiency)。 以下利用第1A〜第1C圖以及第2圖所示的高頻金氧半場 效電晶體的製程剖面示意圖以及上視圖，以說明習知技術 之一 〇 首先，請參照第1A圖，該圖顯示例如單晶矽構成的半 導體基底（semiconductor substrate)10，此基底 10 表面 形成有複晶矽（polysilicon)構成的閘極（gate)13 ;離子 摻雜區域（doped area)構成的源極（source)14與汲極 (drain)16 ;側壁絕緣物（spacer)15 ;閘極氧化層（gate oxide)12 ;以及形成於閘極13以及源極14/汲極16表面的 石夕化鈷（cobalt silicide )18。 接者，请參照第1 B圖’在半導體基底1 〇表面形成例如 二氧化石夕（silicon oxide)構成的絕緣層（insulating layer)20 ’用以覆蓋上述閘極130及源極14 /汲極16。d6Q227____ 5. Description of the invention (1) Field of the invention The present invention relates to an integrated circuits (ICs) process technology, and particularly to a high frequency metal-oxide-semiconductor field-effect transistor capable of improving component performance. (Metal oxide semiconductor field effect transistor; MOSFET) and manufacturing method thereof. Description of related technologies In recent years, high-frequency metal-oxide-semiconductor FETs have been rapidly developed and applied to mobile communication products (such as mobile phones). The high-frequency metal-oxide-semiconductor MOSFETs are required to have high gain and high gain. High efficiency. The following is a schematic cross-sectional view of the manufacturing process of the high-frequency metal-oxide half-field-effect transistor shown in FIGS. 1A to 1C and FIG. 2 and a top view to explain one of the conventional techniques. For example, a semiconductor substrate 10 made of single crystal silicon, a gate 13 made of polysilicon is formed on the surface of the substrate 10, and a source made of an ion-doped area 14 and drain 16; sidewall spacer 15; gate oxide 12; and cobalt silicide formed on the surface of gate 13 and source 14 / drain 16 ) 18. For details, please refer to FIG. 1B. FIG. 1 'forms an insulating layer 20 made of silicon oxide on the surface of the semiconductor substrate 10, for example, to cover the gate 130 and the source 14 / drain. 16.
0503-5624TWF.ptd 第4頁 46 822 7 五、發明說明（2) 然後5請參照第1C圖，選擇性蝕刻上述絕緣層2 0，以 形成一接觸孔3 1 ’然後將金屬材料填入該接觸孔3丨内以形 成一接觸窗32。 其次’請參照第2圖，此圖顯示習知高頻金氧半場效 電晶體的上視圖，其中符號32表示能夠連接汲極1 6的接觸 插塞（plug) ’另外’符號34表示能夠連接閘極1 3的接觸窗 (contact window) ° 根據（"ULSI Devices11 edited by C.Y. Chang and S.M.Sze)半導體物理元件公式： fmax = fT/( (Rs + Rg)/R〇ut + 2 π x fTRgCgd)0·5 fmax:最大振動頻率 fT:最大切斷頻率 R s :源極阻值 Rg:閘極阻值0503-5624TWF.ptd Page 4 46 822 7 V. Description of the invention (2) Then 5 Please refer to FIG. 1C to selectively etch the above-mentioned insulating layer 20 to form a contact hole 3 1 ′ and then fill the metal material into the A contact window 32 is formed in the contact hole 3 丨. Secondly, please refer to FIG. 2, which shows a top view of a conventional high-frequency metal-oxide-semiconductor half-effect transistor, where symbol 32 indicates a contact plug capable of connecting the drain electrode 16 and “other” symbol 34 indicates that it can be connected. Contact window of gate 1 3 ° According to (ULSI Devices11 edited by CY Chang and SMSze) semiconductor physical element formula: fmax = fT / ((Rs + Rg) / R〇ut + 2 π x fTRgCgd ) 0 fmax: maximum vibration frequency fT: maximum cut-off frequency R s: source resistance Rg: gate resistance
Rout:串聯阻值（源極_ j；及極阻值）Rout: series resistance (source_j; and extreme resistance)
Cgd:閘極/汲極電容 隨著高頻金氧半場效電晶體日益地縮小，源極寬度、 閘極寬度Lg以及其接觸窗縮小，導致Rg、、以及Cgd皆 增加’而Rout則是下降，使得fmax大幅地下降而影響到訊 號放大的能力。 發明之概述及目的 有鑑於此’本發明的目的在於提供一種高頻金氧半場Cgd: The gate / drain capacitance is shrinking with the high-frequency metal-oxide half-field-effect transistor. The source width, gate width Lg, and its contact window are reduced, causing Rg, and Cgd to increase, while Rout is decreasing. , Which makes fmax drop greatly and affects the signal amplification ability. Summary and purpose of the invention In view of this, the object of the present invention is to provide a high-frequency metal-oxygen half field
〇503-5624TSVF.ptd 第5頁 -- 五、發明說明（3) 能夠提高元件—確保高頻金 乳+ %效電日日體放大訊號的能力。 根據上述目的，本發明提供一種高頻金氧 ，結構’包括：一、半導體基底；—閘極，形成於該半導體 土底上方，源極/汲極，形成於該閘極之兩側之 底表面；一導電結構，覆蓋於該閘極表面，並且該 構的尺寸大於該閘極的尺寸；一箕一絕鏠 μ Λ ^ ^ ^ 弟絕緣層，形成於該半 導體基底表面，並且覆蓋該源極/汲極；以及— 層，形成於該第:絕緣層的表面，並且覆蓋該導電結構。 再者，上述高頻金氧半場效電晶體中， fr構可形幻字結構。另外，更包括-第Λ:式接 肉’ f ϋ該第二絕緣層而與該導電結#接觸μ及曰一第二 $槽式接觸窗’穿透該第—絕緣層與該第 該源極/汲極接觸。 〇豕禮tm興 再者，上述高頻金氧半場效電晶體之中， 2於該半導體基底以及該閑極之間，並且“ 極氧化層邊緣的厚度大於中央，此閘極氧化層是 熱氧化時間所形成，同時使得間極成為微笑型心 (smi1ing gate)。 禎曰ϋι'上述高頻金氧半場效電晶體之中，該閘極係由 複曰曰構成。而該導電結構係底部具有氮tit ^trlde)阻障層（barrier Iayer)之鎢金屬結構 (tungsten structure)。 再者，上述高頻金氧半場效電晶體之令，該間極與該〇503-5624TSVF.ptd Page 5-5. Description of the invention (3) It can improve the component—ensure the ability of high-frequency gold emulsion +% efficiency solar energy to amplify the signal. According to the above object, the present invention provides a high-frequency metal oxide structure including: a semiconductor substrate; a gate formed on the semiconductor soil bottom, and a source / drain formed on both sides of the gate; A conductive structure covering the surface of the gate, and the size of the structure is larger than the size of the gate; a μ ^ ^ ^ ^ ^ brother insulating layer is formed on the surface of the semiconductor substrate and covers the source / Drain; and-a layer formed on the surface of the first insulating layer and covering the conductive structure. Furthermore, in the above-mentioned high-frequency metal-oxide-semiconductor field-effect transistor, the fr structure can be formed into a magic word structure. In addition, it further includes -th: Λ: the second insulation layer is in contact with the conductive junction # and a second $ groove contact window 'penetrates the first insulation layer and the first source Pole / drain contact. 〇 豕 礼 tm, again, among the above-mentioned high-frequency metal-oxide half-field-effect transistor, 2 is between the semiconductor substrate and the free electrode, and the thickness of the edge of the electrode oxide layer is greater than the center, and the gate oxide layer is thermal It is formed by the oxidation time, and at the same time, the pole becomes a smiling gate. Among the above-mentioned high-frequency metal-oxygen half-field-effect transistors, the gate is composed of complex. The conductive structure is at the bottom A tungsten metal structure (tungsten structure) with a barrier barrier of nitrogen (t ^ trlde). Furthermore, the above-mentioned order of the high-frequency metal-oxygen half-field-effect transistor, the electrode and the
0503-5624TWF.ptd 第6頁 4 6 8227 五、發明說明（4) 源極/汲極表面形成有例如梦化銘的金屬梦化合物（metal silicide)。 根據上述目的’本發明提供一種高頻金氧半場效電晶 體的製造方法，包括下列步驟：（a)提供一半導體基底， 該基底表面形成有一閘極、源極/沒極，並且該閘極以及 該基底表面之間形成有一閘極氧化層；（b )在該閘極與該 源極/汲極的表面形成一金屬石夕化合物層；（c)在該半導體 基底表面沈積一第一絕緣層，用以覆蓋該閘極與該源極/ 汲極；（d )去除該閘極表面的第一絕緣層，以露出該閘極 表面的金屬矽化合物層；（e)在該閘極表面形成一導電結 構，該導電結構的尺寸大於該閘極；（〇該半導體基底表 面形成一第二絕緣層，用以覆蓋該導電結構；（g)選擇性 银刻该第二絕緣層以及該第一絕緣層以形成一露出該導電 結構的第一溝槽以及露出該源極/汲極的第二溝槽；以及 (h)在該第一溝槽以及該第二溝槽填入金屬材料以分別形 成一第一溝槽式接觸窗以及一第二溝槽式接觸窗。 再者，上述高頻金氧半場效電晶體的製造方法之中， 步驟（d)可以採用化學機械研磨法完成。而步驟Q)在形成 該第一絕緣層之前更包括形成一研磨停止層的步驟。 ^ 再者，上述高頻金氧半場效電晶體的製造方法之中， 3第絕緣層可以是二氧化矽層，並且該研磨停止層可 以是氮化矽層。金屬矽化合物層可以是矽化鈷層。該閘極 :以由複晶矽構成。上述導電結構係底部具有氮化鈦阻障 層之鎢金屬結構並與該閘極與形成τ字結構。0503-5624TWF.ptd Page 6 4 6 8227 V. Description of the invention (4) A metal silicide is formed on the source / drain surface, for example, a metal dream compound. According to the above object, the present invention provides a method for manufacturing a high-frequency metal-oxide-semiconductor field-effect transistor, including the following steps: (a) providing a semiconductor substrate, the surface of which is formed with a gate electrode, a source electrode, and a non-electrode electrode; and the gate electrode And a gate oxide layer is formed between the substrate surface; (b) a metal oxide compound layer is formed on the surface of the gate and the source / drain; (c) a first insulation is deposited on the surface of the semiconductor substrate Layer to cover the gate and the source / drain; (d) remove the first insulating layer on the gate surface to expose the metal silicon compound layer on the gate surface; (e) on the gate surface Forming a conductive structure, the size of the conductive structure is larger than the gate electrode; (0) a second insulating layer is formed on the surface of the semiconductor substrate to cover the conductive structure; (g) the second insulating layer and the An insulating layer to form a first trench exposing the conductive structure and a second trench exposing the source / drain; and (h) filling the first trench and the second trench with a metal material to Form a first trench contact Window and a second trench-type contact window. Furthermore, in the above-mentioned method for manufacturing a high-frequency metal-oxide-semiconductor field-effect transistor, step (d) may be completed by a chemical mechanical polishing method, and step Q) is to form the first The insulating layer further includes a step of forming a polishing stop layer. ^ Furthermore, in the method for manufacturing a high-frequency metal-oxide-semiconductor field-effect transistor, the third insulating layer may be a silicon dioxide layer, and the polishing stop layer may be a silicon nitride layer. The metal silicon compound layer may be a cobalt silicide layer. The gate is composed of polycrystalline silicon. The conductive structure is a tungsten metal structure with a titanium nitride barrier layer at the bottom and forms a τ-shaped structure with the gate.
46 822746 8227
五、發明說明（5) 本發明的特徵之一在於楹 極，由於導電結構的尺寸大^面具有導電結構之閘 溝槽式接觸窗。寸Α於㈣’使得容易在後續形成 本發明另一特徵在於，在閘極與源極/汲極上方分別 供溝槽式接觸窗，以降低Rg以及rs。 本發明另一特徵在於，形成邊緣厚度大於中央的閘極 氧化層’藉以提高fmax。 為了讓本發明之上述目的、特徵、和優點能更明顯易懂， 下文特舉一較佳實施例’並配合所附圖式，作詳細說明如 下： 圖式之簡單說明 第1.4~第1C圖為根據習知技術之高頻金氧半場效電晶 體的製程剖面圖。 第2圖為根據習知技術之高頻金氧半場效電晶體上視 圖。 第3A〜第3E圖為根據本發明實施例之高頻金氧半場效 電晶體的製程剖面圖。 第4圖為根據本發明實施例之高頻金氧半場效電晶體 的上視圖。 符號之說明 10、100〜半導體基底； 12、 120〜閘極氧化層； 13、 130〜閘極； 14、 140〜源極；V. Description of the invention (5) One of the features of the present invention is the pole electrode. Due to the large size of the conductive structure, the gate has a conductive grooved contact window. Inch A to ㈣ 'makes it easy to form it later. Another feature of the present invention is that trench contact windows are provided above the gate and source / drain electrodes, respectively, to reduce Rg and rs. Another feature of the present invention is that a gate oxide layer 'having an edge thickness greater than that of the center is formed to increase fmax. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings, and described in detail as follows: Brief description of the drawings, FIGS. 1.4 to 1C This is a process cross-sectional view of a high-frequency metal-oxide-semiconductor field-effect transistor according to the conventional technology. Fig. 2 is a top view of a high-frequency metal-oxygen half field-effect transistor according to a conventional technique. Figures 3A to 3E are cross-sectional views of the manufacturing process of a high-frequency metal-oxygen half-field-effect transistor according to an embodiment of the present invention. Fig. 4 is a top view of a high-frequency metal-oxide half-field-effect transistor according to an embodiment of the present invention. Explanation of symbols 10, 100 to semiconductor substrate; 12, 120 to gate oxide layer; 13, 130 to gate; 14, 140 to source;
0503-5624TWF.ptd 第8頁 Λ6 822 五、發明說明（6) 1 5、1 5 0〜侧壁絕緣物； 1 6、1 6 0〜汲極； 18、180〜金屬矽化合物； 200〜研磨停止層； 20、220、220a、280〜絕緣層； 240〜黏合阻障層； 260〜鎢金屬層； CS〜導電結構； 300、320〜溝槽式接觸窗。 實施例 以下利用第3A〜第3E圖以及第4圖所示的高頻金氧半場 效電晶體的製程剖面示意圖以及上視圖，以說明本發明實 施例。 首先’請參照第3 A圖，該圖顯示例如單晶石夕構成的半 導體基底100，此基底1〇〇表面形成有複晶發構成的閘極 130 ;離子摻雜區域構成的源極140與汲極160 ;有助於形 成淺摻雜汲極（light doped draiη ; LDD)的侧壁絕緣物 1 50 ;邊緣厚度大於中央的閘極氧化層12〇 ;以及形成於複 晶矽閘極130以及源極140 /汲極16〇表面的矽化鈷（c〇balt si licide )180。上述邊緣厚度大於中央的閘極氧化層12〇 是藉由延長熱氧化時間而形成。 p f著由請參照第3B圖，矛11用低壓化學氣相沈積法以形 成當作研磨停止層200的氨斗坊4-U1I ^ L s L Γ 们氣化石夕材料，其次，在上述研磨 停止層上形成例如二氧彳卜々 Α化夕構成的絕緣層2 2 0，用以覆盎 '46 82 2 7 五 '發明說明（7) 上述閘極130以及源極140/汲極160。 然後，請參照第3C圖，進行化學機械研磨步驟，以去 除部分的絕緣層220 ’而留下絕緣層220a並露出閘極表面 的研磨停止層200，此時研磨停止層200與矽化錯18〇能夠 避免化學機械研磨過程中閘極130與源極U0/汲極160受 損。 其次’請參照第2 D圖’利用鱗酸等溶液去除位於閘極 130上方的氮化石夕研磨停止層2〇〇，直到露出閘極wo上方 的石夕化錄1 8 0為止。之後，利用化學氣相沈積法全面性地 形成當作黏合阻障功能之氮化鈦以及鎢金屬，接著利用傳 統的微影製程以及蝕刻步驟定義黏合阻障層2 4 〇以及鎢金 屬層260的導電結構CS，此導電結構CS的尺寸大於閘極 130 ’並且形成於閘極130的正上方，而與閘極130形成T型 結構。再者，此導電結構CS提供更大的接觸面積，使後續 接觸窗更容易形成’並且此導電結構CS有助於降低閘極阻 值Rg，進而提高fmax。 接下來’請參照第2E圖，利用低壓氣相沈積法在上述 絕緣層220a以及導電結構CS的表面形成例如二氧化矽構成 的絕緣層280。然後’利用傳統的微影製程以及蝕刻步驟 選擇性地去除絕緣層28 0以及2〇〇a，以形成露出導電結構 CS的第一溝槽310以及露出汲極16〇表面之矽化鈷180的第 二溝槽315。其次，在上述第一溝槽31〇以及第二溝槽315 填入例如鶴的金屬材料，以分別形成第溝槽式接觸窗3 〇 〇 以及一第二溝槽式接觸窗32〇。上述溝槽式接觸窗大幅地0503-5624TWF.ptd Page 8 Λ6 822 V. Description of the invention (6) 1 5, 1 5 0 ~ side wall insulator; 1 6, 1 6 0 ~ Drain; 18, 180 ~ metal silicon compound; 200 ~ grinding Stop layer; 20, 220, 220a, 280 ~ insulation layer; 240 ~ adhesive barrier layer; 260 ~ tungsten metal layer; CS ~ conductive structure; 300,320 ~ trench contact window. EXAMPLES The following is a schematic cross-sectional view of the manufacturing process of the high-frequency metal-oxide-semiconductor field-effect transistor shown in FIGS. 3A to 3E and FIG. 4 and a top view to explain the embodiments of the present invention. First, please refer to FIG. 3A, which shows, for example, a semiconductor substrate 100 composed of a single crystal, and a gate 130 composed of a complex crystal is formed on the surface of the substrate 100; a source 140 composed of an ion-doped region and Drain 160; helps to form light doped draiη (LDD) sidewall insulators 150; edge thickness is greater than the center gate oxide layer 120; and is formed on polycrystalline silicon gate 130 and Cobalt silicide 180 on the source 140 / drain 16 surface. The gate oxide layer 120 having a thickness greater than that at the center is formed by extending the thermal oxidation time. Please refer to FIG. 3B for pf reasoning. The spear 11 is formed by using a low-pressure chemical vapor deposition method to form the ammonia doufang 4-U1I ^ L s L Γ as the grinding stop layer 200. Second, the above-mentioned grinding stops An insulating layer 2 2 0 formed of, for example, a dioxin, aluminum alloy, is formed on the layer to cover the '46 82 2 7 5 'Invention Description (7) The gate 130 and the source 140 / drain 160 described above. Then, referring to FIG. 3C, a chemical mechanical polishing step is performed to remove a part of the insulating layer 220 'while leaving the insulating layer 220a and exposing the polishing stop layer 200 on the gate surface. At this time, the polishing stop layer 200 and silicidation layer 18 are removed. It can prevent the gate electrode 130 and the source electrode U0 / drain electrode 160 from being damaged during the CMP process. Next, "Please refer to Fig. 2D", using a solution such as scale acid to remove the nitride stop layer 200 above the gate electrode 130 until the stone layer above the gate electrode wo is exposed to 180. Thereafter, chemical vapor deposition is used to comprehensively form titanium nitride and tungsten metal as the adhesion barrier function, and then the conventional lithography process and etching steps are used to define the adhesion barrier layer 24 and the tungsten metal layer 260. The conductive structure CS has a size larger than the gate electrode 130 ′ and is formed directly above the gate electrode 130, and forms a T-shaped structure with the gate electrode 130. In addition, the conductive structure CS provides a larger contact area, which makes subsequent contact windows easier to form, and the conductive structure CS helps to reduce the gate resistance value Rg, thereby increasing fmax. Next, referring to FIG. 2E, an insulating layer 280 made of, for example, silicon dioxide is formed on the surfaces of the insulating layer 220a and the conductive structure CS by a low-pressure vapor deposition method. Then, the traditional lithography process and the etching step are used to selectively remove the insulating layers 280 and 2000a to form a first trench 310 exposing the conductive structure CS and a first silicon oxide 180 exposing the surface of the drain 160.二 槽 315。 Two trenches 315. Next, the first groove 31o and the second groove 315 are filled with a metal material such as a crane to form a third grooved contact window 300 and a second grooved contact window 32o. The grooved contact window described above greatly
0503-5624TWF.ptd Z-- 第10頁 46 8227 五、發明說明（8) 降低Rg與RS，進而提高fmax。 根據本發明實施例形成之高頻金氧半場效電晶體構造 包含一半導體基底100 ; —閘極130，形成於該半導體基底 100上方；源極140/汲極160，形成於該閘極130之兩側之 半導體基底100表面；一導電結構CS，覆蓋於該閘極130表 面，並且該導電結構CS的尺寸大於該閘極130的尺寸；一 第一絕緣層220a，形成於該半導體基底1〇〇表面，並且覆 蓋該源極140/汲極160 ;以及一第二絕緣層280 ’形成於該 第一絕緣層220a的表面，並且覆蓋該導電結構cs。 為了進一步說明本實施例，請參照第4圖，此圖顯示 高頻金氧半場效電晶體的上視圖，其中符號32〇表示能夠 連接汲極160的溝槽式接觸窗’而符號3〇〇表示能夠連接導 電結構CS以及閘極130的溝槽式接觸窗。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此項技藝者，在不脫離本發明之精 神和範圍内’當可作更動與潤飾’因此本發明之保護範圍 當視後附之申請專利範圍所界定者為準。0503-5624TWF.ptd Z-- Page 10 46 8227 V. Description of the invention (8) Reduce Rg and RS, and then increase fmax. The high-frequency metal-oxide-semiconductor field-effect transistor structure formed according to an embodiment of the present invention includes a semiconductor substrate 100; a gate 130 formed on the semiconductor substrate 100; a source 140 / drain 160 formed on the gate 130; The surface of the semiconductor substrate 100 on both sides; a conductive structure CS covering the surface of the gate 130, and the size of the conductive structure CS is larger than the size of the gate 130; a first insulating layer 220a is formed on the semiconductor substrate 10; A surface and covers the source 140 / drain 160; and a second insulating layer 280 'is formed on the surface of the first insulating layer 220a and covers the conductive structure cs. In order to further illustrate this embodiment, please refer to FIG. 4, which shows a top view of a high-frequency metal-oxide-half field effect transistor, where the symbol 32 is a grooved contact window capable of being connected to the drain 160 and the symbol 30 is used. A trench contact window capable of connecting the conductive structure CS and the gate electrode 130 is shown. Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Any person skilled in the art can change and retouch without departing from the spirit and scope of the present invention. The scope of protection shall be determined by the scope of the attached patent application.
0503-5624TWF.ptd 第11頁0503-5624TWF.ptd Page 11
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| TWI678734B (en) * | 2016-09-05 | 2019-12-01 | 日商日立全球先端科技股份有限公司 | Plasma processing device and method |
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| TWI678734B (en) * | 2016-09-05 | 2019-12-01 | 日商日立全球先端科技股份有限公司 | Plasma processing device and method |
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