TW466744B - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device Download PDF

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Publication number
TW466744B
TW466744B TW088114860A TW88114860A TW466744B TW 466744 B TW466744 B TW 466744B TW 088114860 A TW088114860 A TW 088114860A TW 88114860 A TW88114860 A TW 88114860A TW 466744 B TW466744 B TW 466744B
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Taiwan
Prior art keywords
memory
bit line
word line
read
circuit
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TW088114860A
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Chinese (zh)
Inventor
Syoji Syukuri
Takeshi Sakata
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Hitachi Ltd
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Publication of TW466744B publication Critical patent/TW466744B/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/405—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)

Abstract

A semiconductor integrated circuit device is disclosed, which comprises: allocating the memory capacitors for information charge storage that are on the intersections of multiple bit-lines (BLs) and multiple-read first and multiple-write second word-lines (WLs); connecting the gate to the said first WL and the source/drain to the read adapting MOSFET on the memory node of the said memory capacitor; connecting the gate to the said second WL and the source/drain to the write adapting MOSFET on the memory node of the said memory capacitor; providing substrate area of the read adapting MOSFETs as the collector electrode and their source/drain as base electrode, thereby forming a memory cell composed of an emitter electrode having the amplifier transistors connected to the said BLs.

Description

經濟部智慧財產局員工消費合作社印製Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs

466744 I 五、發明說明（1 ) 本發明係關於半導體積體電路，特別是關於’利用在 備有於動態型記憶單元內具有自行放大功能之半導體記憶 電路時十分有效之技術。 由1個電晶體，1個電容器構成之動態存取記憶體（ Dynamic Random Access Memory )記憶單兀之因細微加工技 術之進展，已達成高度之積體化。在這種動態存取記憶體 ，讀出到位元線之信號之大小，係由電容器電容量C s與 位元線電容器C b之比C s / ( C s + C b )，及電源電 壓V c c而定。在傳統之單元構造，若縮小單元面積將動 態存取記憶體高積體化，電容器容量C s便變小，位元線 電容器C b變大，因此信號量變小，會發生動作界限降低 之問題。 因而有加大電容器表面積，或加大電容器絕緣膜之電 氣膜厚度之必要，但均有一定之限度。另一方面，要減低 位元線電容器C b，分割位元線，使連接在一個感測放大 器之位元線較短比.較有效。惟，位元線分割數一旦變多， 因感測放大器數會增加，其結果是，晶片面積變大。因此 ，藉分割位元線來丨咸低位元線電容器C b ，在成本上有一 定之限度。如此，依傳統技術時，會有因提高動態存取記 憶體之積體度而招致讀出信號量之降低，而妨礙到感測放 大器之高速動作。 爲了解決上述問題點，在日本國特開平 5 - 1 2 9 5 5 4號公報揭示一種具有自行放大功能之記 憶單元之式。此公報所記載之記憶單元，係在轉接 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --‘·----,------'>裝 - ------訂 ---------線 1 (請先閱讀背面之注意事項再填寫本頁) 466744 Α7 Β7 五、發明說明（2 ) P Μ 0 S電晶體之汲極與位元線之間夾裝雙極電晶體，而 在讀出動作時，藉該雙極電晶體來放大儲存於電容器之電 荷。該雙極電晶體之基極連接在轉接PMO S電晶體之汲 極，射極連接在位元線，集極連接在基板領域。 向此在具有自行放大功能之記憶單元寫入資料時，係 利用上述雙極電晶體之基極，射極間之反方向絕緣擊穿電 流，或利用經由寫入電阻之電流。讀出動作時，係令轉接 PMO S電晶體導通，將儲存在電容器之電荷當作雙極電 晶體之基極電流使用，而藉基極電流之電流放大率倍之集 極電流驅動位元線。然而却獲知上述自行放大功能之記憶 單元在性能上存在有很大之問題。 第1個問題是，寫入動作時間較傳統之1個電晶體， 1個電容器型單元爲慢。這是因爲，如上述利用雙極電晶 體之基極，射極間之反方向絕緣擊穿電流當作從位元線之 寫入電流時，要使具有電容器之很大之雜散電容之屏極電 壓改變需要一點時間，以及，利用寫入用之高電阻時，因 寫入用電阻之壓降使施加在轉接ρ Μ 0 S電晶體之電壓降 低，致電流減少。使用上述寫入用電阻時，要使其電阻値 不影響到讀出動作，必須設定成雙極電晶體之射極電阻之 1 0倍以上。因爲射極係由配置在位元接觸孔之中心部之 高濃度Ν型多晶矽膜構成，因此推測爲1〜5 ΙίΩ。因此 ，寫入用電阻應設計爲1 〇〜5 0 k Ω ’但因普通之轉接 MOS電晶體之導通電阻値爲30〜50kQ，差不多是 同樣大小，因此，寫入動作時之單元驅動電流會減少至1 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝------訂— I!---線 經濟部智慧財產局員工消費合作社印製 -b - 經濟部智慧財產局員工消費合作社印製466744 I V. Description of the Invention (1) The present invention relates to a semiconductor integrated circuit, and particularly to a technology which is very effective when a semiconductor memory circuit having a self-amplification function is provided in a dynamic memory cell. The dynamic random access memory (Dynamic Random Access Memory) memory unit consisting of a transistor and a capacitor has achieved a high degree of integration due to the advancement of microfabrication technology. In this type of dynamic access memory, the magnitude of the signal read to the bit line is determined by the ratio C s / (C s + C b) of the capacitor capacitance C s to the bit line capacitor C b and the power supply voltage V cc depends. In the conventional cell structure, if the area of the dynamic access memory is reduced by reducing the cell area, the capacitor capacity C s becomes smaller, and the bit line capacitor C b becomes larger. Therefore, the signal amount becomes smaller, and a problem that the operation limit decreases will occur. . Therefore, it is necessary to increase the surface area of the capacitor or the thickness of the electrical film of the capacitor insulation film, but both have certain limits. On the other hand, it is necessary to reduce the bit line capacitor C b and divide the bit line so that the bit line connected to a sense amplifier is shorter and more effective. However, as the number of bit line divisions increases, the number of sense amplifiers increases, and as a result, the chip area becomes larger. Therefore, by dividing the bit line to the low bit line capacitor C b, there is a certain limit in cost. In this way, according to the conventional technology, there is a decrease in the amount of read signals due to an increase in the integrated degree of the dynamic access memory, which hinders the high-speed operation of the sense amplifier. In order to solve the above problems, Japanese Patent Application Laid-Open No. 5-1 2 9 5 5 4 discloses a memory unit having a self-amplification function. The memory unit described in this bulletin is adapted to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) when transferred to the paper size.-'· ----, ------' > ------- Order --------- Line 1 (Please read the notes on the back before filling this page) 466744 Α7 Β7 V. Description of the invention (2) P Μ 0 S transistor A bipolar transistor is sandwiched between the pole and the bit line, and the charge stored in the capacitor is amplified by the bipolar transistor during a read operation. The base of the bipolar transistor is connected to the drain of the PMO S transistor, the emitter is connected to the bit line, and the collector is connected to the substrate. When writing data to a memory unit with a self-amplification function, the base-electrode of the above bipolar transistor, the reverse direction of the dielectric breakdown current between the emitters, or the current through the write resistor is used. During the read operation, the switching PMO S transistor is turned on, the charge stored in the capacitor is used as the base current of the bipolar transistor, and the collector current is driven by the collector current that is multiple of the base current's current amplification factor. line. However, it is learned that there is a big problem in the performance of the memory unit with the above-mentioned self-amplification function. The first problem is that the write operation time is slower than that of a conventional transistor and a capacitor type cell. This is because when using the base of a bipolar transistor as described above, the dielectric breakdown current in the opposite direction between the emitters is used as the write current from the bit line, so that the screen with a large stray capacitance of the capacitor must be used. It takes a little time for the pole voltage to change, and when the high resistance for writing is used, the voltage applied to the switching p M 0 S transistor decreases due to the voltage drop of the writing resistance, resulting in a reduction in current. When using the above-mentioned writing resistor, in order to make its resistance 値 not affect the reading operation, it must be set to more than 10 times the emitter resistance of the bipolar transistor. Since the emitter is composed of a high-concentration N-type polycrystalline silicon film disposed in the center of the bit contact hole, it is estimated to be 1 to 5 ΙΩ. Therefore, the resistance for writing should be designed as 1 0 ~ 50 k Ω. However, the on-resistance 普通 of a common switching MOS transistor is 30 ~ 50kQ, which is almost the same size. Therefore, the cell drive current during the writing operation Will be reduced to 1 This paper size is applicable to Chinese National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page) Installation ------ Order— I! --- Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs-b-Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs

:466744 I 五、發明說明（3 ) / 2左右。 第2個問題是，起因於使用上述寫入電阻時之位元接 觸孔內部構造之複雜性。上述有自行放大功能之記憶單元 ’係利用膜之堆積與回蝕（etch back )法之側邊隔片（ side spacer)形成技術，在位元接觸孔之外周部配置寫入電 阻，絕緣膜後，再於位元接觸孔之中心部形成雙電極電晶 體之射極。 因此，在相當於大約6 4 Μ位元動態存取記憶體之 0 . 2 〇〜0 . 2 5从m大小之位元接觸孔，寫入電阻， 絕緣膜及射極之平均薄膜厚度有必要設計成4 0〜5 0 n m大小。若考量目前之蝕刻技術實力，寫入電阻之電阻 値及射極接觸基板之平面面積，即射極面積之參差不一， 會令人擔心，推測記憶單元特性上之參差不一可能不小。 爲了要迴避這種自行放大功能之記憶單元之特性參差不一 之問題，須要使位元接觸孔之尺寸十分大，並充分加大寫 入電阻與射極之膜厚度，但其結果將會招致單元面積之增 大。 因此，本發明之目的是在提供，內設有實現高速化與 動作之穩定化之半導體記憶電路之半導體積體電路裝置。 本發明之上述以及其他目的，以及新穎之特徵’可以從本 說明書內之記述，以及所附之圖式’獲得進一步之瞭解。 先說明本案所揭示之發明中，較具代表性者之槪要如 下。亦即，在多數位元線，多數讀出用第1字線及寫入用 第2字線之交點，配置；閘極連接在上述第1字線，一方 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --^----‘-----^ 裝-------- 訂·！'----線 1 (請先閱讀背面之注意事項再填寫本頁) 466744 Α7 Β7 五、發明說明（4 ) (請先閱讀背面之注意事項再填寫本頁) 之源極-汲極連接在記憶電容器之記憶節點之讀出用轉接 Μ〇S F E T ;閘極連接在上述第2字線，源極—汲極路 徑連接在上述位元線與上述記憶電容器之記憶節點之寫入 用轉接MO S F Ε Τ ;以及，以形成有上述讀出用之轉接 Μ 0 S F Ε Τ之半導體領域當作集極，以上述讀出用轉接 Μ〇S F Ε Τ之另一方之源極一汲極當作基極，形成在此 基極領域內之射極連接在上述位元線之放大電晶體所構成 之記憶單元。 茲參照附圖，詳細說明本發明如下。再者，在說明實 施形態用之全圖內，具有同一機能之構件標示同一記號， 其說明從略，以免重複。 第1圖表示本發明之半導體記憶電路之記憶單元之一 實施例之等效電路圖。本實施例之記憶單元係由記憶電容 器Cs ，讀出用之Ρ通道型MOSFET (以後，有時簡 稱爲PMOS) Q1 ，寫入用之N通道型MOSFET ( 以後，有時簡稱爲N Μ 0 S ) Q 2，以及，讀出用之: 466744 I V. Description of the invention (3) / 2 or so. The second problem is due to the complexity of the internal structure of the bit contact hole when the write resistor is used. The above-mentioned memory cell with self-amplification function is a side spacer formation technology using a film stacking and etch back method, and a write resistor is arranged on the outer periphery of the bit contact hole. Then, the emitter of the two-electrode transistor is formed at the center of the bit contact hole. Therefore, it is necessary to average the film thickness of the contact resistance hole, write resistance, insulating film, and emitter at a bit size of m from a bit of 0.26 to 0.25 equivalent to about 64 Mbits of dynamic access memory. Designed to be 40 to 50 nm. If the current etching technology strength is taken into consideration, the resistance of the write resistor and the planar area of the emitter contacting the substrate, that is, the unevenness of the emitter area, will cause people to worry. In order to avoid the problem of the uneven characteristics of the memory cells with this self-amplification function, it is necessary to make the size of the bit contact hole very large and sufficiently increase the film thickness of the write resistance and the emitter, but the result will cause Increase in cell area. Accordingly, it is an object of the present invention to provide a semiconductor integrated circuit device having a semiconductor memory circuit capable of achieving high speed and stable operation. The above and other objects and novel features of the present invention can be further understood from the description in this specification and the accompanying drawings'. First, among the inventions disclosed in this case, the representative ones are as follows. That is, at the intersection of most bit lines, most of the first word line for reading and the second word line for writing are arranged; the gate is connected to the above first word line, and one paper size applies the Chinese national standard (CNS ) A4 size (210 X 297 mm)-^ ----'----- ^ Install -------- Order ·! '---- Line 1 (Please read the notes on the back before filling this page) 466744 Α7 Β7 V. Description of the invention (4) (Please read the notes on the back before filling this page) Source-drain connection MOSFET for reading at the memory node of the memory capacitor; the gate is connected to the second word line, and the source-drain path is connected to the bit line and the write node of the memory capacitor Connect MO SF Ε Τ; and to form the semiconductor field with the above-mentioned read-through switch M 0 SF ET as a collector, and use the above-mentioned read-through switch MOSFET ET E as the source of the other party. The drain is used as a base, and a memory cell composed of an amplifying transistor with the emitter connected to the bit line formed in the base field is formed. The invention is described in detail below with reference to the drawings. Moreover, in the full diagram for explaining the implementation form, components having the same function are marked with the same symbol, and the description is omitted to avoid repetition. Fig. 1 shows an equivalent circuit diagram of an embodiment of a memory cell of a semiconductor memory circuit of the present invention. The memory cell of this embodiment is composed of a memory capacitor Cs, a P-channel MOSFET for reading (hereinafter, sometimes referred to as PMOS) Q1, and an N-channel MOSFET for writing (hereinafter, sometimes referred to as N Μ 0 S ) Q 2 and, for reading

I Ν Ρ Ν雙極電晶體T R所構成。 經濟部智慧財產局員工消費合作社印製 上述讀出用之Ν Ρ Ν電晶體T R之射極連接在位元線 BL，基極連接在讀出用PM0SQ1之一方之源極一汲 極，集極連接在形成上述PM0SQ1之井（well )領域 。上述讀出用之PMO S Q 1之閘極連接在讀出用字線 R W L ;另一方之源極一汲極連接在記憶電容器C s之儲 存用節點。 雖無特別限定，但上述讀出用Ρ Μ 0 S Q 1之閘極絕 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 466744 A7 .___B7 ___________ 五、發明說明（5 ) 緣膜Τ ο X r被設定爲，與寫入用NMO S Q 2之閘極絕 緣膜T 〇 xw同一厚度，或較薄。在上述記憶電容器C s 之另一方電極供應有電壓v p 1。此記億電容器C s之另 一方面電極，係與形成在同一記憶器陣列之其他記憶單元 之電極形成爲一體，成爲所謂屏極（plate )之共同電極。 第2圖表示有說明本發明之記憶單元之寫入·讀出動 作用之閘極電壓•電流特性圖。待機時（standby )之寫入 字線電壓V W W L設定爲V s s ，讀出用字線電壓 ^ 峻匿 όπ鐘 VRWL則設定爲Vcc。 戀_ 寫入（write )資料時，若假設寫入用NMO S之 値電壓爲V t h η，僅將寫入字線電壓VWWL提高到 V c c + V t h η，並使上述寫入用NMO S成導通狀態 ，將位元線電位傳至記憶電容器C s。 讀出（read )資料時，則令讀出字線電壓從V c c降 低到V s s ，使讀出用P Μ 0 S電晶體成爲〇 N狀態，以 記憶電容器C s儲存電荷作爲基極電流I d ’驅動雙極電 晶體TR，藉此電晶體TR所放大之集極電流I B L ( I d X h f e )將位元線充電至電源電壓V c c側。 第3圖表7K本發明之半導體記億電路之目B憶單兀部之 一實施例之布置圖。在該圖，1係定義元件分離領域之活 性領域圖型，2係N型井圖型，3係N型井圖型2之反轉 圖型。4係讀出用字糠圖型，5係寫入用字線圖型，6係 電容器電極連接孔圖型，7係電容器電極圖型。而8係雙 極電晶體之射極領域圖型，1〇係位元接觸孔之圖型， 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝！ 訂！！ 線 '4 6 67 44 a? ____B7_____ 五、發明說明（6 ) 1 1係位元線圖型。 (請先閱讀背面之注意事項再填寫本頁) 在該圖表示，平行延長一對位元線1 1之所謂返折位 元線方式。因此，在一對位元線中之一方之位元線與寫入 用字線5及讀出用字線4之交叉部，配置記憶單元。因此 ，電容器電極7可以形成至另一方之位元線11之一部分 下方。 爲了形成本發明之上述記憶單元，對由1個電晶體’ 1個電容器構成，採上述相輔之位元線成對之平行延長之 返折位元線方式之習知之記憶單元，上述讀出用字線4或 P通道型之MO S F E T，可以與構成週邊電路之P通道 型之MO S F E T同一程序形成，因此，要新追加之圖型 係射極領域圖型8，而通常這是C Μ 0 S處理程序’可以 與高濃度Ν型擴散層圖型共用，實質上並不需要新的處理 程序。 第4圖表示本發明之半導體記憶電路之記憶單元部之 一實施例之截面構造圖。該圖表示有位元線方向之截面圖 。Ν型井領域2 1內形成有，以元件分離領域2 3加以分 離，由讀出用PMO S之閘極氧化膜2 5、讀出用字線 經濟部智慧財產局員工消費合作社印製I N P N bipolar transistor TR. The consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed the above-mentioned NP Ν transistor TR. The emitter is connected to the bit line BL, and the base is connected to the source-drain and collector of PM0SQ1. It is connected to the well area forming the above-mentioned PMOSQ1. The gate of the above-mentioned read PMO S Q 1 is connected to the read word line R W L; the other source-drain is connected to the storage node of the memory capacitor C s. Although there is no special limitation, the paper size of the gate electrode of the above-mentioned PM 0 SQ 1 for reading is applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm). Printed by the Employees ’Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 466744 A7 .___ B7 ___________ 5. Description of the invention (5) The edge film T ο X r is set to be the same thickness as or thinner than the gate insulating film T 0xw of the writing NMO SQ 2. A voltage v p 1 is supplied to the other electrode of the above-mentioned memory capacitor C s. The electrodes of the capacitor C s on the other hand are integrated with electrodes of other memory cells formed in the same memory array, and become a common electrode of a so-called plate. Fig. 2 is a graph showing the gate voltage and current characteristics of the write and read operation of the memory cell of the present invention. In the standby mode, the word line voltage V W W L is set to V s s, and the word line voltage for readout is set to Vcc. When writing data, if the voltage of the writing NMO S is assumed to be V th η, increase the writing word line voltage VWWL to V cc + V th η and make the writing NMO S In a conducting state, the bit line potential is transferred to the memory capacitor C s. When data is read, the voltage of the read word line is reduced from V cc to V ss, so that the P MOS transistor for reading becomes an ON state, and the storage capacitor C s stores the charge as the base current I. d ′ drives the bipolar transistor TR, whereby the collector current IBL (I d X hfe) amplified by the transistor TR charges the bit line to the power supply voltage V cc side. Fig. 3 is a layout diagram of an embodiment of a single-blank part of the semiconductor circuit 100B of the present invention. In this figure, 1 is the active area pattern that defines the component separation field, 2 is the N-type well pattern, and 3 is the N-type well pattern 2 reversal pattern. 4 series of word patterns for reading, 5 series of word lines for writing, 6 series of capacitor electrode connection hole patterns, and 7 series of capacitor electrode patterns. The pattern of the emitter field of the 8 series bipolar transistor, and the pattern of the 10-bit contact hole, this paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the back Please fill in this page again) Order! !! Line '4 6 67 44 a? ____B7_____ 5. Description of the invention (6) 1 1 is a bit line pattern. (Please read the precautions on the back before filling in this page) The figure shows the so-called retraced bit line method of extending a pair of bit lines 11 in parallel. Therefore, a memory cell is arranged at an intersection of one of the pair of bit lines and the writing word line 5 and the reading word line 4. Therefore, the capacitor electrode 7 can be formed below a portion of the bit line 11 on the other side. In order to form the above-mentioned memory unit of the present invention, for a conventional memory unit composed of one transistor 'and one capacitor and adopting the above-mentioned complementary bit line pairing and parallel extended retrace bit line method, the above readout The word line 4 or P-channel type MO SFET can be formed in the same procedure as the P-channel type MO SFET constituting the peripheral circuit. Therefore, the pattern to be newly added is the emitter region pattern 8, which is usually C Μ The 0 S processing program can be shared with a high-concentration N-type diffusion layer pattern, and essentially no new processing program is required. Fig. 4 is a cross-sectional structure diagram of an embodiment of a memory cell portion of a semiconductor memory circuit of the present invention. The figure shows a cross-sectional view with the bit line direction. Formed in the N-type well area 21, separated by the element separation area 23, and read out by the gate oxide film 2 of the PMO S for reading 5. The word line for reading is printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs

2 6，低濃度Ρ型源極•汲極領域2 8、高濃度ρ型擴散 層3 0、及高濃度Ν型射極領域3 1構成之讀出用 PMOS與ΝΡΝ雙極電晶體。Ρ型井領域2 2內則形成 有，以元件分離領域2 3加以分離，由寫入用N M〇S之 閘極氧化膜2 4、寫入字線1 2、低濃度Ν型源極•汲極 領域2 7、高濃度Ν型擴散層2 9構成之寫入用NMOS 本紙張尺度適用中國國家標準（CNS)A4規格（21Q χ 297公餐) 466744 Δ7 Α7 — _____ Β7 五、發明說明（7 ) 0 (請先閱讀背面之注意事項再填寫本頁) 上述寫入用NMO S及讀出用PMO S之一方之源極 •汲極，係經由連接插栓3 3連接在電容器電極3 4。在 此電容器電極3 4之表面領域配置電容器絕緣膜3 5、屏 極電極3 6，構成記憶電容器。形成在上述寫入用 NMO S之另一方之源極、汲極，與讀出用pm〇S之另 一方之源極、汲極內之射極領域，係經由連接插栓3 3連 接在位元線3 8。 在上述之本發明之記憶單元因爲是寫入動作與讀出動 作分別使用不同之字線1 2與2 6，因此寫入動作與傳統 之1個電晶體’ 1個電容器型之動態存取記憶體單元成爲 同樣之動作，可消除寫入速度劣化之問題。讀出動作則可 獲得與傳統之自行放大功能之記憶單元同樣之雙極電晶體 之放大效果。 經濟部智慧財產局員工消費合作社印製 藉上述之架構’則可以抑制製造程序之增加。亦即， 可以不必增加製造程序，便能夠消除傳統之附加寫入用高 電阻之具有自行放大功能之記憶單元複雜化之問題。換言 之’可以抑制如上述公報記載之記憶單元需增加形成寫入 用高電阻之特殊製造程序。因此，依據本發明時，可以提 供不會招致低電壓動作時成爲問題之寫入速度之劣化，能 抑制起因於構造之複雜性之記憶器特性之參差不一，不必 因此而增加製造程序之實用性之自行放大型之記憶單元。 第5圖〜第7圖表示，說明本發明之半導體記憶電路 之記憶單元之製造方法之第1〜第3圖製程之截面圖。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公ϋ A7 466744 ____B7_ 五、發明說明（8 ) 在第5圖所示之第1製程，係在p型半導體基板2 ◦ 上形成深度0 . 3 μ m之元件分離領域2 3 ，利用離子注 入法，以1 X 1 0 1 2 / c m 2之劑量注入加速能量3 5 ◦ KeV之B+離子，以2X1〇12/cm2之劑量注入加 速能量1 5 OK e V之B+離子及以5 X 1 012/cm2 之劑量注入Μ1速能量5 OKeV之BF2 +離子，形成P型 井2 2。 同樣利用離子注入法，以1 X 1 〇 1 2 / c m 2之劑量 注入加速能量5 0 0 K e V之P +離子，以2 x 1 0 12/ c m 2之劑量注入加速能量2 0 0 K e V之P +離子，及以 3x 1 0丨2/cm2之劑量注入加速能量50KeV之 BF2 +離子，形成N型井2 1 ，藉85(KC之熱氧化法成 長膜厚度7 nm之高耐壓系閘氧化瀨2 4，僅在形成 Vc c系電路用MO.SFET之領域，利用溫度850°C 之熱氧化法成長膜厚度4 n m之低耐壓系閘氧化膜2 5後 ，藉溫度6 0 0 °C之CVD法（化學氣相成長法： Chemical Vapar Deposition )堆積，藉離子注入法，以 4 X 1015/cm2之劑量注入加速能量1〇KeV之BF2+ 離子而成之膜厚度1 5 0 nm之多晶矽膜構成，形成普通 之藉石版印刷法加工之寫入字線2 6與讀出字線1 2。寫 入用MOSFET係以2 X 1 013/cm2之劑量注入加 速能量2〇KeV之B+離子，形成低濃度P型源極、汲 極領域28，讀出用MOSFET則以2x1 013/· c m 2之劑量注入加速能量4 0 K e V之p +離子，形成低 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝--------訂---------線· 經濟部智慧財產局員工消費 P作社印製 -ΤΓ- 466744 A7 B7 五、發明說明（9 ) 濃度N型源極、汲極領域2 7後’藉C V D法堆積’形成 利用回蝕刻法形成之膜厚度7 0 n m之氧化膜構成之側邊 隔膜3 9。在讀出用MOSFET以2xl015/cm2 之劑量注入加速能量4 0 K e V之A s +離子，形成高濃 度N型擴散層2 9後，僅在讀出用MO S F E T之之源極 側，以2 X 1 0 1 5 / c m 2之劑量注入加速能量2 0 K e V之B F 2 +離子，形成高濃度P型擴散層3 0後，以 僅雙極電晶體之射極領域開口之厚度1 之抗蝕膜4 0 爲掩蔽（mask )，以2xl015/cm2之劑量注入加速 能量4 0 K e V之A s +離子1 3，形成射極領域3 1。 在第6圖所示之第2製程，係形成由厚度6 0 0 nm 之氧化膜構成而平坦化之層間膜3 2，在所希望之領域藉 乾蝕刻開口，以C V D法堆積，進行回蝕刻，形成由埋設 之鎢構成之連接插栓3 3，而在對應以夾住元件分離領域 2 3狀形成之寫入用及讀出用MO S F E T之一方之源極 、汲極之連接插栓3 3上，加工膜厚度5 0 nm之N型多 晶矽膜之電容器電極3 4之狀態。 第7圖所示之第3製程，係在電容器電極3 4表面領 域堆積由有效膜厚度6 n m之氮化膜構成之電容器絕緣膜 3 5 ，再形成由膜厚度1 0 〇 nm之N型多晶矽膜構成之 屏極電極3 6後形成膜厚度1 〇 〇 〇 nm之氧化膜構成之 平坦化之層間膜3 7 _，在所希望之領域藉乾蝕刻開口位元 接觸孔，然後以C V D法堆積’進行回蝕刻’形成由埋設 之鎢構成之位元線3 8 ’完成如第4圖所示之記憶單元之 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閲讀背面之注意事項再填寫本頁) 裝·！ ---訂11 線 經濟部智慧財產局員工消費合作社印製 -12- 經濟部智慧財產局員工消費合作社印製 4 6 6744 A7 _ ___ B7 五、發明說明（10 ) 主要部分。 第8圖表示本發明之半導體記憶電路之其他一實施例 之記憶單元部之布置圖。在此實施例，P型基板上形成有 N型井8 2與P型井8 3。亦即，在記憶器陣列部，於P 型基板之整個面上形成上述P型井8 3，並在形成上述讀 出用MO S F E T與放大電晶體之部分選擇性形成N型井 8 2° 對讀出用字線8 4與寫入用字線8 5成直交狀形成位 元線9 1。此位元線9 1之配線寬度很寬，在配線寬度之 一方形成讀出用M〇S F E T及放大電晶體，另一方形成 寫入用MOSFET。亦即，上述讀出用MOSFET與 寫入用MO S F E T並非並排在位元線之延長方向之一直 線上，而是對其延長方向錯開配線寬度，且與對應之字線 成平行。 例如在圖示之位元線9 1 ，對橫方向之位元線延長方 向，於下側形成連接在讀出用Μ 0 S F E T之源極、汲極 之連接插栓8 8 ，及與位元線之接觸孔9 0。在此接觸孔 9 0之源極、汲極領域形成放大電晶體之射極。 讀出字線8 4在該圖向縱方向延長，以上述接觸插栓 8 8及接觸孔9 0爲中心，配置成左右對稱狀。其結果， 在位元線方向相鄰接之兩個記憶單元，上述讀出用 MOSFET之源極、汲極及連接插栓88，與接觸孔（ 放大電晶體之射極）9 0被共同化。對應讀出用 MOSFET之另一方源極、汲極之連接插栓86 ，係連 I ί ^—-------* I裝--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -13- 4 6 6744 A7 B7 五、發明說明（11 ) 接在記憶電容器之儲存節點之電容器電極8 7。 (請先閱讀背面之注意事項再填寫本頁) 以夾住上述兩讀出字線8 8狀，成左右對稱狀配置兩 條寫入字線8 5。對應此寫入字線8 5 ，在位元線9 1之 配線寬度上側形成寫入用Μ 0 S F E T。對應此寫入用 MOSFET之連接插栓86，係連接在寫入用 Μ 0 S F Ε Τ之源極、汲極與構成上述記憶電容器之儲存 節點之電容器電極87。而寫入用MOSFET之另一方 之源極、汲極係藉接觸孔9 0連接在位元線。 上述電容器電極8 7在讀出用字線8 4與寫入用字線 8 5上，於上述接觸孔9 0之部分有一部分重疊，在其外 部分則全部重疊。尤其是，對其對應鄰接記憶單元之讀出 字線，則因其間隔稍寬以增加形成上述放大電晶體之部分 ，因此超越讀出字線8 4形成之。 經濟部智慧財產局員工消費合作社印製 在相鄰接位元線，與上述成鏡面反轉形態配置讀出用 MOSFET (放大電晶體）與寫入用MOSFET。亦 即，配置在標示上述記號之位元線上側之位元線，其寫入 用M〇 S FET配置在下側，讀出用MO S F ET配置在 上側。以下，返覆與上述同樣範式，對應位元線配置上述 讀出用MOSFET (放大電晶體）與寫入用 MOSFET。 同樣地，在鄰接字線，若以寫入字線8 5爲中心視之 ，也是以鏡面反轉之形態配置讀出字線與寫入字線。以記 憶單元之放大電晶體之射極（接觸孔9 0 )爲基準，則在 內側配置讀出字線8 4，在外側配置寫入字線8 5。 本紙張尺度適用中國國家標準(CNS)A4規格（210 X 297公釐) _ Ί4 - *46 6744 at B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（12 ) 在上述之位元線之配置，係在相鄰位元線每隔1條共 同化形成N型井8 2與P型井8 3。在這種架構，N型井 8 2與P型井8 3間之分離領域所佔之比例變小，可以有 高度之積體化。 在本實施例，上述N型井8 2除了單純形成讀出用 MO S F E T用之元件形成領域外，另具有放大電晶體之 集極領域之作用。亦即，集極具有將電流被放大之讀出電 流供給位元線之電源線之作用。本實施例係與位元線9 1 成平行方式形成N型井8 2。亦即，1個讀出字線被選擇 時，可在各位元線流通上述被選捧之記憶單元之放大電流 。這時因爲如上述，平行配置有位元線9 1與N型井8 2 ，因此，1個N型井8 2因爲如上述與鄰接位元線共同化 ，因此另要流通對應兩個記憶單元之放大電流即可。因之 ，縱使向N型井8 2供應電源電壓V c c之接觸孔數較少 ，仍可使電源阻抗降低。 換言之，與字線平行延長形成N型井時，必須由上述 1個N型井供應對應連接在1條字線之多數記憶單元之放 大電流，因而有，必須加粗電源配線，或配設多數接觸孔 之問題。 第9圖表示本發明之半導體記憶電路之記憶單元部之 一實施例之電路圖。本實施例之電路對應上述第8圖所示 之布置。 本實施例之記憶器陣列係採，記憶單元配置在字線 R W L ; w W L與位元線B L之各交點之所謂1交點方式 (請先閱讀背面之注意事項再填寫本頁) 裝 ϋ ----訂---------線 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） A7 466744 -------B7___ 五、發明說明（13 ) °這種1交點方式因爲可以將記憶單元配置在字線與位元 線之各交點，因此能夠高積體化。在位元線B L，鄰接記 憶單元之放大電晶體被共同化。亦即，如上述第8圖，夾 著鄰接記憶單元之讀出字線，形成讀出用MO S F E T之 源極、汲極，及放大電晶體之射極，藉此如該圖之電路圖 所示，放大電晶體可由兩個記憶單元之共用。因此，較之 1個電晶體，1個電容器之記憶單元，在面積上只是追加 1個寫入用之M〇S F E T，則可形成。 第1 0圖表示本發明之半導體記億電路之直接周邊電 路之一實施例之電路圖。在該圖表示，字線之選擇電路及 形成基準電壓之虛擬單元，位元線預充電電路及感測放大 器之具體電路圖。 在位元線B L與虛擬寫入字線D W W L及虛擬讀出字 線D R W L之交點形成虛擬單元。虛擬單元之記憶電容器 其面積爲記憶單元之1 / 2。亦即，記憶單元之電容器之 電容値爲C s時，虛擬單元之電容器之電容値爲C s/2 〇 本實施例係在該圖，以感測放大器爲中心，將相輔之 位元線B L與/B L向左右延伸構成之。本架構係屬於， 在字線與各位元線之各交點分別形成1個記憶單元之上述 1交點方式。 其讀出動作，係以感測放大器爲中心，選擇對應左側 之位元線B L之1條讀出用字線R W L時，則選擇右側之 虛擬讀出字線D R W L。藉此，以讀出到右側之位元線之 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ~ 1ϋ ' ' (請先閱讀背面之注意事項再填寫本頁) 裝！ 訂----I--線 經濟部智慧財產局員工消費合作社印製 466744 A7 ____B7___;_ 五、發明說明（14 ) (請先閱讀背面之注意事項再填寫本頁) 虛擬單元之信號當作基準電壓，供給讀出到左側之位元線 B L之讀出信號，而辨別其高位準/低位準。反之’以感 測放大器爲中心，選擇對應右側之位元線/ B L之1條讀 出用位元線R W L時，則選擇左側之虛擬讀出字線 D R W L。藉此，以讀出到左側之位元線之虛擬單元之信 號當作基準電壓，供給讀出到右側之位元線/ B L之讀出 信號，而辨別其高位準/低位準。 感測放大器係將P通道型MO S F E T及N通道型 M〇S F E T構成之兩個CMO S反相器電路之輸入與輸 出交叉連接而成。本實施例之感測放大器省略傳統之1個 電晶體，1個電容器構成之動態存取記億體之感測放大器 之電力開關MOSFET。亦即，構成CMOS反相器電 路之N通道型MO S F E T之源極恆常供應有電路之接地 電位Vs s ，在P通道型MOSFET之源極則供應有， 對應電源電壓V c c之高位準之定時信號S A，作爲感測 放大器之活性化定時。 經濟部智慧財產局員工消費合作社印製 在對應上述相輔之位元線B L與/ B L之感測放大器 之一對輸入輸出節點設有預充電電路。預充電電路係由， 向上述各位元線B L與/ B L供應接地電位V s s之 Μ〇S F E T，以及，短路上述兩位元線B L與/ B L之 短路MO S F Ε Τ所構成。 字線選擇電路係藉選擇定時信號/WWL Ε、 /RWLE及WWLE、 RWLE，使X解碼器所形成之 選擇信號成爲以上所說明之組合，以進行字線W W L、 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） "' ' 經濟部智慧財產局員工消費合作社印製 466744 Α7 _ Β7 五、發明說明（15 ) RWL及虛擬字線DWWL、 DRWL之選擇動作°以上 可由以下之動作說明很容易獲得瞭解。 第1 1圖表示本發明之半導體記憶電路之動作之—個 例子用之波形圖。 在預充電信號P C呈高位準時，位元線.B L預充電成 低位準。上述預充電信號P C成爲低位準後，讀出用字線 選擇信號RWL E成爲高位準。/RWL E成爲低位準。 對應此，由X解碼器形成之選擇信號，以感測放大器爲中 心選擇一方之讀出用字線RWL，選擇未圖不之另一方之 讀出用虛擬字線D R W L。 藉此，對應選擇字線之位元線B L (或/ B L )在所 選擇之電容器無資訊電荷時成爲低位準0 〃 ），在電 容器儲存資訊電荷時，與此對應讀出高位準1 〃 ）。 在對應虛擬字線之位元線/ B L (或B L )輸出，對應從 虛擬單元向上述電容器儲存資訊電荷時之1 / 2之基準電 壓。對應如此之高位準之1/2之基準電壓，與上述高位 準或低位準之電位差，係由上述放大電晶體加以放大，因 此其電位差比較大。 因之，由於使感測放大器活性化之定時信號S A成爲 高位準，上述C Μ ◦ S閂鎖電路將使位元線B L與/ B L 之電位差擴大成爲如放大之V c c之高位準與V s s之低 位準。 . 如上述，在感測放大器被活性化之狀態下，定時信號 /WWL Ε成爲低位準，定時信號WWL Ε成爲高位準， 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -1¾ - I I Γ---!!L 裝！ — 訂·! ----線 1 (請先閲讀背面之注意事項再填寫本頁) 466744 A7 B7 五、發明說明（16 ) 寫入用之字線WWL成爲如V ρ p (V c c + V t h η ) 之昇壓電壓。藉此，由感測放大器放大之位元線B L (或 (請先閱讀背面之注意事項再填寫本頁)26. Low-concentration P-type source / drain region 2 8. High-concentration ρ-type diffusion layer 30 and high-concentration N-type emitter region 31 are read-out PMOS and NPN bipolar transistors. Formed in the P-type well area 2 2 and separated in the element separation area 2 3 by the gate oxide film 2 of the writing NMOS, and the writing word line 1 2. The low-concentration N-type source · sink Polar field 2 7. High-concentration N-type diffusion layer 29. NMOS for writing. This paper size applies the Chinese National Standard (CNS) A4 specification (21Q χ 297 meals) 466744 Δ7 Α7 — _____ Β7 V. Description of the invention (7 ) 0 (Please read the precautions on the back before filling this page.) The source and drain of one of the above-mentioned writing NMO S and reading PMO S are connected to the capacitor electrode 3 4 through the connection plug 3 3. A capacitor insulating film 35 and a screen electrode 36 are arranged on the surface area of the capacitor electrode 34 to form a memory capacitor. Formed in the field of the source and drain of the other NMO S for writing, and the source and drain of the other pm 0S for read and the emitter in the drain are connected in place via the connection plug 3 3 Yuan line 3 8. In the above-mentioned memory cell of the present invention, since the writing operation and the reading operation use different word lines 1 2 and 2 6 respectively, the writing operation and the conventional one transistor '1 capacitor type dynamic access memory The bulk unit operates in the same manner, which eliminates the problem of degradation in writing speed. The reading action can obtain the same amplification effect of the bipolar transistor as the conventional memory cell with the self-amplification function. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs By using the above-mentioned structure ', the increase in manufacturing processes can be suppressed. That is, it is possible to eliminate the problem of complication of a memory cell having a self-amplification function with a conventional high resistance for additional writing without adding a manufacturing process. In other words, it is possible to suppress the need for a special manufacturing process for the memory cell described in the above-mentioned publication to form a high resistance for writing. Therefore, according to the present invention, it is possible to provide a deterioration in writing speed that does not cause a problem during low-voltage operation, and to suppress variations in the characteristics of the memory due to the complexity of the structure without increasing the practicality of the manufacturing process. Sexual self-amplifying memory unit. Figures 5 to 7 show cross-sectional views of the manufacturing process of Figures 1 to 3, illustrating the method of manufacturing the memory cell of the semiconductor memory circuit of the present invention. This paper size is in accordance with Chinese National Standard (CNS) A4 specification (210 X 297 public ϋ A7 466744 ____B7_ V. Description of the invention (8) The first process shown in Figure 5 is formed on the p-type semiconductor substrate 2 ◦ 0.3 μm element separation area 2 3, using ion implantation method to implant acceleration energy at a dose of 1 X 1 0 1 2 / cm 2 3 5 ◦ KeV's B + ions, implantation acceleration at a dose of 2 × 10 12 / cm 2 B + ions of energy 1 5 OK e V and BF2 + ions of energy 5 OKeV are implanted at a dose of 5 X 1 012 / cm2 to form a P-type well 2 2. Also using the ion implantation method, 1 X 1 〇1 2 / cm 2 is implanted with P + ions of acceleration energy of 50 0 K e V, 2 x 1 0 12 / cm 2 is implanted with P + ions of acceleration energy of 2 0 0 K e V, and 3x 1 0 丨A dose of 2 / cm2 is implanted with BF2 + + ions with an acceleration energy of 50KeV to form an N-type well 2 1. A 85 ° K thermal oxidation method is used to grow a high-pressure-resistant gate oxide sesame 2 4 with a film thickness of 7 nm. In the field of MO.SFETs for circuit use, the thermal oxidation method at a temperature of 850 ° C is used to grow a low-withstand voltage gate oxide film with a thickness of 4 nm, and then the CVD method is used at a temperature of 60 ° C. Chemical vapor growth method: Chemical Vapar Deposition), a polycrystalline silicon film with a film thickness of 150 nm formed by implanting BF2 + ions with an acceleration energy of 10 KeV at a dose of 4 X 1015 / cm2 by ion implantation, forming a common The writing word line 26 and the reading word line 12 processed by the lithographic printing method. The writing MOSFET is implanted with B + ions having an acceleration energy of 20 KeV at a dose of 2 X 1 013 / cm2 to form a low-concentration P-type. The source and drain areas are 28, and the read-out MOSFET is implanted with p + ions of 40 K e V at an accelerating energy of 2 × 1 013 / · cm 2 to form a low paper size that applies the Chinese National Standard (CNS) A4 specification ( 210 X 297 mm) (Please read the precautions on the back before filling out this page) Packing -------- Order --------- Line · Consumers ’Consumption of Intellectual Property Bureau of the Ministry of Economic Affairs Printed-ΤΓ- 466744 A7 B7 V. Description of the invention (9) Concentration N-type source and drain area 2 7 After 'stacked by CVD method', an oxide film with a film thickness of 70 nm formed by the etch back method is formed Side diaphragm 39. A s + ion of 40 K e V is injected into the readout MOSFET at a dose of 2 × 1015 / cm2 to form After the concentration of the N-type diffusion layer 29, only the source side of the read-out MO SFET was implanted with BF 2 + ions at an acceleration energy of 20 K e V at a dose of 2 X 1 0 1 5 / cm 2 to form a high After the concentration of the P-type diffusion layer 30, a resist film 40 having a thickness of only 1 opened in the emitter region of the bipolar transistor is used as a mask, and an acceleration energy of 40 K e V is injected at a dose of 2xl015 / cm2. A s + ions 1 3 form the emitter region 3 1. In the second process shown in FIG. 6, an interlayer film 32 is formed and flattened by an oxide film having a thickness of 600 nm. Dry etching openings are deposited in a desired area by CVD to deposit and etch back. , Forming a connection plug 3 made of buried tungsten, and a connection plug 3 of a source and a drain corresponding to one of the writing and reading MO SFETs formed in a shape that sandwiches the element separation area 2 3 3, the state of processing the capacitor electrode 34 of the N-type polycrystalline silicon film with a film thickness of 50 nm. The third process shown in FIG. 7 is to deposit a capacitor insulating film 35 made of a nitride film with an effective film thickness of 6 nm on the surface area of the capacitor electrode 34, and then form an N-type polycrystalline silicon with a film thickness of 100 nm. After forming the screen electrode 36 of the film, a flat interlayer film 3 7 _ formed of an oxide film having a film thickness of 1000 nm is formed, and the open bit contact holes are dry-etched in a desired area, and then stacked by a CVD method. 'Etching back' to form bit lines made of buried tungsten 3 8 'Complete the paper size of the memory cell shown in Figure 4 to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (please (Please read the precautions on the back before filling out this page) --- Order No. 11 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs -12- Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 6 6744 A7 _ ___ B7 5. Description of the invention (10) The main part. Fig. 8 is a layout diagram of a memory cell section of another embodiment of the semiconductor memory circuit of the present invention. In this embodiment, an N-type well 82 and a P-type well 83 are formed on the P-type substrate. That is, in the memory array section, the P-type wells 8 3 are formed on the entire surface of the P-type substrate, and the N-type wells 8 2 ° are selectively formed in the portion where the read-out MO SFET and the amplifying transistor are formed. The word line 84 for reading and the word line 85 for writing form a bit line 91 at right angles. The bit line 91 has a wide wiring width, and one of the wiring widths forms a read MOSFET and an amplification transistor, and the other forms a write MOSFET. That is, the read MOSFET and the write MOSFET are not placed side by side on the line extending in the bit line, but the line width is shifted from the extending direction and parallel to the corresponding zigzag line. For example, in the bit line 9 1 shown in the figure, the bit line extending in the horizontal direction is extended to form a connection plug 8 8 connected to the source and drain of the readout M 0 SFET on the lower side, and the bit Line of contact holes 9 0. An emitter of an amplifying transistor is formed in the source and drain regions of the contact hole 90. The read word line 84 is extended in the figure in the vertical direction, and is arranged symmetrically about the contact plug 88 and the contact hole 90 as the center. As a result, the two memory cells adjacent to each other in the direction of the bit line, the source, the drain, and the connection plug 88 of the above-mentioned read-out MOSFET are shared with the contact hole (the emitter of the amplifier transistor) 90. . Corresponding to the other source and drain connection plug 86 of the read-out MOSFET, I ^ ------------ * I installed -------- order ------ --- Line (please read the notes on the back before filling this page) This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) -13- 4 6 6744 A7 B7 V. Description of the invention (11 ) Capacitor electrode 87 connected to the storage node of the memory capacitor. (Please read the precautions on the back before filling in this page.) Hold the two read word lines 8 8 above, and arrange two write word lines 8 5 in a left-right symmetrical shape. Corresponding to the writing word line 8 5, a writing M 0 S F E T is formed on the upper side of the wiring width of the bit line 9 1. The connection plug 86 corresponding to the writing MOSFET is connected to the source, the drain and the capacitor electrode 87 constituting the storage node of the memory capacitor as described above. On the other hand, the source and the drain of the write MOSFET are connected to the bit line through a contact hole 90. The capacitor electrode 87 is partially overlapped on the contact word 90 on the word line 84 for reading and the word line 85 for writing, and is entirely overlapped on the outer part. In particular, the read word lines corresponding to the adjacent memory cells are formed slightly beyond the read word line 84 because the interval is slightly wider to increase the portion forming the amplifying transistor described above. Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Adjacent bit lines are arranged in a mirror-inverted configuration with the above-mentioned MOSFET (amplifying transistor) and MOSFET for writing. That is, the bit line arranged on the bit line on which the above-mentioned symbol is marked has a writing MOS FET arranged on the lower side and a reading MOS F ET arranged on the upper side. In the following, the same paradigm as the above is repeated, and the read MOSFET (amplifier transistor) and the write MOSFET are arranged corresponding to the bit lines. Similarly, when the adjacent word line is viewed with the writing word line 85 as the center, the reading word line and the writing word line are arranged in a mirror-inverted manner. Based on the emitter (contact hole 90) of the amplifying transistor of the memory cell, a read word line 8 4 is arranged on the inside and a write word line 85 is arranged on the outside. This paper size applies to China National Standard (CNS) A4 specifications (210 X 297 mm) _ Ί4-* 46 6744 at B7 Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (12) The configuration is based on the formation of N-type wells 8 2 and P-type wells 3 at every other bit line. In this structure, the proportion of the separation area between N-type wells 8 2 and P-type wells 8 3 becomes smaller, which can be highly integrated. In this embodiment, in addition to simply forming the element formation field for read-out MO S F E T for the N-type well 82, the above-mentioned N-type well 82 also functions as a collector field for amplifying a transistor. That is, the collector has the function of supplying the amplified read current to the power line of the bit line. In this embodiment, an N-shaped well 8 2 is formed in parallel with the bit line 9 1. That is, when one read word line is selected, the amplified current of the selected memory cell can be circulated in each element line. At this time, as described above, the bit line 91 and the N-type well 8 2 are arranged in parallel. Therefore, one N-type well 8 2 is common with the adjacent bit line as described above, so another one corresponding to the two memory cells needs to be circulated. Just amplify the current. Therefore, even if the number of contact holes for supplying the power source voltage V c c to the N-type well 8 2 is small, the power source impedance can still be reduced. In other words, when an N-type well is formed to extend in parallel with the word line, the amplified current corresponding to the majority of the memory cells connected to one word line must be supplied from the above-mentioned one N-type well. Problems with contact holes. Fig. 9 is a circuit diagram showing an embodiment of a memory cell portion of a semiconductor memory circuit of the present invention. The circuit of this embodiment corresponds to the arrangement shown in Fig. 8 above. The memory array of this embodiment is adopted, and the memory cells are arranged on the word line RWL; the so-called 1 intersection method of each intersection of WL and bit line BL (please read the precautions on the back before filling this page) Decoration- --Order --------- The size of the paper is applicable to China National Standard (CNS) A4 (210 X 297 mm) A7 466744 ------- B7___ V. Description of the invention (13) ° In this one-intersection method, since the memory cells can be arranged at the intersections of the word line and the bit line, it can be highly integrated. At bit line BL, the amplifying transistors adjacent to the memory cells are commonized. That is, as shown in FIG. 8 above, a source word, a drain electrode of the read-out MO SFET, and an emitter electrode of the amplification transistor are formed by sandwiching the read word line adjacent to the memory cell, thereby showing the circuit diagram of the figure. The amplification transistor can be shared by two memory cells. Therefore, compared to a transistor and a capacitor, a memory cell can be formed by adding only one MOS F E T for writing. Fig. 10 is a circuit diagram showing an embodiment of a direct peripheral circuit of the semiconductor billion circuit of the present invention. The figure shows the specific circuit diagram of the word line selection circuit and the virtual unit forming the reference voltage, the bit line pre-charging circuit, and the sense amplifier. A virtual cell is formed at the intersection of the bit line B L with the dummy write word line D W W L and the dummy read word line D R W L. The memory capacitor of the virtual unit has an area of 1/2 of the memory unit. That is, when the capacitance 记忆 of the capacitor of the memory unit is C s, the capacitance 电容器 of the capacitor of the virtual unit is C s / 2. This embodiment is based on the figure, and the complementary bit line is centered on the sense amplifier. BL and / BL are formed by extending left and right. This architecture belongs to the above-mentioned 1 intersection method in which a memory cell is formed at each intersection of a word line and each element line. The read operation is based on the sense amplifier, and when one read word line R W L corresponding to the bit line B L on the left is selected, the right read word line D R W L is selected. With this, the paper size read to the bit line to the right applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ~ 1ϋ '' (Please read the precautions on the back before filling this page). !! Order ---- I--Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 466744 A7 ____ B7 ___; _ 5. Description of the invention (14) (Please read the precautions on the back before filling this page) The signal of the virtual unit is treated as The reference voltage is supplied to a read signal read to the bit line BL on the left, and the high level / low level is discriminated. On the other hand, when the sense amplifier is used as the center, and one bit line R W L corresponding to the bit line on the right side / BL is selected, the virtual word line D R W L on the left side is selected. Thereby, the signal of the virtual cell read to the bit line on the left is used as a reference voltage, and the read signal read to the bit line / BL on the right is supplied to discriminate its high level / low level. The sense amplifier is formed by cross-connecting the input and output of two CMO S inverter circuits composed of a P-channel MO S F E T and an N-channel MO S F E T. The sense amplifier of this embodiment omits the conventional one transistor, and one capacitor is a dynamic switching MOSFET of a sense amplifier with a memory capacity. That is, the source of the N-channel type MO SFET constituting the CMOS inverter circuit is always supplied with the ground potential Vs s of the circuit, and the source of the P-channel type MOSFET is supplied, corresponding to the high level of the power supply voltage V cc The timing signal SA is used as the activation timing of the sense amplifier. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. One of the sense amplifiers corresponding to the above complementary bit lines B L and / B L is provided with a pre-charge circuit for the input and output nodes. The pre-charging circuit is composed of MOS F E T that supplies the ground potential V s s to each of the element lines B L and / B L and a short circuit MO S F Ε T that short-circuits the two-bit element lines B L and / B L. The word line selection circuit uses the selection timing signals / WWL Ε, / RWLE and WWLE, RWLE to make the selection signals formed by the X decoder into the combinations described above for word line WWL. CNS) A4 specification (210 X 297 mm) " '' Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives 466744 Α7 _ Β7 V. Description of the invention (15) RWL and virtual word line DWWL, DRWL selection above ° The following action descriptions are easy to understand. Fig. 11 is a waveform diagram showing an example of the operation of the semiconductor memory circuit of the present invention. When the precharge signal PC is at a high level, the bit line .BL is precharged to a low level. After the precharge signal PC is set to the low level, the read word line selection signal RWL E is set to the high level. / RWL E goes low. In response to this, the selection signal formed by the X decoder selects one of the read word lines RWL with the sense amplifier as the center, and selects the other read word line D R W L not shown in the figure. Therefore, the bit line BL (or / BL) corresponding to the selected word line becomes the low level 0 0 when the selected capacitor has no information charge, and when the capacitor stores the information charge, the corresponding read high level 1 〃) . The bit line / B L (or B L) output corresponding to the virtual word line corresponds to a reference voltage of 1/2 when the information charge is stored from the virtual unit to the capacitor. The potential difference between the reference voltage corresponding to 1/2 of such a high level and the above-mentioned high or low level is amplified by the above-mentioned amplifying transistor, so the potential difference is relatively large. Therefore, because the timing signal SA that activates the sense amplifier becomes a high level, the above-mentioned C M ◦ S latch circuit will expand the potential difference between the bit lines BL and / BL to a high level such as the amplified V cc and V ss Low level. As mentioned above, when the sense amplifier is activated, the timing signal / WWL Ε becomes a low level, and the timing signal WWL Ε becomes a high level. This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm). ) -1¾-II Γ --- !! L installed! — Order ·! ---- Line 1 (Please read the notes on the back before filling this page) 466744 A7 B7 V. Description of the invention (16) The WWL for writing becomes V ρ p (V cc + V th η). With this, the bit line B L amplified by the sense amplifier (or (please read the precautions on the back before filling this page)

/BL)之高位準（V c c )或低位準使經由寫入用之N 通道型MOSFET，再度寫入記憶電容器C s。在上述 位元線B L以高位準寫入時，因字線W W L之選擇位準較 電源電壓V c c爲高，因此傳至電容器C s時沒有損耗。 在未圖示之寫入動作，也會爲更新動作而選擇上述讀 出字線R W L，將感測放大器活性化。在此狀態下，將寫 入資料經由行開關寫入選擇之位元線。由於輸入這種寫入 資料，閂鎖架構之感測放大器若輸入與上述原來記憶狀態 相反位準之寫入資料，其記憶狀態會反轉。然後選擇寫入 用字線W W L，將連接於此之多數記憶單元，一起寫入上 述寫入資料與感測放大器所放大之角度寫入信號。 更新模式與上述讀出動作相同。惟，讀出模式係由未 圖示之行選擇電路選擇位元線，通過主放大器將讀出信號 讀出到記憶電路之外部。而更新模式則省略上述行選擇動 作，僅進行連接在字線之記憶單元之角度寫入。 第1 2圖表示本發明之半導體記憶電路之角一其他實 經濟部智慧財產局員工消費合作社印製 施例之記憶單元部之布置圖。本實施例係在位元線方向將 讀出用M〇S F E T與寫入用MO S F E T配置在一直線 _) 上。 亦即，在N型井1 〇 2形成對應記憶單元之讀出用 M〇 S F E T與放大電晶體。在對應兩個記憶單元之讀出 用MOSFET之共同化之一方之源極、汲極108，配 -iy - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 466744 A7 B7 五、發明說明（17 ) 設連接插栓1 1 0 ’接觸孔1 0 9 ，而以此爲中心，形成 對應上述兩個記憶單元之讀出用字線1 〇 4。讀出用 Μ 0 S F E T之另一方之源極，汲極係經由接觸孔1 〇 6 ，連接在電容器電極1 0 7。 在Ρ型井1 0 3形成寫入用之Ν通道型MO S F Ε Τ 。寫入用Μ 0 S F Ε Τ也是以不同於上述之鄰接記憶單元 之共同化之源極，汲極爲中心，形成對應兩個記憶單元之 寫入用字線1 0 5。在此共同化之源極，汲極形成接觸孔 1 1 0，而連接在位元線1 1 1。上述讀入用 MO S F Ε Τ之另一方之源極，汲極係經由接觸孔1 〇 6 ，連接在電容器電極1 0 7。 本實施例因爲是在位元線方向將兩個MO S F Ε Τ排 列配置在一直線上，因此可以縮小位元線寬度。字線之返 覆範式與上述實施例一樣，說明從略。 第1 3圖表示應用本發明之系統L S I之一實施例之 整體電路方塊圖。本實施例之半導體積體電路裝置 CH I Ρ含有，如圖示之多數電路方塊，即含有輸入輸出 電路1/0、基板偏壓控制電路VBBC、控制電路 ULC、唯讀記憶器ROM、D/A變換器DAC、Α/ D變換器ADC、***控制電路IVC、有時鐘脈衝產生 電路CGC之系統電力管理電路SPMC、中央處理部 C P U、靜態型記憶器s R A Μ、直接記憶存取控制器直 接記憶存取、動態型記憶器動態存取記憶體。 此等電路方塊係結合在內部匯流排B u s、控制匯流 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝 ----訂---------線 經濟部智慧財產局員工消費合作社印製 '-20- 466744 五、發明說明（18 ) 排C B U S。該等係搭載於應構成半導體積體電路裝置之 示圖示之半導體基板。上述系統電力管理電路S PMC具 (請先閲讀背面之注意事項再填寫本頁) 有，控制搭載於系統L S I之各模組所消耗之電力之機能 〇 半導體積體電路裝置具備有，連在輸入輸出電路I / ◦之輸入輸出外部端子T i ο 1至T i ο η，供給如負邏 輯位準之復置信號ν e s b之外部端子Τ 1 ，控制用外部 端子T 2 ，供給第1動作控制信號c m q之第1動作控制 用外部端子T 3 ，供給第2動作控制信號c p m q之第2 動作控制用外部端子T 4，供給外部時脈信號c 1 k之時 脈用外部端子T 5 ，以及，供給多數電源電壓（v d d、 VCcdr、 vsS)之多數電源用外部端子T6、 丁7 、Τ 8。 經濟部智慧財產局員工消費合作社印製 雖無特別限制，但電源電壓v d d係供內部電路方塊 之動作用之電源電壓，取1 . 8伏特± 0 . 1 5伏特之値 。電源電壓V c c d r係依半導體積體電路裝置所要求之 輸入輸出位準，主要爲輸入輸出電路I /O所設定之電源 電壓，取3.3伏特±0.3伏特、2.5伏特 ±0 . 2 5伏特及1 . 8伏特±0 . 1 5伏特之値中之一 個値。電位v s s係所謂接地電位之電路之基準電位。 圖示之半導體積體電路裝置構成A S I C ( application Specified Integrated Circuits )，即特定用途 I C 。亦良P， 圖示之大多數電路方塊分別成爲獨立電路功能單位之模組 或大單元，俾能容易達成A S I C架構。各功能單位之規 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ^466744 A7 ___ B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（19 ) 模’架構均可變更。A S I C可以將圖示之電路方塊內之 應實現之電子系統所不需要之電路方塊，避免搭載在半導 體基板上。反之，也可以追加未圖示之功能單位之電路方 塊。 中央處理部C P U未特別限制，但其架構與所謂微處 理器相同。亦即，中央處理部C P U在其內部具備命令暫 存器，將寫入命令暫存器之命令解碼，形成各種微命令或 控制信號之微命令ROM，運算電路，萬用暫存器（ R G 6等），結合於內部匯流排B U S之匯流排驅動器， 以及，匯流排接收器等之輸入輸出電路。 中央處理部C P U讀出儲存在唯讀記億器R Ο Μ等之 命令，進行對應該命令之動作。中央處理裝置C P U將取 進經由輸入輸出電路I / 0輸入之外部資料，對控制電路 UL C輸入輸出資料，讀出從唯讀記憶器之命令或執行命 令所需要之如固定資料之資料，向D/A變換器D A C供 應需D/A變換之資料，讀出由A/D變換器加以A/D 變換之資料，向靜態型記憶器S R A Μ ’動態型記憶器動 態存取記憶體之資料之讀出、寫入，D Α Μ控制器直接記 憶存取C之動作控制等。 ***控制電路I v c在外部端子了 1接受如負邏輯位 準之復置信號，經由外部端子τ 3接受第1動作信號 c m q，經由外部端子Τ 4接受第2控制信號c p m q ’ 並在外部端子T 2輸出指示半導體積體電路裝置之動作狀 態之狀態指示信號。***控制電路I v c備有’對應此等 (請先閱讀背面之注意事項再填寫本頁) 裝 n i I I I — 訂.— ！ I I 1 . 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公髮） >Μ6 6744 Α7 —— Β7 經濟部智慧財產局員工消費合作杜印製 五、發明說明（20 ) 復置信號r e s b，動作控制信號c m Q、c p m q及狀 態指示信號，分別設定其位置之位元之暫存器R G 5。 雖未特別限制，但***控制電路I V C在其內部備有 ’動態型記憶器之更新動作用之未圖示之更新位址計數器 。***控制電路I V C之這種更新位址計數器，若由第1 、第2動作控制信號c m q、 c p m Q指定一定之模式時 ，即，指示對半導體積體電路裝置是動作模式，或動作待 機模式時，則依據時脈產生電路C G C之系統時脈信號步 進，形成週期性更新之動態存取記憶體之更新位址資訊。 輸入輸出電路I/O接受經由外部端子T i ο 1至 T i ο η內之所希望之外部端子由外部供給之信號，並經 由內部匯流排B U S接受並輸出到外部端子T i ο 1至 T i ο η內所希望之端子之信號。輸入輸出電路I / ◦在 其內部分別備有，由C Μ 0 S靜態電路構成之控制暫存器 RG4及未圖示之資料暫存器。 控制暫存器RG4，由中央處理部CPU所選擇，且 由中央處理部C P U供給該輸入輸出電路I / ◦用之控制 資料，例如資料輸入/輸出指示，或高輸出阻抗狀態指示 等之控制資料。資料暫存器被利用在外部端子T i ο 1至 T i ο η，與內部匯流排B U S之間轉送資料。輸入輸出 電路I /0之輸入信號用電路及輸出信號用電路’其輸入 及輸出動作由系統時脈信號所控制。因之，輸入輸出電路 I / 0在無法供應系統時脈信號時，與上述中央處理部 C P U —樣，成爲低電力消耗狀態。 (請先閱讀背面之注意事項再填寫本頁) .裝 ----:訂----- 線 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 4 6 6744 Α7 Β7 五、發明說明（21 ) 控制電路U L C係依電子系統之需要而適宜配設之控 制電路。此控制電路ϋ L C係依例如硬碟裝置之馬達伺服 控制、磁頭之追蹤控制、錯誤更正處理、或影像、語音處 理之影像或語音資料之壓縮伸長處理等，視應實現之電子 系統適宜配設之。控制電路U L C與中央處理部C P U — 樣，其動作由系統時脈信號加以控制。 唯讀記憶器R ◦ Μ係如上述，記憶由中央處理裝置 C P U讀出之應執行之命令，固定資料。 D/A變換器DA C具備有，用以接受經由內部匯流 排B U S供給之應變換成類比信號之數位信號之暫存器 R G 2，而依據此項數位資料形成類比信號。暫存器 RG 2由控制電路UL C或中央處理部C PU定置數位資 料。由D / Α變換器D A C形成之類比信號係經由內部匯 流排B U S及輸入輸出電路I / ◦，供給外部端子τ 1〜 Τ η中所希望之端子，但不特別限制。 A/D變換器AD C接受經由外部端子Τ 1至Τ η中 之所希望之端子與輸入輸出電路I/0及內部匯流排 B U S供給之類比信號，由控制電路u L C或中央處理部 C P U控制其A / D變換之開始，在依循系統時脈信號 C 2之時脈控制下，將上述類比信號變換成數位信號，將 獲得之數位信號定置在暫存器RG1。 靜態型記憶器S R A Μ，其記憶單元之詳情未圖示， 但具備有C 0 M S靜態型記憶單元，亦即，具備有由 C Μ 0 S閂鎖電路及對此之資料輸入輸出用之一對 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） Γ2Τ^ ------------裝！ —訂 i I------線 (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作杜印製 《466744 A7 B7 五、發明說明（22 ) Μ 0 S F E T所構成之記憶單元。C Μ 0 S靜態型記憶單 元之特徵是，以靜態方式保持資訊，且保持資訊僅需非常 小之動作電流。 直接記憶存取控制器.，亦即，Direct Memory Access Controller —直接記憶存取由中央處理部C P U控制其動作 ，並取代中央處理部C P U控制由中央處理部C P U所指 示之經由電路方塊間之內部匯流排B U S之資料轉送。 動態型記憶器動態存取記憶體之記憶單元，即動態型 記憶單元由儲存具有以上說明之電荷形態之資訊之資訊儲 存用電容器，及選擇用之讀出用MOSFET、放大電晶 體及寫入用MO S F E T所成之少數元件構成，可形成爲 較小之記憶單元尺寸。因此，動態型記憶器之記憶容量較 大時，其整體尺寸也可以較小。茲說明此動態型記憶器動 態存取記憶體如下。 第1 4圖表示應用本發明之半導體積體電路裝置所搭 .載之動態型記憶器（以下簡稱爲動態存取記憶體）之一實 施例之方塊圖。此動態存取記憶體構成，例如上述系統 LSI (半導體積體電路裝置）之一個模組，或功能單元 〇 圖示之動態存取記憶體採儲存體（Bank )架構，俾適 合大記憶容量，但不特別限制。記憶儲存體數之數目以， 例如最多1 6，而爲可變。一個記憶器儲存體，例如第1 個儲存體b a n k 1係由，記憶器陣列M A 1、感測放大 器SA〇、SA1及與感測放大器成一體之未圖示之位元 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） — ΙΓΙ — —.— — —---- 裝！—訂-------線 1 (請先聞讀背面之注意事項再填寫本頁) 466744 A7 ________ B7 五、發明說明（23 ) 線預充電電路，定時產生電路及行選擇器T C 1、列解碼 器RD 1及行轉接電路c s 1所構成。 (請先閱讀背面之注意事項再填寫本頁) 對此等多數記憶器儲存體，設定有位址信號及控制信 號用之位址匯流排/控制匯流排A D C B，並設定有輸入 輸出資料用之記憶器內部匯流排（I / 〇內部匯流排） IOB。對該等匯流排ADCB、 IOB設定有共同之記 憶器輸入輸出電路Μ — I / 0。記憶器輸入輸出電路Μ — I / 〇在其內部備有，結合於內部匯流排B U S之端埠。 動態存取記憶體又具備有，經由配線群V L & C L結 合在基板偏壓控制電路V B B C之基板偏壓切換電路 V Β Β Μ，內部電源電路I Μ V C，接受內部動作控制信 號m d、p m q，復置信號r e s b及經由控制匯流排 CBUS之各種動作控制信號之記憶器控制電路MMC， 以及，電源初期化電路V I N T C。上述內部電源電路 I MV C也含有如上述之昇壓電路之充電泵浦電路。 例如，一個記憶儲存體之記憶單元陣列（M A 1 )、 感測放大器、列解碼器（R 〇 1 )及行轉接器（C S 1 ) 可視爲構成一片記憶墊，定時產生電路及行選擇器（ 經濟部智慧財產局員工消費合作社印製 T C 1 )可以視爲構成儲存體控制電路。這個時候，各記 憶器儲存體可以更單純地看作是由記憶墊及儲存體控制電 路所構成。 在圖示之動態存取記憶體，上述記憶墊（Memory mat )或其選擇電路等，與獨立構成CMO S型半導體積體電 路裝置之習知之動態存取記憶體幾乎完全相同。因此關於 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） A7 466744 ____B7______ 五、發明說明（24 ) 其內部架構之詳細說明擬從略，僅槪略說明如下。 (請先閱讀背面之注意事項再填寫本頁) 在以上之記述，用語「MO S」本來應是簡稱金屬氧 化物半導體。惟，近年來一般稱呼之「MO S」應包含， 將半導體裝置之本質部分中之Metal改用多晶矽等非金屬之 電氣導電體，或將Oxide改用其他絕緣體者。C Μ 0 S也應 該是與上述M〇 S —樣，具有較廣泛之技術意義。 MOSFET也同樣，不是狹義之MOSFET，實質上 應包含絕緣閘電場效果電晶體之廣義之架構。本發明之 CMOS、MOSFET等係依照一般之稱呼。 如本實施例之將動態型R A Μ，對此進行資料之寫入 或讀出之中央處理裝置CPU，或直接記憶存取C等之邏 輯電路混合形成在1個半導體積體電路裝置時，上述邏輯 電路會發生對應電源電壓之大波幅之信號變化，因此會在 電源線或接地線發生較大之雜訊。對此，習知之動態存取 記憶體係將對應儲存在小記憶電容器之電荷之微小電壓讀 出到位元線，而藉高靈敏度之感測放大器加以放大，因此 容易受到上述電源線所發生之雜訊之影響。 經濟部智慧財產局員工消費合作社印製 本案發明因爲令動態型記憶單元具有自行放大功能， 因此，讀出到位元線之信號電壓可以使其成較不具自行放 大功能之習知之動態型記憶單元爲大之電壓信號。因之， 縱使對應上述電源電壓之大波幅產生信號變化之邏輯電路 與動態存取記億體混合在一起時，動態存取記憶體仍可以 不受邏輯電路側之動作所發生之電源雜訊之影響，穩定進 行動作。亦即，本實施例之動態存取記憶體具有，與邏輯 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -Ζί - ϋ 6 6744 Α7 _ Β7 五、發明說明（25 ) 電路之適應性優異之特徵。 從上述實施例獲得之作用效果如下。 (請先閱讀背面之注意事項再填寫本頁) (1 )在多數位元線，多數讀出用第1字線及寫入用 第2字線之交點，配設閘極連接在上述第1字線，一方之 源極-汲極連接在記憶電容器之記憶節點之讀出用轉接 Μ 0 S F E T ;閘極連接在上述第2字線，源極一汲極路 徑連接在上述位元線與上述記憶電容器之記憶節點之寫入 用轉接MO S F Ε Τ ;以及，以形成有上述讀出用之轉接 MO S F Ε Τ之半導體領域當作集極，以上述讀出用轉接 MO S F Ε Τ之另一方之源極—汲極當作基極，形成在此 基極領域內之射極連接在上述位兀線之放大電晶體，以構 成記憶單元，藉此可實現，能夠抑制起因於構造之複雜性 之記憶單元特性之參差不一，不需要爲此增加製造程序之 實用性之自行放大型之記憶單元，而不會招致低電源電壓 動作時成爲問題之寫入速度之劣化。 (2 )由上述（1 )，可以獲得內設可實現高速化與 動作穩定化之半導體記憶電路之半導體積體電路裝置之效 果。 經濟部智慧財產局員工消費合作社印製 (3 )由於形成上述放大電晶體之讀出用 Μ 0 S F Ε Τ之一方之源極一汲極領域，由位元線方向相 鄰接之兩個記憶器單元所共用，因此可以收到，能夠使放 大電晶體與接點部之共同化成爲可能，因而得實現記憶單 元之高密度實裝之效果。 (4)夾著連接在形成於上述讀出用MOSFET之 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ^6674^ a7 ___；_R7 ___ 五、發明說明（26 ) (請先閱讀背面之注意事項再填寫本頁) 一方之源極-汲極領域之放大電晶體之射極之位元線之接 觸部，成對稱狀配置鄰接記憶單元之第1字線，夾著上述 寫入用Μ 0 S F E T之源極—汲極與上述位元線相連接之 接觸部，成對稱狀配置與上述不同之相鄰接記憶單元之第 2字線，藉此可以在相鄰接記憶單元，使與位元線連接之 接觸部，及連接在此之Μ ◦ S F Ε Τ之源極_汲極領域能 夠共同化，收到實現記憶單元之高實裝密度之效果。 (5 )對位元線方向並排配置之記憶單元，形成共同 之形成有上述第1導電型讀出用M〇 S F Ε Τ之第2導電 型之井領域， 並對位元線方向並排配置之記憶單元，形成共同之形 成有上述第2導電型之寫入用MO S F Ε Τ之第1導電型 之井領域，爲其特徵之半導體積體電路裝置。 (6 )由於在字線方向相鄰接之兩個記憶單元間，將 上述第1及第2導電型之井領域共同化，因此可以收到， 減小讀出時之放大電晶體之電源阻抗，獲得效率良好之讀 出放大信號之效果。 經濟部智慧財產局員工消費合作社印製 (7 )因爲進一步設有，一方之輸入端子連接在上述 位元線，兩個CMO S反相電路之輸入與輸出成交叉連接 之C Μ 0 S閂鎖電路所構成之感測放大器，在感測放大器 進行放大動作時，在另一方之輸入加上基準電壓，施加對 應電源電壓之動作電壓，而得收到簡化感測放大器之效果 〇 (8 )使用具有上述記憶單元之記憶電容器之電容値 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -29- 經濟部智慧財產局員工消費合作社印製 *466744 A7 ______B7__ _ 五、發明說明（27 ) 之1/ 2電容器之虛擬單元，形成上述基準電壓，夾著上 述感測放大器在左右延伸配置位元線，選擇一方之位元線 之記憶單元時，選擇連接在另一方之位元線之虛擬單元， 藉此架構得在字線與位元線之交點恆常配置記憶單元，收 到實現記憶單元陣列部之高密度化之效果。 (9 )對上述半導體記憶電路組合用以進行資料之寫 入與讀出之數位信號處理電路，可使上述半導體記憶裝置 高速化，動作穩定化，與邏輯電路之適應性良好，因此可 以收到獲取高性能之半導體積體電路裝置之效果。 (1 0 )上述數位信號處理電路與具有獨立電路功能 單位之模組，或大單元組合，而使其電路規模，系統架構 爲可變，因之可收到，能高效率製成由多品種少量生產而 成之具有所需資料處理功能之高性能半導體積體電路裝置 之效果。 以上係依據實施例具體說明由本發明人所完成之發明 ’但本發明並不限定如上述實施例，當然可以在未脫離其 主旨之範圍內，作各種變更。例如，Μ 0 S F E T或電晶 體之導電型可以與上述者相反。例如，讀出用 MOS FET用Ν通道型，放大電晶體用ΡΝΡ電晶體， 寫入用Μ ◦ S F Ε Τ用Ρ通道型。這時，使位元線之預充 電電壓等於電源電壓V c c即可。記憶單元陣列之周邊電 路可採各種實施例形態。上述動態存取記憶體除了可搭載 於如上述之A S I C等之半導體積體電路裝置者之外，也 可以使用其本身則構成一個半導體積體電路裝置者。 -----------」裝--------訂-------！線( (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -30- 466744 五、發明說明（28 ) (請先閱讀背面之注意事項再填寫本頁) 本發明可以廣泛應用在，動態型記憶單元內具有自行 放大功能之半導體記憶電路，及搭載此電路之半導體積體 電路裝置。 圖式之簡單說明 第1圖係表示本發明之半導體記憶電路之記憶單元之 一實施例之等效電路圖。 第2圖係說明本發明之記憶單元之寫入、讀出動作用 之閘電壓、電流特性圖。 第3圖係表示本發明之半導體記憶電路之記憶單元之 一實施例之布置圖。 第4圖係表示本發明之半導體記憶電路之記憶單元之 一實施例之截面構造圖。 第5圖係表示說明本發明之半導體記憶電路之記憶單 元之製造方法之第1製程之截面圖。 第6圖係表示說明本發明之半導體記憶電路.之記憶單 元之製造方法之第2製程之截面圖。 經濟部智慧財產局員工消費合作社印製 第7圖係表示說明本發明之半導體記憶電路之記憶單 元之製造方法之第3製程之截面圖。 第8圖係表示本發明之半導體記憶電路之記憶單元另 一實施例之布置圖。 第9圖係表示本發明之半導體記憶電路之記憶單元另 一實施例之電路圖。 第1 0圖係表示實施例之半導體記憶電路之直接周邊 -31 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） '466744 A7 _ B7 五、發明說明（29 ) 電路之一實施例之電路圖。 第1 1圖係說明本發明之半導體記憶電路之動作之一 個例子之波形圖。 第1 2圖係表示本發明之半導體記憶電路之另一其他 實施例之記憶單元部之佈置圖。 第1 3圖係表示搭載本發明之半導體記憶電路之半導 體積體電路裝置之一實施例之整體方塊圖。 第1 4圖係表示第1 3圖之半導體記憶電路之一實施 例之整體方塊圖。 主要元件對照表 (請先閱讀背面之注意事項再填寫本頁) ----丨！ 訂-------- 經濟部智慧財產局員工消費合作社印製 Q 1 讀 出 用 P 通道型Μ〇 S F Ε Τ Q 2 寫 入 用 N 通道型Μ 0 S F Ε Τ T R N P N 電 晶體 C S 記 憶 電 容 器 4 5買 出 用 字 線 5 寫 入 用 字 線 7 電 容 器 電 極 1 1 位 元 線 1 2 寫 入 用 字 線 2 1 Ν 型井 2 2 P 型 井 2 6 =¾ 日貝 出 用 字 線 3 4 電 容 器 電 極 3 8 位 元 線 8 2 N 型 井 8 3 P 型 井 8 4 讀 出 用 字 線 8 5 寫 入 用 字 線 8 7 電 容 器 電 極 9 1 位 元 線 1 0 2 N 型 井 1 0 3 P 型 井 1 0 4 讀 出 用 字 線 1 0 5 寫 入 用 字 線 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -32- 經濟部智慧財產局員工消費合作社印製 *466744- a7 _B7 五、發明說明（3〇 ) 107 電容器電極 ---：------------ I--1!1 訂------線' (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -33-/ BL) high level (V c c) or low level causes the memory capacitor C s to be written again via the N-channel MOSFET for writing. When the bit line B L is written at a high level, since the selection level of the word line W W L is higher than the power supply voltage V c c, there is no loss when it is passed to the capacitor C s. In a write operation (not shown), the read word line R W L is also selected for a refresh operation to activate the sense amplifier. In this state, the written data is written into the selected bit line via the row switch. Due to the input of such written data, if the sense amplifier of the latch structure inputs written data of a level opposite to the original memory state described above, its memory state will be reversed. Then, the writing word line W W L is selected, and most of the memory cells connected to the writing word line are written together with the writing data and the angle writing signal amplified by the sense amplifier. The update mode is the same as the read operation described above. However, in the read mode, a bit line is selected by a row selection circuit (not shown), and a read signal is read out of the memory circuit through a main amplifier. In the update mode, the row selection operation is omitted, and only the angle writing of the memory cells connected to the word line is performed. Fig. 12 shows the layout of the memory unit section of the embodiment of the semiconductor memory circuit of the present invention, which is printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. In this embodiment, the MOS F E T for reading and the MO S F E T for writing are arranged on a line _) in the direction of the bit line. That is, a read-out MOS F E T and an amplification transistor corresponding to a memory cell are formed in the N-type well 102. The source and sink 108 of one of the commonization of the read-out MOSFETs corresponding to the two memory cells, with -iy-This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 466744 A7 B7 V. Description of the invention (17) A connection plug 1 10 'contact hole 10 9 is set, and the center is formed to form a readout word line 104 corresponding to the two memory cells. The other source of the readout M 0 S F E T is connected to the capacitor electrode 107 via the contact hole 10 6. An N-channel type MO S F E T for writing is formed in the P-type well 103. The writing M 0 S F ET also uses a common source, which is different from the adjacent memory cells described above, at the center of the drain electrode to form a writing word line 105 corresponding to the two memory cells. In this common source, the drain forms a contact hole 1 1 0 and is connected to the bit line 1 1 1. The other source of the above-mentioned read-in MO S F ET has a drain connected to the capacitor electrode 107 via a contact hole 106. In this embodiment, two MO S F E T arrays are arranged on a straight line in the direction of the bit line, so the bit line width can be reduced. The word line return paradigm is the same as the above embodiment, and the description is omitted. Fig. 13 is a block diagram showing an overall circuit of an embodiment of a system L S I to which the present invention is applied. The semiconductor integrated circuit device CH I P of this embodiment contains, as shown in the figure, most circuit blocks, including input / output circuit 1/0, substrate bias control circuit VBBC, control circuit ULC, read-only memory ROM, D / A converter DAC, A / D converter ADC, plug-in control circuit IVC, system power management circuit SPMC with clock generation circuit CGC, central processing unit CPU, static memory s RA M, direct memory access controller direct Memory access, dynamic memory dynamic access memory. These circuit blocks are combined with the internal bus B us to control the bus. The paper size applies the Chinese National Standard (CNS) A4 (210 X 297 mm) (please read the precautions on the back before filling this page). Installation- --Order --------- Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs' -20- 466744 V. Description of Invention (18) CBUS. These are mounted on a semiconductor substrate as shown in the figure that should constitute a semiconductor integrated circuit device. The above system power management circuit S PMC (please read the precautions on the back before filling out this page) Yes, it controls the power consumed by each module mounted on the system LSI. It has semiconductor integrated circuit devices and is connected to the input. The input / output external terminals T i ο 1 to T i ο η of the output circuit I / ◦ supply the external terminal T 1 of the reset signal ν esb with a negative logic level, the external terminal T 2 for control, and the first operation control The first operation control external terminal T 3 of the signal cmq is supplied to the second operation control external terminal T 4 of the second operation control signal cpmq, and the clock external terminal T 5 is provided to the external clock signal c 1 k, and, External terminals T6, D7, and T8 for supplying most of the power supply voltages (vdd, VCcdr, vsS). Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Although there is no special restriction, the power supply voltage v d d is the power supply voltage for the operation of the internal circuit block, which is 1.8 volts ± 0.1 volts. The power supply voltage V ccdr is based on the input and output levels required by the semiconductor integrated circuit device. It is mainly the power supply voltage set by the input / output circuit I / O. 3.3 volts ± 0.3 volts, 2.5 volts ± 0.5 volts and 1 8 Volts ± 0.1 One of 15 Volts. The potential v s s is the reference potential of a circuit called a ground potential. The semiconductor integrated circuit device shown in the figure constitutes A S I C (application Specified Integrated Circuits), which is a specific application I C. Yiliang P. Most of the circuit blocks shown in the figure become modules or large units of independent circuit functional units, which cannot easily achieve the A S I C architecture. The paper size of each functional unit applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ^ 466744 A7 ___ B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (19) Modular structure Can be changed. A S I C can avoid circuit blocks that are not needed for the electronic system in the circuit blocks shown in the figure, and avoid mounting on the semiconductor substrate. Conversely, circuit blocks of functional units (not shown) may be added. The central processing unit CPU is not particularly limited, but its structure is the same as that of a so-called microprocessor. That is, the central processing unit CPU has a command register inside it, which decodes the commands written into the command register to form micro-command ROMs for various micro-commands or control signals, arithmetic circuits, and general-purpose registers (RG 6 Etc.), combined with the bus driver of the internal bus BUS, and the input and output circuits of the bus receiver. The central processing unit CPU reads the commands stored in the read-only register R OM and performs operations corresponding to the commands. The central processing unit CPU will take in the external data input through the input / output circuit I / 0, input and output data to and from the control circuit UL C, read out the data from the read-only memory or execute the command, such as fixed data, to the The D / A converter DAC supplies the data that needs D / A conversion, reads the data that is A / D converted by the A / D converter, and dynamically accesses the data in the memory to the static memory SRA M 'dynamic memory. Read and write, D Α controller directly memorizes and accesses C's motion control and so on. The insert control circuit I vc receives a reset signal with negative logic level at the external terminal 1, receives the first action signal cmq via the external terminal τ 3, and receives the second control signal cpmq 'via the external terminal T 4 and the external terminal T 2 Output a status indication signal indicating the operating status of the semiconductor integrated circuit device. Insertion control circuit I v c is provided with ‘corresponding to these (please read the precautions on the back before filling in this page) n n i I I I — order. —! II 1. The paper size applies to Chinese National Standard (CNS) A4 (210 X 297) and > M6 6744 Α7 —— Β7 Duplicate printing of employee cooperation of Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of invention (20) No. resb, motion control signals cm Q, cpmq, and status indication signals, respectively set the register RG 5 of the bit of its position. Although it is not particularly limited, the inserted control circuit I V C has an internal update address counter (not shown) for the update operation of the dynamic memory. The update address counter inserted in the control circuit IVC, if a certain mode is designated by the first and second motion control signals cmq, cpm Q, that is, when the semiconductor integrated circuit device is in the operation mode or the operation standby mode is indicated. , According to the system clock signal stepping of the clock generation circuit CGC, the update address information of the dynamic access memory that is periodically updated is formed. The input / output circuit I / O receives a signal externally supplied through a desired external terminal among the external terminals T i ο 1 to T i ο η, and receives and outputs to the external terminals T i ο 1 to T through an internal bus BUS. i ο η The signal of the desired terminal. The input / output circuit I / ◦ is equipped with a control register RG4 and a data register (not shown) composed of C MOS static circuits. The control register RG4 is selected by the central processing unit CPU and is supplied by the central processing unit CPU for the input / output circuit I / ◦ control data, such as data input / output instructions, or high output impedance status instructions. . The data register is used to transfer data between the external terminals T i ο 1 to T i ο η and the internal bus B B S. The input signal circuit and the output signal circuit of the input / output circuit I / 0 are controlled by the system clock signal. Therefore, when the input / output circuit I / 0 cannot supply the system clock signal, it is in the same state as the central processing unit C P U and has a low power consumption state. (Please read the precautions on the back before filling out this page.) --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Printed by the Bureau's Consumer Cooperatives 4 6 6744 Α7 Β7 V. Description of the Invention (21) Control circuit ULC is a control circuit that is suitable to be equipped according to the needs of the electronic system. This control circuit ϋ LC is based on, for example, the servo control of the hard disk drive, the tracking control of the magnetic head, the error correction processing, or the compression and elongation processing of the image or voice processing image or voice data. Of it. The control circuit U L C is the same as the central processing unit C P U, and its operation is controlled by the system clock signal. The read-only memory R ◦ As described above, it stores the commands to be executed read by the central processing unit C P U and fixes the data. The D / A converter DA C is provided with a register R G 2 for receiving a digital signal which should be converted into an analog signal supplied through the internal bus B U S, and an analog signal is formed based on the digital data. Register RG 2 sets digital data by control circuit UL C or central processing unit C PU. The analog signal formed by the D / A converter D A C is supplied to the desired terminal among the external terminals τ 1 to τ η via the internal bus B U S and the input / output circuit I / ◦, but it is not particularly limited. The A / D converter AD C accepts analog signals supplied through the desired terminals of the external terminals T 1 to T η and the input / output circuit I / 0 and the internal bus BUS, and is controlled by the control circuit u LC or the central processing unit CPU At the beginning of the A / D conversion, under the control of the system clock signal C 2, the above analog signal is converted into a digital signal, and the obtained digital signal is set in the temporary register RG1. Static memory SRA Μ, the details of its memory unit are not shown, but it has a C 0 MS static memory unit, that is, it has a latch circuit by C Μ 0 S and one of the data input and output for this For this paper size, the Chinese National Standard (CNS) A4 specification (210 X 297 mm) applies. Γ2Τ ^ ------------ installed! —Order i I ------ line (please read the precautions on the back before filling this page) DuPont of Intellectual Property Bureau, Ministry of Economic Affairs, printed 466744 A7 B7 V. Description of Invention (22) The unit of memory. The characteristic of the C M 0 S static type memory unit is that the information is held statically, and only a very small operating current is required to maintain the information. Direct memory access controller. That is, Direct Memory Access Controller—direct memory access is controlled by the central processing unit CPU and replaces the central processing unit CPU to control the internal instructions between the circuit blocks instructed by the central processing unit CPU. Data transfer of bus BUS. The dynamic memory unit is a memory unit for dynamically accessing the memory, that is, the dynamic memory unit is composed of an information storage capacitor that stores the information of the charge form described above, and a selective MOSFET for reading, amplifying transistor, and writing The MO SFET has a small number of components and can be formed into a smaller memory cell size. Therefore, when the dynamic memory has a larger memory capacity, its overall size can also be smaller. The following describes the dynamic access memory of this dynamic memory. Figure 14 shows a block diagram of an embodiment of a dynamic memory (hereinafter referred to as a dynamic access memory) carried by a semiconductor integrated circuit device to which the present invention is applied. This dynamic access memory structure is, for example, a module of the above-mentioned system LSI (semiconductor integrated circuit device), or a functional unit. The dynamic access memory shown in the figure adopts a bank structure, which is suitable for large memory capacity. It is not particularly limited. The number of memory banks is variable, for example, up to 16. A memory bank, for example, the first bank bank 1 is composed of the memory array MA 1, the sense amplifiers SA0, SA1, and the unillustrated bit integrated with the sense amplifier. The paper size is applicable to China. Standard (CNS) A4 size (210 X 297 mm) — ΙΓΙ — — — — — ——— Install! —Order ------- Line 1 (Please read the precautions on the back before filling out this page) 466744 A7 ________ B7 V. Description of the invention (23) Wire precharge circuit, timing generator circuit and row selector TC 1 , Column decoder RD 1 and row switching circuit cs 1. (Please read the precautions on the back before filling this page.) For most of these memory banks, the address bus and control bus ADCB for address signals and control signals are set, and the input and output data are set for them. Internal bus of memory (I / 〇 internal bus) IOB. A common memory input / output circuit M — I / 0 is set for the bus ADCB and IOB. The memory input / output circuit M — I / 〇 is provided internally, and is combined with the end port of the internal bus B U S. The dynamic access memory is also provided with a substrate bias switching circuit V Β Β Μ, which is combined with a substrate bias control circuit VBBC via a wiring group VL & CL, and an internal power supply circuit LM VC, which receives internal operation control signals md, pmq , A memory control circuit MMC that resets the signal resb and various motion control signals through the control bus CBUS, and a power supply initialization circuit VINTC. The internal power supply circuit I MV C also includes a charge pump circuit of the booster circuit as described above. For example, a memory cell array (MA 1), a sense amplifier, a column decoder (R 〇1), and a row adapter (CS 1) of a memory bank can be regarded as forming a memory pad, a timing generating circuit and a row selector. (Printed by TC 1 in the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs) It can be regarded as constituting the storage control circuit. At this time, each memory bank can be regarded more simply as being composed of a memory pad and a bank control circuit. In the illustrated dynamic access memory, the above-mentioned memory mat or its selection circuit is almost the same as the conventional dynamic access memory that independently constitutes a CMO S-type semiconductor integrated circuit device. Therefore, the Chinese paper standard (CNS) A4 (210 X 297 mm) applies to this paper size. A7 466744 ____B7______ V. Description of the invention (24) The detailed description of its internal structure is omitted, and only the description is omitted below. (Please read the cautions on the back before filling out this page.) In the above description, the term "MO S" should have been referred to as a metal oxide semiconductor for short. However, in recent years, the "MOS" generally referred to should include the conversion of Metal in the essential part of semiconductor devices to non-metallic electrical conductors such as polycrystalline silicon, or Oxide to other insulators. C M 0 S should also be the same as the above-mentioned M S, which has broader technical significance. The same is true for MOSFETs. It is not a MOSFET in a narrow sense, but it should essentially include a broad structure of an insulated gate electric field effect transistor. The CMOS and MOSFET of the present invention are generally called. For example, when a dynamic RAM is used in this embodiment, a central processing device CPU that writes or reads data, or a logic circuit such as direct memory access C is mixed to form a semiconductor integrated circuit device. The logic circuit will have a large amplitude signal change corresponding to the power supply voltage, so a large noise will occur in the power line or ground line. In this regard, the conventional dynamic access memory system reads the tiny voltage corresponding to the charge stored in a small memory capacitor to the bit line, and amplifies it with a high-sensitivity sense amplifier, so it is susceptible to the noise generated by the power line. Influence. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs because the dynamic memory cell is provided with a self-amplification function. Therefore, the signal voltage read out to the bit line can make it a less-known dynamic memory cell with a self-amplification function. Great voltage signal. Therefore, even if the logic circuit that generates a signal change corresponding to the large amplitude of the above-mentioned power supply voltage is mixed with the dynamic access memory, the dynamic access memory can still be protected from power noise caused by the operation of the logic circuit side. Affect and move stably. That is to say, the dynamic access memory of this embodiment has the same paper size as the Chinese National Standard (CNS) A4 (210 X 297 mm) -Zί-ϋ 6 6744 Α7 _ Β7 V. Description of the invention (25 ) Excellent adaptability of the circuit. The effects obtained from the above embodiments are as follows. (Please read the precautions on the back before filling in this page) (1) In most bit lines, the intersection of the first word line for reading and the second word line for writing, the gate is connected to the first Word line, the source-drain of one side is connected to the read-out switch M 0 SFET of the memory node of the memory capacitor; the gate is connected to the second word line, and the source-drain path is connected to the bit line and The transfer node MO SF ET for writing to the memory node of the above memory capacitor; and the semiconductor field in which the transfer MO SF ET for reading is formed as a collector, and the transfer MO SF for readout is used as a collector The drain source of the other side of Ε serves as the base, and an amplifier transistor with an emitter connected to the above-mentioned bit line formed in the base field to form a memory unit. This can be achieved and the cause can be suppressed. The characteristics of the memory cells vary in the complexity of the structure, and there is no need to increase the practicality of the manufacturing process by a self-amplifying memory cell without incurring the degradation of the writing speed, which becomes a problem when operating at low power supply voltages. (2) According to the above (1), the effect of a semiconductor integrated circuit device having a semiconductor memory circuit capable of achieving high speed and stable operation can be obtained. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs (3) Due to the formation of the source-drain field of one of the above-mentioned read-out transistors M 0 SF Ε Τ, two memories adjacent to each other by the bit line direction The unit is shared, so it can be received, and it is possible to make the common of the amplifying transistor and the contact portion, so that the effect of high density mounting of the memory unit can be achieved. (4) The size of the paper sandwiched between the MOSFETs formed in the above-mentioned readout is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ^ 6674 ^ a7 ___; _R7 ___ 5. Description of the invention (26) ( (Please read the precautions on the back before filling in this page) The contact portion of the bit line of the emitter of the source-drain region of the amplifier transistor is symmetrically arranged next to the first word line of the memory cell, sandwiching The contact between the source and drain of the M 0 SFET for writing and the bit line is arranged symmetrically to the second word line of the adjacent memory cell that is different from the above, so that it can be connected adjacently. The memory unit enables the contact portion connected to the bit line and the source-drain area of the M ◦ SF ET to be connected in common, receiving the effect of achieving a high mounting density of the memory unit. (5) The memory cells arranged side by side in the bit line direction form a common well field having the second conductivity type of the first conductivity type readout MOSF ET, and are arranged side by side in the bit line direction. The memory cells form a semiconductor integrated circuit device in which the first conductive type well field in which the above-mentioned second conductive type writing MO SF ET is formed in common. (6) Since the above-mentioned first and second conductive well fields are common between two memory cells adjacent to each other in the word line direction, they can be received and the power impedance of the amplified transistor during reading can be reduced , To obtain the effect of reading the amplified signal with good efficiency. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs (7) Because it is further provided, one input terminal is connected to the above bit line, and the inputs and outputs of the two CMO S inverting circuits are cross-connected C Μ 0 S latches The sense amplifier formed by the circuit, when the sense amplifier performs an amplification operation, adds a reference voltage to the other input and applies an operating voltage corresponding to the power supply voltage to obtain the effect of simplifying the sense amplifier. (8) Use Capacitance of memory capacitors with the above-mentioned memory unit. The paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm). Explanation (27) The virtual unit of 1/2 capacitor forms the above-mentioned reference voltage, and arranges the bit line on the left and right by sandwiching the above-mentioned sense amplifier. When the memory cell of one bit line is selected, the bit connected to the other is selected. The virtual cell of the element line, with this structure, the memory cell is constantly arranged at the intersection of the word line and the bit line, and the high density of the memory cell array unit is received. Degree of effect. (9) A digital signal processing circuit that combines the above semiconductor memory circuits for writing and reading data can speed up the semiconductor memory device, stabilize the operation, and have good adaptability to logic circuits, so it can be received. Get the effect of high-performance semiconductor integrated circuit devices. (1 0) The above digital signal processing circuit is combined with a module or a large unit with independent circuit function units to make its circuit scale and system architecture variable, so it can be received and can be made efficiently with multiple varieties. The effect of high-performance semiconductor integrated circuit devices with required data processing functions produced in small quantities. The above has specifically described the invention made by the present inventors based on the embodiments', but the invention is not limited to the embodiments described above, and of course, various changes can be made without departing from the spirit thereof. For example, the conductivity type of M 0 S F E T or an electric crystal may be opposite to the above. For example, an N-channel type for read MOS FET, a PNP transistor for amplification transistor, and a P-channel type for M ◦ S F ET. In this case, the precharge voltage of the bit line may be equal to the power supply voltage V c c. The peripheral circuit of the memory cell array can adopt various embodiments. The above-mentioned dynamic access memory can be mounted on a semiconductor integrated circuit device such as the above-mentioned A S IC, or it can also be used to construct a semiconductor integrated circuit device. ----------- "installed -------- order -------! ((Please read the precautions on the back before filling this page) This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) -30- 466744 V. Description of the invention (28) (Please read the back first Please pay attention to this page and fill in this page again) The present invention can be widely used in semiconductor memory circuits with self-amplification function in dynamic memory cells and semiconductor integrated circuit devices equipped with this circuit. An equivalent circuit diagram of one embodiment of the memory cell of the semiconductor memory circuit of the present invention. FIG. 2 is a graph showing the gate voltage and current characteristics of the write and read operations of the memory cell of the present invention. FIG. The layout of one embodiment of the memory unit of the semiconductor memory circuit of the invention. FIG. 4 is a cross-sectional structure diagram showing one embodiment of the memory unit of the semiconductor memory circuit of the invention. FIG. 5 is a diagram showing the semiconductor memory of the invention A cross-sectional view of the first manufacturing process of a circuit memory cell manufacturing method. FIG. 6 is a diagram illustrating the manufacturing of a memory cell illustrating a semiconductor memory circuit of the present invention. Cross-sectional view of the second process of the manufacturing method. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. FIG. 7 is a cross-sectional view of the third process illustrating the manufacturing method of the memory cell of the semiconductor memory circuit of the present invention. FIG. 9 is a layout diagram showing another embodiment of a memory unit of the semiconductor memory circuit of the present invention. FIG. 9 is a circuit diagram showing another embodiment of a memory unit of the semiconductor memory circuit of the present invention. FIG. 10 is a diagram showing the semiconductor memory of the embodiment. Circuit's Direct Peripheral -31-This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) '466744 A7 _ B7 V. Description of the invention (29) Circuit diagram of one embodiment of the circuit. Figure 1 1 FIG. 12 is a waveform diagram illustrating an example of the operation of the semiconductor memory circuit of the present invention. FIG. 12 is a layout diagram of a memory cell portion of another embodiment of the semiconductor memory circuit of the present invention. FIG. An overall block diagram of one embodiment of a semiconductor integrated circuit device of a semiconductor memory circuit of the present invention. Fig. 14 shows the semiconductor memory circuit of Fig. 13 The overall block diagram of an embodiment of the road. The main component comparison table (please read the precautions on the back before filling this page) ---- 丨! Order -------- Employee Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed Q channel for readout P channel type MOSF Ε Τ Τ Q 2 Write for N channel type MOS 0 SF Ε TRNPN transistor CS memory capacitor 4 5 Word line for buying 5 Word line for writing 7 Capacitor electrode 1 1 Bit line 1 2 Word line for writing 2 1 N-type well 2 2 P-type well 2 6 = ¾ Ribe output word line 3 4 Capacitor electrode 3 8 Bit line 8 2 N-type well 8 3 P type Well 8 4 Word line for reading 8 5 Word line for writing 8 7 Capacitor electrode 9 1 Bit line 1 0 2 N-type well 1 0 3 P-type well 1 0 4 Word line for reading 1 0 5 For writing The size of the word paper is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) -32- Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs * 466744- a7 _B7 V. Description of the invention (3〇) 107 Capacitor electrode ---: ------------ I--1! 1 Order ------ '(Read the back of the precautions to fill out this page) This paper scale applicable Chinese National Standard (CNS) A4 size (210 X 297 mm) -33-

Claims (1)

/66744 Α8 Β8 C8 D8 經濟部智慧財產局員工消費合作社印製 7、申請專利範圍 1 . 一種半導體積體電路裝置，其特徵在於，具備有 ’包含： 多數位元線； 多數讀出用第1字線； 多數寫入用第2字線；以及， 由分別配置在上述位元線，第1字線及第2字線之交 點，用以記憶資訊電荷之記憶電容器，閘極連接在上述第 1字線，源極-汲極之一方連接在上述記憶電容器之記憶 節點之具有第一導電型通道之讀出用轉接MO S F E T ’ 閘極連接在上述第2字線，源極-汲極路徑連接在上述位 元線與上述記憶電容器之記憶節點之具有第.2導電型通道 之寫入用轉接MO S F E T，以及，以形成有上述讀出用 之轉接MO S F E T之第2導電型之第1半導體領域當作 集極領域，以上述讀出用轉接Μ ◦ S F E 丁之另一方之源 極-汲極當作基極，令形成在此基極領域內之第1導電型 之第2半導體範圍爲射極上述射極連接在上述位元線之放 大電晶體，所構成之記憶單元之半導體記憶電路。 2 ·如申請專利範圍第1項之半導體積體電路裝置， 其特徵在於， 上述寫入用MOSFET係由’形成在第1導電型之 第3半導體領域內者。 3 .如申請專利範圍第2項之半導體積體電路裝置， 其特徵在於， 形成有上述放大電晶體之讀出用1^10 s F Ε τ之一方 I n —l· n I I kR^ n j Βϋ I- 1 I— n n n n «I aBi-#-rOJ «1 [ n n I n I I f (請先閱讀背面之注意事項再填窝本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） -34 - '466744 0^888 ABCD 經濟部智慧財產局員工消費合作社印製 六、申請專利範圍 之源極一汲極領域，係位元線方向相鄰接之兩個記憶單元 之共同領域。 4 ·如申請專利範圍第3項之半導體積體電路裝置， 其特徵在於， 夾著連接形成於上述讀出用MO S F E T之一方之源 極-汲極領域之放大電晶體之射極之位元線之接觸部，成 對稱狀配置相鄰接記憶率元之第1字線， 並夾著連接上述寫入用MO SF E T之源極一射極與 上述位元線之接續部，成對稱狀配置與上述相異之相鄰接 記憶單元之第2字線.。 5. 如申請專利範圍第4項之半導體積體電路裝置， 其特徵在於， 對在位元線延伸存在之方向並排配置之2個記憶單元 ，共同形成有，用以形成上述第1導電型之讀出用 M〇S F E T之第2導電型之第1半導體領域， 對在位元線延伸存在之方向並排配置之2個記億單元 ，共同形成有，用以形成上述第2導電型之寫入用 M〇S F E T之第1導電型之第3半導體領域。 6. 如申請專利範圍第5項之半導體積體電路裝置’ 其特徵在於， 上述第1及第2半導體領域，係在配置於字線延伸存 在之方向的複數記億單元之間加以共同化者。 7. 如申請專利範圍第4項之半導體積體電路裝置’ 其特徵在於， (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公楚） -35 - 0Q80Q8 ABaD 466744 ☆、申請專利範圍 進一步備有，由一方之輸入端子連接在上述位元線， 兩個CMO S反相器電路之輸入與輸出交叉連接而成之 C Μ 0 S閂鎖電路所構成之感測放大器。 感測放大器之放大動作時，在另一方之輸入施加基準 電壓，同時施加對應電源電壓之動作電壓，藉此使其活性 化。 8·如申請專利範圍第7項之半導體積體電路裝置， 其特徵在於， 上述基準電壓係使用具有上述記憶單元之記憶電容 器之1/2電容値之電容器之虛擬單元所形成， 夾著上述感測放大器，位元線向左右延伸，當選擇一 方之位元線之記憶單元時，選擇連接在另一方之位元線之 虛擬單元。 9 .如申請專利範圍第4項之半導體積體電路裝置， 其特徵在於， ' 進一步備有，對上述半導體記憶電路進行資料之寫入 與讀出之數位信號處理電路。 1 0 .如申請專利範圍第9項之半導體積體電路裝置 ，其特徵在於， 上述數位信號處理電路可藉組合獨立的電路功能單位 之模組或巨大單元，以變更其電路規模，系統架構。 --------I! ! ^--------訂-------- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -36-/ 66744 Α8 Β8 C8 D8 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 7. Application for patent scope 1. A semiconductor integrated circuit device, characterized in that it includes' contains: most bit lines; most readout first Word line; most of the second word line for writing; and, a memory capacitor for storing information charge is arranged at the intersection of the bit line, the first word line, and the second word line, and the gate is connected to the first One word line, one of the source-drain is connected to the memory node of the memory capacitor, and the read-through switching MO SFET with the first conductive channel is connected to the second word line, the source-drain The path is connected to the bit line and the memory node of the memory capacitor, and has a .2 conductive type switching MO SFET for writing, and a second conductive type having the above-mentioned switching MO SFET for reading. The first semiconductor field is regarded as the collector field, and the above-mentioned read-through switch M is used as the base, so that the first conductive type formed in this base field is used as the base. The second semiconductor range is Emitter electrode connected to the above-described amplifying transistor above the bit line, the memory cell of a semiconductor memory circuit composed of. 2. The semiconductor integrated circuit device according to item 1 of the scope of the patent application, wherein the write MOSFET is formed by '' in the third semiconductor field of the first conductivity type. 3. The semiconductor integrated circuit device according to item 2 of the scope of patent application, characterized in that one of the 1 ^ 10 s F Ε τ readouts formed with the amplifying transistor I n —l · n II kR ^ nj Βϋ I- 1 I— nnnn «I aBi-#-rOJ« 1 [nn I n II f (Please read the notes on the back before filling in this page) This paper size is applicable to China National Standard (CNS) A4 (210 X 297 public love) -34-'466744 0 ^ 888 ABCD Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 6. The source-drain area of the patent application scope is the two memory cells adjacent to each other in the direction of the bit line. Common areas. 4. The semiconductor integrated circuit device according to item 3 of the scope of patent application, characterized in that the bit of the emitter of the amplifier transistor connected to the source-drain region of one of the above-mentioned read-out MO SFETs is sandwiched. The contact portions of the lines are symmetrically arranged with the first word lines adjacent to the memory rate element, and are sandwiched between the source-emitter of the MO SF ET for writing and the continuation portion of the bit line. Arrange a second word line adjacent to the memory cell that is different from the above. 5. The semiconductor integrated circuit device according to item 4 of the scope of patent application, which is characterized in that two memory cells arranged side by side in the direction in which the bit line extends are formed together to form the first conductive type. For the first semiconductor field of the second conductivity type of the MOSFET for readout, two hundred million cells arranged side by side in the direction in which the bit line extends are formed together to form the write of the second conductivity type. The third semiconductor field is the first conductivity type of MOSFET. 6. The semiconductor integrated circuit device according to the scope of application for patent No. 5 is characterized in that the above-mentioned first and second semiconductor fields are common among a plurality of hundreds of millions of cells arranged in a direction in which a word line extends. . 7. For the semiconductor integrated circuit device with the scope of patent application No. 4, it is characterized by: (Please read the precautions on the back before filling this page) This paper size is applicable to China National Standard (CNS) A4 (210 X 297) (Chu) -35-0Q80Q8 ABaD 466744 ☆ The scope of patent application is further provided by C Μ 0 S formed by one input terminal connected to the above bit line, and the input and output of two CMO S inverter circuits are cross-connected. A sense amplifier consisting of a latch circuit. During the amplification operation of the sense amplifier, a reference voltage is applied to the other input, and an operating voltage corresponding to the power supply voltage is applied to activate the sense amplifier. 8. The semiconductor integrated circuit device according to item 7 of the scope of the patent application, wherein the reference voltage is formed by using a dummy unit of a capacitor having a half capacitance of a memory capacitor of the memory unit and sandwiching the above sense. For measuring amplifiers, the bit lines extend to the left and right. When a memory cell of one bit line is selected, a virtual cell connected to the bit line of the other is selected. 9. The semiconductor integrated circuit device according to item 4 of the scope of patent application, further comprising: a digital signal processing circuit for writing and reading data to and from the semiconductor memory circuit. 10. The semiconductor integrated circuit device according to item 9 of the scope of patent application, characterized in that the above-mentioned digital signal processing circuit can change the circuit scale and system architecture by combining modules or huge units of independent circuit function units. -------- I!! ^ -------- Order -------- (Please read the notes on the back before filling out this page) Employee Cooperatives of Intellectual Property Bureau, Ministry of Economic Affairs The paper size for printing is applicable to China National Standard (CNS) A4 (210 X 297 mm) -36-
TW088114860A 1999-06-30 1999-08-30 Semiconductor integrated circuit device TW466744B (en)

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