TW466724B

TW466724B - Micro-range flip chip structure and the manufacturing method thereof

Info

Publication number: TW466724B
Application number: TW089125977A
Authority: TW
Inventors: Chian-Wei Jang; Sheng-Chuan Huang
Original assignee: Kinsus Interconnect Tech Corp
Priority date: 2000-12-06
Filing date: 2000-12-06
Publication date: 2001-12-01

Abstract

The present invention is a micro-range flip chip structure and the manufacturing method thereof, wherein a black oxide dam is directly formed on the metal circuit among the bump pads to replace the conventional solder resist, so that the bump pad will not be buried in the solder resist. Also, a method is developed to form the circuit conducting structure by drilling a minute hole and filling the hole with plated copper. Therefore, it can be directly formed on the hole, which greatly improves the routing space and the flexibility. Furthermore, in accordance with said improvement of routing space, the present invention provides a micro-range flip chip structure, which can have a design of mesh pattern to increase the anti-bending strength of the substrate under the limitation of the finite space.

Description

466724 五、發明說明（l) 【發明領域】本發明係有關一種使用載板的結構及其製造方法，求的困難，解決I C対裝不良【發明背景】於半導體封裝製程中微距覆晶了解决I C結合區之對位精度要的問題。 Η 土：目珂電子產-疋朝向更輕薄短小之趨勢發展加上其電子產品之功能也不斷增加’使得電子產品中 I/O數快速增加，因此其相對的封裝技術也必須不斷更新以因應實際需要，封裝技術由早期的插件式到表面黏著 (Surface Mounting Technology，SMT)，如以美國'466724 V. Description of the invention (l) [Field of the invention] The present invention relates to a structure using a carrier board and a method for manufacturing the same. The present invention relates to the difficulty in solving the problem of poor IC mounting. Solve the problem of the alignment accuracy of the IC bonding area. Η Soil: Mu Ke Electronics-疋 towards a trend of lighter, thinner and shorter, coupled with the increasing functions of its electronic products' makes the number of I / O in electronic products increase rapidly, so its relative packaging technology must also be constantly updated to respond to Actual needs, packaging technology from the early plug-in to surface mounting (SMT), such as the United States'

Fairchi Id公司提出的雙列直插式封裝（Dual·-In-Line Package，DIP)與美國德州儀器公司所發展之扁平封裝 (F 1 at Package, FP)為其代表；另外一最引人注目之打線式球格陣列（Ball Grid Array,BGA)封裝也隨之興起，這疋.一種以大·起狀的電極，排成格子狀以取代棚格陣列（P i η G r i d A r r a y，P G A )封裝的插腳（p i η)，栅格陣列（P G A)為一通孔封裝容易受到印刷載板之格子間距的限制，但球格陣列（BG A )是屬於一表面封裝，因此毫無限制，最適合小型且高I / 0密度的封裝，所以配合現今在高階產品最新技術之覆_-日日、..封+.裝（.F.C_h.i p)的興起’而...使得球...格.陣列..…(.B..G.A:...)-成為~3見^.封^^11忠趟主遮„、，但實際操.作中在使用覆晶載板Fairchi Id's dual-in-line package (DIP) and the flat package (F 1 at Package, FP) developed by Texas Instruments are the representatives; the other is the most striking Ball Grid Array (BGA) packaging has also emerged. This is a kind of large, raised electrodes arranged in a grid to replace the grid array (P i η Grid Array, PGA ) Package pins (pi η), grid array (PGA) is a through-hole package, which is easily limited by the grid pitch of the printed substrate, but the ball grid array (BG A) is a surface package, so there is no limit. Suitable for small and high I / 0 density packages, so in line with the latest technology in high-end products today _-day, .. seal +. The rise of .. (.F.C_h.ip) 'and ... make the ball. ..Grid.Array ..... (. B..GA: ...)-Become ~ 3 See ^. 封 ^^ 11 Loyalty to the main cover, but in practice, using a flip chip carrier board

466724 ，, —：——~~~-—- _________——------ 五 '發明說明（2) . 球格陣列（Flip Chip-Ball Garry Array, FCBGA)，於一航傳統現有技術製程及結構，在配合覆晶载板（F丨丨p Ch i P Substrate)於球格陣列封·裝時發現，習知球格陣列（BGA) 封秦結構上會產生有佈線空間緊迫、載板易變形 (Warpage)及防焊阻劑厚度變化太大造成ic封裂時黏著不良等問題，所以必須開發一種新的封裝結構及製造方法以提供解決對策。在習知結構上的一般覆晶載板通常為具有Μ 多層印刷電路板，如第一（Α)圖所示，其載板材7至8層的或有機材料，其中多層結構的線路導通，係為陶瓷丨屯Μ — 4¾ -或雷射鑽微小孔為之，再拉導線製作I 〇連接凸蛾鑽孔結合塾（Bump Pad ) ’此種統作法在線路飾局上（BUnip )的間’且相對於佈線密度及彈性上均將受極大限较估空須開發一種於雷.射鑽微小孔後以鍍鋼填孔方^ 1 °所以必ι .H、结，因此可直接在孔上直接形成，^ %成該線路吼大幅改荖％間及佈線彈性。 °佈線空由於I C封裝時，必須經過一高溫流程，二+ 載板會受熱變形，造成板翹或板扭的情形，此情況下裝晶片.於電性連接時連接不良’為改善^f造成IC封 S' 1CG文熱變 ^ 點，並配合上述佈線空間的改善，本發明提供〜·^的缺, 晶載板的結構，可達成在有限空間的限制.之;種微駔覆一支撐線路（Mesh Pattern)以增加載板抗另外毁計叫5$度，并 .迷縮小466724 ， ———————— ~~~ -—- _________——------ Five 'invention description (2). Flip Chip-Ball Garry Array (FCBGA), a traditional existing technology in Yihang The manufacturing process and structure are matched with the flip-chip carrier board (F 丨丨 p Ch i P Substrate) in the ball grid array package. It is found that the conventional ball grid array (BGA) Feng Qin structure will produce tight wiring space and easy carrier board. Deformation (Warpage) and the thickness of the solder resist are too large to cause problems such as poor adhesion during IC sealing. Therefore, a new package structure and manufacturing method must be developed to provide solutions. The general flip-chip carrier board in the conventional structure is usually a multilayer printed circuit board with M layers. As shown in the first (A) diagram, the carrier board has 7 to 8 layers or organic materials. For ceramics 丨 M 4— 4—or laser drill for micro holes, and then pull the wire to make I 〇 Connect the convex moth drilling 塾 (Bump Pad) 'This kind of unified method is used on the line decoration board (BUnip)' And relative to the wiring density and elasticity will be subject to extreme limits. It is necessary to develop a kind of lightning. After drilling small holes, fill the holes with steel plating ^ 1 ° so must be .H, knot, so it can be directly on the hole It is directly formed, and ^% into this line greatly improves the wiring and wiring flexibility. ° Wiring is empty. Because the IC package must go through a high temperature process, the second + carrier board will be deformed by heat, causing board warpage or board twisting. In this case, the chip is installed. Poor connection during electrical connection is caused by the improvement ^ f The IC package S '1CG is thermally changed, and in conjunction with the improvement of the above-mentioned wiring space, the present invention provides the lack of ~. ^, The structure of the chip carrier can achieve the limitation in a limited space. Among them; a kind of micro-covered support The line (Mesh Pattern) is called 5 $ degrees to increase the resistance of the carrier board.

五、發明說明（3) 挺^，解決乱裝不良的問日日載板在1C封裝製程巾，一般傳統習知的製作方法為在其嫁焊CSolder ReHow)時’於覆晶載板的表面為防止融化之焊錫流動而造成該IC中之錫橋短路，因此在載板表面會使用一於表面塗佈Epoxy感光防焊阻劑（s〇lde，，二=的處理方式，並在和IC中每—個1/〇的微小連接& 塊（Solder Bump)的地、區’形成精確的結合塾（^抑 ^d)，使之該結合墊得以和LC封裝時連之用。方式在微距高密度的覆晶載板上’特別是在Ic結合區之對位精度要求需在25# m以内之覆晶載板上，其.製造的困難度極 :’同時因製作防焊阻劑時’其.防谭阻劑厚度變化必須控 $在15〜45" ™之間，且同時將結合塾（Bump pad)如水井奴课埋在防焊阻劑中，這也會對10連接凸塊和載板間的連接會造成接.合不良的影響。本發明首揭提供一種微距覆晶載板的結構，如第一 (B)圖所示，其在結合墊（Bump pad)間，於金屬線路上直接形成金屬氧化防焊阻堤（B丨a c k 0 X i d e D a m)作為取代習知技術中之防焊阻劑之用，而且其結合墊間之防焊阻堤厚度大小可輕易的控制可在1〜3私m以下，使得該結合墊 (Bump pad)不會深埋在防焊阻劑中，.同時本發明在i C結合區也將不需要再受防焊阻劑對位精度之要求的限制’因此V. Description of the invention (3) Tightly, to solve the problem of random assembly, the daily carrier board is in a 1C packaging process towel. Generally, the conventional manufacturing method is 'on the surface of the flip chip carrier board when it is CSolder ReHow.' In order to prevent the short circuit of the solder bridge in the IC caused by the melted solder flow, a surface coated with Epoxy photosensitive solder resist (solode,, two =) is used on the surface of the substrate, and Each of the 1/0 micro-connected & blocks (Solder Bump) 's land and area' forms a precise bond (^ 抑 ^ d), so that the bond pad can be used in LC packaging. The way is The macro-density high-density chip-on-chip substrates, especially the chip-on-chip substrates with an alignment accuracy requirement of 25 # m in the Ic bonding area, are extremely difficult to manufacture. The thickness of the anti-tan resist must be controlled within the range of 15 ~ 45 " ™, and at the same time, a bonding pad (Bump pad) such as a water well slave is buried in the solder resist, which will also connect to 10 The connection between the bump and the carrier board will cause a bad connection. The first disclosure of the present invention provides a junction of a macro-chip flip-chip carrier board. As shown in the first figure (B), it directly forms a metal oxide solder resist barrier (B 丨 ack 0 X ide Dam) on the metal circuit between the bonding pads (Bump pads) as a substitute for the conventional technology. It is used as a solder resist, and the thickness of the solder resist bank between the bonding pads can be easily controlled. It can be less than 1 ~ 3 μm, so that the bonding pad (Bump pad) will not be buried in the solder resist. At the same time, the present invention will not need to be limited by the requirements of the positioning accuracy of the solder resist in the i C bonding area.

第6頁 466724 五、發明說明（4) 可解決I C結合區之對位精度要求的困難。外與本發明類/的技術為在金屬氧化阻層是以電滅化鎳層（Νΐϋ方式為之，其氧化錄層厚度為必須控 ίίΙ'Γ下，雖Α 本發明有類似之功能，但其缺其金屬線路對灌膠的附著力不高，因此^ ) 有相當大之影響，而本發明係在金屬線.=之可靠度會之金屬氧化防焊阻堤（Black 0xide Damn長忠織毛狀增加灌膠的附著力，對電路長期信托利用此方式會知之增加氧化鎳層為金屬層合/大助益，而習 |此胃峭加此功能。【發明目的】' 有基於上述習知技藝 . 技術佈線導通方式，β著、，本毛明提供一種由現有精度及線路製造困難度降改D其佈線彈性，同時對製造本發明提供一種由佈線彈】可^幅即省生產成本的目的；線路的結構設計，此設生改善可挪出空間增加補強結構本發明提供一種以線路達改善載板變形問題的目的；統之防焊阻劑結構以解製造金屬氧化防焊阻堤取代傳項目的可大幅提高J 拉、子度控制不易的問題，並配合前 J戒良品率。因此本發明提供— 搜微距覆晶載板的結構及其製造方 466724 五、發明說明（5) ' 法· _，包括下列步驟： •提供一载板（Substrate)步驟，係將該載板表面先形成第一金屬層’且該載板上預先形成一複數個載板#通孔，並於該第一金屬層表面與該載板通孔中形成—第一鍵金屬層；. •形成一内層線路步驟，係利用形成之乾膜將影像轉移，以當作罩幕蝕刻該第一鍍金屬層與該第—金屬層形成溝渠，未被银刻之部分形成該内層線路； •黑氧化内層線路步驟，係以氧化該内層線路的方式，形成一黑氧化内層線路層於該内層線路表面； ..形成一介電層與第二金屬層步驟，係以介電物質填入該载板通孔與該溝渠中，並覆蓋整個該内層線路，再於該介電面形成一金屬箱，之後將該金屬箱薄化形成該 • •以雷射·形成介電層通移形成一雷射光罩’並依此 (Laser Drilling)形成—複層通孔中形成一第二鍍金屬 Filled Copper)於該介電層屬層表面；孔步驟，係形成乾膜以影像轉雷射光罩之開口處以雷射鑽孔數個介電層通孔，並於該介電層’並填孔鍍銅（Plating 通孔中，之後整理該第二鍍金 •形成一線路層步驟 « π/ , a 雜a 驟係形成乾膜作為罩幕於該第二金屬層上形成一鎳金 Λ „ „ , ^ Ν1 /Au )層，再利用影像轉移蝕刻該Page 6 466724 V. Description of the invention (4) It can solve the difficulty of the alignment accuracy requirements of the IC bonding area. The technology similar to the present invention is that the metal oxide resistive layer is an electrically extinguished nickel layer (NZ method, and the thickness of the oxide recording layer must be controlled). Although the present invention has similar functions, but Its lack of metal lines does not have a high adhesion to the glue, so ^) has a considerable impact, and the present invention is based on the metal wire. = The reliability of the metal oxidation soldering barrier (Black 0xide Damn Changzhong wool) Increase the adhesion of the glue, for the long-term trust of the circuit, it will be known to increase the nickel oxide layer as a metal laminate / large benefit, and this feature is added to this stomach. [Objective of the invention] 'There is a technique based on the above-mentioned knowledge . Technical wiring conduction mode, β ,, Ben Maoming provides a method of reducing the wiring flexibility from the existing accuracy and circuit manufacturing difficulties, and at the same time provides a method of manufacturing the present invention by wiring bombs, which can save production costs. The structural design of the circuit, which can improve the space and increase the reinforcement structure. The invention provides a circuit to improve the problem of deformation of the carrier board; a unified solder resist structure to solve the manufacturing of metal oxide solder barriers The generation of the project can greatly improve the problem of J pull and the difficulty of controlling the degree, and cooperate with the former J. yield rate. Therefore, the present invention provides-search the structure of the chip-covered chip carrier and its manufacturer 466724 V. Description of the invention (5 ) 'Method · _, including the following steps: • Provide a substrate step (Substrate) step, the first metal layer is formed on the surface of the substrate' and a plurality of carrier plates # through holes are formed in advance on the substrate, and Forming a first bond metal layer on the surface of the first metal layer and in the through hole of the carrier board; • forming an inner layer circuit step, using the formed dry film to transfer the image to use as a mask to etch the first plating The metal layer and the first metal layer form a trench, and the inner layer circuit is formed by the portion that is not engraved with silver. The black oxide inner circuit step is to form a black oxide inner circuit layer on the surface of the inner circuit by oxidizing the inner circuit. ; .. the step of forming a dielectric layer and a second metal layer is to fill a through hole of the carrier board and the trench with a dielectric substance and cover the entire inner layer circuit, and then form a metal box on the dielectric surface, After that the metal box • Forming a laser mask by laser-forming dielectric layer migration and forming it according to (Laser Drilling)-forming a second metal-plated Filled Copper in the multilayer via hole Layer surface; the hole step is to form a dry film to convert the image of the laser reticle to the hole of the laser reticle by drilling several dielectric layer through holes, and fill the holes with copper (Plating through holes, and then Finishing the second gold plating • forming a circuit layer step «π /, a heteroa step is to form a dry film as a mask to form a nickel gold Λ„ „, ^ Ν1 / Au) layer on the second metal layer, and then reuse Image transfer etching

第二金屬層 '未被蝕刻夕却八L , 之部分形成該線路層； •形成一複數個防锂十，广，鮮阻劑區域步騍，係於該第二金屬The second metal layer 'is not etched, but it forms part of the circuit layer; it forms a plurality of lithium-proof ten, wide, and fresh resist areas, which are tied to the second metal.

466724 . I ........... ~~~— . _ ______ _ 五、發明說明（6) 層上之非i C結合區直接形成防銲阻劑區域； •形成一複數個黑氧化防銲阻堤步驟，係以一氧化方式直接形成該複數個黑氧化阻堤（β丨ack 〇x i de Dam )於該第二金屬層上； •封袭覆晶步驟，係灌膠（U n d e r f i 1 1)於I C底部，覆晶結合凸堍與該鎳金層電性連接，且電性導通於該覆晶載板通孔與謗介電層通孔中之線路。【本發明實施例之詳細說明】以下第二圖（A)〜（T)為本發明之一種微距覆晶載板的製造方法之實施例的詳細說明，包括下列之步驟：如弟二圖（A)〜（C )所示為提供一載板（Subs t r a t e )声驟’第二圖（A)為提供一載板2 0 1，該載板2 0 1可為一覆晶載板（Flip chip Substrate)，其中載板20 1材料係可為一466724. I ........... ~~~ —. _ ______ _ V. Description of the invention (6) The non-i C bonding area on the layer directly forms the solder resist area; • Forms a plurality of The black oxide solder barrier step is directly forming the plurality of black oxide barrier banks (β 丨 ack xi de Dam) on the second metal layer in an oxidizing manner; Underfi 1 1) At the bottom of the IC, the flip-chip bonding bumps are electrically connected to the nickel-gold layer, and are electrically connected to the lines in the flip-chip carrier board vias and the dielectric layer vias. [Detailed description of the embodiment of the present invention] The following second figures (A) to (T) are detailed descriptions of an embodiment of a method for manufacturing a macro-scale chip-on-chip carrier board of the present invention, including the following steps: (A) ~ (C) show the sound of providing a carrier board (Subs trate). The second picture (A) is to provide a carrier board 201, which can be a flip chip carrier board ( Flip chip Substrate), in which the carrier board 20 1 material can be a

Bismaleimide Triazine(BT)介電材料或為其它之有機材料甚至可為無機之陶瓷材料，且其厚度約為〇.丨〜〇. 4mm; 實施之方式係將該載板2 〇 1表面預先形成第一金屬層2 〇 2，且該第一金屬層2 0 2材料可為銅（Cu)，其厚度約為12" m; 且第二圖（B )為該載板2 0 l·上預先以一機械方式或雷射鑽孔形成一複數個載板通孔2 0 3，且該載複數個載板通孔2 〇 3之孔徑約.為1 〇〇〜2 5 0 // m;並第二围（c )於該第一金屬層2 0 2Bismaleimide Triazine (BT) dielectric material or other organic materials can even be inorganic ceramic materials, and its thickness is about 0.1 ~ 0.4 mm; the implementation method is to form the surface of the carrier board 201 in advance. A metal layer 202, and the material of the first metal layer 202 may be copper (Cu), and its thickness is about 12 "m; and the second figure (B) shows the carrier plate 20 A mechanical method or laser drilling forms a plurality of carrier board through-holes 203, and the hole diameter of the carrier carrier through-holes 203 is about .00 ~ 2 5 0 // m; and the first Enclosure (c) on the first metal layer 2 0 2

4 66 724 五、發明說明（7) 表面與該載板通孔2 0 3中形成一第一鍍金屬層2〇4，該第一鍍金屬層204材料可為銅（Cu)，且其厚度約為15# m。如第二圖（D )〜（E )所示為形成一内層線路步驟，第二圖（D)係利用形成之乾膜2 0 5 CD r y F i 1 m)將形成該内層線路之影像轉移，並以乾膜2 0 5當作罩幕（M a s k )姓刻去除部分之該第一鍍金屬層20 4與該第一金屬層20 2以形成溝渠 206(Trace)，如第二圖（)来被蝕刻且留下來之部分該第一鍍金屬層與該第一金屬層形成該内層線路。如..第二圖（F )所示為黑氧化（B1 a c k Ο X i d e)内層線路步驟’ I以氧化該内層線路之表面金屬的方式，形成—黑氧羼内層線路層20 7於該内層線路表面。如第二圖（G)〜（H)所示為形成一介電層舆第二金屬步驟，第二圖（G)係以介電物質以熱壓熱融方式填入該_ 板通孔與該溝渠中形成一介電層208，並覆蓋整個該^ 線路’其中該介電層2 0 8材料可為一 Bismaleimide Triazine，BT介電材料或其它介電材料，同時再於該介。層2 0 8表面結合一金屬箔2 0 9，該金屬領2 0 9材料可為鋼電 (Cu )，且其厚度約為1 2# m;第二圖（G )係將該金屬落薄化形成該第二金屬層2 0 9 a，且該金屬箔2 0 9經薄化來之該第二金屬層209 a厚度約為7〜9#m。 "" 2〇9 戍4 66 724 V. Description of the invention (7) A first metal plating layer 204 is formed on the surface and the carrier board through hole 203. The material of the first metal plating layer 204 may be copper (Cu) and its thickness It is about 15 # m. As shown in the second figure (D) ~ (E), the steps of forming an inner layer line are shown in the second figure (D). The formed dry film (2 0 5 CD ry F i 1 m) is used to transfer the image forming the inner layer line. And using the dry film 2 05 as a mask (M ask) to remove the first metallized layer 20 4 and the first metal layer 20 2 to form a trench 206 (Trace), as shown in the second figure ( ) To be etched and left part of the first metal plating layer and the first metal layer to form the inner layer circuit. For example, the second picture (F) shows the black oxide (B1 ack OX X ide) inner layer step 'I. By oxidizing the surface metal of the inner layer, a black oxide layer is formed on the inner layer. Line surface. As shown in the second figure (G) ~ (H), a step of forming a dielectric layer and a second metal is shown. The second figure (G) is filled with a dielectric substance by hot pressing and melting. A dielectric layer 208 is formed in the trench and covers the entire circuit. The material of the dielectric layer 208 may be a Bisaleimide Triazine, BT dielectric material, or other dielectric material, and then on the dielectric. A layer of metal foil 2 0 9 is bonded to the surface of layer 2 08. The material of the metal collar 2 0 9 can be steel (Cu), and its thickness is about 12 # m; the second figure (G) shows that the metal is thin The second metal layer 209 a is formed by chemical conversion, and the thickness of the second metal layer 209 a obtained by thinning the metal foil 209 is about 7 ~ 9 # m. " " 2〇9 戍

第10頁 h i S 7 2 4 五、發明說明（8) . 如第二圖（I )〜（Μ )所示為以雷射形成介電層通孔步驟’第二圖C I )係形成乾膜2 1 〇以影像轉移形成如第二圖 (J)中之雷射光罩21i(Laser Conformal)，並依此雷射光罩之開口（ Laser Conf orma 1 Open i ng)處，以雷射鑽孔 (Laser Dr i U ing)形成如第二圖（κ)之一複數個介電層通孔2 1 2其孔-徑約為1 0 〇/z ，並如第二圖（L)於該介電層通孔 21 2中及第二金.屬層2 〇 9 a上形成一第二鍍金屬層2丨3，並以電鐘方式填孔鍵銅2丨4(Plating Filled Copper )於該介電層通孔中，第二圖（Μ )罵-¾理該第二鍍金屬層2丨3表面，且整理該第二鍍金屬層2 1 3係以薄化處理，而露出形成該第二金屬層2 0 9a，其厚度仍約為7〜9# m。如第二圖（N.)〜（R)所示為形成一線路層步驟，第二圖 (N)係形成乾膜214作為罩幕，第二圖（〇)於該第二金屬層上未被乾膜214覆蓋之處形成一鎳金（Ni/Au)層21 5，該鎳拿層21 5是以電鍍方式形成，其形成之厚度約為m，且以該錄金層215作為覆晶結合凸塊之連接區；第二圖（p)再 ^用一乾膜歷合技術或液態光阻劑塗伟作為罩幕2 1 6，接著如第.二圖（q)之影像轉移製作217,最後再如第二圖（R) 钱刻該第二金屬層2丨8，未被蝕刻之部分形成該線路層，其中該線路層除了導通電性以外，可同時另外設計形成一，樓線路（M e s h P a ΐ t e r η)以增加載板抗曲強度，並縮小因鍵'熱變形而形成之板翹或板扭量。Page 10 hi S 7 2 4 V. Description of the invention (8). As shown in the second figure (I) ~ (M), the step of forming a dielectric layer through hole by laser (the second figure CI) is to form a dry film 2 1 〇 The laser mask 21i (Laser Conformal) shown in the second figure (J) is formed by image transfer, and the laser mask (Laser Conf orma 1 Open i ng) is used to drill holes ( Laser Dr i U ing) forms a plurality of through holes 2 1 2 of the dielectric layer as shown in one of the second picture (κ), the hole-diameter is about 100 / z, and as shown in the second picture (L) on the dielectric A second metal plating layer 2 丨 3 is formed on the layer through-hole 21 2 and the second metal. The metal layer 2 09a, and the hole-bonding key copper 2 丨 4 (Plating Filled Copper) is formed in the dielectric by an electric clock. In the layer through hole, the second picture (M) scolds the surface of the second metallized layer 2 丨 3, and arranges the second metallized layer 2 1 3 to be thinned to expose the second metal. Layer 2 0a, its thickness is still about 7 ~ 9 # m. As shown in the second figures (N.) to (R), the steps for forming a circuit layer are shown in the second figure (N). A dry film 214 is formed as a mask. The second figure (0) is not formed on the second metal layer. A nickel / gold (Ni / Au) layer 21 5 is formed at the place covered by the dry film 214. The nickel pick-up layer 21 5 is formed by electroplating, and the thickness of the formed layer is about m, and the gold recording layer 215 is used as a flip chip. Combine the connection area of the bumps; the second picture (p) and then use a dry film calendar technology or liquid photoresist Tu Wei as the mask 2 1 6 and then the image transfer production as shown in the second picture (q) 217, Finally, as shown in the second figure (R), the second metal layer 2 丨 8 is engraved. The unetched portion forms the circuit layer. In addition to the electrical conductivity, the circuit layer can also be designed to form another circuit at the same time. M esh P a ΐ ter η) to increase the flexural strength of the carrier plate and reduce the amount of plate warpage or plate twisting caused by the thermal deformation of the bond.

/ ^ΒΊ2Λ 五、發明說明（9) 如第二圖（S )所示為形成一複數個防銲阻劑區域步驟’儀於該第二金屬層上之非I c結合區直接形成防銲阻劑區域2 1 9，該防銲阻劑2 1 9可為一表面塗佈之Epoxy感光防焊阻劑。如第二圖（T )所示為形成一複數個黑氧化防銲阻.¾步驟’係以一氧化方式直接於未被餘刻之部分該第二金屬層表面’形成該複數個黑氧化阻堤22 0 (Black Oxide Dam)於該第二金屬層209a上，該複數個異氧化阻堤22 0厚度約為I 〜3μ m以下。如第二圖（U)所示封裝覆晶步驟，係灌膠（Underi i 1 1 ) 2 23於I C2 2 2底部，覆晶·結合凸塊221與該鎳.金層2.1 5電性連接，且電性導通於該覆晶載板與該介電層通孔中之線路，且連接至BGA錫球2 2 4上。· 如第三圖所示為本發明一種微距覆晶載板的結構示意圖，包括：一載板（Substrate)301，該載板表面係預先形成第一金屬層302，且其第一金屬層3 0 2厚度約為1 2# πι ’ 且該載板上預先形成一複數個載板通孔303 ’該載複數個載板通孔3 0 3之礼徑約為1 0 0〜2 5 0# m ’並於該第一金屬層 3 0 2表面與該載板通孔3 0 3中形成一第一鍍金屬層3 0 4 ’其厚度約為1 5从m; 一内層線路，係蚀刻該第一鍵金屬層3 〇 4 與該第一金屬層3 0 2形成溝渠3 0 6，未被姓刻之部分形成該/ ^ ΒΊ2Λ V. Description of the invention (9) As shown in the second figure (S), the steps of forming a plurality of solder resist areas are formed on the non-I c bonding area on the second metal layer to directly form a solder resist. 2 1 9, the solder resist 2 1 9 can be a surface-coated Epoxy photosensitive solder resist. As shown in the second figure (T), a plurality of black oxide solder resists are formed. ¾ The step is to form the plurality of black oxide resists directly on the surface of the second metal layer by an oxidation method. A bank 22 0 (Black Oxide Dam) is on the second metal layer 209 a. The thickness of the plurality of different oxidation barrier banks 22 0 is about 1 to 3 μm. As shown in the second figure (U), the chip-on-package step is underfilling (Under i 1 1) 2 23 at the bottom of I C2 2 2. The chip-on-bonding bump 221 is electrically connected to the nickel-gold layer 2.15. And is electrically connected to the lines in the flip-chip substrate and the through hole of the dielectric layer, and is connected to the BGA solder ball 2 2 4. As shown in the third figure, a schematic diagram of a macro-chip flip-chip carrier board according to the present invention includes a substrate 301. The surface of the carrier board is formed with a first metal layer 302 in advance, and the first metal layer The thickness of 3 0 2 is about 1 2 # π ′, and a plurality of through-board holes 303 ′ are formed in advance on the carrier board 303 ′ The courtesy diameter of the plurality of through-board holes 3 0 3 is about 1 0 0 ~ 2 5 0 # m 'and form a first metal plating layer 3 0 4 on the surface of the first metal layer 3 2 and the through hole 3 0 3 of the substrate, and its thickness is about 15 from m; an inner layer circuit, which is etched The first bond metal layer 3 0 4 and the first metal layer 3 0 2 form a trench 3 0 6, and the portion not engraved with the last name forms the trench 3 0 6.

第12冥五、發明說明（ίο) : —- 内層線路，黑氧化内層3 0 7線路，係於該内層線路表面；一介電層、，係以介電物質3〇8填入該載板通孔3〇3與該溝渠3 0 6中，並覆蓋整個該内層線路形成，再於該介電層 3 0 8表面形成一金屬箔309,其金屬箔厚度約為12" m，之後再將該金屬箔30 9薄化形成一第二金屬層3〇9a，該第二金屬層3 0 9 a厚度約為7〜9以一複數個介電層通孔312，該以雷射鑽孔之通孔的孔徑約為i 〇 m，且於該介電層通孔312中形成一第二鍍金屬層313，並填孔鍍銅（151^丨叩 Filled Copper)於該介電層通孔.312中；一線路層，係於該第二金屬層3 0 9a上形成一鎳金層3丨5作為與覆晶結合凸塊與該鎳金層31 5電性連接之用，該鎳金層3i5厚度約為5 # m，再蝕刻去除部份之該第二金屬層3〇9a形成該線路層，該線路層同時另外形成一支撐線路（Mesh pattern)以增力:載板抗曲強度，並縮小因受熱變形而形成之板翹或板扭量；.一複數個防銲阻劑區域3丨9，係於該第二金屬層 3 0 9 a^L之非I C結合區直接形成防銲阻劑區域3丨9; 一複數，黑氧化防鲜阻堤，係以—氧化方式直接形成該複數個黑氧=阻堤3 2 0 (Black Oxide Dam)於該第二金屬層20 9a上， «亥複數個黑氧化阻堤3 2 0厚度約為1〜3# m以下。經由以上本發明之一實施例與「現有技術」比較，本發明有著以下之優點： — 1.本發明所提供之黑氧化層阻堤（Black 〇xide 口㈣）的製Twelfth, fifth, description of the invention (ίο): --- inner layer circuit, black oxide inner layer 3 07 circuit, is attached to the surface of the inner layer circuit; a dielectric layer, is filled with a dielectric substance 308 on the carrier board A through hole 3 03 and the trench 3 06 are formed to cover the entire inner layer circuit, and then a metal foil 309 is formed on the surface of the dielectric layer 3 0 8 with a thickness of about 12 " m. The metal foil 309 is thinned to form a second metal layer 309a. The thickness of the second metal layer 309a is about 7-9. A plurality of dielectric layer vias 312 are formed by laser drilling. The hole diameter of the through hole is about i 0 m, and a second metal plating layer 313 is formed in the dielectric layer through hole 312, and copper (151 ^ 丨叩 Filled Copper) is filled in the dielectric layer through hole. 312; a circuit layer is formed on the second metal layer 309a to form a nickel-gold layer 3 丨 5 for electrically connecting the flip-chip bonding bump to the nickel-gold layer 3315, the nickel-gold layer The thickness of 3i5 is about 5 # m, and then a portion of the second metal layer 309a is etched to form the circuit layer. The circuit layer also forms a support line (Mesh pattern) to increase the strength: the carrier board Flexural strength, and reduce the amount of plate warpage or torsion caused by thermal deformation; a plurality of solder resist areas 3 丨 9 are directly connected to the non-IC bonding area of the second metal layer 3 0 9 a ^ L A solder resist area 3 丨 9 is formed; a plurality of black oxide anti-fresh barriers are directly formed in a oxidative manner by a plurality of black oxygen = barriers 3 2 0 (Black Oxide Dam) on the second metal layer 20 On 9a, the thickness of the plurality of black oxide barriers 3 2 0 is about 1 to 3 # m. By comparing one embodiment of the present invention with the “existing technology” described above, the present invention has the following advantages: — 1. The black oxide layer barrier (Black Oxide port) provided by the present invention

五、發明說明U]) 作’為在非結合墊（N〇n-Bump Pad)的線路上生成該熏氧化層’县可以降低該阻堤厚度’並作為提供相當習知於一般過高之防焊阻劑的功能。但相較習知使用之防焊阻劑的精確對位’應控制在+/-25^ m的需求下，可輕易取得50// m 的裕度（A1 i g nm e n t Τ ο 1 e r a η c e) ’同b夺本發明以鐵銅填孔方式楚.成該線路導通結構的設計可減少佈線數目，對Bump P a d s P i t c h縮小約5 0 # m ’可更增加其佈線密度，使佈線空間廣，造成有空.間設計補強載板變形的金屬.線路補強網（Mesh Pattern),使覆晶封裝良品率提高的結構及設計。 2.本發明所形成之黑氧化層（B 1 a c k Ο X i d e )的厚度約為1〜 .3/z m，可提供相較於習知使用之防焊阻劑厚度控制在 + /-25/^ m的需求下，更清晰的形狀及解析度，且其對位精度更可容易控制在20/z m以下。深似留類殘構有結留其易因容中 ’ 程部過底造的製墊在合劑結阻小焊微防度光密感高中極藝在技而知因習，’黑 3 井物之用使所明發本而響。影生大產極之有題會問率此良免裝避封全對完物可留層殘化此氧 4.利用黑軋化防焊阻堤B i a c k Ο χ i d e D am (或相類似金屬表面氧化製程）作為高密度覆晶.連接凸塊在；[c封裝焊接過程替習知之焊錫阻劑的應用。並其結合墊（Bump Pad)上V. Description of the invention U]) is used as 'for generating the fumigated oxide layer on the non-bump pad' line. 'Country can reduce the thickness of the bank' and serves as a fairly familiar general over-high. Function of solder resist. However, compared with the precise alignment of the conventional solder resist, the margin should be controlled at +/- 25 ^ m, and a margin of 50 // m can be easily obtained (A1 ig nm ent Τ ο 1 era η ce ) 'Same as the present invention, the method is to fill the hole with iron copper. The design of the conductive structure of the line can reduce the number of wirings, and reduce the Bump P ads Pitch by about 50 0 # m' can increase its wiring density and make wiring space The structure and design of the metal and line reinforcement mesh (mesh pattern) that are designed to reinforce the deformation of the carrier board in free time and space, so as to improve the yield of the flip-chip package. 2. The thickness of the black oxide layer (B 1 ack Ο X ide) formed by the present invention is about 1 ~ .3 / zm, which can provide a thickness of +/- 25 / compared to the conventionally used solder resist. ^ m requirements, clearer shape and resolution, and its alignment accuracy can be easily controlled below 20 / zm. Deeply similar to the residual structure, the structure is easy to leave due to the middle of the process. The cushion made by the process department at the bottom of the mixture is small, the resistance is small, the light resistance is high, the light density is high. Use it to make the announcement sound. There is a problem in the shadow production pole, and the question rate is good, avoiding, avoiding, sealing, and leaving the remaining layer to complete the residual oxygen. 4. The use of black rolling solder barrier B iack 〇 χ ide D am (or similar metals Surface oxidation process) as a high-density flip-chip. The connection bump is in the [c package soldering process instead of the conventional solder resist application. And its bonding pad (Bump Pad)

第14頁 466724 五 '發明說明（12) 鍍錄金層之厚度約為m，其中金屬氧化阻堤（Black Ο X i d e D a m )低於結合墊，相較以現有技術防焊阻劑厚度大小約為2 5" m仍高於結合墊的結構，因此在覆晶結合凸塊（F 1 i p C h i p B u m p i n g )封裝其結合性對於高良率及長期信賴度方面有非常優越的改善。 • . · 5 .現有習知之封裝大都以錫錯凸塊（S ο 1 d e r B u m p )結合技術為之，未來必須配合環保述求改為無鉛技術，而本發明所揭露、各黑_氧化防焊阻堤仍可配合'運用無誤。因此，本發明之『一種微距覆晶載板的結構及其製造方法』，確能藉所揭露之技藝，達到所預期之目的與功效，符合發明專利之新穎性，進步_性與產業利用性之要件。 -_ 惟，以"上所揭露之圖式及說明，僅為本發明之較-佳實施例而已=非為用以限定本發明之實施，大凡熟悉該項技藝之人士其所依本發胡之精神，所作之變化或修飾，皆應涵盖在以下本案之申請專利範圍内。Page 14 466724 Five 'invention description (12) The thickness of the gold plating layer is about m, in which the metal oxide barrier (Black 〇 X ide D am) is lower than the bonding pad, compared with the thickness of the prior art solder resist About 2 " m is still higher than the structure of the bonding pad, so the bonding performance of the flip-chip bonding bump (F1ipChipBumping) package is very superior in terms of high yield and long-term reliability. •. · 5. The conventionally known packages are mostly based on the combination of tin bumps (S ο 1 der Bump). It must be changed to lead-free technology in accordance with environmental protection requirements in the future. Welding dyke can still cooperate with 'use without error. Therefore, the "structure of a macro-scale chip-on-chip carrier board and its manufacturing method" of the present invention can indeed achieve the desired purpose and effect by the disclosed technology, which is consistent with the novelty, progress, and industrial use of invention patent Essentials of Sex. -_ However, the drawings and descriptions disclosed above are only comparatively preferred embodiments of the present invention. They are not intended to limit the implementation of the present invention. Anyone who is familiar with the technology will rely on this issue. Hu's spirit, changes or modifications should be covered by the scope of patent application in the following case.

第]5頁 46 6 724 圖式簡單說明【圖式簡單說明】第一( A )圖為習知覆晶載板結構不意圖第一（B )圖為本發明之微距覆晶載板結構示意圖第二圖（A )〜（U )為本發明之一種微距覆晶載板的製造方法之實施例的詳細說明示意圖第三圖為本發明實施例之微距覆晶載板的結構示意圖【圖號說明】載板 201 301 第一金屬層 202 302 載板通孔 203 3 0-3 第一鍍金屬層 204 304 乾膜（Dry Fi lm) ； 205 溝渠（Trace) 206 306 黑氧化金屬内層線路層 207 307 介電層 208 308 金屬箔 - 209 309 第二金屬層 2 0 9a 3 0 9 a 乾膜 210Page] 5 46 6 724 Brief description of the drawings [Simplified description of the drawings] The first (A) picture shows the structure of the conventional flip chip carrier. The first (B) picture shows the structure of the macro flip chip carrier of the present invention. The second diagram (A) ~ (U) is a detailed description of an embodiment of a method for manufacturing a macro-scale chip-covered substrate of the present invention. The third diagram is a schematic diagram of the structure of the macro-scale chip-covered substrate of the embodiment of the present invention. [Illustration of drawing number] Carrier board 201 301 First metal layer 202 302 Carrier board through hole 203 3 0-3 First metal plating layer 204 304 Dry film; 205 Trench 206 306 Black oxide metal inner layer Circuit layer 207 307 Dielectric layer 208 308 Metal foil-209 309 Second metal layer 2 0 9a 3 0 9 a Dry film 210

第]6頁 466724 圖式簡單說明雷射光罩（Laser Conformal) 211 介電層通孔 212 第二鍍金屬層 213 填孔經銅（Plating Filled Copper 鎳金（Ni/Au)層罩幕影像轉移製作敍刻該第二金屬.層防銲阻劑區域黑氧化阻堤覆晶結合凸塊 1C 灌膠 CUnderf i 1 1 ) B G A錫球 312 313 315 214 215 216 217 218 219 319 220 320221 222 223 224Page] 6 466724 Schematic description of Laser Conformal 211 Dielectric layer through hole 212 Second metal plating layer 213 Plating Filled Copper Ni / Au layer mask image transfer production Describe the second metal. The layer of solder resist area, black oxide barrier, flip chip bonding bump 1C, potting Cunderf i 1 1) BGA solder ball 312 313 315 214 215 216 217 218 219 319 220 320221 222 223 224

第丨7頁Page 丨 7

Claims

89125977 月日· 絛正 1. 一種微距覆晶載板的製造方法，包括： .提供一載板（Substrate)步驟，係將該載板表面預先形成第一金屬層，且該载板上預先形成一複數個载板通孔，並於該第一金屬層表面與該載板通孔中形成一第一鍵金屬層； •形成一内層線路步驟，係利用形成之乾膜將影像轉移，以當作罩幕蝕刻該第一鍍金屬層與該第一金屬層形成溝渠，未被蝕刻之部分形成該内層線路； •黑氧化内層線路步驟，係以氧化該内層線路的方式，形成一黑氧化内層線路層於該内層線路表面； •形成一介電層與第二金屬層步驟，係以介電物質填入該載板通孔與該溝渠中，並覆蓋整個該内層線路，再於該介電層表面形成一金屬箔，之後將該金屬箔薄化形成該第二金屬層； .以雷射形成介電層通孔步驟，係形成乾膜以影像轉移形成一雷射光罩，並依此雷射光罩之開口處以雷射鑽孔 (laser Drilling)形成一複數個介電層通孔，並於該介電層通孔中形成一第二鍍金屬層，並填孔鑛銅（pla1;ing Filled Copper)於該介電層通孔中，之後整理該第二鍍金屬層表面； •形成一線路層步驟，係形成乾膜作為罩幕於該第二金屬層上形成一鎳金（Ni/Au)層，再利用影像轉移蝕刻該第二金屬層’未被蝕刻之部分形成該線路層； •形成一複數個防銲阻劑區域步驟，係於該第二金屬89125977 month · Zheng Zheng 1. A method for manufacturing a macro-chip flip-chip carrier board, comprising:. Providing a substrate step, in which a first metal layer is formed on the surface of the carrier board in advance, and the carrier board is provided in advance Forming a plurality of through-holes of the carrier board, and forming a first bond metal layer on the surface of the first metal layer and the through-holes of the carrier board; • the step of forming an inner layer circuit, using the formed dry film to transfer the image to The first metal plated layer is etched as a mask to form a trench with the first metal layer, and the unetched portion forms the inner layer circuit. The step of black oxide inner layer is to form a black oxide by oxidizing the inner layer circuit. The inner circuit layer is on the inner circuit surface; the step of forming a dielectric layer and a second metal layer is to fill the through hole of the carrier board and the trench with a dielectric substance, and cover the entire inner circuit, and then to the dielectric layer. A metal foil is formed on the surface of the electrical layer, and then the metal foil is thinned to form the second metal layer. The step of forming a through-hole of the dielectric layer by laser is to form a dry film for image transfer to form a laser mask, and follow this mine A plurality of through holes of the dielectric layer are formed by laser drilling at the opening of the photomask, and a second metal plating layer is formed in the through holes of the dielectric layer, and pore copper (pla1; ing Filled) is formed. Copper) in the through hole of the dielectric layer, and then finishing the surface of the second metal plating layer; the step of forming a circuit layer is to form a dry film as a mask to form a nickel-gold (Ni / Au) layer on the second metal layer; ) Layer, and then use image transfer to etch the unetched portion of the second metal layer to form the circuit layer; • forming a plurality of solder resist region steps, tied to the second metal

第18頁 2001.10. 04.018 466724 修正案號 89125977 六、申請專利範圍層上之非I C結合區直接形成防銲阻劑區域； .形成一複數個黑氧化防銲阻堤步驟，係以·一氧化方式直接形成該複數個黑氧化阻堤（Black Oxide Dam)於該第二金屬層上； •封裝覆晶步驟，係灌膠（Underfill)於1C底部，覆晶結合凸塊與該鎳金層電性連接，且電性導通於該覆晶載板通孔與該介電層通孔中之線路。 2 .如申請專利範圍第1項所述之製造方法，其中該提供一載板（Substrate )步驟中，載板材料係可為— Bismaleimide Triazine(BT)介電材料或為其它之有機材料甚至可為無機之陶瓷材料，且其厚度約為〇.丨〜〇. 4mm。 3.如申請專利範圍第丨項所述之製造方法，其中該提供一載板（Substrate )步驟中，載板表面預先形成之該第一金屬層材料可為銅（Cu)，且其厚度一12以[ its”範圍第1項所述之製造方法，其中該提供- t板jSUbStIate)步驟中，載板卫—預先形成該複數個載板通孔係以一機械方式哎雷射错丨w戟极 u丨夕：?丨你的*飞双田射鑽孔形成’且該載複數個載板通孔之孔徑約為1 0 0〜2 5 0〆m。圍，1項所述之-製造方法，其中該形成-" ，载板通孔中形成之該第一鍍金屬層材料Page 18 2001.10. 04.018 466724 Amendment No. 89125977 6. The non-IC bonding area on the layer of the patent application directly forms the solder resist area;. Forms a plurality of black oxide solder barrier steps, which are based on the oxidation method Forming the plurality of Black Oxide Dams directly on the second metal layer; • The step of encapsulating the chip, which is underfill at the bottom of the 1C, and the chip combines the electrical properties of the bump and the nickel-gold layer Are connected, and are electrically connected to the lines in the through hole of the flip chip substrate and the through hole of the dielectric layer. 2. The manufacturing method described in item 1 of the scope of patent application, wherein in the step of providing a substrate, the material of the substrate may be-Bismaleimide Triazine (BT) dielectric material or other organic materials or even 4mm。 Inorganic ceramic material, and its thickness is about 〇. 丨 ~ 〇. 4mm. 3. The manufacturing method according to item 丨 of the patent application scope, wherein in the step of providing a substrate, the first metal layer material formed in advance on the surface of the substrate may be copper (Cu), and the thickness thereof is [12] The manufacturing method described in [its] range item 1, wherein in the step of providing -t board jSUbStIate), the carrier board-pre-formed the plurality of carrier board through holes is mechanically shot wrongly w极极 u 丨夕:? 丨 Your * Fei Shuangtian shot drill hole is formed ', and the hole diameter of the plurality of carrier board through holes is about 1 0 ~ 2 5 0〆m. Manufacturing method, wherein the formation of the first metal plating layer material formed in the through hole of the carrier plate

第19頁 2001.10. 04.019 _案號 89125977_年月日_iti_ 六、申請專利範圍可為銅（Cu)，且其厚度約為15μ m。 6 .如申請專利範圍第1項所述之製造方法，其中該介電層材料可為一 Bismaleimide Triazine，BT介電材料或其它介電材料。 7. 如申請專利範圍第1項所述之製造方法，其中該形成一介電層與第二金屬層步驟中，介電層表面形成之該金屬箔材料可為銅（Cu)，且其厚度約為12# m。 8. 如申請專利範圍第.7項所述之製造方法，其中該金屬箔經薄化形成之該第二金屬層厚度約為7〜9 μ m。 9 .如申請專利範圍第1項所述之辱造方法，其中該以雷射形成介電層通孔步驟中，該介電層通孔之孔徑約為1 0 0 # m，且整理該第二鍍金屬層表面係以薄化處理該第二金屬層厚度約為7〜9以m。 1 〇 .如申請專利範圍第1項所述之製造方法，其中該形成線路步驟中，該鎳金層是以電鍍方式形成，其形成之厚度約為5μ m，且以該鎳金層作為覆晶結合凸塊之連接區。 1 1 .如申請專利範圍第1項所述之製造方法，其中該形成線路步驟中，影像轉移蝕刻該第二金屬層係以一乾膜壓合技Page 19 2001.10. 04.019 _ case number 89125977_ year month_iti_ Sixth, the scope of patent application can be copper (Cu), and its thickness is about 15 μm. 6. The manufacturing method according to item 1 of the scope of patent application, wherein the dielectric layer material can be a Bismaleimide Triazine, BT dielectric material or other dielectric material. 7. The manufacturing method according to item 1 of the scope of patent application, wherein in the step of forming a dielectric layer and a second metal layer, the metal foil material formed on the surface of the dielectric layer may be copper (Cu), and its thickness It is about 12 # m. 8. The manufacturing method as described in item .7 of the scope of patent application, wherein the thickness of the second metal layer formed by thinning the metal foil is about 7 ~ 9 μm. 9. The manufacturing method as described in item 1 of the scope of the patent application, wherein in the step of forming a dielectric layer through hole by laser, the diameter of the dielectric layer through hole is about 100 #m, and the first The surface of the second metal plating layer is thinned. The thickness of the second metal layer is about 7 to 9 m. 10. The manufacturing method according to item 1 of the scope of the patent application, wherein in the step of forming the circuit, the nickel-gold layer is formed by electroplating, and the thickness of the nickel-gold layer is about 5 μm, and the nickel-gold layer is used as a coating. The bonding area of the crystal bonding bump. 1 1. The manufacturing method as described in item 1 of the scope of patent application, wherein in the step of forming the line, the image transfer etching of the second metal layer is performed by a dry film lamination technique.

第20頁 2001.10. 04. 020 66724 Λ_η 修正曰 Γ7Τ^--Μ25971 俶/專利範圍 I街或液绳IR I 〜光阻劑塗佈作為罩幕蝕刻 1 2 .如申地胃 I線路層步明驟專利範圍第1項所述之製造方法，其中該形成一形成一支^中，該線路層除了導通電性以外，可同時另外縮小因成j線路（Mesh Pattern)以増加載板抗曲強度’並 1 又熟變形而形成之板翹或板扭量。 |i3數"專利範圍第1項所述之製造方法，其中該形成一 1之Epoxv# 1阻劑區域步驟中，該防銲阻劑可為一表面塗佈 xy感光防焊阻劑。請Λ利範圍第1項所述之製造方法’其中該形成一黑軋化防銲阻堤步驟中，該複數個黑氧化阻堤厚度 i’j馮1〜3um以下。 I 15.—種微距覆晶載板的結構，包括： •一载板（Substrate)，該載板表面係預先形成第一 |金屬層’且該載板上預先形成一複數個載板通孔，並於該第一金屬層表面與該載板通孔中形成一第一鍍金屬層； I •一内層線路，係蝕刻該第一鍍金屬層與該第一金屬 |層形成溝渠，未被蝕刻之部分形成該内層線路； •一黑氧化内層線路，係於該内層線路表面；一介電層，係以介電物質填入該載板通孔與該溝渠中’並覆蓋整個該内層線路形成，再於該介電層表面形成 m 酬第21頁 2001.10. 04. 021 466724 _案號89125977_年月日修正_ 六、申請專利範圍一金屬箔之後，再將該金屬箔薄化形成一第二金屬層； •—複數個介電層通孔，且於該介電層通孔中形成一第二鑑金屬層，並填孔鐘銅（Plating Filled Copper)於該介電層通孔中； .一線路層，係於該第二金屬層上形成一錄金層，且蝕刻部份之該第二金屬層形成； •一複數個防銲阻劑區域，係於該第二金屬層上之非 I C結合區直接形成防銲阻劑區域； •—複數個黑氧化防銲阻堤，係以一氧化方式直接形成該複數個黑氧化阻堤（B 1 a c k 0 X i d e D a m )於該第二金屬層上。 1 6 .如申請專利範圍第1 5項所述之結構，其中載板材料係可為一 Bismaleimide Triazine(BT )介電材料或為其它之有機材料甚至可為無機之陶瓷材料，且其厚度約為0. 1〜 0. 4mm 〇 1 7 .如申請專利範圍第1 5項所述之結構，其中該載板表面之該第一金屬層材料可為銅（Cu)，且其厚度約為12// m。 1 8.如申請專利範圍第1 5項所述之結構，其中該載板上之該複數個載板通孔係以一機械方式或雷射鑽孔形成，且該載複數個載板通孔之孔徑約為100〜2 5 0/z m。Page 20 2001.10. 04. 020 66724 Λ_η Correction: Γ7Τ ^-M25971 俶 / Patent range I street or liquid rope IR I ~ Photoresist coating as a mask etching 1 2. As shown in Figure 1 The manufacturing method described in the first patent range, wherein the forming layer is formed into a branch, in addition to the electrical conductivity, the circuit layer can also reduce the j-circuit (Mesh Pattern) to increase the flexural strength of the loading plate. '和 1 The amount of plate warp or plate twist formed by ripening and deformation. | i3 # The manufacturing method described in item 1 of the patent range, wherein in the step of forming a 1 Epoxv # 1 resist region, the solder resist may be a surface coated with an xy photosensitive solder resist. Please refer to the manufacturing method ′ described in the first item of the Λ Lee range, wherein in the step of forming a black rolling solder barrier, the thickness of the plurality of black oxide barriers i′j is 1 to 3 μm or less. I 15. A structure of a macro-chip flip-chip carrier board, including: a substrate, the surface of the carrier board is formed with a first | metal layer in advance and a plurality of carrier boards are formed in advance on the carrier board. Hole, and a first metal plating layer is formed on the surface of the first metal layer and the through hole of the carrier board; I • an inner layer circuit, which etches the first metal plating layer and the first metal layer to form a trench, The etched part forms the inner layer circuit; a black oxide inner layer circuit is attached to the surface of the inner layer circuit; a dielectric layer is filled with a dielectric substance into the through hole of the carrier board and the trench and covers the entire inner layer The circuit is formed, and then the m layer is formed on the surface of the dielectric layer. Page 21 2001.10. 04. 021 466724 _ Case No. 89125977 _ year month day amendment _ Sixth, after applying for a metal foil, the metal foil is thinned to form A second metal layer; a plurality of through holes of the dielectric layer, and a second metal layer is formed in the through holes of the dielectric layer, and a plated filled copper is formed in the through holes of the dielectric layer; Medium; a circuit layer tied to the second metal layer A gold layer is recorded, and the second metal layer of the etched part is formed; • a plurality of solder resist regions, the non-IC bonding regions on the second metal layer directly form solder resist regions; The plurality of black oxide solder barriers are directly formed on the second metal layer in an oxidative manner by the plurality of black oxide barriers (B 1 ack 0 X ide D am). 16. The structure described in item 15 of the scope of the patent application, wherein the carrier material can be a Bisaleimide Triazine (BT) dielectric material or other organic material or even an inorganic ceramic material, and its thickness is about 0. 1 ~ 0. 4mm 〇1 7. The structure described in item 15 of the scope of patent application, wherein the material of the first metal layer on the surface of the carrier board may be copper (Cu), and the thickness is about 12 // m. 1 8. The structure described in item 15 of the scope of patent application, wherein the plurality of through-holes of the carrier plate are formed by a mechanical method or laser drilling, and the plurality of through-holes of the carrier plate are formed The pore diameter is about 100 ~ 2 5 0 / zm.

第22頁 2001, 10. 04.022 6 724 案號 89125977 年月曰修正六、申請專利範圍 1 9 .如申請專利範圍第1 5項所述之結構，其中該載板通孔中形成之該第一鍍金屬層材料可為銅（Cu)，且其厚度約為 15/z m。 2 0 .如申請專利範圍第1 5項所述之結構，其中該介電層材料可為一 Bismaleimide Triazine，BT介電材料或其它介電材料。 2 1.如申請專利範圍第1 5項所述之結構，其中該介電層通孔之孔徑約為100# m，且該介電層表面形成之該金屬箔材料可為銅（Cu)，且其厚度約為1 2/z m。 2 2 .如申請專利範圍第2 1項所述之結構，其中該金屬箔經薄化形成之該第二金屬層厚度約為7〜9μ ra。 2 3.如申請專利範圍第1 5項所述之結構，其中該鎳金層是以電鍍方式形成，其形成之厚度約為5# m，且以該鎳金層作為覆晶結合凸塊之連接區。 2 4.如申請專利範圍第1 5項所述之結構，其中該線路層係以蝕刻部份之第二金屬層，且是以一真空乾膜壓合技術或液態光阻劑塗佈作為罩幕银刻形成。 2 5 .如申請專利範圍第1 5項所述之結構，其中該線路層除Page 22 2001, 10. 04.022 6 724 Case No. 89125977 Amendment VI. Patent application scope 19. The structure described in item 15 of the patent application scope, wherein the first formed in the through hole of the carrier board The metal plating material may be copper (Cu), and its thickness is about 15 / zm. 20. The structure described in item 15 of the scope of patent application, wherein the dielectric layer material may be a Bismaleimide Triazine, BT dielectric material or other dielectric material. 2 1. The structure as described in item 15 of the scope of patent application, wherein the hole diameter of the through hole of the dielectric layer is approximately 100 # m, and the metal foil material formed on the surface of the dielectric layer may be copper (Cu), And its thickness is about 1 2 / zm. 2 2. The structure as described in item 21 of the scope of the patent application, wherein the thickness of the second metal layer formed by thinning the metal foil is about 7 ~ 9 μ ra. 2 3. The structure described in item 15 of the scope of the patent application, wherein the nickel-gold layer is formed by electroplating, and the thickness of the nickel-gold layer is about 5 # m, and the nickel-gold layer is used as a flip-chip bonding bump. Connection area. 2 4. The structure described in item 15 of the scope of patent application, wherein the circuit layer is a second metal layer in an etched part, and is covered by a vacuum dry film lamination technology or a liquid photoresist coating The screen silver engraving was formed. 25. The structure described in item 15 of the scope of patent application, wherein the circuit layer is divided

第.23頁 200L 10. 04. 023 _案號 89125977 六、申請專利範圍年月曰修正了導通電性以外，可同時另外形成一支撐線路（Mesh Pa11erη)以增加載板抗曲強度，並縮小因受熱變形而形成之板翹或板扭量。 2 6 .如申請專利範圍第1 5項所述之結構，其中該防銲阻劑可為一表面塗佈之Epoxy感光防焊阻劑。 2 7.如申請專利範圍第1 5項所述之結構，其中該複數個黑氧化阻堤厚度約為1〜3私m以下。P.23 200L 10. 04. 023 _ Case No. 89125977 6. The scope of the patent application In addition to the revised conductivity, an additional support line (Mesh Pa11erη) can be formed at the same time to increase the flexural strength of the carrier board and reduce it. The amount of plate warpage or plate twist caused by thermal deformation. 26. The structure described in item 15 of the scope of patent application, wherein the solder resist can be a surface-coated Epoxy photosensitive solder resist. 2 7. The structure according to item 15 of the scope of the patent application, wherein the thickness of the plurality of black oxide barriers is approximately 1 to 3 μm.

第24頁 2001.10. 04.024Page 24 2001.10. 04.024