4 6 6 6 δ b 7146twf*doc/006 A7 五、發明說明（1 ) 本發明是有關於一種覆晶晶片及其覆晶製程，且特 別是有關於一種可消除測試探針痕跡，以提高凸塊與晶片 接合之可靠度的覆晶晶片及其對應之製造方法。 在半導體製程之積集度愈高及尺寸愈小的情況下， 其製程之複雜度及困難度也愈來愈高，因此如何進行製程 即時監控以快速反應問題，以降低錯誤所造成的損失，是 目前半導體製程的重要課題。一般而言，在晶片製作完成 後，會進行測試的工作，首先探針會施加適當的壓力於晶 片之焊墊上，以確保碰觸到焊墊，然後再進行電性測試。 然而上述之測試工作，探針會損及焊墊之表面甚至***到 焊墊的內部，並且探針會多次與焊墊接觸，如此使得焊墊 的表面不平整且會有凹孔。就記憶體產品而言，爲提高產 品之良率，通常會預留多個備用電路單元（redundant cell)，以便進行修復之用，在記憶體初步完成時，會先 經由探針測試，檢測出壞的或是較差的電路單元，將這些 壞的或較差的電路單元進行雷射修復（laser repair)，使 其連至預留的備用電路單元，然後再進行探針電性測試。 如此記憶體會經過一次以上的探針電性測試，更加造成焊 墊表面的破壞，使焊墊表面更不平整且凹孔更不規則。若 是接下來還要進行覆晶之製程時，會導致球底金屬層 (Under Bump Metal，UBM)在靠近焊墊表面的地方有空孔 (voids)的產生，甚至有雜質會堆積於空孔中，如水氣、 氣體、溶劑、電鍍液等。 請參照第1圖，其繪示習知覆晶晶片之剖面放大示 (請先閲讀背面之注意事項再填寫本頁) I --------訂·-------I > k . 經濟部智慧財產局員Η消費合作杜印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐） 經濟部智慧財產局員工消費合作社印製 4 6 6 65 5 7146twf,doc/006 A7 —___B7 五、發明說明（之） 意圖，在此爲簡化圖示及說明，在此圖中僅繪出多個焊墊 及凸塊之其中一組。一晶片110具有一主動表面120，在 晶片110之主動表面120具有一保護層122及多個焊墊 124(在第1圖中僅繪示其中的一個），而保護層122暴露 出焊墊124。在每一焊墊124上具有一球底金屬塊130, 而球底金屬塊130可以由鉻、鈦、鈦化鎢、鎳或銅等金屬 所組成，而在每一球底金屬塊130上還具有一凸塊 140(Bump) ’透過凸塊140晶片110可以與外界電路（未繪 示）電性連接。 請參照第1圖、第2圖，其中第2圖繪示對應於第 1圖中區域150之局部放大圖。在晶片11〇製作完成後， 會先進行測試的工作，然後才會進行製作凸塊140之製程， 然而在進行測試工作時，探針（未繪示）會先施加適當的壓 力於晶片110之焊墊124上，以確保碰觸到焊墊124，然 後再進行電性測試。然而上述之測試工作，探針會損及焊 墊124之表面，甚至***到焊墊124的內部，並且探針會 多次與焊墊124接觸，如此使得焊墊124的表面不平整且 甚至會有不規則的凹孔160產生，一般稱之爲探針痕跡 (probe mark)。在接下來的製作凸塊丨40之製程時，由於 球底金屬塊130之階梯覆蓋（Step Coverage)的能力並不 理想，會導致球底金屬塊Π0在靠近焊墊丨24表面之凹孔 160的地方有荦孔]70的產生，甚至有雜質會堆積於空孔 170中，比如是水氣。一旦受到熱作用，空孔170內水氣 之膨脹力道會使得凸塊H0與晶片110剝離，導致覆晶製 4 .---------—------線 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 五 »ίιϊιϋ.. >..· i i:i i-n-T--lsi· f. »1 } n 經濟部智慧財產局員工消費合作社印製 466655 7146twf,doc/006 A7 B7 、發明說明（>) 程之可靠度大幅降低。 因此本發明的目的就是在提供一種覆晶晶片及其覆 晶製程，可消除上述之測試探針痕跡，以提高凸塊與晶片 接合之可靠度。 爲達成本發明之上述和其他目的，提供一種覆晶晶 片，包括：一晶片，此晶片具有一主動表面，晶片之主動 表面具有一保護層及複數個焊墊，其中保護層具有多個第 一開口，每一焊墊具有至少一第二開口，每一第一開口分 別對應於第二開口之一的位置，而每一第一開口的截面積 大致等於對應之第二開口的截面積，並且第二開口貫穿焊 墊。多個球底金屬塊，每一球底金屬塊分別嵌入於焊墊之 一的第二、第二開口內。以及多個凸塊，每一凸塊分別位 於球底金屬塊之一上。 爲達成本發明之上述和其他目的，提供一種覆晶製 程，包括：提供一晶片，此晶片具有一主動表面，晶片之 主動表面具有一保護層及多個焊墊，而保護層具有多個第 一開口，每一第一開α分別暴露出焊墊之一。進行一測試 晶片之步驟，使用至少一探針碰觸至焊墊的表面，以進行 測試的工作。進行一製作第二開口之製程，形成至少一第 開π於每一焊墊，而第二開口貫穿焊墊，並且第二開口 與第一開口相貫通，而第二開口的截面積大致等於對應之 第·開口的截面積。以及進行一製作凸塊之製程。 依照木發明的一較佳實施例，第二開口亦可以是僅 貫穿焊墊之部份，並未完全貫穿焊墊，而對應於每-第二 5 — II I I----- · I I ί (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（2】0 X 297公髮） A7 B7 6 6 6 5 5 7146twf.doc/006 五'發明說明（十） 開口區域，焊墊之厚度介於500埃至2000埃的範圍之間。 爲讓本發明之上述和其他目的 '特徵、和優點能更 明顯易懂，下文特舉一較佳實施例，並配合所附圖式，作 詳細說明如下： 圖式之簡單說明： 第1圖繪示習知覆晶晶片對應於凸塊區域之剖面放 大示意圖。 第2圖繪示對應於第1圖中區域150之局部放大圖。 第3圖至第6圖繪示依照本發明第一較佳實施例的 一種覆晶製程對應於製作凸塊區域之剖面放大示意圖。 第7圖繪示本發明第二較佳實施例的一種覆晶結構 對應於凸塊區域之剖面放大示意圖。 第8圖繪示本發明第三較佳實施例的一種覆晶結構 對應於凸塊區域之剖面放大示意圖。 第9圖與第10圖繪示本發明第四較佳實施例的一 種覆晶製程對應於製作凸塊區域之剖面放大示意圖。 第11圖繪示本發明第五較佳實施例的一種覆晶結 構對應於凸塊區域之剖面放大示意圖。 第12圖繪示本發明第六較佳實施例的一種覆晶結 構對應於凸塊區域之剖面放大示意圖。 第13圖繪示本發明第七較佳實施例的一種覆晶結 構對應於凸塊區域之剖面放大示意圖。 第14圖繪示本發明第八較佳實施例的一種覆晶結 構對應於凸塊區域之剖面放大示意圖。 本紙張尺度適用中國國家標準（CNS)A4規格（2〗〇χ 297公釐） (請先閱讀背面之沒意事項再填寫本頁) ----It--訂·---I----_ 經濟部智慧財產局員工消費合作社印製 6 6 6 5 5 7146twf,doc/006 A7 —_B7_ :£、發明說明（$ ) 圖式之標示說明： 200 .覆晶晶片 (請先閱讀背面之注意事項再填寫本頁) 110、210、310、510 ' 610 :晶片 120、220、520 ' 620 :主動表面 122、222、526 :保護層 124 、 224 、 324 、 424 ' 524 ' 624 、 724 、 824 、 924 : 焊墊 226 :目標區域 223 :第一·開口 228、428、528 ' 628、728、828、928 :第二開口 230、330、630 :絕緣層 332、632 :貫孔 334、634 :導電物質 240 :球底金屬層 130、242 :球底金屬塊 250 :光阻 252 :通孔 140、260、560 :凸塊 經濟部智慧財產局員工消費合作社印製 570、670 :絕緣層結構體 523 ' 623 :孔洞 160 :凹孔 170 :空孔 150 區域 本紙張尺度適用中S國家標準（CNS)A4規格（21〇χ 297公釐） /16 6 6 5 1: 7l46twf.doc/〇〇6 A7 _ B7 s、發明說明（乙） 340、640 :導電層 實施例 請參照第3圖至第6圖，其繪示依照本發明第一較 佳實施例的一種覆晶製程對應於製作凸塊區域之剖面放大 示意圖。在此爲簡化圖示及說明，在圖示中僅繪出多個焊 墊及凸塊之其中一組。 請參照第3圖，首先提供一晶片210，晶片210具 有一主動表面220，而晶片210之主動表面220具有一保 護層222及至少一焊墊224，且保護層222具有至少一第 一開口 223以暴露出焊墊224，而第一開口 223的形狀約 略爲近似圓形之多邊形形狀，而其第一開口 223的半徑約 爲100微米至120微米之間。另外，晶片210的內部還具 有一絕緣層230，而絕緣層230與焊墊224接觸。然後進 行一測試晶片之步驟，在進行晶片測試時，探針（未繪示) 會瞄準焊墊224的中間，然而由於探針準確度之關係，並 非每次在探測時，探針皆能夠碰觸到焊墊的中間，亦有可 能在焊墊中間的周圍區域，當愈接近焊墊中間的區域，其 探針碰觸的機率愈高。因此一探針痕跡分佈區域226(probe mark region)會發生在焊墊的中間區域，並且探針在下壓 時會損及焊墊224之探針痕跡分佈區域226的表面，造成 凹孔，其中探針痕跡分佈區域226約爲一圓形區域，就目 前控制良好的測試機台，其探針痕跡分佈的區域約可控制 在直徑60微米以內。 -J— - (請先閱讀背面之注意事項再填窵本頁) 經濟邨智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210x 297公芨） 6 65 5 7 14 6twf. doc/0 0 6 A7 B7 丑、發明說明（ 請參照第3圖、第4圖，接下來進行一製作第 經濟邡智慧財產局員工消費合作社印製 口之製程，可直接以保護層222爲蝕刻罩幕，進行紗到的 步驟，將焊墊224暴露於外的部份去除，使得焊墊224形 成一第二開口 228，第二開口 228貫穿焊墊224，而每/ 第二開口 228與對應之每一第一開口 223相貫通，第二開 口 228對應於第一開口 223，且第二開口 2M的截®積會 大致等於第一開口 223的截面積。 接下來便進行一製作凸塊之製程，首先鋪上 金屬層240於晶片210之主動表面220上，並且球底金靡 層240嵌入於第一開口 223、第二開口 228內’而球底金 屬層240可以由鉻、鈦' 鈦化鎢、鎳或銅等金屬所組成’ 然後再鋪上一光阻250於球底金屬層240上’並且透過微 影蝕刻的步驟，形成通孔252於光阻250中’而通孔252 的位置對應於第二開口 228的上方。 請參照第5圖，然後以電鍍、蒸鏟或網板印刷等方 式，塡入一凸塊260於通孔252中’其中凸塊260的材質 包括錫給合金。 請參照第5圖、第6圖，接下來將光阻250剝除， 然後透過蝕刻的方式將未被凸塊260覆蓋住的球底金屬層 24〇去除，而形成獨立的多個球底金屬塊242 ’並且透過 迴焊（Ref low)的方式，使凸塊260之結構形成類似球狀。 而上述之覆晶晶片200可以配置於·承載器（未繪％ )上， 承載器可以是晶片、印刷電路板或是其他類型的基板等， 丨1承載器具有多個接點（未繪示）’而晶片210可藉由g塊 球底 請 先 聞 讀 背 面 之 項 存 填 % 裝 订 線 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐） Λ 6 6 6 5 5 7 14 6twf- doc/Ο 0 6 Α7 Β7 s.、發明說明（2 ) 260與承載器之接點電性連接。 請參照第3圖至第6圖，在上述之製程中，由於製 作第二開口 228於蝕刻前焊墊224暴露於外的區域，故可 以將焊墊224被探針損及的區域去除，而避免球底金屬塊 240在靠近焊墊224表面的地方形成空孔，故可以提高凸 塊260與晶片210接合之可靠度。 請參照第7圖，其繪示本發明第二較佳實施例的一 種覆晶結構對應於凸塊區域之剖面放大示意圖。本發明亦 可以應用在其他形式的晶片310結構，比如在對應於焊墊 324之下的絕緣層330區域，具有多個貫孔332於其中， 而貫孔332內塡充有導電材質334，以與下方的導電層340 連接。此時，球底金屬塊342則是與導電材質334及焊墊 324電性連接。 請參照第8圖，其繪示本發明第三較佳實施例的一 種覆晶結構對應於凸塊區域之剖面放大示意圖。前述之第 一較佳實施例中，第二開口之結構係貫穿整個焊墊，然而 第二開口之結構並非侷限於上述的方式，第二開口 428亦 可以僅貫穿焊墊424之部份，並未完全貫穿焊墊424。而 對應於第二開口 428區域，蝕刻剩下的焊墊424厚度可介 於500埃至2000埃之間，較佳情況爲2000埃左右。 請參照第9圖、第10圖，其中繪示本發明第四較 佳實施例的一種覆晶製程對應於製作凸塊區域之剖面放大 ^5意圖。除『前述類型的覆晶晶片結構外’本發明亦可 以應用在其他類型的覆晶晶片結構，如下所述。請參照第 (請先閱讀背面之注意事項再填寫本頁) • ---- _ t I I 訂 _11!111_ · 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規袼（210 x 297公釐） A7 B7 '6 6 65 5 7146twf.doc/006 5 广 ------ ||盡、發明說明（q ) 9圖，首先提供一晶片510，在晶片510之主動表面520 的保護層526上還具有一絕緣結構體570，而絕緣結構體 570的材質包括聚亞醯胺（p〇lyimide)，並且絕緣結構體570 具有至少一孔洞523，而孔洞523貫穿絕緣結構體570 ’ 暴露出焊墊524。然後會進行一測試的步驟，利用至少一 探針（未繪示）進行晶片510之檢測。 請參照第10圖，接下來會進行一製作第二開口之 製程，可直接以絕緣結構體570爲蝕刻罩幕，進行蝕刻的 步驟，將焊墊524暴露於外的部份去除，使得焊墊524形 成一第二開口 528，第二開口 528貫穿焊墊524，而第二 開口 528對應於孔洞523的位置，每一第二開口 528與對 應之每一孔洞523相貫通，第二開口 528的截面積會大致 等於孔洞523的截面積。接下來進行一製作凸塊560的製 程，其製程與前述的第一較佳實施例雷同，在此不再贅述。 請參照第11圖，其繪示本發明第五較佳實施例的 一種覆晶結構對應於凸塊區域之剖面放大示意圖。然而本 發明之覆晶結構可以依上述實施例中所述之方式相互組合 應用，可有多種變化。比如是晶片610的結構採用如第二 較佳實施例中所述之結構’在對應於焊墊624之下的絕緣 層630區域，可以形成多個貫孔632於其中，而貫孔632 內塡充有導電材質6 3 4與卜方的導電層6 4 0電性連接；而 第二開口 628結構可採用如第三較佳實施例所述之結構， 第二開口 628僅貫穿焊墊624之部份，並未完全貫穿焊墊 624，而對應於第二開口 628區域’蝕刻剩下的焊墊6244 6 6 6 δ b 7146twf * doc / 006 A7 V. Description of the invention (1) The present invention relates to a flip-chip wafer and its flip-chip manufacturing process, and in particular to a method for removing traces of test probes to improve convexity. Chip-on-chip wafer-to-chip reliability and corresponding manufacturing method. The higher the accumulation and the smaller the size of the semiconductor process, the more complex and difficult the process becomes. Therefore, how to monitor the process in real time to quickly respond to problems and reduce the losses caused by errors. Is an important issue in the current semiconductor process. Generally speaking, after the wafer is manufactured, the test work will be performed. First, the probe will apply appropriate pressure to the pad of the wafer to ensure that it touches the pad, and then the electrical test is performed. However, in the above test work, the probe will damage the surface of the pad and even be inserted into the interior of the pad, and the probe will contact the pad several times, so that the surface of the pad is not flat and there are concave holes. As far as memory products are concerned, in order to improve the yield of the product, multiple redundant circuit cells are usually reserved for repair purposes. When the memory is initially completed, it is first detected by a probe test. Bad or poor circuit units, laser repair these bad or poor circuit units, connect them to the reserved spare circuit units, and then perform probe electrical test. In this way, the memory will undergo more than one probe electrical test, which will further damage the pad surface, making the pad surface more uneven and the recesses more irregular. If the next process is to perform the flip-chip process, voids will be generated near the surface of the pad under the bump metal layer (UBM), and even impurities will accumulate in the voids. , Such as water vapor, gas, solvent, plating solution, etc. Please refer to Figure 1, which shows a magnified cross-section of a conventional flip-chip wafer (please read the precautions on the back before filling this page) I -------- Order · ------- I > k. Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperation. Printed on paper. Applicable to China National Standard (CNS) A4 (210 x 297 mm). Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 4 6 6 65 5 7146twf , doc / 006 A7 —___ B7 V. Description of the Invention (in) In order to simplify the illustration and description, only one set of multiple pads and bumps is drawn in this figure. A wafer 110 has an active surface 120. The active surface 120 of the wafer 110 has a protective layer 122 and a plurality of solder pads 124 (only one of which is shown in FIG. 1), and the protective layer 122 exposes the solder pads 124. . Each solder pad 124 has a ball-bottom metal block 130, and the ball-bottom metal block 130 may be composed of a metal such as chromium, titanium, tungsten titanide, nickel, or copper. The chip 110 has a bump 140 (Bump). The chip 110 can be electrically connected to an external circuit (not shown) through the bump 140. Please refer to FIG. 1 and FIG. 2, where FIG. 2 is a partial enlarged view corresponding to the area 150 in the first figure. After the wafer 110 is manufactured, the test work will be performed first, and then the manufacturing process of the bump 140 will be performed. However, when the test work is performed, the probe (not shown) will first apply appropriate pressure to the wafer 110. The solder pads 124 are to be in contact with the solder pads 124 before the electrical test is performed. However, in the above test work, the probe will damage the surface of the pad 124 and even be inserted into the inside of the pad 124, and the probe will contact the pad 124 multiple times, so that the surface of the pad 124 is uneven and may even Irregular recesses 160 are generated and are generally referred to as probe marks. In the next process of manufacturing bumps and 40, the step coverage of the ball bottom metal block 130 is not ideal, which will cause the ball bottom metal block Π0 to be near the recessed hole 160 on the surface of the solder pad. There are countersunk holes] 70, and even impurities will accumulate in the empty holes 170, such as moisture. Once subjected to heat, the expansion force of the water vapor in the cavity 170 will cause the bump H0 and the wafer 110 to peel off, resulting in a flip-chip 4 .----------------- line (please first Read the notes on the reverse side and fill in this page) This paper size is applicable to Chinese National Standard (CNS) A4 (210 X 297 mm) 5 »ίιϊιϋ .. > .. · ii: i inT--lsi · f.» 1} n Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 466655 7146twf, doc / 006 A7 B7, and the reliability of the invention (>) process has been greatly reduced. Therefore, an object of the present invention is to provide a flip-chip wafer and a flip-chip manufacturing process, which can eliminate the above-mentioned test probe traces and improve the reliability of bonding between the bump and the wafer. In order to achieve the above and other objectives of the present invention, a flip-chip wafer is provided, including: a wafer having an active surface, the active surface of the wafer having a protective layer and a plurality of pads, wherein the protective layer has a plurality of first Openings, each pad has at least one second opening, each first opening corresponds to a position of one of the second openings, and the cross-sectional area of each first opening is substantially equal to the cross-sectional area of the corresponding second opening, and The second opening penetrates the solder pad. A plurality of ball bottom metal blocks, each ball bottom metal block is respectively embedded in the second and second openings of one of the pads. And a plurality of bumps, each bump is respectively located on one of the ball bottom metal blocks. In order to achieve the above and other objectives of the present invention, a flip-chip process is provided, which includes: providing a wafer having an active surface, the active surface of the wafer having a protective layer and a plurality of pads, and the protective layer having a plurality of first layers. An opening, each first opening α respectively exposes one of the pads. A test wafer is carried out, and at least one probe is used to touch the surface of the pad to perform the test work. A process of making a second opening is performed to form at least a first opening at each pad, and the second opening penetrates the pad, and the second opening and the first opening penetrate, and the cross-sectional area of the second opening is approximately equal to The cross-sectional area of the opening. And a process for making bumps. According to a preferred embodiment of the wooden invention, the second opening may also be a portion that penetrates the pads only, and does not completely penetrate the pads, and corresponds to every-second 5 — II I I ----- · II ί (Please read the precautions on the back before filling this page) This paper size applies to China National Standard (CNS) A4 specifications (2) 0 X 297 issued) A7 B7 6 6 6 5 5 7146twf.doc / 006 Five 'invention Note (10) The thickness of the pads in the open area is in the range of 500 Angstroms to 2000 Angstroms. In order to make the features and advantages of the above and other objects of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Brief description of the drawings: FIG. 1 An enlarged schematic cross-sectional view of a conventional flip-chip wafer corresponding to a bump region is shown. FIG. 2 shows a partially enlarged view corresponding to the area 150 in the first figure. Figures 3 to 6 show enlarged schematic cross-sectional views of a flip-chip process corresponding to the fabrication of bump regions according to the first preferred embodiment of the present invention. FIG. 7 is an enlarged schematic cross-sectional view of a flip-chip structure corresponding to a bump region according to a second preferred embodiment of the present invention. FIG. 8 is an enlarged schematic cross-sectional view of a flip-chip structure corresponding to a bump region according to a third preferred embodiment of the present invention. FIG. 9 and FIG. 10 are enlarged schematic cross-sectional views of a flip-chip manufacturing process corresponding to the fabrication of a bump region according to a fourth preferred embodiment of the present invention. FIG. 11 is an enlarged schematic cross-sectional view of a flip-chip structure corresponding to a bump region according to a fifth preferred embodiment of the present invention. FIG. 12 is an enlarged schematic cross-sectional view of a flip-chip structure corresponding to a bump region according to a sixth preferred embodiment of the present invention. FIG. 13 is an enlarged schematic cross-sectional view of a flip-chip structure corresponding to a bump region according to a seventh preferred embodiment of the present invention. FIG. 14 is an enlarged schematic cross-sectional view of a flip-chip structure corresponding to a bump region according to an eighth preferred embodiment of the present invention. This paper size applies to China National Standard (CNS) A4 specification (2) 0 × 297 mm (please read the unintentional matter on the back before filling this page) ---- It--Order · ----- --_ Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 6 6 6 5 5 7146twf, doc / 006 A7 —_B7_: £, Description of Invention ($) Symbols of the diagram: 200 .Flip-Chip Wafer (Please read the back first Please note this page before filling in this page) 110, 210, 310, 510 '610: Wafer 120, 220, 520' 620: Active surface 122, 222, 526: Protective layer 124, 224, 324, 424 '524' 624, 724 , 824, 924: Pad 226: Target area 223: First opening 228, 428, 528 '628, 728, 828, 928: Second opening 230, 330, 630: Insulating layer 332, 632: Through hole 334, 634: conductive material 240: ball-bottom metal layer 130, 242: ball-bottom metal block 250: photoresist 252: through hole 140, 260, 560: bump printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 570, 670: insulation layer Structure 523 '623: Hole 160: Concave hole 170: Hollow hole 150 Area This paper size is applicable to China National Standard (CNS) A4 specification (21〇 × 297 mm) / 16 6 6 5 1: 7l46twf.doc / 〇〇6 A7 _ B7 s, description of the invention (B) 340, 640: Please refer to Figures 3 to 6 for examples of conductive layers. A flip-chip process of the preferred embodiment corresponds to an enlarged schematic cross-sectional view of a bump region. To simplify the illustration and description, only one set of a plurality of pads and bumps is drawn in the illustration. Referring to FIG. 3, a wafer 210 is first provided. The wafer 210 has an active surface 220, and the active surface 220 of the wafer 210 has a protective layer 222 and at least one pad 224, and the protective layer 222 has at least a first opening 223. The pad 224 is exposed, and the shape of the first opening 223 is approximately a polygonal shape that is approximately circular, and the radius of the first opening 223 is between about 100 μm and 120 μm. In addition, the inside of the wafer 210 is further provided with an insulating layer 230, and the insulating layer 230 is in contact with the bonding pad 224. Then perform a step of testing the wafer. During the wafer test, the probe (not shown) will be aimed at the middle of the pad 224. However, due to the accuracy of the probe, the probe cannot be touched each time It may also be in the middle of the pads when it touches the middle of the pads. The closer it is to the middle of the pads, the higher the probability that the probe will touch. Therefore, a probe mark distribution region 226 (probe mark region) will occur in the middle region of the pad, and when the probe is pressed down, the surface of the probe mark distribution region 226 of the pad 224 will be damaged, causing a recessed hole. The needle trace distribution area 226 is approximately a circular area. Currently, for a well-controlled testing machine, the probe trace distribution area can be controlled within about 60 microns in diameter. -J—-(Please read the precautions on the back before filling out this page) Printed by the Economic Village Intellectual Property Bureau Staff Consumer Cooperatives This paper is sized for the Chinese National Standard (CNS) A4 (210x 297 cm) 6 65 5 7 14 6twf. Doc / 0 0 6 A7 B7 Ugly, invention description (please refer to Figure 3, Figure 4, and then carry out a process of making the printed mouth of the employee consumer cooperative of the Economic and Intellectual Property Bureau, can be directly protected 222 is an etching mask, and a step of yarn-removing is performed to remove the exposed portion of the bonding pad 224, so that the bonding pad 224 forms a second opening 228, and the second opening 228 penetrates the bonding pad 224, and every second opening 228 communicates with each corresponding first opening 223, the second opening 228 corresponds to the first opening 223, and the cross-sectional area of the second opening 2M is approximately equal to the cross-sectional area of the first opening 223. Next, a production is performed. In the process of bumps, a metal layer 240 is first laid on the active surface 220 of the wafer 210, and the ball-bottom metal layer 240 is embedded in the first opening 223 and the second opening 228. Titanium 'metals such as tungsten titanate, nickel or copper Composition ', and then spread a photoresist 250 on the ball-bottom metal layer 240' and through the lithographic etching step, a through hole 252 is formed in the photoresist 250 ', and the position of the through hole 252 corresponds to the top of the second opening 228 Please refer to Figure 5, and then insert a bump 260 into the through hole 252 by electroplating, steaming shovel or screen printing, etc. 'The material of the bump 260 includes tin alloy. Please refer to Figure 5, In Figure 6, the photoresist 250 is peeled off, and then the ball-bottom metal layer 24 that is not covered by the bumps 260 is removed by etching to form an independent plurality of ball-bottom metal blocks 242 'and reflow soldering is performed. (Ref low), so that the structure of the bump 260 is formed into a spherical shape. The above-mentioned flip-chip wafer 200 can be configured on a carrier (not shown), and the carrier can be a wafer, a printed circuit board, or other Type of substrate, etc. 丨 1 carrier has multiple contacts (not shown) 'and the chip 210 can be read by g-ball bottom first and fill in the items on the back% binding line This paper size applies Chinese national standards (CNS) A4 size (210 x 297 mm) Λ 6 6 6 5 5 7 14 6twf- doc / Ο 0 6 Α7 Β7 s. Invention Description (2) 260 is electrically connected to the contact point of the carrier. Please refer to Figures 3 to 6 in the above process. The two openings 228 are in the area where the pad 224 is exposed before the etching, so the area where the pad 224 is damaged by the probe can be removed, and the ball-bottom metal block 240 is prevented from forming a hole near the surface of the pad 224, so It is possible to improve the reliability of bonding of the bumps 260 and the wafer 210. Please refer to FIG. 7, which is an enlarged schematic cross-sectional view of a flip-chip structure corresponding to a bump region according to a second preferred embodiment of the present invention. The present invention can also be applied to other forms of wafer 310 structures. For example, in the area of the insulating layer 330 corresponding to the pad 324, there are a plurality of through holes 332 therein, and the through holes 332 are filled with a conductive material 334. It is connected to the lower conductive layer 340. At this time, the ball bottom metal block 342 is electrically connected to the conductive material 334 and the bonding pad 324. Please refer to FIG. 8, which is an enlarged schematic cross-sectional view of a flip-chip structure corresponding to a bump region according to a third preferred embodiment of the present invention. In the foregoing first preferred embodiment, the structure of the second opening penetrates the entire pad, however, the structure of the second opening is not limited to the above-mentioned manner, and the second opening 428 may also penetrate only a portion of the pad 424, and The pad 424 is not completely penetrated. Corresponding to the area of the second opening 428, the thickness of the remaining pad 424 etched may be between 500 Angstroms and 2000 Angstroms, and preferably about 2000 Angstroms. Please refer to FIG. 9 and FIG. 10, wherein a flip-chip process corresponding to a fourth preferred embodiment of the present invention is shown corresponding to an enlarged cross-section of a bump region. The present invention can be applied to other types of flip-chip wafer structures in addition to "the aforementioned types of flip-chip wafer structures" as described below. Please refer to section (Please read the precautions on the back before filling this page) • ---- _ t II Order _11! 111_ · Printed on paper standards of the Ministry of Economic Affairs and Intellectual Property Bureau Staff Consumer Cooperatives Applicable to China National Standards (CNS) A4 specification (210 x 297 mm) A7 B7 '6 6 65 5 7146twf.doc / 006 5 Cantonese -------- || Explain the invention (q) 9 Figures, first provide a wafer 510, in the wafer The protective layer 526 of the active surface 520 of 510 also has an insulating structure 570, and the material of the insulating structure 570 includes polyimide, and the insulating structure 570 has at least one hole 523, and the hole 523 Pads 524 are exposed through the insulating structure 570 '. Then, a test step is performed, and at least one probe (not shown) is used for the inspection of the wafer 510. Please refer to FIG. 10, a process of making a second opening will be performed next. The insulating structure 570 can be directly used as an etching mask to perform the etching step, and the exposed portion of the solder pad 524 is removed to make the solder pad 524 forms a second opening 528, the second opening 528 penetrates the solder pad 524, and the second opening 528 corresponds to the position of the hole 523. Each second opening 528 is connected to each corresponding hole 523. The cross-sectional area will be approximately equal to the cross-sectional area of the hole 523. Next, a process for making the bumps 560 is performed. The process is the same as that of the foregoing first preferred embodiment, and details are not described herein again. Please refer to FIG. 11, which is an enlarged schematic cross-sectional view of a flip-chip structure corresponding to a bump region according to a fifth preferred embodiment of the present invention. However, the flip-chip structure of the present invention can be applied in combination with each other in the manner described in the above embodiments, and there can be various changes. For example, the structure of the wafer 610 adopts the structure described in the second preferred embodiment. In the region corresponding to the insulating layer 630 under the bonding pad 624, a plurality of through holes 632 can be formed therein, and the through holes 632 are internally formed. The conductive material 6 3 4 is filled with the conductive layer 6 4 0 of the cube. The structure of the second opening 628 can adopt the structure described in the third preferred embodiment. The second opening 628 only penetrates the pad 624. Partially, the pads 624 are not completely penetrated, and the remaining pads 624 are etched corresponding to the area of the second opening 628
1 閱 讀 背 面 之 注 意 事 項 再 < 填 1 寫裝 頁I 訂 % 經 濟 部 智 慧 財 產 局 員 X 消 費 合 作 杜 印 製 本紙張尺度適用中國國家標準（CNS)A4規格（210 κ 297公爱） 經濟部智慧財產局員工消費合作社印製 b 6 6 5 5 7146twf.doc/006 五、發明說明（P) 厚度可介於500埃至2000埃之間。另外，晶片610之主 動表面620上亦可以覆蓋.一絕緣結構體670，如第四較佳 實施例中所述之結構，其中絕緣結構體670之孔洞623的 截面積大致等於第二開口 628的截面積。 請參照第12圖、第丨3圖 '第14圖，其中第12圖 繪示本發明第六較佳實施例的一種覆晶結構對應於凸塊區 域之剖面放大示意圖；第13圖繪示本發明第七較佳實施 例的一種覆晶結構對應於凸塊區域之剖面放大示意圖；第 14圖繪示本發明第八較佳實施例的一種覆晶結構對應於凸 塊區域之剖面放大示意圖。如第12圖所示，其覆晶晶片 之凸塊區域結構類似第五較佳實施例，只是將第二開口的 形式變更爲類似第一較佳實施例的形式，亦即第二開口 728 貫穿焊墊724。如第13圖所示，其覆晶晶片之凸塊區域結 構類似第二較佳實施例，只是將第二開口的形式變更爲類 似第三較佳實施例的形式，亦即第二開口 828僅貫穿焊墊 824之部份，並未完全貫穿焊墊824。如第14圖所示，其 覆晶晶片之凸塊區域結構類似第四較佳實施例，只是將第 二開口的形式變更爲類似第三較佳實施例的形式，亦即第 二開口 928僅貫穿焊墊924之部份，並未完全貫穿焊墊 924 0 綜上所述，本發明之覆晶晶片及其覆晶製程，由於 製作第二開口於焊墊之目標區域，故可以將焊墊被探針損 及的區域去除，而避免球底金屬塊在靠近焊墊表面的地方 形成空孔，故可以提高凸塊與晶片接合之可靠度。 本紙度適用中闯國家標準（CNS)A,1規格（210 X 297公坌） ------I I I I I I I I ---------111 — (請先閱讀背面之注$項再填寫本頁) 6 65 5 7l46twf.doc/006 A7 B7 i、發明說明（1\) 雖然本發明已以一較佳實施例揭露如上，然其並非 用以限定本發明，任何熟習此技藝者，在不脫離本發明之 精神和範圍內，當可作些許之更動與潤飾，因此本發明之 保護範圍當視後附之申請專利範圍所界定者爲準。 -----------.，裝--------訂.(請先閱讀背面之注意事項再填寫本頁) -線 經濟部智慧財產局員工消费合作社印製 衣紙張尺度洎用中®國家標準（CNSM4規格（210 X 297公釐）1 Read the notes on the back of the page and then fill in 1 Write page I Order% Member of Intellectual Property Bureau of the Ministry of Economic Affairs X Consumption Du Duprinted This paper applies the Chinese National Standard (CNS) A4 specification (210 κ 297 public love) Ministry of Economic Wisdom Printed by the Consumer Cooperative of the Property Bureau b 6 6 5 5 7146twf.doc / 006 V. Description of the invention (P) The thickness can be between 500 Angstroms and 2000 Angstroms. In addition, the active surface 620 of the chip 610 may also be covered. An insulating structure 670, as described in the fourth preferred embodiment, wherein the cross-sectional area of the hole 623 of the insulating structure 670 is substantially equal to that of the second opening 628. Cross-sectional area. Please refer to FIG. 12 and FIG. 3 and FIG. 14, where FIG. 12 is an enlarged schematic cross-sectional view of a flip-chip structure corresponding to a bump region according to a sixth preferred embodiment of the present invention; An enlarged schematic cross-sectional view of a flip-chip structure corresponding to a bump region according to a seventh preferred embodiment of the present invention; FIG. 14 is an enlarged schematic cross-sectional view of a flip-chip structure corresponding to a bump region according to an eighth preferred embodiment of the present invention. As shown in FIG. 12, the structure of the bump region of the flip-chip wafer is similar to that of the fifth preferred embodiment, except that the form of the second opening is changed to a form similar to the first preferred embodiment, that is, the second opening 728 passes through Pad 724. As shown in FIG. 13, the structure of the bump region of the flip-chip wafer is similar to that of the second preferred embodiment, but the form of the second opening is changed to a form similar to the third preferred embodiment, that is, the second opening 828 is only The portion that penetrates the solder pad 824 does not completely penetrate the solder pad 824. As shown in FIG. 14, the structure of the bump region of the flip-chip wafer is similar to that of the fourth preferred embodiment, except that the form of the second opening is changed to a form similar to that of the third preferred embodiment, that is, the second opening 928 is only The part that penetrates the solder pad 924 does not completely penetrate the solder pad 9240. In summary, the flip-chip wafer and the flip-chip manufacturing process of the present invention, because the second opening is made in the target area of the solder pad, the solder pad can be The area damaged by the probe is removed to prevent voids from forming in the ball-bottom metal block near the surface of the pad, so the reliability of the bump-to-wafer bonding can be improved. This paper is applicable to the National Standard (CNS) A, 1 specifications (210 X 297 gong) ------ IIIIIIII --------- 111 — (Please read the note in the back before filling in (This page) 6 65 5 7l46twf.doc / 006 A7 B7 i. Description of the invention (1 \) Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Anyone skilled in this art, in Without departing from the spirit and scope of the present invention, some modifications and retouching can be made. Therefore, the protection scope of the present invention shall be determined by the scope of the attached patent application. -----------., Install -------- order. (Please read the precautions on the back before filling out this page)-Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Paper size in use® National Standard (CNSM4 specification (210 X 297 mm)