TW465031B - Copper manufacture process for semiconductor - Google Patents

Abstract

This invention provides a copper manufacture process for semiconductor industry. Firstly, a semiconductor substrate with complete front-end integrated circuit process is provided. Damascene trench is then formed on the substrate and copper film is electroplated on the substrate. An annealing treatment is carried out in vacuum state with a pressure less then 10<SP>-5</SP> torr. Finally, chemical mechanical polishing process is performed on the copper film to obtain copper wiring with low via resistance.

Description

五、發明說明（1) 發明領域： 本發明係有關於一種銅製程的方法，特別是有關於一 種可形成低介質阻抗之銅導線的製程方法。 發明背景： 為了追求更快的運作速、率以及更大的集積密度，積體 電路之研究單位及製造業者無不竭盡心力地設計及製造關 鍵尺寸（Critical Dimension; CD)更小的元件。根據實驗 顯示’當積體電路的製程進入0.18微米甚至0.13微米的技 術領域之後，影響元件運作速率的關鍵因素已從閘極的寬 度轉換至金屬内連線（metal interconnection)的電阻-電 容遲滯（RC delay)效應。 因導線的介層阻抗與其截面積成反比，隨著積體電路 之集積密度的提高’金屬内連線的線寬和厚度都隨之縮 小，因此其介層阻抗便隨之提高；尤有甚者，隨著積體電 路之集積密度的提高’亦使金屬内連線的線距隨之縮小， 因而造成導線之間的搞合電容升高。因此當積體電路的製 程進入深次微米領域之後，金屬内連線的電阻-電容遲滯 大幅提高’也因此影響積體電路的運算速率和存取速率。 為了提高積體電路的集積密度，在線寬和線距都不宜提高 的條件之下，更換金屬内連線和層間介電層的材質是最佳^ 的選擇。 在金屬内連線方面，金屬材質由原先的鋁矽銅合金或 鋁銅合金換成銅金屬，除了具有低電阻的特性外，更具有 良好的抗電子遷移性和良好的抗應力性，除了可以提高元V. Description of the invention (1) Field of the invention: The present invention relates to a method for copper process, and more particularly to a method for manufacturing copper wire with low dielectric resistance. Background of the Invention: In order to pursue faster operating speed, rate, and greater accumulation density, research units and manufacturers of integrated circuits have endeavored to design and manufacture components with smaller critical dimensions (CD). According to experiments, when the process of integrated circuits enters the technical field of 0.18 microns or even 0.13 microns, the key factors affecting the operating speed of components have been switched from the width of the gate to the resistance-capacitance hysteresis of the metal interconnection (metal interconnection). RC delay) effect. The resistance of the interlayer of a wire is inversely proportional to its cross-sectional area. As the integrated density of integrated circuits increases, the line width and thickness of the metal interconnects decrease, so the interlayer resistance increases. Or, as the integration density of the integrated circuit is increased, the line pitch of the metal interconnects is also reduced, resulting in an increased capacitance between the wires. Therefore, when the process of integrated circuits enters the deep sub-micron field, the resistance-capacitance hysteresis of the metal interconnects is greatly improved ', which also affects the operation rate and access rate of integrated circuits. In order to improve the integration density of integrated circuits, under the condition that the line width and line spacing should not be increased, it is the best choice to change the material of the metal interconnects and interlayer dielectric layers. In terms of metal interconnects, the metal material is changed from the original aluminum-silicon-copper alloy or aluminum-copper alloy to copper metal. In addition to the characteristics of low resistance, it also has good resistance to electron migration and good stress resistance. Raise yuan

第4頁 4650 ; 五、發明說明（2) ' ------ 件的操作速率外，同時可以择斗-料以 面，入Nf 了以栓升兀件的可靠度；在另一方 s 3 ;丨電s則必須選擇低介電常數（Dielectric octant)的材質以取代原有的二氧化石夕，以降低金属内 f線之間的麵合電容。二氧化石夕的介電常數約為3.9，因 必須選取介電常數小於3 · 9的介電質做為層間介電層， :可達到降低電阻-電容遲滯的功效，例如：氟摻雜之二 氧化矽（SiOF)、有機旋塗玻璃（HSQ)等等。另外一種有效 之低介電常數的材質為黑鑽石（Mack diam〇nd)，其係由 甲基矽烷UethylsUane)所形成，其成分為矽2〇%、氧 30%、碳9%、氫36%、及其他元素。因黑鑽石約有36%的體 積為孔洞’因此其介電常數僅約為2. 9，是一種很具潛力 的低介電常數材質。 〃 在銅製程的技術中，因銅金屬無法如同鋁合金一般用 氣氣進行蝕刻’因此業界發展出一種鑲嵌溝渠（damas cene trench)的製程方法。鑲嵌溝渠的製程技術可參考 Motoro 1 a公司Boeck ; Bruce A 11 en等人在美國專利第 5880 0 1 8 號所揭露之&quot;Method for manufacturing a low dielectric constant inter-level integrated circuit structure11 。請參閱圖一A〜一C所示，首先在一已完成前 段製程的半導體基板1 〇上連續形成第一氮化矽層11、第_ 低介電常數介電層12、第二氮化矽層13、和第二低介電常 數介電層1 4，再以連續兩道微影與蝕刻技術形成如圖_ A 之開口 1 5，該開口 1 5係為『鎮嵌溝渠』。其中氛化砂層 11，13的沉積，係以SiH4和NH3為反應氣體，利用電漿增强Page 4650; 5. Description of the invention (2) '------ In addition to the operating speed of the piece, at the same time, you can choose the bucket-material to face, and enter Nf to plug the reliability of the piece; on the other side s 3; 丨 electricity must choose a low dielectric constant (Dielectric octant) material to replace the original dioxide, in order to reduce the surface capacitance between the f lines in the metal. The dielectric constant of the dioxide is about 3.9. Because a dielectric with a dielectric constant less than 3 · 9 must be selected as the interlayer dielectric layer, the effect of reducing the resistance-capacitance hysteresis can be achieved, for example, fluorine-doped Silicon dioxide (SiOF), organic spin-on glass (HSQ), etc. Another effective material with low dielectric constant is black diamond (Mack diam〇nd), which is formed by Uethyls Uane). Its composition is 20% silicon, 30% oxygen, 9% carbon, and 36% hydrogen. , And other elements. Because about 36% of the volume of black diamonds is holes ’, its dielectric constant is only about 2.9, which is a low-dielectric constant material with great potential. 〃 In the technology of copper process, because copper metal cannot be etched with gas like aluminum alloy ’, the industry has developed a damas cene trench process method. For the process technology of inlaid trenches, please refer to "Method for manufacturing a low dielectric constant inter-level integrated circuit structure11" disclosed by Motoro 1a Company Boeck; Bruce A 11 en et al. In US Patent No. 5880 0 18. Please refer to FIGS. 1A to 1C. First, a first silicon nitride layer 11, a low-k dielectric layer 12, and a second silicon nitride layer are successively formed on a semiconductor substrate 10 that has completed the previous process. The layer 13 and the second low-k dielectric layer 14 are formed by two successive lithography and etching techniques as shown in FIG. A. The opening 15 is an "embedded trench". Among them, the deposition of atmospheric sand layers 11 and 13 is based on SiH4 and NH3 as reaction gases and enhanced by plasma.

第5頁 4650 3 五、發明說明（3) 式化學汽相沉積法（PECVD )在N2的環境之下沉積而形成 約500埃（Angstrom)的薄膜，所需RF的功率約為4 0 0瓦。依 一般製程條件所形成的氮化矽層有一 1 E 9達因/平方公分左 右的壓縮應力。第一低介電常數介電層12和第二低介電常 數介電層1 4的沉積步驟，則以N20和甲基矽烷 (methyl si lane)為反應氣體，利用電漿增強式化學汽相沉 積法（PECVD )沉積而成，其中所需RF的功率約為70瓦， N20的流量約為370sccm，曱基矽烷的流量約為68sccm，反 應時間約為6 0秒以形成約5 0 0 0埃的黑鑽石薄膜。接下來請 參考圖一B ’以電鍍方法形成一層銅薄膜16，再將其送入 反應爐（furnace)内部進行回火（anneaiing)約3〇分鐘’其 中該反應爐内部之壓力係控制在卜7 6 0Torr之間，而温度 係控制在2 0 0〜4 0 0 °C之間。最後如圖一 c所示，利用化學機 械研磨法（Chemical Mechanical Polishing; CMP)對所述 銅薄膜1 6進行研磨’以形成銅導線丨7。 隨著半導體的製程技術的提升，元件的製造也越來越 小’由於銅導線之』I層阻抗resistant)係與介電常 數P和長度L成正比並與截面積a成反比，因此當銅導線越 做越小其所產生之介層阻抗R也越來越高，其結果將造成 銅導線整體的導電性不佳而導致製程良率的降低，根據實 際數據的顯示，在平均每88萬個銅導線的製程中，因為介 層阻抗R過高而導致製程的失敗約佔3 〇〜丨〇 〇 % ，因此，降 低介層阻抗R以提高銅製程的良率，便成為半導體業界一 項很重要的課題。Page 5 4650 3 V. Description of the invention (3) Chemical vapor deposition method (PECVD) is deposited under an N2 environment to form a thin film of about 500 Angstroms. The required RF power is about 400 Watts. . The silicon nitride layer formed under normal process conditions has a compressive stress of about 1 E 9 dyne / cm 2. The deposition steps of the first low-k dielectric layer 12 and the second low-k dielectric layer 14 use N20 and methyl si lane as reaction gases, and use a plasma-enhanced chemical vapor phase. Deposition (PECVD) deposition, in which the required RF power is about 70 watts, the flow rate of N20 is about 370 sccm, the flow rate of fluorenylsilane is about 68 sccm, and the reaction time is about 60 seconds to form about 5 0 0 0 Black diamond film. Next, please refer to FIG. 1B 'a layer of copper film 16 is formed by electroplating, and then it is sent to the inside of a furnace for annealing for about 30 minutes', wherein the pressure inside the reactor is controlled in Bu 7 6 0Torr, and the temperature is controlled between 2 0 ~ 4 0 0 ° C. Finally, as shown in FIG. 1c, the copper thin film 16 is polished by using chemical mechanical polishing (CMP) to form a copper wire. With the advancement of semiconductor process technology, the manufacturing of components is becoming smaller and smaller. “Because of the copper layer I layer resistance resistance” is proportional to the dielectric constant P and the length L and inversely proportional to the cross-sectional area a. As the wires become smaller and smaller, the interlayer resistance R produced by them becomes higher and higher. As a result, the overall conductivity of the copper wires will be poor and the yield of the process will be reduced. According to the actual data, the average per 880,000 In the process of copper conductors, the failure of the process due to the excessively high interlayer resistance R accounts for about 30% to 100%. Therefore, reducing the interlayer resistance R to improve the yield of the copper process has become an issue in the semiconductor industry. Very important subject.

第6頁 6503 ： 五、發明說明（4) 發明目的： 本發明之主要目的在於提供一種可降低介層阻抗以提 高銅導線之良率之銅製程方法。 本發明係揭露一種銅製程的方法，其步驟係包括首先提供 —已完成積體電路之前段製程的半導體基板，並在上述半 導體基板上形成鑲嵌溝渠；以沉積方式形成一阻障層和電 極層；再以電鍍方法形成一層銅薄膜；以反應爐進行回火 約1分鐘，其中該反應爐之壓力係控制在10E —5T〇rr以下， 溫度係介於100〜200 c之間；最後再以CMP對上述銅薄膜進 行研磨以形成銅導線。 ' 由於本發明所提供之銅製程的方法在回火的過程中， 苛以使銅導線内部晶粒的缺陷大幅地改·善，使介電係數降 低以減少銅導線之介層阻抗，進而提高銅製程的良率。此 外，由於本發明進行回火所需要的時間約為丨分鐘，盥習 知技術相較之下，本發明可以大幅度的減少製程的時間， 以提鬲半導體之生產效率和產能。 為使貴審查委員能確實瞭解本發明之目的、特徵及 功效有更進一步的瞭解與認同，兹配合圖式詳細說明如 圖式之簡要說明： 圖係為習知技術形成鑲嵌溝渠之剖面圖； 圖一B係為習知技術形成銅薄膜之剖面圖； 圖4係為習知技術以CMp方式形成銅導線之剖面圖 圖/係為本發明之銅製程方法之流程圖；Page 6503: 5. Description of the invention (4) Purpose of the invention: The main purpose of the present invention is to provide a copper process method which can reduce the resistance of the interlayer to improve the yield of copper wires. The invention discloses a method for copper process. The steps include firstly providing a semiconductor substrate that has completed the previous stage of the integrated circuit, and forming a mosaic trench on the semiconductor substrate; forming a barrier layer and an electrode layer by a deposition method. And then forming a layer of copper film by electroplating; tempering in a reaction furnace for about 1 minute, wherein the pressure of the reaction furnace is controlled below 10E-5T0rr, and the temperature is between 100 ~ 200 c; CMP grinds the copper film to form a copper wire. '' During the tempering process provided by the present invention, during the tempering process, the defects of the internal grains of the copper wire are greatly improved, and the dielectric constant is reduced to reduce the dielectric resistance of the copper wire, thereby improving the impedance of the copper wire. Yield of copper process. In addition, since the time required for the tempering of the present invention is about 1 minute, compared with the conventional technology, the present invention can greatly reduce the process time to improve the production efficiency and capacity of the semiconductor. In order to allow your reviewers to have a better understanding and recognition of the purpose, features and effects of the present invention, we will explain the schematic diagram in detail with the drawings: The diagram is a cross-sectional view of a mosaic trench formed by conventional techniques; FIG. 1B is a cross-sectional view of forming a copper thin film by the conventional technique; FIG. 4 is a cross-sectional view of forming a copper wire by the CMP method of the conventional technique; FIG.

第7頁 4 6 5 C 3Page 7 4 6 5 C 3

已完成積體電路前段製程的半 五、發明說明（5) 圖三A係為本發明所提供之 導體基板示意圖： 圖三B係為本發明形成鑲嵌溝渠示意圖； 圖三C係為本發明形成阻障層和種子層之示意圖 圖三D係為本發明形成銅薄膜之示意圖； 圖三E係為本發明以CMP方式形成銅導線之示意圖 圖式之圖號說明： 11〜第一氤化矽層 第一氣化石夕層 1 5〜開口 1 7〜銅導線 3 1〜第一氮化矽層 33〜第二氮化石夕層 3 5 ~鑲嵌溝渠 37〜種子層 3 9〜鋼導線 10〜半導體基板 12~第一低介電常數介電層 14〜第二低介電常數介電層 1 6〜銅薄膜 30〜半導體基板 32〜第一低介電常數介電層 34〜第二低介電常數介電層 3 6〜阻障層 3 8 ~銅薄膜 詳細說明： 請參閱圖二所示’其係本發明之銅製程方法之流程 圖’本發明之製程方法包括：首先提供一已完成積體電路 之前段製程的半導體基板（21);在上述半導體基板上开^ 成鑲谈溝渠（damacene trench) (22);以沉積方式形成 一阻障層（barrier layer)和種子層（seed layer) (23 );再以電鍍方法形成一層銅薄膜（24 );送入反應爐之 中進行回火1分鐘，其中該反應爐内部之壓力係控制在Half of the previous stage of the integrated circuit has been completed. 5. Description of the invention (5) Figure 3A is a schematic diagram of the conductor substrate provided by the present invention: Figure 3B is a schematic diagram of forming a mosaic trench according to the present invention; Figure 3C is a diagram of the present invention Schematic diagram of barrier layer and seed layer Figure 3D is a schematic diagram of forming a copper thin film of the present invention; Figure 3E is a schematic diagram of forming a copper wire by CMP in the present invention. Layer 1 gasification stone layer 1 5 to opening 1 7 to copper wire 3 1 to first silicon nitride layer 33 to second nitride stone layer 3 5 to inlaid trench 37 to seed layer 3 9 to steel wire 10 to semiconductor Substrate 12 to first low dielectric constant dielectric layer 14 to second low dielectric constant dielectric layer 16 to copper film 30 to semiconductor substrate 32 to first low dielectric constant dielectric layer 34 to second low dielectric constant The constant dielectric layer 36 to the barrier layer 3 8 to the copper thin film are described in detail: Please refer to FIG. 2 'It is a flowchart of the copper process method of the present invention' The process method of the present invention includes: first providing a completed product Semiconductor substrate (21) in the previous stage of the bulk circuit; A dacene trench (22) is formed on the body substrate; a barrier layer and a seed layer (23) are formed by a deposition method; and a copper film (24) is formed by an electroplating method (24). ); Sent to the reaction furnace for tempering for 1 minute, where the pressure inside the reaction furnace is controlled at

第8頁 465031 五、發明說明（6) 10E-5Torr以下’溫度係控制在1〇〇〜2〇(rc之間（25);最 後再以化學機械研磨法（Cheffiical MechanicalPage 8 465031 V. Description of the invention (6) Below 10E-5 Torr, the temperature is controlled between 100 ~ 20 (rc (25); finally, chemical mechanical polishing method (Cheffiical Mechanical

Pol ishing ’ CMP)對上述銅薄膜進行研磨以形成銅導線 (26 )。 請參閱圖三A所示，其係為本發明在步驟（21)所提供 之已完成積體電路前段製程的半導體基板3〇，該半導體基 板3 0表面係依序形成第一氮化矽層3 1，第一低介電常數介 電層32，第二氮化矽層33，第二低介電常數介電層34，請 參閱圖三B所示，係為本發明之步驟（22)在半導體基板上 形成之鑲嵌溝渠35示意圖’其中該鑲嵌溝渠35係藉由連續 兩道微影與银刻技術所形成，請參閱圖三C所示，其係為 本發明之步驟（2 3 )’在半導體基板3 〇表面形成阻障層3 6和 種子層36之示意圖，其中阻障層36係用以阻隔銅薄膜38滲 入氮化矽層之中，其材質係為氮化鈕（TaN)，又該種子層 3 7係做為電鍵電極使銅薄膜3 8可以順利地沉積（請參閱圖 三D所示），圖三E係為銅薄膜38在經過CMP研磨之後形成銅 導線39之示意圖。 本發明之特徵主要係藉由步驟（2 5 )所提供之回火製程 技術’將反應爐内部之壓力控制在l〇E-5Torr以下，同時 將溫度控制在100〜20 0 °C之間並持續回火約i分鐘，以改善 銅導線内部晶粒之缺陷的發展（evolution)，因此本發明 可以降低銅導線於銅介電窗（Cu via)由於熱應力所產生的 破壞（如斷線），根據實際測試結果可知，利用本發明所提 供之鋼製程方法’可以使每8 8萬個銅導線製程之中，因為Pol ishing 'CMP) polishes the copper film to form a copper wire (26). Please refer to FIG. 3A, which is a semiconductor substrate 30 which has completed the previous stage of the integrated circuit provided in step (21) of the present invention, and a first silicon nitride layer is sequentially formed on the surface of the semiconductor substrate 30 3 1. The first low-k dielectric layer 32, the second silicon nitride layer 33, and the second low-k dielectric layer 34, as shown in FIG. 3B, are steps of the present invention (22) Schematic diagram of the inlaid trench 35 formed on the semiconductor substrate 'wherein the inlaid trench 35 is formed by two successive lithography and silver engraving techniques, please refer to FIG. 3C, which is a step of the present invention (2 3) 'A schematic diagram of forming a barrier layer 36 and a seed layer 36 on the surface of the semiconductor substrate 30, wherein the barrier layer 36 is used to prevent the copper thin film 38 from penetrating into the silicon nitride layer, and the material is a nitride button (TaN) The seed layer 37 is used as a key electrode so that the copper film 38 can be deposited smoothly (see FIG. 3D), and FIG. 3E is a schematic diagram of the copper film 38 after the CMP polishing to form a copper wire 39 . The characteristics of the present invention are mainly controlled by the tempering process technology provided in step (2 5) to control the pressure inside the reaction furnace below 10E-5 Torr, and at the same time control the temperature between 100 ~ 20 0 ° C and Tempering is continued for about i minutes to improve the evolution of grain defects inside the copper wire. Therefore, the present invention can reduce the damage (such as wire breakage) of the copper wire in the copper dielectric window (Cu via) due to thermal stress. According to the actual test results, it can be known that the steel process method provided by the present invention can be used to make every 88,000 copper conductors because

4 6· 5 Ο 31 五、發明說明（7) 介層窗R(Cu via resistance)的不良而道 原來的30-100%降低至〇〜2% ，進而使铜制致製程的失敗由 大幅地改善，此外’本發明之銅製程方程的良率獲得 鐘進行回火製程，相較於習知技術必須=需要花費1分 火製程’本發明可以大幅地縮短整體製30分鐘進行回 半導體的產能和生產效率。 、時間’以提高 種方法之較佳實施 ’任何熟習該項技 均應屬於本發明之 所述之申請專利範 當然’以上所述僅為本發明之銅製 例’其ϋ非用以限制本發明之實施範圍 藝者在不違背本發明之精神所做之修改 範圍，因此本發明之保護範圍當以下列 圍做為依據。4 6 · 5 Ο 31 V. Description of the invention (7) The defect of the via window R (Cu via resistance) is reduced from 30-100% to 0 ~ 2%, and the process failure caused by copper is greatly reduced. Improvement, in addition, 'the yield rate of the copper process equation of the present invention is obtained by performing the tempering process, compared with the conventional technology, it must = 1 minute of the tempering process is required.' The present invention can greatly reduce the overall production capacity of 30 minutes for semiconductor recycling. And productivity. "Time to improve the implementation of this method." Any familiarity with this technology should belong to the patent application scope of the present invention. Of course, the above is only a copper example of the present invention. It is not intended to limit the present invention. The scope of implementation The scope of modifications made by the artist without departing from the spirit of the invention, so the scope of protection of the invention should be based on the following.

圖式簡單說明 圖式之簡要說明： 圖一 A係為習知技術形成鑲嵌溝渠之剖面圖； 圖一 B係為習知技術形成銅薄膜之剖面圖； 圖一C係為習知技術以CMP方式形成銅導線之剖面圖； 圖二係為本發明之銅製程方法之流程圖； 圖三A係為本發明所提供之已完成積體電路前段製程的半 導體基板示意圖， 圖三B係為本發明形成鑲嵌溝渠示意圖； 圖三C係為本發明形成阻障層和種子層之示意圖； 圖三D係為本發明形成銅薄膜之示意圖； 圖三E係為本發明以CMP方式形成銅導線之示意圖。Brief description of the drawing Brief description of the drawing: Figure 1A is a cross-sectional view of forming a mosaic trench using conventional techniques; Figure 1B is a cross-sectional view of forming a copper thin film using conventional techniques; Figure 1C is a conventional technique using CMP Figure 2 is a cross-sectional view of a copper wire method; Figure 2 is a flowchart of the copper process method of the present invention; Figure 3A is a schematic diagram of a semiconductor substrate that has completed the pre-process of a integrated circuit provided in the present invention, and Figure 3B is a Schematic diagram of the formation of inlaid trenches according to the invention; Fig. 3C is a schematic diagram of the formation of a barrier layer and a seed layer according to the invention; Fig. 3D is a schematic diagram of the formation of a copper thin film according to the invention; schematic diagram.

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Claims (1)

46 50 31 六、申請專利範園 申請專利範圍 1. —種銅製程的方法，其製程步 U)提供一已完成積體電路 匕括. (b) 在上述半導體基板上 又製軚的半導體基板； (c) 以電鍍方法形成—層鋼薄膜；冓木， (d) 在小於l〇E_5t〇rr的大氣壓 (e) 以CMP對上述銅薄膜進 下進行回火； 2, 如申請專利範圍第1項所述之二形成銅導線。 之半導體基板表面係依/銅I程方法’其中步驟U) 電常數介電層，第二氮化J第；氮第-低介 層。 ’曰 第一低介電常數介電 範圍第1項所述之銅製程方法，其中步驟⑻ 4如ί i連續兩道微影與蝕刻技術形成鑲嵌溝渠。 .σ申請專f範圍第1項所述之銅製程方法，其中步驟（c) 5 電鍵銅薄臈之前係先沉積一阻障層和一種子層。 其中步驟（c) 其中步驟（c ) 述之銅製程方法，其中步驟（d) •ΐΐίΐί範圍第4項所λ之銅製程方法，其中s步驟（c) ^ s糸可以避免銅薄膜渗入亂化砂層之中。 ..如申請專利範固第4項所述之銅製程方法^ ’ 7 2阻Ϊ層之材質係為氮化组。 .°申請專利範圍第4項所述之銅製程方法 8如ί:層係做為電鍍電極° .:申请專利範圍第1像所述之銅製程方法，其中步驟（d 係以反應爐進行回火，其内部之溫度係控制在1〇〇~2〇〇 C之間。46 50 31 VI. Applying for a patent Fan Yuan applies for a patent scope 1. — A method of copper process, its process step U) provides a completed integrated circuit dagger. (B) a semiconductor substrate fabricated on the above semiconductor substrate (C) formed by electroplating—a layer of steel film; alder, (d) tempering the above-mentioned copper film by CMP at an atmospheric pressure of less than 10E_5 torr; 2, as described in the patent application The second item of item 1 forms a copper wire. The surface of the semiconductor substrate is in accordance with the copper I-process method, wherein step U) the dielectric constant dielectric layer, the second nitride is the first, and the nitrogen is the low dielectric layer. The copper process method described in item 1 of the first low-dielectric-constant range, wherein step 如 4 is to form a mosaic trench as two successive lithography and etching techniques. The .σ application applies to the copper process method described in item 1 of the scope, wherein step (c) 5 is a step of depositing a barrier layer and a sub-layer prior to the copper thin bond wire. Wherein step (c) is the copper process method described in step (c), wherein step (d) is the copper process method of lambda in the 4th item of the scope of ΐΐίΐί, where step s (c) ^ s 糸 can prevent the infiltration and disorder of the copper film Among the sand. .. The copper process method described in item 4 of the patent application ^ ^ 7 2 The material of the hafnium resist layer is a nitride group. . ° Application of the copper process method described in item 4 of the patent scope 8 such as: layer system as the electroplating electrode °.: Application of the copper process method described in the first scope of the patent application, wherein step (d is performed by a reaction furnace The internal temperature of the fire is controlled between 1000 and 2000C. 12 I 46503112 I 465031 第13頁Page 13