經濟部智慧財產局具工消費合作社印製 4 6 32 9 5 a? B7 五、發明說明（） 發明領M· 本發明是有關於一種之半導體記憶體的製造方法，且 特別是有關於一種隔離垂直式電晶體與深溝渠電容器之絕 緣結構的製造方法。 發明背量 隨著半導體電路的積集度提高，半導體元件的尺寸也 必須隨著縮小。因此傳統之縮小元件尺寸的技術將會受到 對於元件漏電流之嚴格要求限制。對於傳統的動態隨機存 取記憶體（Dynamic Random Access Memory ; DRAM)之單 元記億胞，雖然其電容器之設計已經朝三度空間來發展’ 但是其電晶體之設計仍侷限在二度空間上。因此使得 DRAM的積集度受到相當程度的限制。 在1"9年IEEE專業雜誌上，Gmening等人發表了 sub-8F2之DRAM記憶胞的結構。此DRAM記億胞係由位 於深溝渠之垂直電晶體與深溝渠電容器所構成，可以大幅 提昇 DRAM 言Η 憚脾積隼茚（A Novel Trench DRAM Cell With a VERtTcal Access Transistor and RnriEd Strap (VERI RFST、for 4Gh/16Ghr p25. 19Q9 TFDM)。在 sub-8F2 之 DRAM記憶胞中，位於深溝渠內水平方向的溝渠頂氧化層 (trench top 0Xide)是做爲深溝渠電容器與垂直電晶體間之 絕緣結構用的。一般來說，要在溝渠內製造垂直向的絕緣 • 2 ^^1 - n ti n IK· i - , i I^HI -n n n 一&， ^1- _ 4 1 n I 線--- (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 4 6 32 9 5 Α7 Β7 經濟部智慧財產局員工消費合作社印製 五、發明說明（） 層較容易，可以利用間隙壁(spacer)的製造方法來製作之。 但是溝渠內水平方向的絕緣層就比較餘j故了。 發朋目韵與槪沭 因此本發明的主要目的就是在提供一種隔離垂直電晶_ Μ與深溝渠電容器之絕緣結構的製造方法。絕緣結構之製 造方法可以整合至後續之垂直電晶體的製程中，並有效隔 離深溝渠電容器與垂直電晶體。 此方法可應用於一基底上。在基底上依序形成一層墊 氧化層與一層氮化矽層，接著以蝕刻方式在基底中形成一 個深溝渠，再於此深溝渠底部已形成一個深溝渠電容器。 此方法至少包括以高密度電漿化學氣相沈積法形成絕緣層 於基底上與部分塡充於深溝渠中，其中位在深溝渠側壁上 之絕緣層的厚度小於位在深溝渠電容器與基底上之絕緣層 &5_屋度。然後去除絕緣層’直至深溝渠之側壁暴露出來爲 止，並使絕緣層轉化成位於深溝渠中之第一絕緣層與位於 該氮化矽層上之第二絕緣層。接著形成保護層於第一絕緣 層上，再以濕蝕刻法去除氮化矽層’使第二絕緣層亦一起 被去除。然後植入離子於深溝渠周圍之基底中，再依序去 除墊氧化層與保護層。接著形成閘氧化層於暴露出之基底 表面上，並形成淺溝渠隔離於基底中，此淺溝渠隔離部分 重疊於深溝渠之上’然後形成閘極於深溝渠上。 3 (請先閱讀背面之注意事項再填寫本頁) Τ 么·ί 良 本紙張尺度適用ΐ國國家標準（CNS)A4規格（210 χ 297公釐） A7 463295 __B7__________ 五、發明說明（） 本發明的另一目的是在提供一種垂直電容器的製造方 法，包括有提供一基底，在基底上依序形成一墊氧化層與 —氮化矽層，接著在此基底中形成深溝渠，然後在深溝渠 底部形成深溝渠電容器。接下來，形成絕緣層於基底上與 深溝渠中，且絕緣層之表面高於基底之表面。然後去除絕 緣層直至深溝渠之上端部分之側壁暴露出來爲止，再形成 保護層於深溝渠中之殘餘絕緣層上。接著去除氮化矽層， 再植入離子於該深溝渠周圍之該基底中。依序去除墊氧化 層與保護層，然後形成閘氧化層於暴露出之基底表面上。 再形成導電層於基底上與深溝渠中，然後形成淺溝渠隔離 於基底中，並使其部分重疊於深溝渠之上，再圖案化導電 層以形成閘極於深溝渠上端。 其中上述去除部分絕緣層之方法，例如可以先利用化 學機械硏磨法去除高於氮化矽層之絕緣層，再使用乾蝕刻 法來回蝕深溝渠中之絕緣層的上端部分。爲了方便化學機 械硏磨法之進行，絕緣層之表面高度較佳爲比氮化矽層之 表面高度高出大約8000至10000埃。 本發明之再一目的爲提出一種隔離垂直電晶體與深溝 渠電容器之絕緣結構的製造方法，可應用於一基底上。此 基底上依序已形成墊氧化層與氮化矽層。基底中已形成深 4 本紐尺度適閱家標準（CNS)A4規格（210 X 297公^ -ΠΪ n »^1 ^1- n I ^ F ^1 ^1 1 l^i H 一OJt I (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 4 632 9 5 A7 B7 五、發明說明（） 溝渠，且深溝渠底部已形成深溝渠電容器。該方法至少包 括以高密度電漿化學氣相沈積法形成絕緣層於基底上與深 溝渠中，其中深溝渠中之絕緣層的表面約和氮化矽層之表 面等高。然後彤成犧牲層於絕緣層上，此犧牲層之表面比 氮化矽層之表面高出約8000至10000埃。以化學機械硏 磨法去除高於氮化矽層之犧牲層與絕緣層，再回蝕位於深 溝渠中之絕緣層之上端部分，並形成垂直電晶體於深溝渠 中0 由上述可知，應用本發明可製造出位於深溝渠中之水 平方向絕緣層，用以隔絕深溝渠電容器與垂直電晶體。發 展出此製程，將可大幅提昇半導體積體電路，尤其是DRAM 之積集度。 (請先閱讀背面之注意事項再填寫本頁) Γ 經濟部智慧財產局員工消費合作社印製 圖式之簡單說明 爲讓本發明之上述和其他目的'特徵、和優點能更明 顯易懂’下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 第1A - 1G圖係繪示依照本發明一較佳實施例的一種 隔離垂直電晶體與深溝渠電容器之絕緣結構的製造流程剖 面圖； 第2A - 2C圖係繪示依照本發明另一較佳實施例的一 5 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 463295 A7 B7 ^ ^ ---- 五、發明說明（） 種隔離垂直電晶體與深溝渠電容器之絕緣結構的製胃 剖面圖；以及 第3A - 3C圖係繪示依照本發明再一較佳實施例的一 種隔離垂直電晶體與深溝渠電容器之絕緣結構的製造流程 剖面圖。 圖式之標記說明 100、200、300 :基底 105、205、305 :墊氧化層 120、220、320 :氮化矽層 125、225、325 :深溝渠 130、230、330 :摻雜區 135、235、335 :薄介電層 140、240、340 :摻雜多晶矽層 145、245、345 :環氧化層 150、250、350 :摻雜多晶矽層 155、255、355 :摻雜多晶矽層 160、260、360 :絕緣層 160a、160b、260a、360a :絕緣層 165、265、365 :保護層 170、270、370 :摻雜區 175、175a :閘氧化層 180、180a :摻雜區 6 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ]I I ----Ί l· I.---i 1 ———— — —1— · I I i 1 I I I I (請先閱讀背面之注意事項再填寫本頁) A7 463295 B7__ 五、發明說明（） 181、181a、181b 慘雜多晶砂層 182 :氮化砂層 184 :開口 186 :淺溝渠隔離 188 :金屬矽化物層 190 :頂蓋層 192 :間隙壁 362 :犧牲層 實施例一 請參照第1A - 1G圖，其繪示依照本發明一較佳實施 例的一種隔離垂直電晶體與深溝渠電容器之絕緣結構的製 造流程剖面圖。在實施例一中，不僅敘述了此絕緣結構的 製造方法，也說明了如何整合此絕緣結構與後續垂直電晶 體的製造方法。 請參考第1A圖，在基底100上依序形成墊氧化層 105、氮化矽層120與硼矽玻璃層（圖上未示出）。然後圖案 化硼矽玻璃層，以硼矽玻璃層做爲蝕刻罩幕來蝕刻氮化矽 層120、墊氧化層105與基底100，在基底1〇〇中形成深 溝渠125。蝕刻完成後，除去硼矽玻璃層。 對深溝渠125之底部部分的基底1〇〇中進行離子摻 7 — — — —-——-— — —1— ^ ———— — —II «— — ill — —— <請先間讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） A7 4 6 32 9 5 ___B7___ 五、發明說明（） 雜，以形成摻雜區130來做爲深溝渠電容器之下電極板。 在摻雜區130之表面上形成一薄介電層135，做爲深溝渠 電容器之介電層，其材質例如可爲氮化矽/氧化矽複層或 其他適合的介電材料。接著在深溝渠125底部塡入摻雜多 晶矽層140以做爲深溝渠電容器之上電極板。 然後，在深溝渠125上電極板上方之部分側壁上形成 環氧化層(collar oxide) 145以減少深溝渠125側壁之寄生 漏電流(parasitic leakage)。接著在由環氧化層145所圍繞 著的空間內塡入摻雜多晶矽層150,在於其上形成摻雜多 晶矽層155。摻雜多晶矽層150與155是用來做爲深溝渠 電容器與垂直電晶體間之導電通路。 在基底1〇〇上形成絕緣層160以覆蓋氮化矽層120、 摻雜多晶矽層155與深溝渠125之側壁。絕緣層160的形 成方法較佳爲高密度電漿化學氣相沈積法（high-density plasma chemical vapor deposition ; HDPCVD)，而其材質 例如可爲氧化矽。在使用高密度電漿化學氣相沈積法來沈 積絕緣層的過程中，因爲高密度電漿中之高能量離子不停 地撞擊，使得深溝渠125側壁之絕緣層的厚度遠小於摻雜 多晶矽層155或氮化矽層Π0上之厚度。使用高密度電漿 化學氣相沈積法來沈積絕緣層160之原因係由於其良好的 階梯覆蓋性(step coverage)。 . 8 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -I--—IT·'-------^ --------訂--I-----線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 463295 A7 __B7_____ 五、發明說明（）， 在第1B圖中，去除位於深溝渠Π5側壁的絕緣層160 與位於摻雜多晶矽層與氮化矽層上之部分表層厚 度的絕緣層〖6〇，只留下摻雜多晶矽層丨55之上的絕緣層 l6〇a與氮化砍層12〇上之絕緣層160b。去除部分絕緣層160 的方法，例如可爲濕蝕刻法。若絕緣層16〇的材質舄氧化 矽時，可使用9F溶液來進行蝕刻之。其中在摻雜多晶石夕 層I55上之絕緣層160a將做爲深溝渠電容器與後續將會 形成的垂直電晶體間之絕緣結構，而其厚度較佳爲300 -900 埃。 接著在絕緣層160a之上形成保護層165，其材質例如 可爲光阻。若保護層165之材質爲光阻，其形成方法例如 可爲先利用旋塗法(spin coating)光阻塗佈在基底100上， 並塡滿深溝渠125，再利用回蝕法將深溝渠125外之光阻 去掉，只留下深溝渠125內之絕緣層160a上的部分光阻， 即爲保護層165。 在第1C圖中，去除氮化矽層120，而在氮化矽層120 上之絕緣層160b也一起跟著被剝離而去除了。去除氮化 矽層120的方法例如可使用濕蝕刻法，因爲熱磷酸對於氮 化矽之蝕刻選擇性很高，其蝕刻劑以熱磷酸爲較佳之選 擇。接下來，進行離子植入步驟，在深溝渠125周圍之基 9 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） Ί--1ΙΙΓΙ····二 —1訂- - - ------ (請先閱讀背面之达意事項再填寫本頁) 463295 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（） 底100中形成摻雜區170。 在第1D圖中，例如可以濕蝕刻法來去除墊氧化層 105，較佳之蝕刻劑爲HF溶液。然後去除保護層165，若 保護層165之材質爲光阻時，例如可以氧電漿將其灰化 (ashing)，再以淸潔溶液淸洗。接著進行熱氧化步驟，在 暴露出之基底1〇〇表面形成一層閘氧化層175。在進行熱 氧化步驟期間，因爲是處於高溫狀態下，因此摻雜區Π0 之摻雜離子可以一起進行活化步驟，同時，摻雜多晶矽層 155之摻雜離子也可以擴散至其周圍之基底100中，形成 摻雜區180。如此摻雜區180與170可分別做爲垂直電晶 體之源極與汲極。 在第1E圖中，接著在深溝渠125中與基底100上形 成摻雜多晶矽層181，再於摻雜多晶矽層181上形成氮化 石夕層182。然後在氮化砍層182中形成一個開口 184，暴 露出摻雜多晶矽層181之表面。開口 184有部分是和深溝 渠125重疊的。一般來說開口 184是圍繞著主動區的，通 常在主動區上至少有一電晶體會形成於其上。 在第1F圖中，以氮化矽層182做爲蝕刻罩幕，蝕刻 暴露出之摻雜多晶矽層181與位於其下之各層形成一個溝 渠於基底100中。再塡入絕緣材料於溝渠中，形成淺溝渠 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） υ I ] f— n n I - i 一OJI p^i n n I (請先閱讀背面之注意事項再填寫本頁) 463295 A7 B7 五、發明說明（） 隔離186。殘留之摻雜多晶矽層181以181a表示。 在第1G圖中，去除氮化矽層182，再於基底100上 依序形成金屬矽化物層188與頂蓋層190。然後圖案化頂 蓋層190、金屬矽化物層188與摻雜多晶矽層181a，形成 由摻雜多晶矽層1 8 lb、金屬矽化物層188與頂蓋層190所 組成之閘極結構，其中摻雜多晶矽層181b與金屬矽化物 層188爲垂直電晶體之閘極。接下來，在閘極結構之側壁 上形成間隙壁192。 ' 其中金屬矽化物層188的材質例如可爲矽化鎢、矽化 鈦或其他合適之金屬矽化物。頂蓋層190之材質例如可爲 氧化矽或氮化矽。而間隙壁192的材質例如可爲氮化矽或 氧化砂。 在實施例一之第1A圖中，絕緣層160是使用高密度 電漿化學氣相沈積法所沈積的。在沈積過程中，高密度電 漿中之離子濺鍍造就了絕緣層160之特殊外形，使得深溝 渠125側壁上之絕緣層160厚度較薄。因此將其去除所需 之時間亦較短，所以可控制蝕刻時間長短，使深溝渠 側壁上之絕緣層160被蝕刻掉之後’深溝渠125內摻雜多 晶矽層155上仍留有絕緣層160a(請見第1B圖）’形成深 溝渠電容器與垂直電晶體間之絕緣結構。 (請先閱讀背面之注意事項再填寫本頁) 言 Γ 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 463295 A7 _______B7_ 玉、發明說明（） 實施例二 請參考第2A — 2c圖，其係繪示依照本發明另一較佳 實施例的一種隔離垂直電晶體與深溝渠電容器之絕緣結構 的製造流程剖面圖。在第2A - 2C圖中比第1A - 1G圖大 100之標號’其所代表之材料與製造方法是相同的。 在第2A圖中，自在基底200上形成墊氧化層205至 在深溝渠225中形成摻雜多晶砂層255之製造流程和第1A 圖是類似的’因此不再贅述。接下來在氮化矽層220與深 溝渠225內形成絕緣層260，其形成方法例如可爲高密度 電漿化學氣相沈積法，而其材質例如可爲氧化矽。 在第2B圖中，去除在氮化矽層220表面上與在深溝 渠2M中上端部分的絕緣層260，在深溝渠225中摻雜多 晶矽層255上形成深溝渠電容器與垂直電晶體間之絕緣結 構，亦即絕緣層260a。絕緣層260a之厚度較佳約爲300 -900 埃。 去除部分絕緣層260 方法，例如可使用化學機械硏 磨法先將氮化矽層220上之絕緣層260去除之，再利用回 蝕去除位於深溝渠225內部分之絕緣層260，留下特定厚 12 I-----------------i I-----訂·---------- (請先間讀背&之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 4 6 32 9 5 A7 B7 五、發明說明（） 度之絕緣層260a。因此在形成絕緣層260時’較佳爲使其 高度比氮化矽層220之高度高出大約8〇〇〇 - 10000埃，以 利化學機械硏磨法之進行。而在回蝕步驟中’較佳爲使用 乾蝕刻法，例如可使用反應離子蝕刻法（Reactive Ion Etching ; RIE)來進行回蝕步驟。 在第2C圖中，在絕緣層260a上形成保護層265，保 護層265之材質例如可爲光阻。然後去除氮化矽層220， 再進行離子植入步驟於基底200中形成摻雜區27〇。後續 之步驟和在第ID - 1G圖所說明之流程類似，在此不再贅 述。 在實施例二中，在第2A圖之氮化矽層220上之絕緣 層260的厚度比第1A圖之氮化矽層120上之絕緣層160 的厚度要厚，以利於後續使用化學機械硏磨法來去除位於 氮化矽層220上之絕緣層260。如此可藉由絕緣層260的 回蝕步驟/準確控制絕緣層260a的厚度，並視需要大幅 調整絕緣層260a的厚度。 實施例三 請參照第3A - 3C圖，其係繪示依照本發明再一較佳 實施例的一種隔離垂直電晶體與深溝渠電容器之絕緣結構 ----—-1—------ r--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） A7 463295 _____B7_____ 五、發明說明（） 的製造流程剖面圖。在第3A-3C圖中之標號比第ία - 1G 圖標號大200者，其所代表之意義是相同的。 在第3A圖中，自在基底300上形成墊氧化層至在深 溝渠3M中形成摻雜多晶矽層355之製造流程和第1A圖 是類似的，因此不再贅述。接下來在氮化矽層320與深溝 渠325中形成絕緣層360，而且在深溝渠325中之絕緣層 360表面和氮化矽層320表面的高度差不多。絕緣層360 之形成方法例如可爲高密度電漿化學氣相沈積法，而其材 質例如可爲氧化矽。 接下來，在絕緣層360上形成犧牲層362，其材質例 如可爲利用低壓化學氣相沈積法或次常壓化學氣相沈積法 所形成之氧化矽或者是旋塗式玻璃。犧牲層_362是用來增 加自氮化矽層？20上之絕緣層360與犧牲層362之總厚度， 此總厚度較佳約爲8000 - 10000埃，以利後續化學機械硏 磨法之進行。 在第3B圖中，使用化學機械硏磨法來去除高於氮化 矽層320之絕緣層360與犧牲層362。接著進行回蝕步驟， 去除位於深溝渠3M內上端大部分之絕緣層360 ’留下絕 緣層360a於摻雜多晶矽層355上，做爲深溝渠電容器與 垂直電晶體間之絕緣結構。 14 -I------- U--------^ ------------i — 線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中困國家標準<CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 6 32 9 b A7 ________B7____ 五、發明說明（） 在第3C圖中，在絕緣層360a上形成一層保護層365， 其材質例如可爲光阻材料。接著，去除氮化矽層320。再 進行離子植入，在基底300中形成摻雜區370，做爲後續 將形成之垂直電晶體的一個源極/汲極。後續之步驟和在 第ID - 1G圖所說明之流程類似，因此不再贅述》 在實施例三中，第2A圖中之絕緣層260的上層部分 被犧牲層362取代。其因爲高密度電漿化學氣相沈積法之 花費較貴，所以使用成本較低之低壓化學氣相沈積法或次 常壓化學氣相沈積法來形成犧牲層，或者使用旋塗式玻璃 來形成犧牲層。如此仍能維持氮化矽層320上之絕緣層360 與犧牲層362之一定總厚度以方便化學機械硏磨法之進 行，但是又可以降低成本。 由上述本發明較佳實施例可知，應用本發明可以相當 容易地在深溝渠內形成水平方向之絕緣層，對於提昇半導 體元件的積集度有極大助益。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 本紙張尺度適用中國國家標準（CNS)A4規格（210x297公釐） I. „--------------訂---------線 (請先閱讀背面之注意事項再填寫本頁)Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Industrial Cooperatives 4 6 32 9 5 a? B7 V. Description of the Invention () Invention Field M · The present invention relates to a method for manufacturing a semiconductor memory, and in particular to an isolation method. Manufacturing method of insulating structure of vertical transistor and deep trench capacitor. Back to the Invention With the increase in the degree of accumulation of semiconductor circuits, the size of semiconductor elements must also be reduced. Therefore, traditional technology for reducing component size will be limited by the strict requirements for component leakage current. For the traditional dynamic random access memory (DRAM) units, which are recorded in billions of cells, although the capacitor design has been developed towards three degrees of space, 'the design of its transistors is still limited to two degrees of space. Therefore, the accumulation degree of DRAM is limited to a considerable degree. In 1 &9; IEEE Professional Magazine, Gmening et al. Published the structure of DRAM memory cell of sub-8F2. This DRAM memory cell line is composed of vertical transistors and deep trench capacitors located in deep trenches, which can greatly improve DRAM speech. A Novel Trench DRAM Cell With a VERtTcal Access Transistor and RnriEd Strap (VERI RFST, for 4Gh / 16Ghr p25. 19Q9 TFDM). In the DRAM memory cell of sub-8F2, the trench top oxide layer (trench top 0Xide) located horizontally in the deep trench is used as the insulation structure between the deep trench capacitor and the vertical transistor. Used. Generally speaking, vertical insulation is to be made in the trenches. 2 ^^ 1-n ti n IK · i-, i I ^ HI -nnn 一 &, ^ 1- _ 4 1 n I line- -(Please read the notes on the back before filling out this page) This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 4 6 32 9 5 Α7 Β7 Printed by the Consumers ’Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 5. The description of the invention () layer is relatively easy, and it can be made by the method of manufacturing the spacer. However, the horizontal insulation layer in the trench is more redundant. Therefore, the present invention The main purpose is to provide a Isolation of vertical transistor _ M and deep trench capacitor insulating structure manufacturing method. The manufacturing method of the insulating structure can be integrated into the subsequent vertical transistor manufacturing process, and effectively isolate the deep trench capacitor from the vertical transistor. This method can be applied to A substrate. A pad oxide layer and a silicon nitride layer are sequentially formed on the substrate, and then a deep trench is formed in the substrate by etching, and a deep trench capacitor has been formed at the bottom of the deep trench. This method includes at least The high-density plasma chemical vapor deposition method is used to form an insulating layer on the substrate and partially fill the deep trench. The thickness of the insulating layer on the side wall of the deep trench is smaller than the insulating layer on the deep trench capacitor and the substrate. 5_ 屋 度. Then remove the insulation layer 'until the sidewall of the deep trench is exposed, and convert the insulation layer into a first insulation layer located in the deep trench and a second insulation layer located on the silicon nitride layer. Then A protective layer is formed on the first insulating layer, and then the silicon nitride layer is removed by wet etching so that the second insulating layer is also removed together. Then implanted Subsequent to the substrate around the deep trench, the pad oxide layer and the protective layer are sequentially removed. Then, a gate oxide layer is formed on the exposed substrate surface, and a shallow trench isolation is formed in the substrate. The shallow trench isolation portion overlaps the deep trench. Above the ditch 'and then the gate is formed on the deep ditch. 3 (Please read the precautions on the back before filling in this page) Τ Mody · The paper size of the good paper is applicable to the national standard (CNS) A4 (210 x 297) (Centi) A7 463295 __B7__________ 5. Description of the invention () Another object of the present invention is to provide a method for manufacturing a vertical capacitor, which includes providing a substrate, and sequentially forming a pad oxide layer and a silicon nitride layer on the substrate. A deep trench is then formed in this substrate, and then a deep trench capacitor is formed at the bottom of the deep trench. Next, an insulating layer is formed on the substrate and in the deep trenches, and the surface of the insulating layer is higher than the surface of the substrate. Then the insulation layer is removed until the side wall of the upper end portion of the deep trench is exposed, and then a protective layer is formed on the remaining insulating layer in the deep trench. Then, the silicon nitride layer is removed, and ions are implanted in the substrate around the deep trench. The pad oxide layer and the protective layer are sequentially removed, and then a gate oxide layer is formed on the exposed substrate surface. Then, a conductive layer is formed on the substrate and in the deep trench, and then a shallow trench is formed in the substrate to be partially overlapped with the deep trench, and then the conductive layer is patterned to form a gate at the upper end of the deep trench. The above method for removing a part of the insulating layer may, for example, first use a chemical mechanical honing method to remove the insulating layer higher than the silicon nitride layer, and then use a dry etching method to etch back the upper end portion of the insulating layer in the deep trench. To facilitate the chemical mechanical honing method, the surface height of the insulating layer is preferably about 8000 to 10,000 Angstroms higher than the surface height of the silicon nitride layer. Another object of the present invention is to provide a method for manufacturing an insulating structure that isolates a vertical transistor from a deep trench capacitor, which can be applied to a substrate. A pad oxide layer and a silicon nitride layer have been sequentially formed on the substrate. A depth of 4 CNS A4 specifications (210 X 297 mm ^ -ΠΪ n »^ 1 ^ 1- n I ^ F ^ 1 ^ 1 1 l ^ i H-OJt I ( Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 632 9 5 A7 B7 V. Description of the invention () The trench, and a deep trench capacitor has been formed at the bottom of the trench. This method includes at least A high-density plasma chemical vapor deposition method is used to form an insulating layer on a substrate and in a deep trench. The surface of the insulating layer in the deep trench is about the same height as the surface of the silicon nitride layer. Then, a sacrificial layer is formed on the insulating layer. The surface of this sacrificial layer is about 8000 to 10,000 Angstroms higher than that of the silicon nitride layer. The sacrificial layer and the insulating layer higher than the silicon nitride layer are removed by a chemical mechanical honing method, and the insulation located in the deep trench is etched back The upper part of the layer forms a vertical transistor in the deep trench. From the above, it can be known that the application of the present invention can produce a horizontal insulation layer in the deep trench to isolate the deep trench capacitor from the vertical transistor. This process was developed Will greatly improve semiconductor Circuit, especially the accumulation of DRAM. (Please read the notes on the back before filling out this page.) Γ A simple description of the printed drawings of the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs is to make the above and other purposes of the present invention. , And advantages can be more obvious and easy to understand 'The following is a detailed description of a preferred embodiment, and in conjunction with the accompanying drawings, the detailed description is as follows: Figures 1A-1G show an isolated vertical according to a preferred embodiment of the present invention Cross-sectional view of the manufacturing process of the insulating structure of the transistor and the deep trench capacitor; Figures 2A-2C show a 5th paper according to another preferred embodiment of the present invention. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 463295 A7 B7 ^ ^ Ⅴ. Description of the invention () A sectional view of the stomach of a kind of insulation structure that isolates vertical transistors from deep trench capacitors; and Section 3A -3C is a cross-sectional view showing the manufacturing process of an insulating structure that isolates a vertical transistor from a deep trench capacitor in accordance with yet another preferred embodiment of the present invention. 300: substrates 105, 205, 305: pad oxide layers 120, 220, 320: silicon nitride layers 125, 225, 325: deep trenches 130, 230, 330: doped regions 135, 235, 335: thin dielectric layer 140 , 240, 340: doped polycrystalline silicon layers 145, 245, 345: epoxidized layers 150, 250, 350: doped polycrystalline silicon layers 155, 255, 355: doped polycrystalline silicon layers 160, 260, 360: insulating layers 160a, 160b, 260a, 360a: Insulating layers 165, 265, 365: Protective layers 170, 270, 370: Doped regions 175, 175a: Gate oxide layers 180, 180a: Doped regions 6 This paper standard applies to China National Standard (CNS) A4 specifications (210 X 297 mm)] II ---- Ί l · I .--- i 1 ———— — —1— · II i 1 IIII (Please read the notes on the back before filling this page) A7 463295 B7__ V. Description of the invention (181) 181a, 181b Miscellaneous polycrystalline sand layer 182: Nitrided sand layer 184: Opening 186: Shallow trench isolation 188: Metal silicide layer 190: Cap layer 192: Spacer wall 362: Sacrificial layer Embodiment 1 Please refer to FIGS. 1A to 1G, which illustrate an insulation junction between a vertical transistor and a deep trench capacitor according to a preferred embodiment of the present invention. Sectional flow-making system of FIG. In the first embodiment, not only the manufacturing method of the insulating structure is described, but also how to integrate the insulating structure with the subsequent manufacturing method of the vertical electric crystal is described. Referring to FIG. 1A, a pad oxide layer 105, a silicon nitride layer 120, and a borosilicate glass layer (not shown in the figure) are sequentially formed on the substrate 100. Then, a borosilicate glass layer is patterned, and the borosilicate glass layer is used as an etching mask to etch the silicon nitride layer 120, the pad oxide layer 105 and the substrate 100, and a deep trench 125 is formed in the substrate 100. After the etching is completed, the borosilicate glass layer is removed. Ion doping in the substrate 100 of the bottom part of the deep trench 125 — — — — — — — — — — 1 — ^ — — — — II «— — ill — —— < Read the notes on the back and fill in this page) Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper is printed in accordance with China National Standard (CNS) A4 (210 X 297 mm) A7 4 6 32 9 5 ___B7___ V. Description of the invention () Doped to form the doped region 130 as the electrode plate under the deep trench capacitor. A thin dielectric layer 135 is formed on the surface of the doped region 130 as a dielectric layer of a deep trench capacitor. The material may be, for example, a silicon nitride / silicon oxide multilayer or other suitable dielectric material. Next, a doped polysilicon layer 140 is implanted at the bottom of the deep trench 125 as an electrode plate above the deep trench capacitor. Then, a collar oxide layer 145 is formed on a part of the sidewall above the electrode plate on the deep trench 125 to reduce parasitic leakage on the sidewall of the deep trench 125. Next, a doped polycrystalline silicon layer 150 is implanted into the space surrounded by the epoxidized layer 145, and a doped polycrystalline silicon layer 155 is formed thereon. The doped polycrystalline silicon layers 150 and 155 are used as conductive paths between deep trench capacitors and vertical transistors. An insulating layer 160 is formed on the substrate 100 to cover the sidewalls of the silicon nitride layer 120, the doped polycrystalline silicon layer 155, and the deep trench 125. The method for forming the insulating layer 160 is preferably a high-density plasma chemical vapor deposition (HDPCVD) method, and the material thereof may be, for example, silicon oxide. In the process of depositing an insulating layer using a high-density plasma chemical vapor deposition method, because the high-energy ions in the high-density plasma constantly strike, the thickness of the insulating layer on the side wall of the deep trench 125 is much smaller than that of the doped polycrystalline silicon layer. 155 or silicon nitride layer Π0. The reason why the high-density plasma chemical vapor deposition method is used to deposit the insulating layer 160 is due to its good step coverage. . 8 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) -I --- IT · '------- ^ -------- Order--I- ---- Line (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Employee Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by 463295 A7 __B7_____ V. Description of Invention () In FIG. 1B, the insulating layer 160 located on the side wall of the deep trench Π5 and a part of the surface thickness insulating layer [60] on the doped polycrystalline silicon layer and the silicon nitride layer are removed, leaving only the insulation on the doped polycrystalline silicon layer 55. The layer 160a and the insulating layer 160b on the nitride cutting layer 120. A method of removing a part of the insulating layer 160 may be, for example, a wet etching method. If the material of the insulating layer 16 is silicon oxide, a 9F solution can be used for etching. The insulating layer 160a on the doped polycrystalline silicon layer I55 will serve as an insulating structure between a deep trench capacitor and a vertical transistor to be formed later, and its thickness is preferably 300 to 900 Angstroms. Next, a protective layer 165 is formed on the insulating layer 160a, and the material may be, for example, a photoresist. If the material of the protective layer 165 is a photoresist, the formation method may be, for example, firstly coating the photoresist on the substrate 100 with a spin coating method, filling the deep trench 125, and then using the etchback method to cover the deep trench 125. The external photoresist is removed, leaving only a portion of the photoresist on the insulating layer 160a in the deep trench 125, which is the protective layer 165. In FIG. 1C, the silicon nitride layer 120 is removed, and the insulating layer 160b on the silicon nitride layer 120 is also stripped and removed together. The method for removing the silicon nitride layer 120 can be, for example, a wet etching method, because hot phosphoric acid has a high etching selectivity for silicon nitride, and a hot phosphoric acid is used as an etchant. Next, the ion implantation step is performed, and the base 9 around the deep trench 125 is in accordance with the Chinese National Standard (CNS) A4 specification (210 X 297 mm) Ί--1ΙΙΓΙ ··· 2-1 Order-- ------- (Please read the notice on the back before filling this page) 463295 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Description of the invention () The doped region 170 is formed in the bottom 100. In FIG. 1D, for example, the pad oxide layer 105 can be removed by a wet etching method, and the preferred etchant is an HF solution. Then, the protective layer 165 is removed. If the material of the protective layer 165 is a photoresist, for example, it can be ashed by an oxygen plasma, and then washed with a cleaning solution. Then, a thermal oxidation step is performed to form a gate oxide layer 175 on the exposed surface of the substrate 100. During the thermal oxidation step, because it is at a high temperature, the doping ions of the doped region Π0 can be activated together. At the same time, the doping ions of the polycrystalline silicon layer 155 can be diffused into the surrounding substrate 100. To form a doped region 180. In this way, the doped regions 180 and 170 can be used as the source and the drain of the vertical transistor, respectively. In FIG. 1E, a doped polycrystalline silicon layer 181 is formed on the deep trench 125 and the substrate 100, and a nitride layer 182 is formed on the doped polycrystalline silicon layer 181. An opening 184 is then formed in the nitride cutting layer 182, exposing the surface of the doped polycrystalline silicon layer 181. The opening 184 partially overlaps the deep trench 125. Generally, the opening 184 surrounds the active area, and usually at least one transistor is formed on the active area. In FIG. 1F, a silicon nitride layer 182 is used as an etching mask, and the exposed doped polycrystalline silicon layer 181 and the layers below it are etched to form a channel in the substrate 100. Then inject the insulating material into the trench to form a shallow trench. The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) υ I] f— nn I-i-OJI p ^ inn I (please first Read the notes on the back and fill out this page) 463295 A7 B7 V. Description of the invention () Isolation 186. The remaining doped polycrystalline silicon layer 181 is represented by 181a. In FIG. 1G, the silicon nitride layer 182 is removed, and a metal silicide layer 188 and a cap layer 190 are sequentially formed on the substrate 100. Then, the cap layer 190, the metal silicide layer 188, and the doped polycrystalline silicon layer 181a are patterned to form a gate structure composed of the doped polycrystalline silicon layer 18 lb, the metal silicide layer 188, and the cap layer 190. The polycrystalline silicon layer 181b and the metal silicide layer 188 are gates of a vertical transistor. Next, a spacer 192 is formed on the side wall of the gate structure. ′ The material of the metal silicide layer 188 may be, for example, tungsten silicide, titanium silicide, or other suitable metal silicide. The material of the cap layer 190 may be, for example, silicon oxide or silicon nitride. The material of the partition wall 192 may be, for example, silicon nitride or sand oxide. In FIG. 1A of the first embodiment, the insulating layer 160 is deposited using a high-density plasma chemical vapor deposition method. During the deposition process, the ion sputtering in the high-density plasma creates a special shape of the insulating layer 160, which makes the insulating layer 160 on the sidewall of the deep trench 125 thinner. Therefore, the time required to remove it is also short, so the length of the etching time can be controlled, so that after the insulating layer 160 on the sidewall of the deep trench is etched away, the insulating layer 160a remains on the doped polycrystalline silicon layer 155 in the deep trench 125 ( (See Figure 1B.) 'Form an insulation structure between the deep trench capacitor and the vertical transistor. (Please read the notes on the back before filling out this page.) Words Γ Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper is printed in accordance with the Chinese National Standard (CNS) A4 (210 X 297 mm) Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Consumer Cooperative 463295 A7 _______B7_ Jade, description of the invention () For the second embodiment, please refer to Figures 2A-2c, which shows an insulation structure that isolates a vertical transistor from a deep trench capacitor according to another preferred embodiment of the present invention. Sectional view of the manufacturing process. In Figs. 2A-2C, which is larger than that in Figs. 1A-1G, the reference numeral 100 'represents the same material and manufacturing method. In FIG. 2A, the manufacturing process from the formation of the pad oxide layer 205 on the substrate 200 to the formation of the doped polycrystalline sand layer 255 in the deep trench 225 is similar to that of FIG. 1A, and therefore will not be described again. Next, an insulating layer 260 is formed in the silicon nitride layer 220 and the deep trench 225. The method for forming the insulating layer 260 may be, for example, a high-density plasma chemical vapor deposition method, and the material may be silicon oxide, for example. In FIG. 2B, the insulating layer 260 on the surface of the silicon nitride layer 220 and the upper end portion of the deep trench 2M is removed, and the deep trench capacitor 225 is doped with the polycrystalline silicon layer 255 to form an insulation between the deep trench capacitor and the vertical transistor. Structure, that is, the insulating layer 260a. The thickness of the insulating layer 260a is preferably about 300 to 900 Angstroms. The method for removing a part of the insulating layer 260 may be, for example, using a chemical mechanical honing method to remove the insulating layer 260 on the silicon nitride layer 220 first, and then using etchback to remove the insulating layer 260 located in the deep trench 225, leaving a specific thickness. 12 I ----------------- i I ----- Order ----------- (Please read the notes before & (Fill in this page) This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 6 32 9 5 A7 B7 V. Insulation layer of the invention () 260a. Therefore, when the insulating layer 260 is formed, its height is preferably about 8000 to 10,000 Angstroms higher than that of the silicon nitride layer 220, so as to facilitate the CMP process. In the etchback step, it is preferable to use a dry etching method. For example, a reactive ion etching method (Reactive Ion Etching; RIE) may be used to perform the etchback step. In FIG. 2C, a protective layer 265 is formed on the insulating layer 260a. The material of the protective layer 265 may be, for example, a photoresist. Then, the silicon nitride layer 220 is removed, and an ion implantation step is performed to form a doped region 270 in the substrate 200. The subsequent steps are similar to those described in Figure ID-1G, and will not be repeated here. In the second embodiment, the thickness of the insulating layer 260 on the silicon nitride layer 220 in FIG. 2A is thicker than the thickness of the insulating layer 160 on the silicon nitride layer 120 in FIG. 1A to facilitate the subsequent use of chemical machinery. A grinding method is used to remove the insulating layer 260 on the silicon nitride layer 220. In this way, the thickness of the insulating layer 260a can be accurately controlled by the etch-back step of the insulating layer 260 / accurately controlling the thickness of the insulating layer 260a. Embodiment 3 Please refer to FIGS. 3A to 3C, which illustrate an insulation structure for isolating a vertical transistor from a deep trench capacitor according to yet another preferred embodiment of the present invention ----- 1 --------- -r -------- Order --------- Line (Please read the precautions on the back before filling this page) This paper size is applicable to China National Standard (CNS) A4 (210 X 297) (Mm) A7 463295 _____B7_____ 5. Sectional drawing of the manufacturing process of the invention description (). In Figures 3A-3C, the number that is 200 times larger than the number Γα-1G icon number has the same meaning. In FIG. 3A, the manufacturing process from the formation of the pad oxide layer on the substrate 300 to the formation of the doped polycrystalline silicon layer 355 in the deep trench 3M is similar to that of FIG. 1A, and therefore will not be described again. Next, an insulating layer 360 is formed in the silicon nitride layer 320 and the deep trench 325, and the height of the surface of the insulating layer 360 in the deep trench 325 and the surface of the silicon nitride layer 320 are similar. The method for forming the insulating layer 360 may be, for example, a high-density plasma chemical vapor deposition method, and the material may be, for example, silicon oxide. Next, a sacrificial layer 362 is formed on the insulating layer 360, and the material may be, for example, silicon oxide formed by a low-pressure chemical vapor deposition method or a sub-normal pressure chemical vapor deposition method or a spin-on glass. Sacrificial layer_362 is used to add a self-silicon nitride layer? The total thickness of the insulating layer 360 and the sacrificial layer 362 on 20, and the total thickness is preferably about 8000 to 10,000 angstroms, so as to facilitate the subsequent chemical mechanical honing method. In FIG. 3B, a chemical mechanical honing method is used to remove the insulating layer 360 and the sacrificial layer 362 which are higher than the silicon nitride layer 320. Next, an etch-back step is performed to remove most of the insulating layer 360 ′ located at the upper end of the deep trench 3M, leaving an insulating layer 360a on the doped polycrystalline silicon layer 355 as an insulating structure between the deep trench capacitor and the vertical transistor. 14 -I ------- U -------- ^ ------------ i — Line (Please read the precautions on the back before filling this page) Ministry of Economy Printed by the Intellectual Property Bureau Employee Cooperative Cooperative Paper Standard Applicable to National Standards for Difficulties < CNS) A4 (210 X 297 mm) Printed by the Intellectual Property Bureau Employee Consumer Cooperative Cooperative of the Ministry of Economic Affairs 6 32 9 b A7 ________B7____ V. Description of Invention ( In FIG. 3C, a protective layer 365 is formed on the insulating layer 360a, and the material may be, for example, a photoresist material. Then, the silicon nitride layer 320 is removed. Then, ion implantation is performed to form a doped region 370 in the substrate 300 as a source / drain of a vertical transistor to be formed later. The subsequent steps are similar to the processes illustrated in FIG. 1G, and therefore will not be repeated. In the third embodiment, the upper part of the insulating layer 260 in FIG. 2A is replaced by the sacrificial layer 362. Because the high-density plasma chemical vapor deposition method is more expensive, a lower-cost low-pressure chemical vapor deposition method or a sub-normal pressure chemical vapor deposition method is used to form a sacrificial layer, or a spin-on glass is used to form the sacrificial layer. Sacrifice layer. In this way, a certain total thickness of the insulating layer 360 and the sacrificial layer 362 on the silicon nitride layer 320 can be maintained to facilitate the CMP process, but the cost can be reduced. It can be known from the above-mentioned preferred embodiments of the present invention that the application of the present invention can relatively easily form a horizontal insulation layer in a deep trench, which is of great help to improve the degree of accumulation of semiconductor elements. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. This paper size applies to China National Standard (CNS) A4 specification (210x297 mm) I. „-------------- Order --------- Line (Please read the back first (Notes for filling in this page)