TW463172B - NAND type nonvolatile memory - Google Patents
NAND type nonvolatile memory Download PDFInfo
- Publication number
- TW463172B TW463172B TW089105280A TW89105280A TW463172B TW 463172 B TW463172 B TW 463172B TW 089105280 A TW089105280 A TW 089105280A TW 89105280 A TW89105280 A TW 89105280A TW 463172 B TW463172 B TW 463172B
- Authority
- TW
- Taiwan
- Prior art keywords
- memory
- potential
- reference potential
- transistor
- memory cell
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
- G11C16/3445—Circuits or methods to verify correct erasure of nonvolatile memory cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
Landscapes
- Read Only Memory (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
Description
4 6 317 2 A7 B7 經濟部智慧財產局3工消費合作社印製 五、發明說明（1 ) 1. 發明之技術範圍 本發明有關於反及閘型非依電性記憶體，以及尤特別 地有關於一種反及閘型非依電性記憶體，在其確保一較大 抹除邊限之同時能實施抹除驗證者。 2. 相關技藝之說明 在快閃記憶體和其他類型之非依電性記憶體之有反及 閘型記憶體單元結構者中，FN墜道效應係經運用以注射 電子進入一浮閘内以便能編程’並用以排出電子以便能抹 除。能量消耗因此係較反或型快閃記憶體為低。數個記憶 體單元電晶體係事聯地連接於記憶體單元串中心連接至一 數元線，以及於讀取操作時一讀取電壓係應用於一選擇之 單元電晶體之閘極，以高電壓係應用於其餘之單元電晶體 以使它們均成為導電。依此，當電流流動通過單元串者係 比較低時，讀取操作中之電力消耗係亦低。由於該處受限 於可以裝設於一單元串内之單元電晶體之數目，故該部門 大小係較反或型非依電性記憶體所具有者為小，以及抹除 單元之尺寸係更小。反及型非依電性記憶體之有上文所說 明之特性者近年來享有廣泛之採用。 第12圖係在一典型反及閘型快閃記憶體中一記憶體單 元電晶體之剖視圖。在第12圖中，（a)顯示此抹除狀態以 及（b)顯不編程之狀悲。卓元電晶體結構包含一源極區s和 一汲極區D經形成於一半導體基體表面上，一透納氧化薄 膜0X經形成於兩極區之間，一浮閘FG以及一控制閘CG。 在抹除狀態（a)内之顯示於第12圖中者，電子業已自浮閘fg 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公窆） ------------裝-------訂-------線· (請先閱讀背面之汶意事項再填寫本頁) A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（ 排出；單元電晶體臨限電壓vt係負電壓，因此其功能係一 二乏模電晶體。另一方面，在第12圖内所示之編程狀態（b) 中’電子業已注射入浮閘FG内，以及單元電晶體臨限電 壓Vt係正電壓’因此其功能係增強模電晶體之一。 第13圖係一圖顯示一單元串和一反及閘型快閃記憶體 之轉頁緩衝器電路。單元串CS係經由一選擇電晶體NSG1 連接至一數元線BL，並已串聯地連接記憶體單元MC〇_ MCn。至單元串CS之相對邊者係經提供一選擇電晶體供 對一陣列Vss電位ARVss之連接用。 數元線BL係經由電晶體N10，N11，而連接至感測緩 衝器100。感測緩衝器1 〇〇於讀取，編程驗證，和抹除驗證 操作中感測記憶體單元臨限電壓之狀態，並有一閂扣之作 用。在此圖中’ N係N頻道電晶體，以及p係一 p頻道電晶 體，感測緩衝器1 00有一閂扣電路1 〇。 電晶體N1係一轉頁緩衝器選擇電晶體經連接至輸出 接頭PB0UT。電晶體P2，P3，N4，N5，和N6係輸出CMOS 電路。電晶體P7係一正常電流供應源。 對一讀取操作言，選擇之記憶體單元之字線WL係經 驅動至大約0V ’同時另一字線WL係經驅動至大約4V，因 而此選擇之記憶體單元接上或關斷耽視臨限電壓之狀態而 定’同時所有之未選擇之單元接上。耽視此選擇之記憶體 單元疋否係接上抑或關斷而定’節點SNS行進至高位準抑 或至低位準；當一讀取脈衝係應用於信號SET用以電導電 晶體N9，並係由閂扣電路1〇所閂扣時，此一經由 本紙張尺度賴 (CNS)Ali：^ (210 X 297 -------------裝--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 6 463172 A7 '______ 五、發明說明（3 ) —感測電晶體N8之導電或非導電而讀取。 ί * i I f ί I I --- (請先閱讀背面之注意事項再填寫本頁)4 6 317 2 A7 B7 Printed by the Intellectual Property Office of the Ministry of Economic Affairs and printed by the Industrial and Commercial Cooperatives V. Description of the invention (1) 1. The technical scope of the invention Regarding an anti-gate type non-dependent memory, it can perform erasure verification while ensuring a large erasure margin. 2. Description of related techniques. In flash memory and other types of non-electrical memory with anti-gate memory cell structure, the FN fall channel effect is used to inject electrons into a floating gate so that Can be programmed 'and used to eject electrons so that they can be erased. Energy consumption is therefore lower than that of anti-or flash memory. Several memory cell transistor systems are connected in series to the center of the memory cell string and connected to a digit line, and a read voltage is applied to the gate of a selected unit transistor during a read operation, with a high The voltage system is applied to the remaining unit transistors to make them all conductive. Accordingly, when the current flowing through the cell string is relatively low, the power consumption in the reading operation is also low. Because the area is limited by the number of unit transistors that can be installed in a unit string, the size of this department is smaller than that of anti-or non-electric memory, and the size of the erase unit is more small. Anti-inverted non-electrostatic memory with the characteristics described above has enjoyed widespread adoption in recent years. Figure 12 is a cross-sectional view of a memory cell transistor in a typical anti-gate flash memory. In Figure 12, (a) shows this erased state and (b) shows no programming. The Zhuoyuan transistor structure includes a source region s and a drain region D formed on a semiconductor substrate surface, a penetrating oxide film 0X is formed between the two electrode regions, a floating gate FG and a control gate CG. In the erasing state (a), as shown in Figure 12, the electronics industry has self-floating the fg. The paper size applies the Chinese National Standard (CNS) A4 specification (210 x 297 cm). -------- ---- install ------- order ------- line · (Please read the Wenyi matters on the back before filling in this page) A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Description of the invention (Exhaust; the threshold voltage of the unit transistor vt is a negative voltage, so its function is one or two modeless transistors. On the other hand, in the programming state (b) shown in Fig. 12, the electronics have been injected Within the floating gate FG, and the threshold voltage Vt of the unit transistor is a positive voltage, so its function is one of the enhancement mode transistors. Figure 13 is a diagram showing the transition of a unit string and an inverse gate-type flash memory. Page buffer circuit. The cell string CS is connected to a digit line BL via a selection transistor NSG1 and is connected in series to the memory cells MC0_MCn. The opposite side to the cell string CS is provided with a selection circuit The crystal is for connection to an array Vss potential ARVss. The element line BL is connected to the sensing buffer 1 via the transistors N10, N11. 00. Sense buffer 1 〇 〇 Read, program verification, and erase verification operation to sense the state of the memory cell threshold voltage, and has a role of a latch. In this figure 'N series N channel power The crystal, and p is a p-channel transistor, the sensing buffer 100 has a latch circuit 1 0. The transistor N1 is a page buffer selection transistor connected to the output connector PB0UT. The transistors P2, P3, N4 , N5, and N6 are output CMOS circuits. Transistor P7 is a normal current supply source. For a read operation, the word line WL of the selected memory cell is driven to about 0V while the other word line WL is It is driven to about 4V, so this selected memory unit is connected or turned off depending on the state of the threshold voltage. At the same time, all unselected units are connected. Whether the selected memory unit is connected or not Depending on whether it is turned on or off, the node SNS goes to a high level or a low level; when a read pulse is applied to the signal SET to electrically conduct the crystal N9 and is latched by the latch circuit 10, this one Via this paper size (CNS) Ali: ^ (210 X 297 ------- ------ install -------- order --------- line (please read the notes on the back before filling this page) 6 463172 A7 '______ V. Description of the invention (3 ) —Sensor N8 is conductive or non-conductive to read. Ί * i I ί II --- (Please read the precautions on the back before filling this page)
編程驗證及抹除驗證操作係類比式地對讀取操作而實 %。不過’對編程驗證彳呆作言，取代驅動所選擇記憶體單 元之字線至0V者，一相當於編程驗證位準之一正電壓， 例如0.8V者，係經應用。對一抹除驗證操作言，選擇之記 憶體單元之字線係被驅動至相當於抹除驗證位準之負電壓 以取代0V。不過，由於在半導體裝置内來產生負電壓係 不切實際’標準習慣係要驅動選擇之記憶體之字線至〇V 而此陣列Vss電位ARVss至正電壓，例如〇.6V，俾使選擇 之記憶體單元之字線電位變成同等地負電位D 經濟部智慧財產局員工消費合作社印製 第14 A圖顯示使用於一反及閘型快閃記憶體中之多餘 資料貯存電路。以此一電路，用以貯存多餘地址之一多餘 記憶體單元RMC係置於選擇電晶體RSG1，RSG2之間之中 間’並連接至一感測放大器10丨。多餘記憶體單元RMC之 臨限電壓狀態係由感測放大器1〇 1内之電晶體p21，N2〇和 一反及閘丨2讀取至節點SNS，以及節點SNS之狀態係由含 有電晶體P22，N23之一CMOS反相器來感測。一如以一般 兄憶體單元’此多餘記憶體單元RMC於抹除操作中有負 臨限電壓以及於編程操作中有正臨限電壓。 用於一讀取操作時，多餘記憶體單元RMC之字線WL 係被驅動至0V，因而它接上抑或關斷耽視臨限電壓之狀 態而定’以及其中之資訊係讀取至節點SNS。於編程驗證 操作時’多餘記憶體單元RMC之字線係被驅動至相當於 編程驗證位準之正電壓，以及臨限電壓是否超過此编程驗 本纸張尺度適用中國國家襟準（CNS)A4規格（2】〇 X 297公釐） 經濟部智慧財產局員工消費合泎钍印製 A7 B7 五、發明說明（4 ) 證位準之資訊係讀取至節點SNS並由CMOS及相器所感測 。抹除驗證時，多餘記憶體單元RMC之字線係被驅動至0V ’陣列Vss電壓ARVss係被驅動至正電壓，以及字線WL係 被驅動至等值之負電壓》用於各操作之電壓之範例係提供 於第14B圖内。 一如上文所說明者’反及閘型快閃記憶體有一較及或 型快閃記憶體不同之結構’其中記憶體單元臨限電壓於編 程操作時係正以及於抹除操作時係負。因此，以反及閘型 記憶體言，習慣係要控制陣列Vss電壓ARVss至正電壓以 便能驗證該記憶體單元或多餘單元臨限電壓Vt於抹除驗證 操作中係負電壓。 不過’第13圖中之轉頁緩衝器電路10〇和第14圖之感 測放大器101之電路設計有屬於抹除驗證操作之問題。 以第13圖之轉頁緩衝器丨00之構造言，在抹除驗證操 作時’以0V應用於用於選擇之記憶體單MC〇之字線WL0 ’以及以4V應用於其他字線並至選擇線sgi，SG2，電晶 體N10，Nil係被提供導電。如果選擇之記憶體單元MC〇 之臨限電壓係充分地負電壓時，則選擇之記憶體單元MC〇 變成導電而節點SNS上之電壓係、被拉曳，此一電壓係由電 晶體N 8所感測並由閂扣電路1 〇問扣。 不過，用於電晶體N82臨限電壓典型地係在〇.8乂之 範圍上，耽視生產程序而定。藉由選擇記憶體單元MC〇之 導電，知點SNS必須是被驅動至較電晶體N8之臨限電壓為 低。在如此情勢下，該處自一可靠之基點言，吾人必須來 本紙張尺度適用中國國家標準(CNS)A4 (2Ϊ〇 8 Γ --------裝·-------訂---------線 (請先閱讀背面之注意事項再填寫本頁) A7The program verify and erase verify operations are analogous to the read operation. However, when talking about programming verification, instead of driving the word line of the selected memory cell to 0V, a positive voltage equivalent to one of the programming verification levels, such as 0.8V, is applied. For an erase verification operation, the word line of the selected memory cell is driven to a negative voltage equivalent to the erase verification level instead of 0V. However, since it is impractical to generate a negative voltage in a semiconductor device, the standard habit is to drive the word line of the selected memory to 0V and the array Vss potential ARVss to a positive voltage, such as 0.6V, so that it is selected The zigzag potential of the memory unit becomes equal to the negative potential. D Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Figure 14A shows the redundant data storage circuit used in a flip-flop flash memory. With this circuit, an extra memory cell RMC for storing extra addresses is placed between the selection transistors RSG1 and RSG2 'and connected to a sense amplifier 10 丨. The threshold voltage status of the redundant memory unit RMC is read by the transistors p21, N20 and a negative sum gate 2 in the sense amplifier 101 to the node SNS, and the status of the node SNS is by the transistor P22. , N23 is a CMOS inverter to sense. As usual, the extra memory unit RMC has a negative threshold voltage in the erase operation and a positive threshold voltage in the programming operation. For a read operation, the word line WL of the extra memory cell RMC is driven to 0V, so it is connected or turned off depending on the state of the threshold voltage 'and the information therein is read to the node SNS . During programming verification operation, the word line of the extra memory cell RMC is driven to a positive voltage equivalent to the programming verification level, and whether the threshold voltage exceeds this programming check. The paper size is applicable to China National Standard (CNS) A4 Specifications (2) 0X 297 mm) A7 B7 printed by employees of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (4) The information of the certificate level is read to the node SNS and sensed by the CMOS and phase detector. . During erasure verification, the word line of the extra memory cell RMC is driven to 0V 'array Vss voltage ARVss is driven to positive voltage, and word line WL is driven to equivalent negative voltage "voltage for each operation Examples are provided in Figure 14B. As explained above, the anti-gate flash memory has a structure different from that of or flash memory. The threshold voltage of the memory unit is positive during the programming operation and negative during the erasing operation. Therefore, in the case of anti-gate memory, it is customary to control the array Vss voltage ARVss to a positive voltage in order to verify that the memory cell or excess cell threshold voltage Vt is a negative voltage in the erase verification operation. However, the circuit design of the page buffer circuit 10 in FIG. 13 and the sense amplifier 101 in FIG. 14 has a problem of erasing verification operation. According to the structure of the page buffer buffer 00 in FIG. 13, when erasing the verification operation, 'apply 0V to the word line WL0 of the selected memory cell MC0' and apply it to other word lines at 4V and reach The selection lines sgi, SG2, and transistors N10, Nil are provided to conduct electricity. If the threshold voltage of the selected memory cell MC0 is a sufficiently negative voltage, the selected memory cell MC0 becomes conductive and the voltage on the node SNS is pulled. This voltage is controlled by the transistor N 8 Detected by the latch circuit 100. However, the threshold voltage for transistor N82 is typically in the range of 0.8 乂, depending on the production process. By selecting the conductivity of the memory cell MC0, the knowledge point SNS must be driven to be lower than the threshold voltage of transistor N8. In such a situation, the Department has a reliable basis for saying that we must apply the Chinese National Standard (CNS) A4 (2Ϊ〇8 Γ) to the paper size. Order --------- Line (Please read the precautions on the back before filling this page) A7
463彳 7 2 五、發明說明（5 ) 確保以讀取操作為準之較大抹除邊限，陣列Vss電壓ARVss ，例如，係增大至大約1V，以及用於選擇之記憶體單元 MCO之閘電壓同值地變成_iV。藉如此作為’在選擇之記 憶體單元MCO由於充分之電子於抹除操作中自浮閘排出而 變成負臨限電壓Vt之情況中，俾使即令在導電狀態’節點 SNS上之電位最多下落至陣列Vss電壓ARVss卜丨v);在此 一節點SNS電位處，電晶體!^8，其源極係連接至接地線電 位Vss者不能使其成為非導電，而最終地此抹除驗證操作 不能實施。亦即，由於一成功之抹除驗證操作需要感測電 晶體N8之導電以倒反閂扣電路丨〇之狀態，感測電晶體N8 即令在一抹除之狀態中係不能使其成為導電。 有關於抹除驗證之相同問題亦一樣地存在於第〖4A圖 之多餘資料貯存電路之情況中。就像第13圖之轉頁緩衝器 電路100,第丨4圖之感測放大器1〇1有一多餘記憶體單元 RMC經由選擇電晶體rsg 1和電晶體N20與一 p型頻道電晶 體P21相連接’作用如一正常電流供應源，而節點SNS取 高位準或低位準則耽視此多餘記憶體單元RMC是否係導 電或非導電而定’以在節點SNS上之電位係由有一感測電 經濟部智慧財產局員工消費合作社印製 晶體N23之CMOS反相器所感測，以其源極連接至地線Vss 〇 在此一情況中一樣地’由於吾人需要來確保以讀取操 作為準之一較大抹除邊限，此陣列Vss電壓ARVss係被增 大，例如，至大約iv，以及用於多餘記憶體單元RMC之 閘電壓同值地變成-IV於此抹除驗證操作時。藉如此作為 本纸張尺度適用中國固家標準（CNS>A4規格（210x 297公釐） 9 A7 -~^------ 五、發明說明（6 ) (請先閱讀背面之注意事項再填寫本頁) ，多餘記憶體單元RMC由於充分之電子自此浮閘排出而 變成負臨限電壓vt ’俾使即令是在導電狀態中，在節點SNS 上之電位最多下落至陣列Vss電壓ARVss(=lV) 〇此一節點 SNS電位係較CM0S反相器P22，N23之跳脫位準為高，以 及電晶體N23，其源極係經連接至地線電位Vss，不能使 成為非導電，因此最終地此抹除驗證操作不能予以實施。 自前文將至為顯明者’即在電路中，其中一記憶體單 元和一正常電流之間之節點位準係使出現在有一接地線之 源極之感測電晶體之閘極，而驗證操作係經由此—感測電 晶體之導電而實施’故其抹除驗證操作將被傷害。 本發明之概述 本發明之目的係在提供一反及閘型非依電性記憶體， 具有能力正常地實施抹除驗證操作。 本發明之另一目的係在提供，在一非依電性記憶體内 ’其中編程操作產生單元電晶體之正臨限電壓，而抹除操 作產生負臨限電壓，一非依電性記憶體具有能力正常地實 施抹除驗證操作者。 經濟部智慧財產局員工消費合作钍印5-^ 要達成所說明之目的，本發明在其一觀點中提供一反 及閘型非依電性記憶體，包含：一感測電路有一正常電流 供應源經連接至一數元線而記憶體單元係連接至此線者， 以及一感測電晶體用以感測其連接點處之電位；一第一基 準電位ARVss，感測電晶體之源極係連接至該電位，其中 ，於抹除驗證操作中，此第一基準電位ARVss和第二基準 電位PBVss係經控制至預定之正電位。藉控制此第一基 本紙張尺度適用_國國各標準（CNS)A4規格（210 X 297公^| ) 10 463172 A7 B7 五、發明說明（7 ) 電位ARVss至正電位，此控制記憶體單元之閘位準可以等 值地被帶引至抹除驗證位準（它係負位準），以及藉另控制 此感測電晶體之第二基準電位PBVss至正電位’—樣地此 感測電晶體之等值臨限電壓可以增大，或者此感測反相器 之等效跳脫位準增大，由是而解決與抹除驗證操作相關聯 之傳統性問題> 要達成所說明之目的，本發明在其第一觀點中提供一 反及閘型非依電性記憶體，有數個記憶體單元串聯地相連 接之單元串在一記憶體陣列中’包含：一感測電路有一正 常電流電路經連接至已連接至此記憶體單元之一數元線， 以及一感測電晶體用以感測在其連接點處之電位；—第一 基準電位在自此記錄體單元之正常電流電路之相對邊上； 以及一第二基準電位經連接至感測電晶體之源極’其中於 抹除驗證操作時，此第一基準電位和第二基準電位係經控 制至一預定之正電位。 經濟部智慧財產局員工消費合作社印製 ---------- I I ---I . - i (請先閱讀背面之注意事項再填寫本頁) -線. 要達成所說明之目的，本發明在其第二觀點中提供一 反及閘型非依電性記憶體，有數個記憶體單元串聯地相連 接之單元串在一記憶體陣列中，包含：一輔助記憶體單元 用以貯存多餘資訊或預定資訊；一多餘感測電路有一正常 電流電路經連接至此輔助記憶體單元，以及一感測電晶體 用以感測在其連接點處之電位；一第一基準電位在輔助記 憶體單元之正常電流電路之相對邊上；以及_第二基準電 位同於感測電晶體’其中於抹除驗證操作中，此第一基準 電位和第二基準電位係經控制至預定之正電位。 本紙張尺度適用t國國家標準（CNS)A4規格（210 X 297公笼）463 彳 7 2 V. Description of the invention (5) To ensure a large erase margin based on the reading operation, the array Vss voltage ARVss, for example, is increased to about 1V, and the memory cell MCO used for selection The gate voltage becomes _iV at the same value. As such, in the case where the selected memory cell MCO becomes negative threshold voltage Vt due to sufficient electrons being discharged from the floating gate in the erasing operation, even if the potential in the conductive state node SNS drops to at most Array Vss voltage ARVss (v); at this node SNS potential, transistor! ^ 8, whose source is connected to the ground line potential Vss can not make it non-conductive, and finally the erasure verification operation cannot Implementation. That is, since a successful erase verification operation needs to sense the conductivity of transistor N8 to reverse the state of the latch circuit, the sense transistor N8 cannot make it conductive in an erased state. The same problem regarding erasure verification also exists in the case of the redundant data storage circuit of FIG. 4A. Just like the page buffer circuit 100 in Fig. 13, the sense amplifier 10 in Fig. 4 has an extra memory cell RMC connected to a p-type channel transistor P21 via a selection transistor rsg 1 and a transistor N20. 'It acts as a normal current supply source, and the node SNS adopts the high or low level criterion depending on whether this extra memory cell RMC is conductive or non-conductive'. The potential on the node SNS is determined by the wisdom of a sensing electrical ministry Sensing by the CMOS inverter of the printed crystal N23 of the Consumer Cooperative of the Property Bureau, its source is connected to the ground Vss 〇 In this case, it is the same 'as I need to ensure that one of the reading operations shall prevail The erase margin, the array Vss voltage ARVss is increased, for example, to about iv, and the gate voltage for the extra memory cell RMC becomes -IV at the same value during the erase verification operation. By doing this, the Chinese solid standard (CNS > A4 size (210x 297 mm)) is applied as the paper size. 9 A7-~ ^ ------ 5. Description of the invention (6) (Please read the precautions on the back before reading) (Fill in this page), the excess memory cell RMC becomes a negative threshold voltage vt 'because sufficient electrons are discharged from this floating gate, so that even if it is in a conductive state, the potential on the node SNS drops up to the array Vss voltage ARVss ( = lV) 〇 This node has a higher SNS potential than the CM0S inverter P22, N23, and the transistor N23, whose source is connected to the ground potential Vss, can not be made non-conductive, so in the end The erasing verification operation cannot be implemented here. As it will become apparent from the previous paragraph, that is, in the circuit, the node level between a memory cell and a normal current is such that it appears at the source of a ground line. The gate of the transistor is tested, and the verification operation is carried out through this-sensing the conductivity of the transistor, so its erasure verification operation will be harmed. SUMMARY OF THE INVENTION The purpose of the present invention is to provide an anti-gate type Electrical memory The erase verification operation is normally performed. Another object of the present invention is to provide a programming operation to generate a positive threshold voltage of a unit transistor in a non-electrically-dependent memory, and the erase operation to generate a negative threshold voltage. A non-electrical memory has the ability to perform erasure verification operations normally. Employees ’Cooperative Seal of the Intellectual Property Bureau of the Ministry of Economic Affairs 5- ^ To achieve the stated purpose, the present invention provides a counterpoint in one of its perspectives. Gate-type non-electric memory includes: a sensing circuit having a normal current supply source connected to a digital line and the memory unit is connected to this line, and a sensing transistor for sensing its connection point A first reference potential ARVss, the source of the sensing transistor is connected to the potential, wherein during the erase verification operation, the first reference potential ARVss and the second reference potential PBVss are controlled to a predetermined Positive potential. By controlling this first basic paper size, it is applicable _ national standards (CNS) A4 specifications (210 X 297 public ^ |) 10 463172 A7 B7 V. Description of the invention (7) potential ARVss to positive potential, this control The gate level of the memory unit can be equally brought to the erasure verification level (it is the negative level), and by controlling the second reference potential PBVss of the sensing transistor to the positive potential'—sample plot The equivalent threshold voltage of the sensing transistor can be increased, or the equivalent trip level of the sensing inverter can be increased, so as to solve the traditional problems associated with the erase verification operation. For the stated purpose, the present invention provides in its first aspect an anti-gate-type non-dependent memory. A string of cells having a plurality of memory cells connected in series in a memory array includes: a sense The circuit has a normal current circuit connected to a digit line that has been connected to the memory unit, and a sensing transistor to sense the potential at its connection point; the first reference potential is from the record unit unit. On the opposite side of the normal current circuit; and a second reference potential is connected to the source of the sensing transistor, wherein during the erase verification operation, the first reference potential and the second reference potential are controlled to a predetermined Positive potential. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ---------- II --- I.-I (Please read the precautions on the back before filling out this page)-line. To achieve the stated purpose In the second aspect of the present invention, an anti-inverter gate type non-dependent memory is provided. A plurality of memory cells connected in series are connected in a memory array, including: an auxiliary memory unit for Store redundant information or predetermined information; a redundant sensing circuit has a normal current circuit connected to this auxiliary memory unit, and a sensing transistor to sense the potential at its connection point; a first reference potential is in the auxiliary On the opposite side of the normal current circuit of the memory unit; and _ the second reference potential is the same as the sensing transistor, where in the erase verification operation, the first reference potential and the second reference potential are controlled to a predetermined positive Potential. This paper size applies to the national standard (CNS) A4 specification (210 X 297 male cage)
II A7 A7 B7II A7 A7 B7
五、發明說明（8) 圖式之簡要說明 第1圖顯示本具體例中8 X4反及閘型快閃記憶體陣列 和緩衝器結構； 第2圖顯示本具體例中一轉頁緩衝器電路； 第3A至3C圖係一定時圖供第2圖之電路於讀取，編程 (寫出）驗證，以及抹除驗證操作時之操作用者； 第4A至4B圖係一圖表，顯示第2圖之電路之電壓狀況 第5A至5B圖係本具體例中記憶體單元陣列和轉頁緩 衝器之構造圖； 第6圖係本具體例中多餘記憶體單元之構造圖； 第7A至7C圖係多餘記憶體單元操作之一時序圖； 第8A至8B圖係顯示多餘記憶體單元之第一範例圖； 第9A至8B圖係顯示多餘記憶體單元之第二範例圖； 第10圖係顯示另一多餘記憶體單元之感測放大圖； 第11A至11B圖係顯示第10囷之電壓狀況之表； 第12圖係一典型之反及閘型快閃記憶體之記憶體單元 之一剖視圖； 第1 3圖係一圖顯示在一反及閘型快閃記憶體中單元串 和轉1緩衝器電路；以及 第14A圖係一圖顯示一傳統式多餘資訊貯存電路； 第14B圖係一表顯示操作之電壓。 較佳具體例之說明 本發明之具體例係以參考附圖在下文中作說明。不過 本紙張尺度適用中固國家標準（CNS)A4規格（210 X 297公釐） I t--^------裝 -------訂---------線 (請先閱讀背面之沒意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 12 46317 2 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（9 ’應予說明者，即此具體例係不以限制本發明之技術範圍 之限制之方式呈現。 第1圖係一圖顯示在本具體例中8 X 4反及閘型快閃記 憶體陣列及緩衝器結構。在第丨圖中，兩個方塊，方塊〇， 1各有一 4 X 4記憶體陣列者係經顯示。在反及閘型快閃記 憶體中’數個（第1圖内四個）記憶體單元MC00-MC30串聯 地相連接，以及選擇閘電晶體NSG1，NSG2串聯地連接至 其頂部和底部形成一基本單元名之為一單串。眾多之這些 串（第1圖内為兩個）係連接至一數元線BLO。一轉頁緩衝器 100係連接至每一此數元線BL0_BL3。 一如所說明者’典型地有兩種狀態用於一反及閘型快 閃記憶體之記憶體單元。在一種狀態中，電子係注射入— 記憶體單元之浮閘内’它貯存一邏輯“ 〇，^在此一時刻記 憶體單元臨限電壓Vt係正以及記憶體單元功能如一 “增強 模式電晶體。在另一種狀態中，電子係自此記憶體單元 之浮閘排出，它貯存一邏輯“1” ^在此一時刻記憶體單元 臨限電壓Vt係負以及記憶體單元功能如一空乏模電晶體。 第2圖係一圖顯示本具體例中之一轉頁緩衝器電路。 第2圖之轉頁緩衝器電路1〇〇有一對第13圖内所示傳統式轉 頁缓衝器電路類似之設計，但在傳統式範例中閂扣電路1 〇 之設定電晶體N9之源接頭（第二基準電位）係連接至地線電 位，但在本體例中，它係連接至一轉頁緩衝器Vss電位 pBVss。像陣列Vss電位ARVss(第一基準電位）_樣，此一 轉頁緩衝器Vss電位PBVss於抹除驗證操作中係經保持在 ^紙張尺度適用中國國豕標準（CNS)A4規格（210 * 297公釐） ί - ί ----·--------.1 --------訂--—IIIII* 線. (請先閱讀背面之注意事項再填寫本頁) 13 - A7 --—______ B7 五、發明說明（10) 預定〜正電位，以及在讀取操作或編程驗證操作中係保持 在較抹除驗證電位為低之一電位或地線電位。 第3圖係一時序圖*用於讀取，編程（寫出）驗證，以 及抹除驗證操作巾第2®之電路之操作I#圖係—表，顯 不在上述二種操#中每一節點處之範例電I。在本具體例 中之s賣取’編程（寫出）驗證，以及抹除驗證操作係以這些 圖為基準說明如下： 讀取操作 在一反及閘型快閃記憶體中之讀取操作，如第3八圖 中所示者，係如下。在一讀取操作中，此陣列Vss電位ARVss 係經保持於ον，以及此轉頁緩衝器Vss電位pBVss係亦保 持於0V。讓它係被假定即記憶體單元MC〇連接至字線wL〇 者業已被選擇。讓它另被假定，即轉頁緩衝器i00内閂扣 電路10之節點A和B業已分別地預先設定為低位準和高位 準。設定信號SET係低位準。 在此一點’ 0V係應用於字線WL〇，以及大約4v係應 用於其他子線WL1 -η。大约4 V係一樣地應用於選擇閘線 路SG1和SG2。因而選擇閘電晶體NSG1*NSG2兩者係置 於導電狀態内，以及此串，此選擇之記憶體單元MC〇係歸 屬其内者，係經選擇B以此一方法，串之一端係連接至數 元線BL ’同時另一端係連接至陣列vss電位arvss(第一基 準電位）。在一讀取操作中，此陣列Vss電位aRVsss〇v。 在此選擇之串内記憶體單元中，記憶體單元Me 1 -n(除了 選擇之記憶體單元CM0以外）均係在導電狀態中而勿干於 本纸張尺度適用中國國家標準（CNS)A4規格（2J〇 X 297公Μ ) -----l· I-------裝 i I (請先閱讀背面之注意事項再填寫本頁) -5J. -線. 經濟部智慧財產局員工消費合作社印製 14 A63 w 2 A7 ____B7_____ 五、發明說明（11 ) 貯存於其内之資料》 (請先閱讀背面之注意事項再填寫本頁) 在此一狀態中，以轉頁緩衝器10内信號BLCNTRL和 BLPROT在高位準’轉頁緩衝器100係已連接至數元線BL 。同一時間地’以信號PBIAS在低位準，p型電晶型P7接 上’以及電流係已輸送至數元線BL。此一電流係用以測 定記憶體單元MC0是否含一邏輯“1”或一邏輯“〇，’之基礎。 更確切言，信號BLCNTRL係經分別地控制至1 v以及信號 BLPORT至電力供應Vcc。 經濟部智慧財產局員工消費合作社印製 一如在第3A圖内左邊一行所示，該處記憶體單元MC0 含邏輯’其臨限電壓Vt係負，因此雖然〇V係已應用於 字線WL0，但儘管如此記憶體單元MC0接上以及電流流動 通過其間，俾使轉頁緩衝器内節點SNS係朝向低位準拉复 。當一高位準脈衝隨後係提供至設定信號SET時，設定電 晶體N9恢復導電狀態，以及感測電晶體N8之源極係被驅 動至轉頁緩衝器Vss電位PBVss(於讀取操作中之0V)，以 節點SNS係由感測電晶體N8來感測。由於記憶體單元MC0 含一邏輯“Γ以及此單元係在導電狀態中，故節點SNS係 低位準以及閂扣電路10内之節點B繼續地被保持於高位準 ;當此設定信號SET回行至低位準時，閂扣電路1 〇貯存一 邏輯“1”狀態，在其中節點A=L以及節點B=H。 一如第3A圖中右行内所示，該處記憶體單元MC0含 一邏輯“0’’ ’其臨限電壓Vt係正，因此雖然〇v係已應用於 字線WL0，但記憶體單元MC0係關斷，以及電流不能流動 通過其間，俾使轉頁缓衝器内之節點SNS係由自正常電流 15 衣纸張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐）V. Description of the invention (8) Brief description of the drawing. Figure 1 shows the structure of the 8 X4 anti-gate flash memory array and buffer in this specific example. Figure 2 shows a page buffer circuit in this specific example. ; Figures 3A to 3C are fixed time diagrams for the circuit in Figure 2 for reading, programming (writing) verification, and erasing verification operations; Figures 4A to 4B are diagrams showing the second The voltage status of the circuit in the figure. Figures 5A to 5B are the structural diagrams of the memory cell array and the page buffer in this specific example; Figure 6 is the structural diagram of the extra memory cells in this specific example; Figures 7A to 7C Fig. 8A to 8B is a first example diagram of the extra memory unit; Figs. 9A to 8B are the second example diagram of the extra memory unit; Fig. 10 is a diagram An enlarged view of the sensing of another redundant memory unit; Figures 11A to 11B are tables showing the voltage status of the 10th frame; Figure 12 is one of the memory cells of a typical anti-gate flash memory Sectional view; Figure 13 is a diagram showing an inverse and gate type flash memory Symbol string and a transfer buffer circuit; FIG. 14A and the second figure shows a system of a conventional type redundant information storage circuit; FIG. 14B based on a table shows the operating voltage. Description of preferred specific examples Specific examples of the present invention are described below with reference to the drawings. However, this paper size applies to the National Solid Standard (CNS) A4 specification (210 X 297 mm) I t-^ ------ installation --------- order --------- Online (Please read the unintentional matter on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 12 46317 2 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs That is, this specific example is not presented in a way that limits the technical scope of the present invention. Figure 1 is a diagram showing the structure of the 8 X 4 anti-gate flash memory array and buffer in this specific example. In the figure, two squares, squares 0 and 1, each with a 4 X 4 memory array are shown. Among the flash memory of the anti gate type, there are 'several (four in Figure 1) memory. The cells MC00-MC30 are connected in series, and the gate transistors NSG1 and NSG2 are connected in series to the top and bottom to form a single string with the basic unit name. Many of these strings (two in Figure 1) are Connected to a number line BLO. A page buffer 100 is connected to each of these number lines BL0_BL3. As explained ' There are two states for the memory cell of the flash memory of the inverted type. In one state, the electrons are injected into the floating gate of the memory unit. 'It stores a logic "〇, ^ here At a moment, the threshold voltage Vt of the memory unit is positive and the memory unit functions as an "enhanced mode transistor. In another state, the electronics are discharged from the floating gate of this memory unit, and it stores a logic" 1 "^ in At this moment, the threshold voltage Vt of the memory cell is negative and the memory cell functions as an empty mode transistor. Figure 2 is a diagram showing a page buffer circuit in this specific example. Page transfer buffer of Figure 2 Circuit 100 has a similar design to the conventional page-turn buffer circuit shown in Figure 13, but in the conventional example, the source connector (second reference potential) of the setting transistor N9 of the latch circuit 10 is the It is connected to the ground potential, but in the body example, it is connected to a page buffer Vss potential pBVss. Like the array Vss potential ARVss (first reference potential), this page buffer Vss potential PBVss Except for verification operation Hold at ^ paper standard applicable to China National Standard (CNS) A4 specifications (210 * 297 mm) ί-ί ---- · --------. 1 -------- order- -—IIIII * line. (Please read the precautions on the back before filling out this page) 13-A7 ---______ B7 V. Description of the invention (10) Predetermined to positive potential, and in reading operation or program verification operation Keep it at a lower potential or ground potential than the erase verification potential. Figure 3 is a timing diagram * for reading, programming (writing out) verification, and erasing the verification operation. I # is a table, which shows the example I at each node in the above two operations. In this specific example, the “sell” program (write) verification, and erase verification operations are described with reference to these figures as follows: The read operation is a read operation in an inverted and gate-type flash memory. As shown in Figure 38, it is as follows. In a read operation, the Vss potential ARVss of the array is maintained at ον, and the page transfer buffer Vss potential pBVss is also maintained at 0V. Let it be assumed that the memory cell MC0 is connected to the word line wL0 has been selected. Let it be assumed that nodes A and B of the latch circuit 10 in the page buffer i00 have been set to the low level and the high level, respectively, in advance. The setting signal SET is a low level. At this point, the '0V system is applied to the word line WL0, and about 4v system is applied to the other sub-lines WL1-η. Approximately 4 V systems are equally applied to select gate lines SG1 and SG2. Therefore, the gate transistor NSG1 * NSG2 is selected to be placed in a conductive state, and this string is selected. The selected memory cell MC0 belongs to it, and by selecting B in this way, one end of the string is connected to The digit line BL 'is connected to the array vss potential arvss (first reference potential) at the other end. In a read operation, the array Vss potential is aRVsssov. Among the selected in-line memory units, the memory units Me 1 -n (except for the selected memory unit CM0) are all in a conductive state and should not be allowed to dry on this paper. Chinese National Standard (CNS) A4 applies Specifications (2J〇X 297mm) ----- l · I ------- install i I (Please read the precautions on the back before filling this page) -5J. -Line. Intellectual Property of the Ministry of Economic Affairs Printed by the Bureau ’s Consumer Cooperatives 14 A63 w 2 A7 ____B7_____ V. Description of the Invention (11) Information stored in it (Please read the precautions on the back before filling this page) In this state, the page buffer The signals BLCNTRL and BLPROT within 10 are connected to the bit line BL at the high level. At the same time, 'the signal PBIAS is at a low level, the p-type transistor P7 is connected' and the current system has been transmitted to the bit line BL. This current is used to determine whether the memory cell MC0 contains a logic "1" or a logic "0, '. More specifically, the signal BLCNTRL is controlled to 1 v and the signal BLPORT to the power supply Vcc, respectively. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, as shown in the left line in Figure 3A, the memory cell MC0 contains logic 'its threshold voltage Vt is negative, so although the 0V system has been applied to the word line WL0 However, despite this, the memory cell MC0 is connected and the current flows through it, so that the node SNS in the page buffer is pulled back toward the low level. When a high level pulse is subsequently provided to the setting signal SET, the setting transistor N9 is set. The conductive state is restored, and the source of the sensing transistor N8 is driven to the page transfer buffer Vss potential PBVss (0V in the reading operation), and the node SNS is sensed by the sensing transistor N8. Because of the memory The body cell MC0 contains a logic "Γ and this cell is in a conductive state, so the node SNS is at a low level and the node B in the latch circuit 10 is continuously maintained at a high level; when this setting signal SET returns to the low level At this time, the latch circuit 10 stores a logic "1" state in which node A = L and node B = H. As shown in the right row of Figure 3A, the memory cell MC0 contains a logic "0". Its threshold voltage Vt is positive. Therefore, although the 0v system has been applied to the word line WL0, the memory cell MC0 The system is turned off, and the current cannot flow through it, so that the node SNS in the page buffer is from the normal current. 15 Paper size is applicable to China National Standard (CNS) A4 specification (210 x 297 mm).
經濟部智慧財產局員工消費合作社印製 電力供應電晶體P7之正常電流充電至高位準。當一高位 準脈衝隨後係經提供至設定信號SET時，心節點SNS係 高位準，故電晶體N8取導電狀態，以及閂扣電路1〇内之 節點B係被推送至低位準；當此設定信號SET回行至低位 準時，閂扣電路10貯存一邏輯狀態，其中節點A=H以 及節點B等於L » 在轉頁緩衝器100之輸出部分内，藉驅動此寫出資料 負載信號LD至低位準，以及讀取資料輸出信號RD至高位 準，兩者電晶體P3，P4係置於導電狀態中，以及上文提 及之閂扣電路10之狀態係藉含有電晶體p2，N52CM〇s反 相器經由選擇閘N1而在轉頁緩衝器輸出接頭pB〇UT上面 輸出。 編程（寫出）驗證操作 編程（寫出）驗證操作現在係予以說明。此編程驗證操 作係顯7F於第3B圏内。在編程操作中，控制係經實施以 便能位移一選擇之記憶體單元電晶體之臨限電壓至一預定 正編程位準Vtpr。因此，吾人必需於編程驗證操作中來驗 證，不官一預定正電壓之應用於選擇之記憶體單元之控制 閘’此記憶體單元將是非依電性。 在編程驗證操作時，此陣列Vss電位ARVss保持在0 V ，而此轉頁緩衝器vss電位PBVss一樣地係被保持在〇v ; 此一操作基本上係與讀取操作相同。一編程驗證操作之不 同於4取操作者’在其中為了要择保記憶想單元之臨限電 ® vt之編程（寫出）位準Vtpr，除了 〇v以外之正電壓係應用 本紙張尺度適用—中國國家標準“:崩雜（21〇 χ观公^- ^} · 16 - ---------------------^----- I---^ (請先閱讀背面之注意事項再填寫本頁) 463172 A7The normal current of the power supply transistor P7 printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs is charged to a high level. When a high level pulse is subsequently provided to the setting signal SET, the heart node SNS is at a high level, so the transistor N8 takes the conductive state, and the node B in the latch circuit 10 is pushed to a low level; when this setting When the signal SET returns to the low level, the latch circuit 10 stores a logic state, where node A = H and node B are equal to L »In the output part of the page turning buffer 100, drive the data load signal LD to the low level And read the data output signal RD to a high level, the transistors P3 and P4 are placed in a conductive state, and the state of the latch circuit 10 mentioned above is obtained by including the transistor p2, N52CM. The phaser is output on the page buffer output connector pBOUT via the selection gate N1. Program (write out) verify operation The program (write out) verify operation is now explained. This program verification operation shows 7F in 3B 圏. In the programming operation, the control is implemented to shift the threshold voltage of a selected memory cell transistor to a predetermined positive programming level Vtpr. Therefore, we must verify in the program verification operation, that a predetermined positive voltage is applied to the control gate of the selected memory cell. This memory cell will be non-electrical. During the program verify operation, the Vss potential ARVss of the array is maintained at 0 V, and the page transfer buffer vss potential PBVss is also maintained at 0v; this operation is basically the same as the read operation. A program verification operation is different from the four-take operator 'in which to select the memory to think about the threshold voltage of the cell ® vt's programming (write-out) level Vtpr, positive voltages other than 0v are applicable to this paper scale —Chinese National Standard ": Bunch Za (21〇χ 观 公 ^-^} · 16---------------------- ^ ----- I- -^ (Please read the notes on the back before filling this page) 463172 A7
五、發明說明（13 ) 經濟部智慧財產局員工消費合作社印製 用於選擇之字線WL。例如，0.8V之應用於字線WL提供以 最小臨限電壓為準之大約〇. 8 V之一邊限，它可以至少在讀 取操作時作為一邏輯來讀取。因此，在字線上之正電 壓係設定為相當於編程位準Vtpr之一電壓。 讓吾人假定該記憶體單元MC0已連接至字線WL0者業 已被選訂。在此一點處’ 〇·8V係應用於選擇之字線WL0以 及大約4V係應用於其他未經選擇之字線wl〇 —樣地大約 4V係應用於選擇閘線SG丨和SG2，以及此串，此選擇之記 憶體單元存在其中者係連接至數元線BL並至陣列Vss電位 ARVss。 在此一狀態中’以信號BLCNTRL和轉頁緩衝器1〇〇内 之BLPROT在高位準’轉頁緩衝器ι00和數元線肌係電相 連接。在同一時間地’以信號PBIAS在低位準，p型電晶 體P7(電流源）接上以及正常電流係輸送至數元線bl ^ 一如 在讀取操作中’此一電流係用以決定記憶體單元MC是否 係充77地被編程（寫出）之偏壓。一記憶趙單元係正被編程 (寫出）之位置，上至此一點，此轉頁緩衝器丨〇〇内閂扣電 路10之節點A和節點B業已分別地預先設定為低位準和高 位準。在沒有一編程（寫出）操作中，此節點A和節點b係 分別地預先設定為高位準和低位準。在此’ 一編程（寫出） 腳本係經考慮’因此節點A和節點B係分別地被假定為設 定至低位準和高位準。 一如第3B圖内左邊行中所示，記憶體單元MC0未曾 充分地編程（寫出）之位置，其臨限電壓Vt係較在字線WL〇 本纸張尺度適用中國國家螵準（CNS)A4規格（210x297公f ) 17 / _ f • I---I ! ------裝--------訂---------線· (請先閱讀背面之注意事項再填寫本頁> 經濟部智慧財產局員工消費合作社印 A7 B7 五、發明說明（14 ) 上之0.8V電壓為小’所以記憶體單元mc〇接上以及電流流 動’以節點SNS係被拉曳至低位準。當一高脈衝隨後係提 供至此設定信號SET時，由於節點SNS係低位準，閂扣電 路1内之節點B繼續地予以保持在高位準；當此設定信號 SET回行至低位準時，閂扣電路10貯存一狀態，其中節點 A=低位準以及節點B=高位準。此即指示該編程（寫出）驗 證已失敗’然後此編程（寫出）操作係重復。 一如第3B圖内右邊行中所示，記憶體單元mc〇業已 充分地編程（寫出）之位置，其臨限電壓Vt係較在選擇之字 線WLO上之0.8V電壓為大，因此記憶體單元％^^關斷並沒 有電流流動，以節點SNS係正被充電至高位準。當一脈衝 隨後係提供至設定信號SET時’由於節點SNS係高位準， 節點B係被拉曳至低位準；當此設定信號SET回行至低位 準時，轉頁緩衝器100内之閂扣電路10係再設定為一狀態 ，其中節點高位準以及節=低位準。此即指示該編 程（寫出）驗證已成功，然後此編程（寫出）操作結束。 抹除驗證操作 現在此抹除驗證操作係予說明。此抹除驗證操作係顯 示於第3C圖A。在才末除操作t，一方塊之所彳記憶體單 元之臨限電壓係位移至負抹除位準Vtre，因此於一抹除驗 證操作中吾人必需等值地應用負電壓至記憶體單元之控制 閘以便能驗證該所有記憶體單元之在一串内者係導電。V. Description of the invention (13) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs for the selection of the zigzag line WL. For example, 0.8V applied to the word line WL provides a margin of about 0.8 V based on the minimum threshold voltage, which can be read as a logic at least during a read operation. Therefore, the positive voltage on the word line is set to a voltage corresponding to one of the programming levels Vtpr. Let us assume that the memory cell MC0 has been connected to the word line WL0 and has been selected. At this point, 〇 · 8V is applied to the selected word line WL0 and about 4V is applied to other unselected word lines w10—likely about 4V is applied to the selected gate lines SG 丨 and SG2, and this string The existence of the selected memory cell is connected to the digit line BL and to the array Vss potential ARVss. In this state, 'the signal BLCNTRL and the BLPROT in the page buffer 100 are at a high level', the page buffer ι00 is electrically connected to the digital line muscle system. At the same time, with the signal PBIAS at a low level, the p-type transistor P7 (current source) is connected and the normal current is sent to the bit line bl ^ as in the reading operation. This current is used to determine the memory Whether the body cell MC is biased to be programmed (written out) 77 times. A memory location of the Zhao unit is being programmed (written). Up to this point, the node A and the node B of the latch circuit 10 in the page-turn buffer 100 have been preset to the low level and the high level, respectively. In a non-programming (write-out) operation, the node A and the node b are respectively set to a high level and a low level in advance. Here, a 'programming (writing) script is considered' so node A and node B are assumed to be set to low and high levels, respectively. As shown in the left line in FIG. 3B, where the memory cell MC0 has not been fully programmed (written), its threshold voltage Vt is higher than the word line WL. This paper standard applies to the Chinese National Standard (CNS) ) A4 size (210x297 male f) 17 / _ f • I --- I! ------ install -------- order --------- line · (Please read first Note on the back, please fill in this page again.> Printed on A7 B7 by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. The 0.8V voltage on the description of the invention (14) is small. SNS is pulled to a low level. When a high pulse is subsequently provided to this setting signal SET, as the node SNS is at a low level, node B in the latch circuit 1 continues to maintain the high level; when this setting signal SET When returning to the low level, the latch circuit 10 stores a state where node A = low level and node B = high level. This indicates that the programming (write-out) verification has failed 'and then this programming (write-out) operation is repeated As shown in the right line in Figure 3B, the location of the memory cell mc0 has been fully programmed (written out). The threshold voltage Vt is larger than the 0.8V voltage on the selected word line WLO, so the memory cell% ^^ is turned off and no current flows, and the node SNS is being charged to a high level. When a pulse follows When provided to the setting signal SET, 'Because the node SNS is at a high level, the node B is pulled to a low level; when the setting signal SET returns to the low level, the latch circuit 10 in the page buffer 100 is set again. This is a state in which the node high level and section = low level. This indicates that the programming (write-out) verification has succeeded, and then the programming (write-out) operation ends. Erase Verification Operation Now this erase verification operation is explained The erase verification operation is shown in Fig. 3C, Fig. A. At the last erase operation t, the threshold voltage of the memory cell in a block is shifted to the negative erase level Vtre, so in an erase verification operation We must apply a negative voltage to the control gates of the memory cells in an equivalent way to be able to verify that all of the memory cells are conductive within a string.
在本具體例f，於一抹除驗證操作時，陣列Vss電位 ARVss(第基準電位）係被保持在一預定之正電壓WER I---F I-------裝-------—訂·--------線 (請先閲讀背面之注意事項再填寫本頁)In this specific example f, during an erase verification operation, the array Vss potential ARVss (the first reference potential) is maintained at a predetermined positive voltage WER I --- F I --------------- ----- Order · -------- Line (Please read the precautions on the back before filling this page)
18 經濟部智慧財產局.員工消f合作社印製 463 W 2 A7 B7 五、發明說明（15) 而此轉頁緩衝器Vss電位PB Vss(第二基準電壓）亦係保持在 此一相同正電壓VVER ’ 一如第4A圖中所示。另一可供選 擇方式如第4B圖所示者，此陣列Vss電位ARVss係被保持 在一預定之第一正電壓VVER1而此轉頁緩衝器Vss電位 PBVss係被保持在一第二正電壓VVER2。驅動此轉頁緩衝 器Vss電位PB Vss以及此陣列Vss電位ARVss至正電壓之能 使由感測電晶體NB作感測操作者係在後文中說明。 此抹除驗證操作基本上係一如讀取操作相同，但自其 相異者其中為了要磘保該選擇之記憶體單元MCO之臨限電 壓係在負抹除位準Vter，選擇之方塊（抹除單元）之所有字 線係被驅動至0V，以及一定之正電壓VVER係應用至陣列 Vss電位ARVss。藉驅動字線WL至0V並應用一定之正電壓 VVER至陣列Vss電位ARVss，記憶體單元之控制閘係等值 地被驅動至負電位’確保記憶體單元内負抹除臨限電壓 Vtre。例如，以0.6V之應用於陣列Vss電位ARVss，則至 少提供一以最小臨限電壓絕對值為準之大約〇.6V2 —邊限 ，它可以於一讀取操作中作為邏輯“1”而讀取。 此抹除驗證操作用於選擇之方塊者現在係予說明《一 如第3C圖中所示’ 0V係應用於所有字線WL，以及大約4V 係應用於選擇閘SG1和SG2 ’選擇選定之方塊中之所有串 。0.6V係應用於陣列Vss電位ARVss，以及一樣地是0.6V 係應用於此轉頁緩衝器Vss電位PB Vss。在此一狀態中， 以轉頁緩衝器100内之信號BLCNTRL和BLPROT係一高位 準，轉頁緩衝器100和數元線BL係電相連。 本纸張又度適用♦园國家標箪（CNS)A4規格（210 X 297公茇） 19 ----^---------ri------訂·--------線. (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧时產局員工消費合作社印製 A7 B7 五、發明說明（16 ) 當信號BLCNTRL於讀取和編程（寫出）驗證操作中係 大約IV時，於抹除驗證操作中它係被驅動至大約i 6V(由 於此陣列Vss電位ARVss係0.6V)，以及因此當記憶體單元 係導電時被置於以數元線BL上之電壓（〇_6V)為準之1.0V之 較高位準。由於一串有數個記憶體單元（例如，16)呈串聯 地相連接，此係完成以便能輸送充分之汲-源電壓Vds至每 —記憶體單元。 同一時間地以轉頁緩衝器1 〇〇之電連接至數元線BL， 以信號PBIAS在低位準’此正常電流源p型電晶體接上， 以及正常電流係輸送至數元線BL。此一正常電流係用以 決定記憶體單元是否係充分地被抹除之基礎。直至此一點 ，轉頁緩衝器100内閂扣電路10之節點A和B分別地業已預 先設定至低位準和高位準。 一如第3c圖内左邊行中所示’一記憶體單元並未充分 地被抹除之位置’其臨限電壓係較字線WL(OV)和陣列Vss 電位ARVss(0.6V)之間之電位差Vgs(=-0.6V)為大（亦即： Vt>-0.6V>，因此記憶體單元之關斷而沒有電流流動，以 節點SNS在轉頁緩衝器内者係被充電至高位準。當一高位 準隨後係提供至設定信號SET時，電晶體N9導電，以及由 於節點SNS係高位準，故感測電晶體N8亦係導電，以及節 點B係被拉曳至低位準。因此’當此設定信號set回行至 低位準時’問扣電路10再設定至一狀態，其中節點高 位準以及節點B=低位準。此將指示該抹除驗證已失敗， 然後此抹除操作係重覆。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ----^--------- ^--------^---------線 (請先閱讀背面之注意事項再填寫本頁) 20 A7 46317 2 、---------- 1、發明說明（17 ) 一如第3C圖内右邊行中所示，相反地一記憶體單元 業已充分地被抹除之位置，其臨限電壓Vt係較字線和陣列 Vss電位之間之電位差Vgs(=-0.6V)為小（亦Vt<_〇 6V)，因 此記憶體單元接上以及電流流動，以節點Sns係被拉曳至 L低位準。應予說明者，即節點SNS低位準最多僅下降至 大約0.6V之陣列Vss電位ARVss。當一高脈衝隨後係提供 至此設定信號SET時，由於節點SNS係低位準，問扣電路 10内之即點B繼續地被保持在高低準；當此設定信號犯丁 回行至低位準時，閂扣電路10保持一狀態，其中節點 低位準而節點高位準。此將指示該抹除驗證業己成功 ，以及此抹除操作結束β 在此一時刻，雖然節點SNS最多僅下降至大約此陣列 Vss電位ARVss(=0.6V)具有由記憶體單元之導電，但由於 轉頁緩衝器100内感測電晶體N8之源電位係pBVss=0.6V， 故此感測電晶體N8可採取一充分地非導電狀態即令在正 常臨限電壓（例如’ 0.8V)時亦然，藉以防止在傳統式範例 中所見到之閂扣電路之差誤中之逆化。依此，自一可靠性 立場言’可能性存在之位置，以讀取操作為準之較大抹除 邊限將係須要’即令足採取，例如’ 1V係應用於此阵列vss 電位ARVss ’但感測電晶體N8之源電位係PBVss=0.6V(或 同樣是IV) ’藉以使感測電晶體N8可安全地繼續地被提供 非導電。在陣列Vss電位ARVss係較高之位置，為對其回 應’感測電晶體N8非導電操作可以同樣地藉增加轉頁緩 衝器Vss電位PBVss而確保。 表紙張尺度適用中國國家標準（CNS)A4規格（210 « 297公笼） -、 ί ^---------裝--------訂---------線· (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局負工消費合作社印製 2118 Intellectual Property Bureau of the Ministry of Economic Affairs. Employees printed by cooperatives. 463 W 2 A7 B7 V. Description of invention (15) The page transfer buffer Vss potential PB Vss (second reference voltage) is also kept at this same positive voltage VVER 'as shown in Figure 4A. Another alternative is shown in FIG. 4B. The array Vss potential ARVss is maintained at a predetermined first positive voltage VVER1 and the page buffer Vss potential PBVss is maintained at a second positive voltage VVER2. . The ability to drive the page transfer buffer Vss potential PB Vss and the array Vss potential ARVss to a positive voltage will be explained later by the sensing transistor NB as a sensing operator. This erase verification operation is basically the same as the read operation, but from the difference, in order to ensure that the threshold voltage of the selected memory cell MCO is at the negative erase level Vter, the selected block ( All the word lines of the erasing unit are driven to 0V, and a certain positive voltage VVER is applied to the array Vss potential ARVss. By driving the word line WL to 0V and applying a certain positive voltage VVER to the array Vss potential ARVss, the control gate of the memory cell is driven to the negative potential equivalently 'to ensure the negative erasure threshold voltage Vtre in the memory cell. For example, if 0.6V is applied to the array Vss potential ARVss, then at least one 0.6V2—the margin based on the absolute value of the minimum threshold voltage—is provided. It can be read as a logic “1” in a read operation. take. Those who use this erase verification operation to select the blocks are now explained "As shown in Figure 3C, '0V is applied to all word lines WL, and approximately 4V is applied to the selection gates SG1 and SG2' to select the selected block All strings in. The 0.6V system is applied to the array Vss potential ARVss, and the 0.6V system is applied to the page buffer Vss potential PB Vss. In this state, the signals BLCNTRL and BLPROT in the page buffer 100 are at a high level, and the page buffer 100 and the bit line BL are electrically connected. This paper is also applicable to the national standard (CNS) A4 size of the garden (210 X 297 cm) 19 ---- ^ --------- ri ------ Order · --- ----- line. (Please read the notes on the back before filling out this page) Printed by the Consumers' Cooperative of the Ministry of Economic Affairs and the Intellectual Property Bureau A7 B7 V. Description of the invention (16) When the signal BLCNTRL is read and programmed (write (Out) When the verification operation is about IV, it is driven to about 6V during the erase verification operation (because the array Vss potential ARVss is 0.6V), and therefore it is set to several digits when the memory cell is conductive. The voltage (0-6V) on the element line BL is higher than 1.0V. Since a string of several memory cells (e.g., 16) are connected in series, this system is completed so as to be able to deliver a sufficient drain-source voltage Vds to each memory cell. At the same time, the paging buffer 1000 is electrically connected to the digital line BL, and the signal PBIAS is connected at a low level to the normal current source p-type transistor, and the normal current is transmitted to the digital line BL. This normal current is used to determine whether the memory cell is sufficiently erased. Up to this point, the nodes A and B of the latch circuit 10 in the page buffer 100 have been preset to the low level and the high level, respectively. As shown in the left line of Figure 3c, 'a location where a memory cell has not been sufficiently erased', the threshold voltage is between the word line WL (OV) and the array Vss potential ARVss (0.6V). The potential difference Vgs (= -0.6V) is large (ie, Vt > -0.6V >, so the memory cell is turned off without current flowing, and the node SNS is charged to the high level in the page buffer. When a high level is subsequently provided to the setting signal SET, the transistor N9 is conductive, and because the node SNS is a high level, the sensing transistor N8 is also conductive, and the node B is pulled to a low level. When the set signal returns to the low level, the interrogation circuit 10 is set to a state where the node high level and the node B = low level. This will indicate that the erase verification has failed, and then the erase operation is repeated. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) ---- ^ --------- ^ -------- ^ ------- --Line (please read the notes on the back before filling this page) 20 A7 46317 2 ------------ 1. Description of the invention (17) As shown in the right line in Figure 3C, Where the anti-ground memory cell has been fully erased, its threshold voltage Vt is smaller than the potential difference Vgs (= -0.6V) between the word line and the array Vss potential (also Vt < _〇6V), Therefore, the memory unit is connected and the current flows, and the node Sns is pulled to the low level of L. It should be noted that the low level of the node SNS only drops to an array Vss potential ARVss of about 0.6V at most. When a high pulse follows When the set signal SET is provided to this point, because the node SNS is at a low level, the point B in the buckle circuit 10 is continuously maintained at a high level; when the set signal returns to the low level, the latch circuit 10 remains at a low level. State, where the node is at a low level and the node is at a high level. This will indicate that the erasure verification has been successful, and that the erasure operation has ended β. At this moment, although the node SNS only drops down to approximately the array Vss potential ARVss (= 0.6 V) It is conductive by the memory unit, but since the source potential of the sensing transistor N8 in the page turning buffer 100 is pBVss = 0.6V, the sensing transistor N8 can take a fully non-conductive state, which will cause the Limiting voltage (eg '0 .8V), so as to prevent the reversal in the error of the latch circuit seen in the traditional example. Therefore, from a reliability standpoint, where the possibility exists, the reading operation shall prevail A larger erasure margin will need to be taken, for example, '1V is applied to this array vss potential ARVss', but the source potential of the sensing transistor N8 is PBVss = 0.6V (or the same IV)' The photodetector N8 can safely continue to be provided non-conductive. In the position where the array Vss potential ARVss is relatively high, in order to respond to the non-conductive operation of the sensing transistor N8, it can be similarly ensured by increasing the page transfer buffer Vss potential PBVss. The paper size of the table is applicable to China National Standard (CNS) A4 specification (210 «297 male cages)-, ί ^ --------- installed -------- order -------- -Line · (Please read the notes on the back before filling out this page) Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 21
五、發明說明（18 ) 第5圖係本具體例中記憶體單元陣列和轉頁緩衝器之 構造圖。第5A圖係相當於第4A圖之一構造圖，其中此陣 列Vss電位ARVss和轉頁緩衝器Vss電位係經控制至相同電 壓。依此’由陣列Vss電位產生電路11 〇所產生之電壓係同 樣地輸送至轉頁緩衝器。 第5B圖係相當於第4B圖之構造圖，其中此陣列Vss電 位ARVss和轉頁緩衝器Vss電位個別地被控制，係 於抹除驗證操作中被控制至不同之正電壓。 多餘記憶體單元或輔助記憔艚輩元 直至比一點之說明已有關反及型快閃記憶體之記憶 體單元和轉頁緩衝器。現在，於用以貯存多餘資訊之多餘 έ己憶體單元上有本發明之一具體例之說明，亦即，使用於 反及閘型快内記憶體中之有缺點之地址。在下文中所說明 之多餘記憶體單元可以由用以貯存除了多餘資訊以外之預 先測定之資訊之一輔助記憶體單元所構成。 在用以貯存資料之一記憶體單元已變為有缺點之位 置，其地址係作為多餘資訊貯存，以及它係由為此一目的 所提供之另一記憶體單元所取代。用以貯存有瑕疵單元地 址作為多餘資訊之一多餘記憶體單元因此係需要。在某些 情勢中’ 一輔助記憶體單元使用以貯存除了多餘資訊以外 之關有此裝置之各種其他資料者可能須要》在此一情況下 ，記憶體單元設計將是類比於多餘記憶體單元。 第6圖係本具趙例中_多餘記憶體單元之構造圖。相 當於第14圖中傳統式範例中之那些構件已指定以相同之符 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ------------I --------^ --------- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 22 經濟部智慧財產局員工消費合作社印製 A7 ____B7_ 五、發明說明（19 ) 號。雖然在第14中在感測放大器101内感測電晶體N23之 源極係在接地線電位Vss，但在第6圖之設計中它係在一 Vss 電位PBVss係控制至一預定之正電位於抹除驗證操作中。 此感測放大器Vss電位PBVss和陣列Vss電位ARVss經連接 至多餘記憶體單元RMC終端上之源極者係經控制至〇v於 讀取操作中，以及至0V於偏程驗證操作中，以及抹除驗 證操作中係經控制至相同之預定正電壓，或至不同正電壓 〇 第8圖說明一範例，其中此陣列Vss電位ARVss(第二 基準電位）和感測放大器Vss電位PBVss(第二基準電位）係 經控制至相同正電壓VVER於抹除驗證操作中。第9圖說 明一範例，其中這些係經控制至不同之正電壓VVER 1和 VVER2。在第8圖之範例中，一如第8A圖之電壓狀況之表 内所示者’此陣列Vss電位ARVss和感測放大器Vss電位 PBVss係經控制至相同電壓於讀取操作，編程驗證操作和 抹除驗證操作時，因此，在第8B圖内所示構造圖中，此 陣列Vss電位產生電路丨1〇之輸出係對記憶體單元和感測放 大器101而呈現。 第9圖内之範例中’此陣列Vss電位ARVss和感測放大 器Vss電位PBVss係經分開地控制。 有關第8圖内對相同正電壓WER之控制之範例，此讀 取操作，編程驗證操作，和抹除驗證操作係在下文中以第 7圖之操作時序圖為基準來說明。 讀取操作 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公g ) - - ---------— I— --- (請先閱讀背面之注意事項再填寫本頁)5. Description of the Invention (18) FIG. 5 is a structural diagram of a memory cell array and a page buffer in this specific example. Figure 5A is equivalent to one of Figure 4A, in which the Vss potential ARVss and the page transfer buffer Vss potential of this array are controlled to the same voltage. In accordance with this, the voltage generated by the array Vss potential generating circuit 110 is transmitted to the page buffer in the same manner. Fig. 5B is a structural diagram equivalent to Fig. 4B, in which the Vss potential ARVss of the array and the potential of the page transfer buffer Vss are individually controlled, which are controlled to different positive voltages during the erase verification operation. Redundant memory unit or auxiliary memory generation up to a point that the memory unit and the page buffer of the inversion type flash memory are related. Now, there is a description of a specific example of the present invention on a redundant memory unit for storing redundant information, that is, a defective address used in a reverse type fast internal memory. The redundant memory unit described below may be constituted by an auxiliary memory unit for storing pre-measured information other than redundant information. Where a memory unit used to store data has become defective, its address is stored as redundant information, and it is replaced by another memory unit provided for this purpose. An extra memory unit is needed to store the address of the defective unit as one of the extra information. In some cases, an auxiliary memory unit may be used to store various other data related to the device in addition to the redundant information. In this case, the memory unit design will be analogized to the redundant memory unit. Figure 6 is the structure diagram of the redundant memory unit in this example. Corresponding to those in the traditional example in Figure 14, the components have been designated with the same standard. The paper size applies to the Chinese National Standard (CNS) A4 (210 X 297 mm) ------------ I -------- ^ --------- (Please read the notes on the back before filling out this page) Printed by the Employees ’Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 22 The cooperative prints A7 ____B7_ V. Invention Description (19). Although the source of the sense transistor N23 in the sense amplifier 101 in the fourteenth is connected to the ground line potential Vss, in the design of FIG. 6 it is controlled at a Vss potential PBVss to a predetermined positive voltage at Erase verification operation. The sense amplifier Vss potential PBVss and the array Vss potential ARVss are connected to the source on the RMC terminal of the redundant memory unit are controlled to 0V in the reading operation, and 0V in the offset verification operation, and erase. The verification operation is controlled to the same predetermined positive voltage or to different positive voltages. Figure 8 illustrates an example in which the array Vss potential ARVss (second reference potential) and the sense amplifier Vss potential PBVss (second reference Potential) is controlled to the same positive voltage VVER during the erase verification operation. Figure 9 illustrates an example where these are controlled to different positive voltages VVER 1 and VVER2. In the example of FIG. 8, as shown in the table of voltage conditions in FIG. 8A, 'the array Vss potential ARVss and the sense amplifier Vss potential PBVss are controlled to the same voltage during the read operation, the program verification operation and During the erase verification operation, therefore, in the structure diagram shown in FIG. 8B, the output of the array Vss potential generating circuit 丨 10 is presented to the memory cell and the sense amplifier 101. In the example in FIG. 9 ', the array Vss potential ARVss and the sense amplifier Vss potential PBVss are separately controlled. Regarding the example of the control of the same positive voltage WER in FIG. 8, this read operation, program verification operation, and erase verification operation are described below with reference to the operation timing diagram of FIG. 7. Reading operation This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 g)-----------— I— --- (Please read the precautions on the back before filling (This page)
I --線一 23 經濟部智慧財產局員工消費合作钍印則农 A7 B7 五、發明說明（20 ) 一如第7A圊中所示，在一讀取操作中，以字線WL在 〇V和選擇閘信號SG1和SG2在4V，以及以信號PBIAS在低 位準，P型電晶體P21接上以及正常電流係輸送至節點SNS 。陣列Vss電位ARVss係0 V以及感測放大Vss電位PB Vss亦 係0V。一逆反抹除驗證信號ERVB(Erase Verify Bar)係在 電力供應電位Vcc。 如果記憶體單元RMC含一邏輯” 1 ”，其臨限電壓Vt係 負電壓，因此即令當字線WL係0V，記憶體單元RMC汲出 電流，以及其結果使在數元線BL上之電位行向低位準， 電晶體N20採取導電狀態，以及節點SNS行向低位準。隨 後，感測電晶體N23關斷’感測電晶體P22接上’以及高 位準係經由電晶體P24和反相器14、15而輸出在輸出接頭 OUT上面。 相反地，如果記憶體單元RMC含一邏輯”0”，由於其 臨限電壓Vt係正位準，記憶體單元RMC關斷於字線WL係 0V時，在數元線BL上之電位行向高位準，電晶體N20關 斷，以及節點SNS係充電至由自正常電流電晶體P2 1之正 常電流光電至高位準。因此，由於此節點SNS係高位準， 感測電晶體N23接上，感測電晶體P2 1關斷，以及低位準 係輸出於輸出接頭OUT上面。 編程（寫出）驗證操作 此編程（寫出）驗證操作現在係以第7B圖為準來說明。 此編程驗證操作基本上係如讀取操作相同，但自其有異者 ，其中正電壓係應用於字線WL以便能確保一編程（寫出） 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 24 --------------------ί 訂-----ί I-- (請先閱讀背面之注意事項再填寫本頁) 463172 經濟部智慧財產局ΐίΚ工消費合作社印製 Α7 Β7 五、發明說明（21 ) 邊限。在本文所說明之範例中，〇·8ν係應用於字線WL。 以選擇閘SG1和SG2在4V以及信號PBIAS為低位準，ρ型電 as體P21接上以及負載電流係經輸送a卩車列vss電位arvSs 係0V以及逆反抹除驗證信號ERVB係高位準。 在記憶體單元RMC係未充分地編程（寫出）之位置，其 臨限電壓Vt係較0.8V之字線電壓為小，因此記憶體單元 RMC導電並汲出電流。其結果，節點SNS行向至低位準， 以及高位準係輪出於輸出接頭OUT上面。此將指示該編程 (寫出）驗證已失敗’然後此寫出操作係再開始。 相反地’在記憶體單元RMC係已充分地編程（寫出）之 位置，其臨限電壓Vt係較0.8V之字線電壓為大，因此記憶 體單元RMC關斷，電晶體N20變成非導電，以及節點SNS 係經充電至高位準。其結果’低位準係輸出於輸出接頭OUT 上面。此將指示該編程（寫出）驗證已成功，以及此編程（ 寫出）操作結束。 抹除驗證操作 抹除驗證操作現在係以第7C圖為準來說明。此抹除 驗證操作亦係基本上如讀取操作相同，但自其有異者，其 中此陣列Vss電位ARVss(第一基準電壓）係經控制至一預定 之正電壓以便能確保一抹除邊限。在同一時間，此感測放 大器Vss電位PBVss(第二基準電壓）係亦經控制至一預定之 正電壓以確使由感測電晶體N23之接上關斷操作。在此一 範例中。0.6V係應用於陣列Vss電位ARVss和感測放大Vss 電位PBVss β 本纸張尺度適用尹國國家標準（CNS)A4規格（210 * 297公釐） 25 1 -^ ----；-----------------訂--------. (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（22 ) 首先，以字線WL在ΟV以及選擇閘線SG1和SG2在4V ，以及以信號PRIAS在低位準，p型電晶體p21接上以及負 載電流係經輸送。以逆反抹除驗證信號ERVB在0V，以電 晶體N20之導電係經確保。由於陣列Vss電位ARVss係0.6V ，即令在該處記憶體單元RMC導電以及數元線BL係被拉 下至ARVSS，足夠之低位準仍不能是被提供至反及閘12 ，因此以逆反抹除驗證信號ERVB在低位準，此反及閘12 之輸出係可靠地被維持於高位準。其結果，Vcc係應用於 連接至節點SNS和數元線BL之N型電晶體N20之閘極，確 保該電晶體N20接上。 在記憶體單元RMC係未充分地被抹除之位置，其臨 限電壓Vt係較-0.6V更大（Vt>-0.6V)，記憶體單元RMC關 斷，以及節點SNS係被充電至高位準。依此，感測電晶體 N23導電，以及低位準係輸出於輸出接頭OUT上面。此將 指示該抹除驗證操作已失敗，以及此抹除操作係再開始。 相反地，記憶體單元RMC係充分地已抹除之位置， 其臨限電壓Vt係較0.6V為小（Vt<-0.6V)，記憶體單元汲取 電流，以及其結果，此節點SNS行向低位準。應予說明者 ，即當陣列Vss電位ARVss係0.6V時，此節點SNS最多僅 下降至0.6V。不過，由於感測放大器101内感測電晶體N23 之源極係已連接至感測放大器Vss電位（=0.6V)，故閘一源 電壓下落至臨限電壓以下，確保該感測電晶體N23係非導 電。其結果，包含電晶體P22、N23之CMOS反相器之輸出 行向至高位準，以及高位準係輸出於輸出接頭OUT上面。 表紙張尺度適用中國國家標準（CNTS)A4規格（21〇χ297公笼） 26 -------------裝.-------訂.--------線 (請先閱讀背面之注意事項再填寫本頁) 經臂部智慧財產局員工消費合作社印製 463172 A7 --------B7____— —___ 五、發明說明（23 ) 此即指示該抹除驗證操作已成功，以及此抹除操作係已結 束。 一如自先前之說明至為顯明者，在抹除驗證操作中 一定之正電壓係應用於此陣列Vss電位ArVss，藉以理想 地使節點SNS係被拉曳至低位準，而但不低於相等於此一 電位ARVss之位準。包括電晶體P22和N23之反相器之跳脫 點（逆向輸入位準）係由此生產程序和電晶體能力所測定。 典型地，它係以電力供應Vcc為準之大約Vcc/2。依此，自 不可靠之立場言可能性存在之位置，以讀取操作為準之 較大抹除邊限將屬需要’例如，IV係應用於陣列Vss電位 ARVss，但如果電力供應Vcc係在此一時刻為低時（例如， 2V) ’抹除驗證即不能予以實施。原因是該節點，即 令在理想之狀況下，下落至不會較1V為低，亦即，陣列 電位ARVss位準’以及在實際之慣例中此節點SNS電壓由 於用於橫越選擇閘電晶體和記憶體單元之源極及汲極之電 壓Vds之需要而係較iv為高。由於此一位準（lv)係接近反 相器之跳脫點（1V)，那係可能使該輸出將是中間位準。 要解決此一問題’吾人可能來運用反相器之電晶體 比率來設定較高之跳脫點。不過，它可以增大之範圍係有 限制’以可能之解決方法在較高電壓係應用於此陣列Vss 電壓ARVss之位置係已枯竭。破壞電晶链比率須要較大電 晶體尺寸和增大佈署區域，此外，寫出邊限之改變它可能 影響讀取速度。 依此’在本具體例中，感測電晶體Ν23之源極PBVss 本纸張尺度適用中囷國家標準(CNSM4規格（21〇χ297公爱） - ί --I ------— — 訂·!------線. (請先閱讀背面之注意事項再填寫本頁) 27 鳇濟部智慧財產局員工消費合作社印製 Δ7 --------— B7 _ 五、發明說明（24 ) 係於抹除驗證操作中經控制至一預定之正電壓。藉如此作 為，吾人可能來等值地增大節點SNS係輸入至其閘極之反 相器P22、N23之跳脫點，能使反相器感測節點SNS類比 於一般讀取操作之低位準，儘管正電壓係於一抹除驗證操 作中應用於此陣列Vss電位ARVss。 在第8圖之範例中，此感測放大器vss電位pbVss和此 陣列電位ARVss係相等電壓；不過，這些不需要一定是相 等電壓’因此一較對陣列電位ARVss不同正電壓可以應用 於感測放大器Vss電位PB Vss，如第9圖内所示。雖然上述 記憶體係一用以貯存多餘資訊之電路，但並不限制其對多 餘資訊’以用以貯存各種其他資訊之電路用以作用之裝置 者亦係可接受。此具體例說明一單一記憶體單元，但數個 單元呈串聯地連接式並聯地連接者係亦可接受。 第10圖係一圖顯示另一多餘記憶體單元和感測放大 器102之結構。第11圖係一圊表，顯示第1〇圖之電壓狀況 。第10圖之電路有一如第5圖之感測放大器1〇1之相同结構 ’除了該感測放大器係屬閂扣類型以外。依此，第1 〇圖之 感測放大器102係經由一電晶體N30而連接至數元線BL， 以及節點SNS之位準係由含CMOS反相器P32 ' N33以及反 相器P22、N23之一閂扣電路所閂扣。 第ΠΑ、ΠΒ圖顯示於讀取’編程（寫出）驗證，和抹除 驗證操作中之電壓狀況。在第i 1A圖之範例中，此感測放 大器電位PB Vss和陣列Vss電位ARVss係經控制至相同電壓， 然而在第11B圖之範例中此讀取和編程驗證操作中其電位 本紙張尺度適用中®國家標準（CNS)A4規格（210 X 297公莹） ----；---I --------I I---訂· I I----I (請先閱讀背面之注意事項再填寫本頁) 28 46317 2 A7 B7 五、發明說明（25 ) 係相同（0V)，但於抹除驗證操作中則控制至不同正電壓 WER1、WER2。此具體例說明一單一記憶體單元，但數 個單元亦可以串聯地相連接。另一可供選擇方式為數個單 元可以並聯地相連接。 同樣地在此一具體例中，於抹除驗證操作時，即令 是如果此節點SNS之低位準下落不較陣列Vss電位ARVss( 例如’ 0.6V)為低時，包含電晶體P22、P23之反相器之跳 脫位準（側反位準）係由於P B V s s而等值地高，確使以電晶 體N23之非導電。 依照本發明，在一反及閘型非依電性記憶體内，其 中此抹除之狀態採取一負、臨限電壓，驗證操作可以於抹除 驗證操作時在一安全可靠方法來執行。 雖然本發明業以一特殊具體例為基準而說明，但本 發明之範圍係不限於該具體例，並係被視為包括如在增錄 之專利申請項目及其相等文件中所設定之範圍。 元件標號對照 ' ' f ----it------» --------訂·--------. (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作钍印製 10…閂扣電 12…反及閘 14…反相器 …反相器 路 100···感測電路 1〇〇…轉頁緩衝器電路 102…多餘記憶體單元 110…電位產生電路 29 各纸張尺度適用中國囷家標準（CNS>A·!規格（210x297公釐）I-Line 1 23 Consumption cooperation between employees of the Intellectual Property Bureau of the Ministry of Economic Affairs and Seal A7 B7 V. Description of the invention (20) As shown in 7A 圊, in a read operation, the word line WL is at 0V. The selection gate signals SG1 and SG2 are at 4V, and the signal PBIAS is at a low level. The P-type transistor P21 is connected and the normal current is transmitted to the node SNS. The array Vss potential ARVss is 0 V and the sensed amplification Vss potential PB Vss is also 0 V. The reverse erasure verification signal ERVB (Erase Verify Bar) is at the power supply potential Vcc. If the memory cell RMC contains a logic "1", its threshold voltage Vt is a negative voltage, so that when the word line WL is 0V, the memory cell RMC draws a current, and as a result, the potential on the bit line BL is increased. To a low level, the transistor N20 adopts a conductive state, and the node SNS line goes to a low level. Subsequently, the sensing transistor N23 is turned off, the sensing transistor P22 is connected, and the high level is outputted to the output connector OUT via the transistor P24 and the inverters 14 and 15. Conversely, if the memory cell RMC contains a logic "0", because its threshold voltage Vt is at the positive level, when the memory cell RMC is turned off at the word line WL at 0V, the potential direction on the bit line BL is High level, transistor N20 is turned off, and node SNS is charged to the high level from the normal current photoelectricity of normal current transistor P2 1. Therefore, because this node SNS is a high level, the sensing transistor N23 is connected, the sensing transistor P2 1 is turned off, and the low level is output on the output connector OUT. Programming (write-out) verification operation This programming (write-out) verification operation is now described with reference to Figure 7B. This program verification operation is basically the same as the read operation, but it is different. The positive voltage is applied to the word line WL so as to ensure a programming (write out). (210 X 297 mm) 24 -------------------- ί Order ----- ί I-- (Please read the notes on the back before filling in this Page) 463172 Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, 工 Κ 工 合作 consuming cooperative A7 Β7 V. Description of invention (21) Margin. In the example described herein, 0.8V is applied to the word line WL. With the selection gates SG1 and SG2 at 4V and the signal PBIAS as the low level, the p-type electric body P21 is connected and the load current is transmitted to the vehicle train vss potential arvSs is 0V and the reverse erasure verification signal ERVB is the high level. Where the memory cell RMC is not sufficiently programmed (written out), its threshold voltage Vt is smaller than the 0.8V zigzag line voltage, so the memory cell RMC conducts electricity and draws current. As a result, the node SNS runs to a low level, and the high level system wheel is out of the output connector OUT. This will indicate that the programming (write-out) verification has failed 'and then this write-out operation will begin. Conversely, at the position where the memory cell RMC is fully programmed (written), its threshold voltage Vt is greater than the 0.8V zigzag line voltage, so the memory cell RMC is turned off and the transistor N20 becomes non-conductive , And the node SNS is charged to a high level. The result 'is output to the output terminal OUT. This will indicate that the programming (write-out) verification was successful and that this programming (write-out) operation is complete. Erase Verification Operation The erase verification operation is now described with reference to Figure 7C. The erase verification operation is basically the same as the read operation, but it is different from it. The array Vss potential ARVss (first reference voltage) is controlled to a predetermined positive voltage to ensure an erase margin. . At the same time, the sense amplifier Vss potential PBVss (second reference voltage) is also controlled to a predetermined positive voltage to ensure that the switching off of the sensing transistor N23 is performed. In this example. 0.6V is applied to the array Vss potential ARVss and the sensed amplification Vss potential PBVss β This paper standard is applicable to Yin National Standard (CNS) A4 specification (210 * 297 mm) 25 1-^ ----; --- -------------- Order --------. (Please read the notes on the back before filling out this page) Printed by A7 B7, Consumer Cooperatives, Intellectual Property Bureau, Ministry of Economic Affairs (22) First, the word line WL is at 0V, and the selection gate lines SG1 and SG2 are at 4V, and the signal PRIA is at a low level. The p-type transistor p21 is connected and the load current is transmitted. The verification signal ERVB is reversed at 0V, and the conductivity of transistor N20 is ensured. Since the array Vss potential ARVss is 0.6V, even if the memory cell RMC is conductive and the digit line BL is pulled down to ARVSS, a sufficient low level cannot be provided to the anti-reverse gate 12, so it is erased by reverse. The verification signal ERVB is at a low level, and the output of the anti-gate 12 is reliably maintained at a high level. As a result, Vcc is applied to the gate of the N-type transistor N20 connected to the node SNS and the element line BL to ensure that the transistor N20 is connected. Where the memory cell RMC is not sufficiently erased, its threshold voltage Vt is greater than -0.6V (Vt > -0.6V), the memory cell RMC is turned off, and the node SNS system is charged to a high level quasi. According to this, the sensing transistor N23 is conductive, and the low level is output on the output connector OUT. This will indicate that the erase verification operation has failed and that the erase operation will begin again. Conversely, the memory cell RMC is a fully erased position, and its threshold voltage Vt is smaller than 0.6V (Vt < -0.6V), the memory cell draws current, and as a result, the node SNS line direction Low level. It should be explained that when the array Vss potential ARVss is 0.6V, the SNS of this node only drops to 0.6V at most. However, since the source of the sense transistor N23 in the sense amplifier 101 is connected to the Vss potential (= 0.6V) of the sense amplifier, the gate-source voltage drops below the threshold voltage to ensure the sense transistor N23 Department is non-conductive. As a result, the output direction of the CMOS inverter including the transistors P22 and N23 reaches the high level, and the high level is output on the output connector OUT. The paper size of the table is applicable to the Chinese National Standard (CNTS) A4 specification (21〇χ297 male cage) 26 ------------- installed. --Line (Please read the precautions on the back before filling this page) Printed by the Arm Intellectual Property Bureau Staff Consumer Cooperative 463172 A7 -------- B7 ____—— —___ V. Description of Invention (23) This is Indicates that the erase verification operation was successful and that the erase operation has ended. As from the previous explanation to the obvious, a certain positive voltage is applied to the array Vss potential ArVss in the erase verification operation, so that the node SNS system is ideally pulled to a low level, but not lower than the phase Equal to the level of this potential ARVss. The trip point (inverted input level) of the inverter including transistors P22 and N23 is determined by this production process and transistor capabilities. Typically, it is about Vcc / 2 based on the power supply Vcc. Accordingly, from the unreliable position, where a possibility exists, a larger erasing margin based on the reading operation will be needed. For example, the IV system is applied to the array Vss potential ARVss, but if the power supply Vcc is at When this moment is low (for example, 2V) 'Erase verification cannot be performed. The reason is that this node, even under ideal conditions, will not fall below 1V, that is, the array potential ARVss level 'and in actual practice this node SNS voltage is used to select the gate transistor and The voltage Vds of the source and drain of the memory cell is higher than iv. Since this level (lv) is close to the trip point (1V) of the inverter, it is possible that the output will be at the middle level. To solve this problem, we may use the transistor ratio of the inverter to set a higher trip point. However, the range in which it can be increased is limited ', and the possible solutions are exhausted at the positions where the higher voltage system is applied to the array Vss voltage ARVss. Destroying the transistor chain ratio requires a larger transistor size and larger deployment area. In addition, changing the write margin may affect reading speed. According to this', in this specific example, the source PBVss of the sensing transistor N23 is applied to the Chinese standard (CNSM4 specification (21〇297297)) of this paper standard-ί --I --------- Order !! ------ line. (Please read the notes on the back before filling out this page) 27 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Δ7 -------- B7 _ V. Invention description (24) is controlled to a predetermined positive voltage in the erasing verification operation. By doing so, we may increase the jump of the node SNS by equivalently to the inverters P22 and N23 of its gate. The off point can make the inverter sensor node SNS analogy to the low level of general read operation, although the positive voltage is applied to the array Vss potential ARVss in an erase verification operation. In the example in FIG. 8, this sense The sense amplifier vss potential pbVss and the array potential ARVss are equal voltages; however, these need not necessarily be equal voltages. Therefore, a different positive voltage compared to the array potential ARVss can be applied to the sense amplifier Vss potential PB Vss, as shown in Figure 9 Shown. Although the above memory system is a circuit for storing redundant information, but Any device that does not limit its use of redundant information to store a variety of other information is acceptable. This specific example illustrates a single memory unit, but several units are connected in series and in parallel. It is also acceptable. Figure 10 is a diagram showing the structure of another redundant memory unit and the sense amplifier 102. Figure 11 is a watch showing the voltage status of Figure 10. The circuit of Figure 10 has a The same structure of the sense amplifier 1001 as shown in FIG. 5 except that the sense amplifier is a latch type. Accordingly, the sense amplifier 102 of FIG. 10 is connected to a digital element through a transistor N30. The level of the line BL and the node SNS is latched by a latch circuit including a CMOS inverter P32 'N33 and one of the inverters P22 and N23. Figures ΠΑ and ΠB are shown in the read-out programming (write out) Verify, and erase the voltage conditions during verify operation. In the example in Figure i 1A, the sense amplifier potential PB Vss and array Vss potential ARVss are controlled to the same voltage, but in the example in Figure 11B read this Fetch and program verify its potential Paper Size Applicable® National Standard (CNS) A4 Specification (210 X 297 Glitter) ----; --- I -------- I I --- Order · I I ---- I (Please read the precautions on the back before filling in this page) 28 46317 2 A7 B7 V. The description of the invention (25) is the same (0V), but it is controlled to different positive voltages WER1 and WER2 during the erase verification operation. This is specific The example illustrates a single memory unit, but several units can also be connected in series. Another alternative is that several units can be connected in parallel. Similarly, in this specific example, in the erasing verification operation, if the low level drop of the SNS of this node is not lower than the array Vss potential ARVss (for example, '0.6V), the transistor P22 and P23 are included The phase trip level (side inversion level) is equivalently high due to the PBV ss, which makes the transistor N23 non-conductive. According to the present invention, a negative and threshold voltage is used in an anti-inverter gate type non-electrical memory, and the verification operation can be performed in a safe and reliable method during the erase verification operation. Although the present invention has been described with reference to a specific specific example, the scope of the present invention is not limited to the specific example, and is considered to include the range as set in the appended patent application items and equivalent documents. Component label comparison '' f ---- it ------ »-------- Order · --------. (Please read the precautions on the back before filling this page) Employees' cooperation of the Intellectual Property Bureau of the Ministry of Economic Affairs, printing 10 ... latching 12 ... reverse gate 14 ... inverter ... inverter circuit 100 ... sensing circuit 100 ... page buffer circuit 102 redundant Memory unit 110 ... potential generating circuit 29 Chinese paper standards (CNS > A ·! Specifications (210x297 mm))
Claims (1)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23007399A JP3888808B2 (en) | 1999-08-16 | 1999-08-16 | NAND nonvolatile memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW463172B true TW463172B (en) | 2001-11-11 |
Family
ID=16902131
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW089105280A TW463172B (en) | 1999-08-16 | 2000-03-22 | NAND type nonvolatile memory |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US6288944B1 (en) |
| EP (1) | EP1077450B1 (en) |
| JP (1) | JP3888808B2 (en) |
| KR (1) | KR100596083B1 (en) |
| DE (1) | DE60017838T2 (en) |
| TW (1) | TW463172B (en) |
Families Citing this family (92)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3888808B2 (en) * | 1999-08-16 | 2007-03-07 | 富士通株式会社 | NAND nonvolatile memory |
| JP3844930B2 (en) * | 2000-02-09 | 2006-11-15 | 株式会社東芝 | Nonvolatile semiconductor memory device |
| KR100383763B1 (en) * | 2000-12-29 | 2003-05-14 | 주식회사 하이닉스반도체 | Method of testing a memory cell in semiconductor device |
| ITRM20010001A1 (en) * | 2001-01-03 | 2002-07-03 | Micron Technology Inc | LOW VOLTAGE FLASH MEMORY DETECTION CIRCUIT. |
| US6480419B2 (en) * | 2001-02-22 | 2002-11-12 | Samsung Electronics Co., Ltd. | Bit line setup and discharge circuit for programming non-volatile memory |
| DE10121131C1 (en) * | 2001-04-30 | 2002-12-19 | Infineon Technologies Ag | data storage |
| US6628563B1 (en) | 2001-07-09 | 2003-09-30 | Aplus Flash Technology, Inc. | Flash memory array for multiple simultaneous operations |
| JP2003030994A (en) * | 2001-07-18 | 2003-01-31 | Fujitsu Ltd | Semiconductor memory and driving method for semiconductor memory |
| US7057935B2 (en) * | 2001-08-30 | 2006-06-06 | Micron Technology, Inc. | Erase verify for non-volatile memory |
| KR100506191B1 (en) * | 2002-07-08 | 2005-08-04 | 주식회사 하이닉스반도체 | Circuit for generating a trim bit signal in a flash memory device |
| US7004564B2 (en) | 2003-07-31 | 2006-02-28 | Hewlett-Packard Development Company, L.P. | Printing-fluid container |
| KR100530930B1 (en) * | 2004-05-11 | 2005-11-23 | 주식회사 하이닉스반도체 | A method for multi-i/o repair of nand flash memory device and a nand flash memory device thereof |
| KR100632637B1 (en) * | 2004-11-11 | 2006-10-11 | 주식회사 하이닉스반도체 | Method for verifying nand flash memory device and nand flash memory device thereof |
| JP4786171B2 (en) * | 2004-12-10 | 2011-10-05 | 株式会社東芝 | Semiconductor memory device |
| US7551492B2 (en) * | 2006-03-29 | 2009-06-23 | Mosaid Technologies, Inc. | Non-volatile semiconductor memory with page erase |
| WO2007132452A2 (en) | 2006-05-12 | 2007-11-22 | Anobit Technologies | Reducing programming error in memory devices |
| WO2007132457A2 (en) | 2006-05-12 | 2007-11-22 | Anobit Technologies Ltd. | Combined distortion estimation and error correction coding for memory devices |
| US8050086B2 (en) | 2006-05-12 | 2011-11-01 | Anobit Technologies Ltd. | Distortion estimation and cancellation in memory devices |
| WO2007132456A2 (en) | 2006-05-12 | 2007-11-22 | Anobit Technologies Ltd. | Memory device with adaptive capacity |
| US7688635B2 (en) * | 2006-07-14 | 2010-03-30 | Micron Technology, Inc. | Current sensing for Flash |
| US8060806B2 (en) | 2006-08-27 | 2011-11-15 | Anobit Technologies Ltd. | Estimation of non-linear distortion in memory devices |
| US7821826B2 (en) | 2006-10-30 | 2010-10-26 | Anobit Technologies, Ltd. | Memory cell readout using successive approximation |
| WO2008053472A2 (en) | 2006-10-30 | 2008-05-08 | Anobit Technologies Ltd. | Reading memory cells using multiple thresholds |
| US7924648B2 (en) | 2006-11-28 | 2011-04-12 | Anobit Technologies Ltd. | Memory power and performance management |
| WO2008068747A2 (en) | 2006-12-03 | 2008-06-12 | Anobit Technologies Ltd. | Automatic defect management in memory devices |
| US7900102B2 (en) | 2006-12-17 | 2011-03-01 | Anobit Technologies Ltd. | High-speed programming of memory devices |
| US7593263B2 (en) | 2006-12-17 | 2009-09-22 | Anobit Technologies Ltd. | Memory device with reduced reading latency |
| US8151166B2 (en) | 2007-01-24 | 2012-04-03 | Anobit Technologies Ltd. | Reduction of back pattern dependency effects in memory devices |
| US7751240B2 (en) | 2007-01-24 | 2010-07-06 | Anobit Technologies Ltd. | Memory device with negative thresholds |
| US8369141B2 (en) | 2007-03-12 | 2013-02-05 | Apple Inc. | Adaptive estimation of memory cell read thresholds |
| US8001320B2 (en) | 2007-04-22 | 2011-08-16 | Anobit Technologies Ltd. | Command interface for memory devices |
| US8234545B2 (en) | 2007-05-12 | 2012-07-31 | Apple Inc. | Data storage with incremental redundancy |
| WO2008139441A2 (en) | 2007-05-12 | 2008-11-20 | Anobit Technologies Ltd. | Memory device with internal signal processing unit |
| US7701780B2 (en) * | 2007-05-31 | 2010-04-20 | Micron Technology, Inc. | Non-volatile memory cell healing |
| US7925936B1 (en) | 2007-07-13 | 2011-04-12 | Anobit Technologies Ltd. | Memory device with non-uniform programming levels |
| US8259497B2 (en) | 2007-08-06 | 2012-09-04 | Apple Inc. | Programming schemes for multi-level analog memory cells |
| US8174905B2 (en) | 2007-09-19 | 2012-05-08 | Anobit Technologies Ltd. | Programming orders for reducing distortion in arrays of multi-level analog memory cells |
| US7773413B2 (en) | 2007-10-08 | 2010-08-10 | Anobit Technologies Ltd. | Reliable data storage in analog memory cells in the presence of temperature variations |
| KR101248942B1 (en) * | 2007-10-17 | 2013-03-29 | 삼성전자주식회사 | Non-volatile memory device |
| US8527819B2 (en) | 2007-10-19 | 2013-09-03 | Apple Inc. | Data storage in analog memory cell arrays having erase failures |
| US8000141B1 (en) | 2007-10-19 | 2011-08-16 | Anobit Technologies Ltd. | Compensation for voltage drifts in analog memory cells |
| US8068360B2 (en) | 2007-10-19 | 2011-11-29 | Anobit Technologies Ltd. | Reading analog memory cells using built-in multi-threshold commands |
| US7916543B2 (en) | 2007-10-22 | 2011-03-29 | Micron Technology, Inc. | Memory cell operation |
| KR101509836B1 (en) | 2007-11-13 | 2015-04-06 | 애플 인크. | Optimized selection of memory units in multi-unit memory devices |
| US8225181B2 (en) | 2007-11-30 | 2012-07-17 | Apple Inc. | Efficient re-read operations from memory devices |
| US8209588B2 (en) | 2007-12-12 | 2012-06-26 | Anobit Technologies Ltd. | Efficient interference cancellation in analog memory cell arrays |
| US8456905B2 (en) | 2007-12-16 | 2013-06-04 | Apple Inc. | Efficient data storage in multi-plane memory devices |
| US8339862B2 (en) * | 2007-12-25 | 2012-12-25 | Genusion, Inc. | Nonvolatile semiconductor memory device |
| US8085586B2 (en) | 2007-12-27 | 2011-12-27 | Anobit Technologies Ltd. | Wear level estimation in analog memory cells |
| US8156398B2 (en) | 2008-02-05 | 2012-04-10 | Anobit Technologies Ltd. | Parameter estimation based on error correction code parity check equations |
| US7924587B2 (en) | 2008-02-21 | 2011-04-12 | Anobit Technologies Ltd. | Programming of analog memory cells using a single programming pulse per state transition |
| US7864573B2 (en) | 2008-02-24 | 2011-01-04 | Anobit Technologies Ltd. | Programming analog memory cells for reduced variance after retention |
| US8230300B2 (en) | 2008-03-07 | 2012-07-24 | Apple Inc. | Efficient readout from analog memory cells using data compression |
| US8400858B2 (en) | 2008-03-18 | 2013-03-19 | Apple Inc. | Memory device with reduced sense time readout |
| US8059457B2 (en) | 2008-03-18 | 2011-11-15 | Anobit Technologies Ltd. | Memory device with multiple-accuracy read commands |
| US7924623B2 (en) | 2008-05-27 | 2011-04-12 | Micron Technology, Inc. | Method for memory cell erasure with a programming monitor of reference cells |
| JP5159477B2 (en) * | 2008-07-08 | 2013-03-06 | 株式会社東芝 | Nonvolatile semiconductor memory device and erase verification method thereof |
| US7924613B1 (en) | 2008-08-05 | 2011-04-12 | Anobit Technologies Ltd. | Data storage in analog memory cells with protection against programming interruption |
| US7995388B1 (en) | 2008-08-05 | 2011-08-09 | Anobit Technologies Ltd. | Data storage using modified voltages |
| US8169825B1 (en) | 2008-09-02 | 2012-05-01 | Anobit Technologies Ltd. | Reliable data storage in analog memory cells subjected to long retention periods |
| US8949684B1 (en) | 2008-09-02 | 2015-02-03 | Apple Inc. | Segmented data storage |
| US8000135B1 (en) | 2008-09-14 | 2011-08-16 | Anobit Technologies Ltd. | Estimation of memory cell read thresholds by sampling inside programming level distribution intervals |
| US8482978B1 (en) | 2008-09-14 | 2013-07-09 | Apple Inc. | Estimation of memory cell read thresholds by sampling inside programming level distribution intervals |
| US8239734B1 (en) | 2008-10-15 | 2012-08-07 | Apple Inc. | Efficient data storage in storage device arrays |
| US8261159B1 (en) | 2008-10-30 | 2012-09-04 | Apple, Inc. | Data scrambling schemes for memory devices |
| US8208304B2 (en) | 2008-11-16 | 2012-06-26 | Anobit Technologies Ltd. | Storage at M bits/cell density in N bits/cell analog memory cell devices, M>N |
| US8174857B1 (en) | 2008-12-31 | 2012-05-08 | Anobit Technologies Ltd. | Efficient readout schemes for analog memory cell devices using multiple read threshold sets |
| US8248831B2 (en) | 2008-12-31 | 2012-08-21 | Apple Inc. | Rejuvenation of analog memory cells |
| US8924661B1 (en) | 2009-01-18 | 2014-12-30 | Apple Inc. | Memory system including a controller and processors associated with memory devices |
| US8228701B2 (en) | 2009-03-01 | 2012-07-24 | Apple Inc. | Selective activation of programming schemes in analog memory cell arrays |
| US8259506B1 (en) | 2009-03-25 | 2012-09-04 | Apple Inc. | Database of memory read thresholds |
| US8832354B2 (en) | 2009-03-25 | 2014-09-09 | Apple Inc. | Use of host system resources by memory controller |
| US8238157B1 (en) | 2009-04-12 | 2012-08-07 | Apple Inc. | Selective re-programming of analog memory cells |
| US8479080B1 (en) | 2009-07-12 | 2013-07-02 | Apple Inc. | Adaptive over-provisioning in memory systems |
| US8355287B2 (en) * | 2009-08-25 | 2013-01-15 | Aplus Flash Technology, Inc. | Method and apparatus for operation of a NAND-like dual charge retaining transistor NOR flash memory device |
| US8495465B1 (en) | 2009-10-15 | 2013-07-23 | Apple Inc. | Error correction coding over multiple memory pages |
| US8677054B1 (en) | 2009-12-16 | 2014-03-18 | Apple Inc. | Memory management schemes for non-volatile memory devices |
| US8694814B1 (en) | 2010-01-10 | 2014-04-08 | Apple Inc. | Reuse of host hibernation storage space by memory controller |
| US8677203B1 (en) | 2010-01-11 | 2014-03-18 | Apple Inc. | Redundant data storage schemes for multi-die memory systems |
| KR101662269B1 (en) * | 2010-02-03 | 2016-10-04 | 삼성전자주식회사 | Flash memory device and verify method thereof |
| US8694853B1 (en) | 2010-05-04 | 2014-04-08 | Apple Inc. | Read commands for reading interfering memory cells |
| US8572423B1 (en) | 2010-06-22 | 2013-10-29 | Apple Inc. | Reducing peak current in memory systems |
| US8595591B1 (en) | 2010-07-11 | 2013-11-26 | Apple Inc. | Interference-aware assignment of programming levels in analog memory cells |
| US9104580B1 (en) | 2010-07-27 | 2015-08-11 | Apple Inc. | Cache memory for hybrid disk drives |
| US8645794B1 (en) | 2010-07-31 | 2014-02-04 | Apple Inc. | Data storage in analog memory cells using a non-integer number of bits per cell |
| US8856475B1 (en) | 2010-08-01 | 2014-10-07 | Apple Inc. | Efficient selection of memory blocks for compaction |
| US8694854B1 (en) | 2010-08-17 | 2014-04-08 | Apple Inc. | Read threshold setting based on soft readout statistics |
| US9021181B1 (en) | 2010-09-27 | 2015-04-28 | Apple Inc. | Memory management for unifying memory cell conditions by using maximum time intervals |
| US9728278B2 (en) | 2014-10-24 | 2017-08-08 | Micron Technology, Inc. | Threshold voltage margin analysis |
| US9928126B1 (en) | 2017-06-01 | 2018-03-27 | Apple Inc. | Recovery from cross-temperature read failures by programming neighbor word lines |
| US11556416B2 (en) | 2021-05-05 | 2023-01-17 | Apple Inc. | Controlling memory readout reliability and throughput by adjusting distance between read thresholds |
| US11847342B2 (en) | 2021-07-28 | 2023-12-19 | Apple Inc. | Efficient transfer of hard data and confidence levels in reading a nonvolatile memory |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR950000273B1 (en) * | 1992-02-21 | 1995-01-12 | 삼성전자 주식회사 | Non-volatile semiconductor memory device and optimal write method |
| JP3359404B2 (en) * | 1993-12-27 | 2002-12-24 | 三菱電機株式会社 | Method of erasing stored data in nonvolatile semiconductor memory device |
| KR970005644B1 (en) * | 1994-09-03 | 1997-04-18 | 삼성전자 주식회사 | Multi-block erase and verify device and method of non-volatile semiconductor memory device |
| KR0169412B1 (en) * | 1995-10-16 | 1999-02-01 | 김광호 | Non-volatile semiconductor memory device |
| US6028794A (en) * | 1997-01-17 | 2000-02-22 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device and erasing method of the same |
| JPH10223866A (en) * | 1997-02-03 | 1998-08-21 | Toshiba Corp | Semiconductor storage device |
| JP3592887B2 (en) * | 1997-04-30 | 2004-11-24 | 株式会社東芝 | Nonvolatile semiconductor memory device |
| KR100284916B1 (en) * | 1997-07-29 | 2001-03-15 | 니시무로 타이죠 | Semiconductor memory device and its write control method |
| JP3888808B2 (en) * | 1999-08-16 | 2007-03-07 | 富士通株式会社 | NAND nonvolatile memory |
-
1999
- 1999-08-16 JP JP23007399A patent/JP3888808B2/en not_active Expired - Fee Related
-
2000
- 2000-03-22 TW TW089105280A patent/TW463172B/en not_active IP Right Cessation
- 2000-04-21 KR KR1020000021220A patent/KR100596083B1/en not_active IP Right Cessation
- 2000-05-23 US US09/577,373 patent/US6288944B1/en not_active Expired - Lifetime
- 2000-06-22 EP EP00305287A patent/EP1077450B1/en not_active Expired - Lifetime
- 2000-06-22 DE DE60017838T patent/DE60017838T2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| DE60017838D1 (en) | 2005-03-10 |
| EP1077450B1 (en) | 2005-02-02 |
| JP3888808B2 (en) | 2007-03-07 |
| DE60017838T2 (en) | 2006-01-05 |
| EP1077450A3 (en) | 2003-06-04 |
| US6288944B1 (en) | 2001-09-11 |
| KR100596083B1 (en) | 2006-07-05 |
| KR20010020770A (en) | 2001-03-15 |
| JP2001057088A (en) | 2001-02-27 |
| EP1077450A2 (en) | 2001-02-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TW463172B (en) | NAND type nonvolatile memory | |
| KR101565775B1 (en) | Low noise sense amplifier array and method for nonvolatile memory | |
| TWI316711B (en) | Word line compensation in non-volatile memory erase operations | |
| TW451481B (en) | Nonvolatile semiconductor memory device | |
| JP3373632B2 (en) | Nonvolatile semiconductor memory device | |
| TW483003B (en) | Multi-state nonvolatile semiconductor memory device which is capable of regularly maintaining a margin between threshold voltage distributions | |
| US8705293B2 (en) | Compact sense amplifier for non-volatile memory suitable for quick pass write | |
| US7688635B2 (en) | Current sensing for Flash | |
| US20080062762A1 (en) | NAND architecture memory with voltage sensing | |
| US20060221739A1 (en) | Page buffer circuit of flash memory device with improved read operation function and method of controlling read operation thereof | |
| US10332593B2 (en) | Semiconductor memory device configured to sense memory cell threshold voltages in ascending order | |
| JP4679528B2 (en) | Semiconductor memory device with refresh trigger | |
| US8630120B2 (en) | Compact sense amplifier for non-volatile memory | |
| JP2005293813A (en) | Nand flash memory device and method of reading the same | |
| JP3906545B2 (en) | Nonvolatile semiconductor memory device | |
| CN111199757B (en) | Non-volatile memory device and peripheral circuit having data verification and rewrite functions | |
| JP2010198720A (en) | Nonvolatile memory device and operation method therefor | |
| US7872918B2 (en) | Nonvolatile memory device and program or erase method using the same | |
| JP3315472B2 (en) | Nonvolatile semiconductor memory device | |
| TWI243380B (en) | Ferroelectric resistor non-volatile memory array | |
| KR0159452B1 (en) | A non-volatile memory circuit | |
| KR910019062A (en) | Nonvolatile Semiconductor Memory with EEPROM Cells, Dummy Cells, and Sense Circuits Increase Stability and Enable 1-Bit Operation | |
| KR100673704B1 (en) | Page buffer of flash memory device | |
| KR102194907B1 (en) | Semiconductor storage device and readout method | |
| US6535427B1 (en) | Nonvolatile semiconductor memory device with initialization circuit and control method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GD4A | Issue of patent certificate for granted invention patent | ||
| MM4A | Annulment or lapse of patent due to non-payment of fees |