TW462109B - Method of forming shallow trench isolation having smooth profile - Google Patents

Abstract

The present invention discloses a method of forming electronic device isolation having smooth profile, mainly by covering a sacrificial layer (such as a polysilicon layer or amorphous silicon layer) on a substrate with a groove pattern defined uniformly, so as to form a smooth profile to replace the original trench pattern with vertical sidewall. Then use anisotropic etch to transfer this profile to the substrate, thereby a trench having a smooth edge is obtained. According to the method of the present invention, defect issues due to sharp edge angle formed at the edge of the trench groove in the traditional process is solved.

Description

462109 五、發明說明（1) 【發明領域】 本發明是有關半導體元件的隔離製程，且特別是有關 於一種形成具有平滑輪廓之電性元件隔離物之方法。 【發明背景】 近年來’隨著半導體積體電路製造技術的發展，晶月 中所含元件的數量不斷增加，元什的尺寸也因積集度的提 昇而不斷地縮小’生產線上使用的線路寬度已進入深次微 米甚或更細微尺寸的範圍。而無論元件尺寸如何縮小化， 在晶片中各個元件之間仍必須有適當地絕緣或隔離，方可 得到良好的元件性質。這方面的技術一般稱為元件隔離技 術（device isolation technology)，其主要目的係在各 元件之間形成隔離物’並且在確保良好隔離效果的情況 下’儘量縮小隔離物的區域，以空出更多的晶片面積來容 納更多的元件。 在各種元件隔離技術中，局部硖氧化方法（L0C0S)和 淺溝槽隔離區（shallow trench isolation ;STI)製程是 最常被採用的兩種技術，尤其後者具有隔離區域小和完成 後仍保持基底平坦性等優點，更是近來頗受重視的半導體 製造技術。傳統上’係先利用化學氣相沈積（CVD)程序， 形成一介電層以填入基底的溝槽中，之後再以化學性機械 研磨程序（CMP)去除表面多餘的介電層，以完成溝槽隔離 區製程。 以下將配合第卜6圖，就習知一種製作淺溝渠隔離的462109 V. Description of the Invention (1) [Field of the Invention] The present invention relates to an isolation process for a semiconductor device, and more particularly to a method for forming an electrical device spacer having a smooth outline. [Background of the Invention] In recent years, with the development of semiconductor integrated circuit manufacturing technology, the number of components contained in the crystal moon has continued to increase, and the size of Yuan Shi has been continuously reduced due to the increase in the degree of accumulation. The width has entered the range of deep sub-microns and even finer sizes. Regardless of how the component size is reduced, each component in the wafer must still be properly insulated or isolated to obtain good component properties. This technology is commonly referred to as device isolation technology, and its main purpose is to form a spacer between components and to ensure a good isolation effect, to minimize the area of the spacer to free up more More chip area to accommodate more components. Among the various element isolation technologies, the local hafnium oxidation method (L0C0S) and shallow trench isolation (STI) process are the two most commonly used technologies, especially the latter has a small isolation area and maintains the substrate after completion. Flatness and other advantages are semiconductor manufacturing technologies that have received much attention recently. Traditionally, a chemical vapor deposition (CVD) process is used to form a dielectric layer to fill the trenches in the substrate, and then a chemical mechanical polishing process (CMP) is used to remove the excess dielectric layer on the surface to complete the process. Trench isolation process. The following will cooperate with Figure 6 to learn a method for making shallow trench isolation.

第4頁 462109 五、發明說明（2) ------ 方法作一說明，以討論現有製程所遭遇的問題。請參照 1圖’首先在一半導體基底10表面上’依序形成一塾氧化 層1 2和氮化矽層1 4。其中氮化矽層1 2將在後續定義溝槽 時，作為硬式罩幕。然後，在氮化矽層14上形成一光^ 案1 6，露出欲形成元件隔離區的部分。請參照第2圖， 用光阻圖案1 6當作罩幕，依序餘刻氮化石夕層1 4、塾氣 12、和半導體基底1〇，以形成溝;||1了。 曰 請參照第3圖，去除光阻圖案丨6後，以化學 法（CVD)形成一氡化層18覆蓋在氮化矽層u上並完全 滿溝槽17。請參照第4圖’施行一化學性機械研磨=' 序，去除氧化層18高出氮化矽層14表面的部分以形成一平 坦的表面構造，並藉此使留在溝槽内的部分形 離區18A。接著，如第5圖所示，將氮化矽層14盘墊氧化 12去除，以定義溝槽隔離區18A。最後，依序施行一犧牲 氧化程序（sacrificial oxidati〇n pr〇cess)與一去除程 序以完成如第6圖所示之溝槽隔離區οb。 然而，根據上述習知的溝槽隔離方法，由於隔離氧化 物與犧牲氧化層的蝕刻性質相近，因此當以蝕刻液浸泡 (dip)去除犧牲氧化層時，不可避免地也會侵蝕到溝槽隔 離區18B’因此隔離氧化物的邊緣會形成如第6圖所示的輪 廓” A"。亦即，元件隔離區在邊緣部分的輪廓是尖銳的， 因此當形成閘氧化層時，在此邊界部分會變得比較薄，造 成電場過度集中…卜，亦會累積較大的應力，導致漏電 流的產生或影響主動區元件的特性。Page 4 462109 V. Description of the invention (2) ------ A description of the method to discuss the problems encountered in the existing process. Please refer to FIG. 1 'firstly forming a hafnium oxide layer 12 and a silicon nitride layer 14 on a surface of a semiconductor substrate 10' in this order. The silicon nitride layer 12 will be used as a hard mask in the subsequent definition of the trench. Then, a light pattern 16 is formed on the silicon nitride layer 14 to expose a portion where an element isolation region is to be formed. Referring to FIG. 2, a photoresist pattern 16 is used as a mask, and a nitride layer 14, a hafnium gas 12, and a semiconductor substrate 10 are sequentially etched to form a trench; || 1. That is, referring to FIG. 3, after removing the photoresist pattern, a halide layer 18 is formed by chemical method (CVD) to cover the silicon nitride layer u, and the trench 17 is completely filled. Please refer to Fig. 4 'Perform a chemical mechanical polishing =' sequence, remove the portion of the oxide layer 18 above the surface of the silicon nitride layer 14 to form a flat surface structure, and thereby shape the portion remaining in the trench. Leaving area 18A. Next, as shown in FIG. 5, the silicon nitride layer 14 and the pad pad 12 are oxidized 12 to define a trench isolation region 18A. Finally, a sacrificial oxidation procedure and a removal procedure are sequentially performed to complete the trench isolation region οb as shown in FIG. 6. However, according to the above-mentioned conventional trench isolation method, since the isolation oxide and the sacrificial oxide layer have similar etching properties, when the sacrificial oxide layer is removed by dipping with an etching solution, the trench isolation is inevitably eroded. The region 18B 'thus forms the contour of the isolation oxide as shown in FIG. 6 "A ". That is, the contour of the element isolation region at the edge portion is sharp, so when the gate oxide layer is formed, at this boundary portion It will become thinner, resulting in excessive concentration of the electric field, etc., and it will also accumulate large stresses, leading to the generation of leakage current or affecting the characteristics of components in the active area.

462109 五、發明說明（3) 因此，為了使淺溝槽隔離技術的應用更臻於完善，實 有必要針對上述問題謀求改善之道。 【發明概述】 ' 有鑑於此’本發明的主要目的就是提供一種溝槽隔離 區的改良製程’其可形成具有平滑輪廓之溝槽隔離物，以 降低溝槽邊緣產生缺陷的機會。： 為達上述目的’本發明提供一種形成溝槽隔離物之方 法，主要係將一犧牲層’例如複.晶石夕層或非晶石夕層，均覆 性地（conformally)沈積在定義有溝槽圖案的基底上。如 此一來’犧牲層在溝槽圖案的邊界處會形成平滑的凹入， 因此只要再利用定向性蝕刻（direct ional etch)將犧牲層 的輪廓沿著溝槽圖案轉移到基底中，便可得到一具有平滑 邊緣的溝槽。 4 根據本發明一較佳實施例，其主要步驟包括：（a )在 一半導體基底上依序形成一墊氧化層'及一罩幕層；（b)利 用一光阻圖案當作罩幕，依序触刻上述罩幕層、塾氧化 層’以形成一開口露出預定形成溝槽之區域；（c)沈積一 均覆性的犧牲層於罩幕層上與開口中；（d)定向性地蝕刻 犧牲層與半導體基底，以將犧牲層的輪廓沿上述開口轉移 到基底中’形成一具有平滑邊緣之溝槽；（e)將一絕緣層 填入上述溝槽；以及（f)將絕緣層平坦化。 根據本發明另一較佳實施例，其主要步驟包括：（a) 在一半導體基底上依序形成一墊氧化層及一罩幕層；（b)462109 V. Description of the invention (3) Therefore, in order to make the application of the shallow trench isolation technology more perfect, it is necessary to seek ways to improve the above problems. [Summary of the Invention] 'In view of this,' the main purpose of the present invention is to provide an improved process for trench isolation regions', which can form trench isolations with smooth contours to reduce the chance of defects at the edges of the trench. : In order to achieve the above-mentioned object, the present invention provides a method for forming a trench spacer, which is mainly a sacrificial layer such as a polycrystalline crystalline layer or an amorphous crystalline layer, which is uniformly deposited on a surface defined as Groove pattern on the base. In this way, the sacrificial layer will form a smooth recess at the boundary of the trench pattern, so as long as the contour of the sacrificial layer is transferred to the substrate along the trench pattern by direct ional etch, it can be obtained A groove with smooth edges. 4 According to a preferred embodiment of the present invention, the main steps include: (a) sequentially forming a pad oxide layer and a mask layer on a semiconductor substrate; (b) using a photoresist pattern as a mask, Sequentially engraving the mask layer and the plutonium oxide layer to form an opening to expose the area where the trench is to be formed; (c) deposit a uniform sacrificial layer on the mask layer and in the opening; (d) orientation Etch the sacrificial layer and the semiconductor substrate to transfer the contour of the sacrificial layer into the substrate along the above openings to form a trench with smooth edges; (e) fill an insulating layer into the trench; and (f) insulate the trench The layer is flattened. According to another preferred embodiment of the present invention, the main steps include: (a) sequentially forming a pad oxide layer and a mask layer on a semiconductor substrate; (b)

五、發明說明（4) 利用一光阻圖案當作罩幕，依序蝕刻上述罩幕層、墊氧化 層、及半導體基底至一既定深度，形成一溝槽圖案；（C) 沈積一均覆性的犧牲層於罩幕層上與基底中；（d )定向性 地蝕刻犧牲層並沿著溝槽圖案繼續蝕刻基底，以將犧牲層 的輪廓轉移到基底中，形成一具有平滑邊緣之溝槽；（e) 將一絕緣層填入上述溝槽；以及（f )將絕緣層平坦化。 為讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳 細說明如下： ^ 【圖式之簡單說明】 第1〜6圖為一系列剖面圖，用以說明習知製作溝槽隔 離物的流程。 第7〜1 3圖為一系列剖面圖，或以說明本發明第一較佳 實施例製作溝槽隔離物的流裎。 第14〜18圖為一系列剖面圖，用以說明本發明第二較 佳實施例製作溝槽隔離物的流程。 【符號說明】 10、100~半導體基底； 1 2、1 0 2〜墊氧化層； 14、104〜罩幕層； 1 6、1 0 6 ~光阻層； 1 7、1 0 9、11 3 〜溝槽 1 8、11 0、1 1 4〜絕緣層；V. Description of the invention (4) Use a photoresist pattern as a mask, and sequentially etch the mask layer, pad oxide layer, and semiconductor substrate to a predetermined depth to form a trench pattern; (C) deposit a uniform coating A sacrificial layer is formed on the mask layer and the substrate; (d) the sacrificial layer is etched directionally and the substrate is continuously etched along the trench pattern to transfer the contour of the sacrificial layer into the substrate to form a groove with smooth edges A trench; (e) filling an insulating layer into the trench; and (f) planarizing the insulating layer. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the following describes the preferred embodiments in detail with the accompanying drawings as follows: ^ [Simplified description of the drawings] Figures 1 to 6 are a series of cross-sectional views to illustrate the conventional process for making trench spacers. Figures 7 to 13 are a series of cross-sectional views, or to illustrate the flow of making trench spacers in the first preferred embodiment of the present invention. Figures 14 to 18 are a series of cross-sectional views for explaining the process of making trench spacers in the second preferred embodiment of the present invention. [Symbol description] 10, 100 ~ semiconductor substrate; 1, 2, 10 2 ~ pad oxide layer; 14, 104 ~ mask layer; 1, 6, 10 ~ photoresist layer; 1, 7, 10, 11 3 ~ Trench 1 8, 11 0, 1 1 4 ~ Insulation layer;

第7頁 4 6 21 0 9 五、發明說明（5) 107、 111〜溝槽圖案； 108、 112〜犧牲層。 【實施例】 請參照第7圖至第13圖，其說明本發明—較佳實施例 製作溝槽隔離區的流程。首先請參照第.7圖，在—半導體 基底，像是矽基底1〇〇的表面上，:覆蓋一墊氧化層（pad oxide)102，一罩幕層1〇4。例如，先以化學氣相沈積程序 (CVD)或熱氧化成長程序（therraai 〇xidati〇n)形成一厚度 介於50~ 20 0人的墊氧化層1〇2，然後在墊氧化層表面上， 以CVD法沈積一厚度介於5〇〇〜2〇〇〇 a的氮化矽層1〇4。墊氧 化層1 0 2與氮化矽層1 〇 4的功用與習知技術相同：墊氧化層 102乃是用以消除氮化矽層1〇4與基底1〇〇之間的應力，而 氣化砂層1 04是用來作為蝕刻淺溝渠時的罩幕，另外也可 作為化學機械研磨（CMP)的終止層（st〇p Uyer) ^ 同樣參照第7圖’塗佈一光阻層1 ό.6於氮化矽層1 04 上’並以微影成像程序定義出—溝槽圖案1〇7。接著，以 光阻層106當作罩幕，利用反應性離子蝕刻法（RIE)，將溝 槽圖案轉移至氮化矽層104、墊氧化層1〇2，露出預定形成 溝槽的區域，如第8圖所示。 請參照第9圖，以適當方式將光阻層1 〇 6去除後，在基 底上沈積一層均覆性（con forma 1)的犧牲層108，覆蓋在H 化妙層104與矽基底1〇〇露出的表面上，如圖中所示，犧牲 層108在氮化矽層1〇4與溝槽圖案1〇7的邊界處會形成平滑Page 7 4 6 21 0 9 V. Description of the invention (5) 107, 111 ~ groove pattern; 108, 112 ~ sacrificial layer. [Embodiment] Please refer to FIG. 7 to FIG. 13, which illustrate the process of fabricating a trench isolation region according to a preferred embodiment of the present invention. First, please refer to Fig. 7. On the surface of a semiconductor substrate, such as a silicon substrate 100, a pad oxide layer 102 and a cover layer 104 are covered. For example, a chemical vapor deposition process (CVD) or a thermal oxidation growth process (therraai 〇xidati〇n) is first used to form a pad oxide layer 10 with a thickness of 50 to 200 people, and then on the surface of the pad oxide layer, A CVD method is used to deposit a silicon nitride layer 104 having a thickness of 500-2000a. The function of the pad oxide layer 102 and the silicon nitride layer 104 is the same as the conventional technology: the pad oxide layer 102 is used to eliminate the stress between the silicon nitride layer 104 and the substrate 100, and The sand layer 104 is used as a mask for etching shallow trenches, and can also be used as a stop layer (stoop Uyer) of chemical mechanical polishing (CMP) ^ Also refer to FIG. 7 'coating a photoresist layer 1 ό .6 on the silicon nitride layer 1 04 'and defined by the lithography imaging procedure-trench pattern 107. Next, using the photoresist layer 106 as a mask, the trench pattern is transferred to the silicon nitride layer 104 and the pad oxide layer 102 by using reactive ion etching (RIE) to expose the area where the trench is to be formed, such as Figure 8 shows. Please refer to FIG. 9. After the photoresist layer 10 is removed in an appropriate manner, a con forma 1 sacrificial layer 108 is deposited on the substrate, covering the H layer 104 and the silicon substrate 100. On the exposed surface, as shown in the figure, the sacrificial layer 108 is smooth at the boundary between the silicon nitride layer 104 and the trench pattern 107.

462109 五、發明說明（6) 的凹入。因此，在後續的步驟中，本發明即是利用此平滑 的輪廓代替原本具有垂直側壁的溝槽圖案，將之轉移 到基底中以形成溝槽。根據本發明，犧牲層丨〇 8的材質以 半導體材質較佳’例如複晶矽或非晶矽。犧牲層丨〇8的厚 度並無特別限定，可視開口 1 07的大小與所欲形成的溝槽 輪廓、縱寬比（aspect ratio)等作適當調整。 請參照第1 0圖’利用氮化層1:〇 4作為蝕刻終止層/蝕刻 罩幕’以定向性的钱刻方式（directional etch)，例如反 應性離子蝕刻法（R IE) ’選擇性地蝕刻犧牲層丨〇 8 '半導體 基底100，以形成溝槽109。如前文中所述，由於在银刻的 過程中’犧牲層1 08的輪廓會沿開口 1〇7轉移到基底10〇 中，因此所形成的溝槽邊緣具有平滑的輪廓，如第丨〇圖中 "B"所示。溝槽109之深度一般可介於35〇〇人和5〇〇〇Α之 間。 請參照第11圖’沈積一絕緣層11 〇，例如氧化矽，於. 半導體基底表面上’並填滿上述之溝‘槽丨09。此絕緣填充 物11 0可利用此技藝人士所熟知的方法來製作，這些方法 包括：以各種化學氣相沈積（CVD)程序所沈積，之氧化層， 例如是常壓化學氣相沈積（APCVD)、次常壓化學氣相沈積 (SACVD)、低壓化學氣相沈積（LPCVD)、或高密度電漿化學 氣相沈積（HDPCVD)程序等；或是由旋轉塗覆玻璃（s〇G)技 術所形成者。此外，在沈積絕緣層11 〇之前，通常可藉由 熱氧化法在溝槽1 0 9的底部與側壁形成一層厚度約1 〇 〇〜3 0 0 Α的襯墊氧化層（1 ining 〇xide)來確保si/si02的界面品462109 V. Indentation of invention description (6). Therefore, in the subsequent steps, the present invention uses this smooth contour to replace the groove pattern with vertical sidewalls originally, and transfers it into the substrate to form a groove. According to the present invention, the material of the sacrificial layer 8 is preferably a semiconductor material, such as polycrystalline silicon or amorphous silicon. The thickness of the sacrificial layer 08 is not particularly limited, and the size of the opening 107 and the desired contour of the trench, the aspect ratio, etc. may be adjusted as appropriate. Please refer to Fig. 10 'Using the nitride layer 1: 04 as an etch stop layer / etching mask' in a directional etch, such as reactive ion etching (R IE) 'Selectively The sacrificial layer 100 is etched to form a trench 109. As described in the foregoing, during the silver engraving process, since the outline of the 'sacrifice layer 108' is transferred into the substrate 100 along the opening 107, the edge of the groove formed has a smooth outline, as shown in FIG. Medium " B ". The depth of the grooves 109 may generally be between 350,000 and 5000A. Please refer to FIG. 11 'for depositing an insulating layer 110, such as silicon oxide, on the surface of the semiconductor substrate' and filling the above-mentioned trench 'slot 09'. The insulating filler 110 can be produced by methods well known to those skilled in the art, including: deposition by various chemical vapor deposition (CVD) procedures, and an oxide layer, such as atmospheric pressure chemical vapor deposition (APCVD) , Sub-atmospheric pressure chemical vapor deposition (SACVD), low pressure chemical vapor deposition (LPCVD), or high-density plasma chemical vapor deposition (HDPCVD) procedures, etc .; or by spin-on-glass (sog) technology Former. In addition, before the deposition of the insulating layer 110, a pad oxidation layer (1 ining 〇xide) having a thickness of about 100 to 3 0 A can be generally formed on the bottom and sidewalls of the trench 10 by thermal oxidation. To ensure the interface product of si / si02

第9頁 4621 π 9 五、發明說明α) -- 質。 請參照第12圖，接著以回蝕刻或化學機械研磨（CMP) 程序，去除絕緣層11 0高出氤化矽層1 0 4表面的部分，以形 成一平坦的表面構造，而使留在淺溝槽109内的部分形成V 一元件隔離區1 1 Ο A。在進行絕緣層丨丨〇的平坦化時 ^底 上的氮化矽層1 〇 4即可作為適當的研磨（蝕刻）終止層。 之後，以適當蝕刻方法依序幸除氮化矽層丨〇 4和墊氧 化層1 0 2，便完成本發明之溝槽隔離製程，得到如第1 3圖 所示的構造。很明顯地’由於溝隔離區丨丨〇A的邊緣為平 滑的輪廓’因此當利用蝕刻液浸泡去除犧牲氧化層時，不 會導致尖銳的凹陷’因此降低發生缺陷的可能性，確保了 元件隔離的品質。 接下來’請參照第1 4圖至第1 8圖，其顯示本發明之第 二較佳實施例，為方便起見，其中與第一實施例具有相同 意義之結構將沿用先前之標號。首先請參照第1 4圖，其對 應第一較佳實施例中第7圖之場合。此時，在半導體基底 100上已形成有墊氧化層102、罩幕層104及光阻層106。利 用光阻圖案106為罩幕，定向性地依序餘刻罩幕層1〇4、塾 氧化層102 ’並餘刻半導體基底1〇〇至一既定深度，以將溝 槽圖案111轉移到基底中。 請參照第1 5圖，以適當方式將光阻層1 0 6去除後，在 基底上沈積一層均覆性（conformal)的犧牲層112，覆蓋在 氮化矽層104與基底中的溝槽圖案111，如圖中所示，犧牲 層112在溝槽圖案1〇7的邊界處會形成平滑的表面輪廓，因Page 9 4621 π 9 V. Description of the invention α)-Quality. Please refer to FIG. 12, and then use an etch-back or chemical mechanical polishing (CMP) process to remove the portion of the insulating layer 110 that is higher than the surface of the siliconized silicon layer 104 to form a flat surface structure and leave it shallow. A portion within the trench 109 forms a V-element isolation region 1 1 0 A. When planarizing the insulating layer, the silicon nitride layer 104 on the bottom can be used as an appropriate polishing (etching) stop layer. After that, the silicon nitride layer 104 and the pad oxidation layer 102 are sequentially removed by an appropriate etching method, and the trench isolation process of the present invention is completed, and the structure shown in FIG. 13 is obtained. Obviously, 'the edge of the trench isolation area 丨 〇A has a smooth outline', so when the sacrificial oxide layer is immersed and removed by the etching solution, no sharp depression will be caused. Quality. Next, please refer to FIG. 14 to FIG. 18, which show a second preferred embodiment of the present invention. For convenience, structures having the same meaning as the first embodiment will use the previous reference numerals. First, please refer to FIG. 14 which corresponds to the case of FIG. 7 in the first preferred embodiment. At this time, a pad oxide layer 102, a mask layer 104, and a photoresist layer 106 have been formed on the semiconductor substrate 100. The photoresist pattern 106 is used as a mask, and the mask layer 104 and the hafnium oxide layer 102 ′ are etched sequentially in order and the semiconductor substrate 100 to a predetermined depth is etched in order to transfer the trench pattern 111 to the substrate. in. Referring to FIG. 15, after the photoresist layer 106 is removed in an appropriate manner, a conformal sacrificial layer 112 is deposited on the substrate to cover the silicon nitride layer 104 and the trench pattern in the substrate. 111, as shown in the figure, the sacrificial layer 112 forms a smooth surface contour at the boundary of the trench pattern 107, because

第10頁 4 6 2 1 0 9 五、發明說明（8) 此在後續的步驟中，即是利用此平滑的輪廓轉移到溝槽， 以代替原本垂直的側壁。根據本發明，犧牲層11 2的材質 以半導體材質較佳，例如複晶石夕或非晶石夕6 請參照第1 6圖，利用氮化層1 0 4作為蝕刻終止層/蝕刻 罩幕’以定向性蝕刻法蝕刻犧牲層112與半導體基底， 以形成溝槽113。如圖中所示’由於在蝕刻的過程中，犧 牲層11 2的輪廓會沿溝槽圖案1 11轉移到基底中，因此所形 成的溝槽邊緣亦具有平滑的輪廊’可避免溝槽隔離區邊緣 發生缺陷的情形。 請參照第1 7圖，形成具有平滑輪廓的溝槽11 3之後， 接下來’可按照前述之化學氣相沈積或旋轉塗覆技術，將 溝槽11 3以一絕緣層11 4填滿，然後再以回蝕刻或是化學機 械研磨法（CMP) ’將多餘的絕緣層‘余除，使絕緣層僅留在 溝槽中，達到隔離的效果。之後，將基底表面上的氮化石夕 層104與墊氧化層1〇2去除，便完成溝槽隔離區114A的製 作’如第18圖所示。 · 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明’任何熟習此技藝者，在不脫離本發明之精神 和範圍内’當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。Page 10 4 6 2 1 0 9 V. Description of the invention (8) In the subsequent steps, this smooth contour is used to transfer to the groove instead of the vertical wall. According to the present invention, the material of the sacrificial layer 11 2 is preferably a semiconductor material, such as polycrystalline or amorphous stone 6 Please refer to FIG. 16, using the nitride layer 1 0 4 as an etching stop layer / etching mask ' The sacrificial layer 112 and the semiconductor substrate are etched by a directional etching method to form a trench 113. As shown in the figure, 'during the etching process, the outline of the sacrificial layer 11 2 will be transferred into the substrate along the groove pattern 1 11, so the groove edge formed also has a smooth contour' to avoid trench isolation. A defect at the edge of a zone. Referring to FIG. 17, after the trenches 11 3 with smooth contours are formed, the trenches 13 may be filled with an insulating layer 11 4 according to the aforementioned chemical vapor deposition or spin coating technology, and then Then, etch back or chemical mechanical polishing (CMP) is used to 'remove the excess insulation layer', so that the insulation layer is left in the trench only to achieve the effect of isolation. After that, the nitride nitride layer 104 and the pad oxide layer 102 on the surface of the substrate are removed, and the fabrication of the trench isolation region 114A is completed as shown in FIG. 18. · Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. 'Any person skilled in the art can make various changes and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application.

第11頁Page 11

Claims (1)

462109462109 1. 很项战苒價隔離物才士、I , t W 主追麻—之方法’包括下列步驟： U)在一 +導體基底上你1. Very competitive price isolation talents, I, t W Master chase hemp method-including the following steps: U) on a + conductor substrate you 層 -上依序形成一墊氡化層及—革幕 (b)利用一光阻圖案當作 你庄私& # s甘 該墊氧化層m ”罩幕，依序刻该罩幕層、 氧、層以形成一開口露出預定形成溝槽之區域； 中.c ,尤冑i句覆性的犧牲層於該單幕層上與該間—口 r (d)疋向性地蝕刻該犧牲層與該半導體基底，以 犧牲層的輪廓沿上述開口轉移到該基底中，形 ^ 滑邊緣之溝槽，· 〃有平 (e)將一絕緣層填入該溝槽；以及 (f )將該絕緣層平坦化。 2.如申請專利範圍第1項所述·之方法，其中該罩 為氮化矽層。 層 3.如申請專利範圍第1項所述之方法，其中該犧牲層 為半導體材質。 4_如申請專利範圍第3項所述之方法，其中該犧牲層 為複晶矽層。 5. 如申請專利範圍第3項所述之方法’其中該犧牲層 為非晶矽層。 6. 如申請專利範圍第1項所述之方法’其中步驟（e)更 包括：以熱氧化法在該溝槽底部與側壁形成一襯墊氧化 層。 7. 如申請專利範圍第1項所述之方法’其中該絕緣層Layer-on top of each other to form a matting layer and leather screen (b) using a photoresist pattern as your Zhuang private &# sgan that pad oxide layer m "mask, sequentially engraving the mask layer, Oxygen, layer to form an opening to expose the area where the trench is intended to be formed; middle, c, especially the overlying sacrificial layer on the single-screen layer and the inter-port r (d) the etching sacrificially Layer and the semiconductor substrate, transferred into the substrate along the above-mentioned opening with the contour of the sacrificial layer, forming a groove with a sliding edge, and (e) filling an insulating layer into the groove; and (f) placing The insulating layer is planarized. 2. The method according to item 1 in the scope of the patent application, wherein the cover is a silicon nitride layer. Layer 3. The method according to item 1 in the scope of patent application, wherein the sacrificial layer is Semiconductor material. 4_ The method described in item 3 of the patent application, wherein the sacrificial layer is a polycrystalline silicon layer. 5. The method described in item 3 of the patent application, wherein the sacrificial layer is an amorphous silicon layer. 6. The method according to item 1 of the scope of patent application, wherein step (e) further includes: thermally oxidizing the bottom of the trench. Forming a sidewall pad oxide layer. 7. The method as recited in item 1 range patent 'wherein the insulating layer 4 6 210 9 申請專利範圍 為氧化矽層3 ▲ 8.如申請專利範圍第i項所述之方法其中步驟係 二忒罩幕層為蝕刻終止層，利用蝕刻法將該絕緣層平坦 化。 、 ' 9.如申請專利範圍第1項所述之方法，其中步驟（f )係 罩幕層為研磨終止層，利用化學機 法將該絕 層平坦化。 ， 〜 I 0 ·如申請專利範圍第J項所述之方法，其中在步驟 之後，更包括將該罩幕層去^。 II ’種开〉成溝槽隔離物之友法，包括下列步驟： 層.（a)在一半導體基底上依序形成一墊氧化層及一罩幕 該勢一光阻圖案當作罩幕·.，，依序蝕刻該罩幕層、 ^案· 、及該半導體基底至一既定深度，形成一溝槽 (c)沈積一均覆性的犧牲層於該拿幕層上與該基底 刻訪t疋向性地蝕刻該犧牲層並沿著該溝槽圖案繼續蝕 mZr ，以將該犧牲層的輪廓轉移到該基底中，形成一 具有平滑邊緣之溝槽； 取 (e)將一絕緣層填入該溝槽；以及 (f )將該絕緣層平坦化。 lj ·如申請專利範圍第丨丨項所述之方法，其中該罩 禮馮鼠化石夕層。4 6 210 9 The scope of the patent application is a silicon oxide layer 3 ▲ 8. The method described in item i of the scope of patent application wherein the steps are that the second mask layer is an etching stop layer, and the insulating layer is planarized by an etching method. 9. The method according to item 1 of the scope of patent application, wherein step (f) is that the mask layer is a polishing stop layer, and the insulation layer is planarized by a chemical mechanical method. ~ I 0 · The method as described in item J of the scope of patent application, wherein after the step, it further comprises removing the mask layer ^. II "Special Opening" Method of Forming a Trench Isolator, including the following steps: Layer. (A) A pad of oxide and a mask are sequentially formed on a semiconductor substrate. A photoresist pattern is used as the mask. ., Sequentially etching the mask layer, the case, and the semiconductor substrate to a predetermined depth to form a trench (c) depositing a uniform sacrificial layer on the mask layer and engraving the substrate t etch the sacrificial layer directionally and continue to etch mZr along the trench pattern to transfer the outline of the sacrificial layer into the substrate to form a trench with smooth edges; take (e) an insulating layer Filling the trench; and (f) planarizing the insulating layer. lj The method according to item 丨 丨 in the scope of patent application, wherein the mask is a layer of fossil rat fossils. 六、申請專利範圍 13.如申請專利範圍第π項所述之方法’其中該犧牲 層為半導體材質。 1 4.如申請專利範圍第丨3項所述之方法’其中該犧牲 層為複晶碎層。 ' 1 5·如申請專利範圍第丨3項所述之方法，其中該犧牲 層為非晶碎層。 1 6.如申請專利範圍第11項所；述之方法，其中步驟（e) 更包括：以熱氧化法在該溝槽底部與側壁形成一襯墊氧化 層。 ·. 1 7·如申請專利範圍第11項所述之方法，其中該絕緣 層為氧化>5夕層。 1 8 ‘如申請專利範圍第i丨項所述之方法，其中步驟（f) 係以該罩幕層為蝕刻終止層，利用蝕刻法將該絕緣層平坦 化。 1 9.如申請專利範圍第11項所述之方， 、， 係以該罩幕層為研磨終止層，利用化*學機械研磨法將該絕 緣層平坦化。 9A ^ ^ .+，之_方法’其中在步驟 20.如申請專利範圍第U項所也之 (f)之後’更包括將該罩幕層去除。6. Scope of patent application 13. The method according to item π of the scope of patent application ', wherein the sacrificial layer is made of semiconductor material. 1 4. The method according to item 丨 3 of the scope of the patent application, wherein the sacrificial layer is a multi-crystal crushed layer. '15. The method according to item 3 of the scope of the patent application, wherein the sacrificial layer is an amorphous broken layer. 16. The method as described in item 11 of the scope of patent application, wherein the step (e) further comprises: forming a pad oxide layer on the bottom of the trench and the sidewall by a thermal oxidation method. · 7 · The method according to item 11 of the scope of patent application, wherein the insulating layer is an oxide layer. 18 ‘The method as described in item i 丨 of the scope of patent application, wherein step (f) is to use the mask layer as an etching stop layer, and planarize the insulating layer by an etching method. 19. According to the method described in item 11 of the scope of the patent application, the mask layer is used as a polishing termination layer, and the insulating layer is flattened by chemical mechanical polishing method. 9A ^ ^. +, The _method ′, wherein after step 20. (f) as described in item U of the scope of patent application, the method further includes removing the mask layer. 第14奠14th