TW461993B - Control device and method for improving data access reliability - Google Patents

Abstract

The present invention relates to a data access control device and the method thereof, and especially to a control device that has abilities in automatic access error detection and error data correction so as to reduce the use of the memory storage device. When storing data in a memory storage device, the present invention uses a data processor to alternately divide the data into several data fields based on the bit. Affected by the effects of a control logic circuit and an encoder, a relative error correcting code (ECC) is appended to each data field. Data are stored into the memory storage device only after the data are alternately divided into several data fields and each data field is appended with an error correcting code. To read the data from the memory storage device, the error correcting codes will be decoded by following the same circuit. Through an error correction logic circuit, it identifies whether these error correcting codes are special codes so as to point out whether any incidental error occurs in these relative data fields. If so, the error correcting codes will be corrected immediately before being output. Thus, not only the data access reliability can be improved but also the data access time can be shortened. Besides, the actual data storage volume of the memory storage device can also be increased.

Description

46 19 93 五、發明説明（ A7 B746 19 93 V. Description of the invention (A7 B7

I 標 淖 局 ηI mark 淖 round η

消 A 交錯=明係有_"'種資料棘之裝置與方法 ，利用 次二二i將欲儲存之資料分成複數個資料攔，每— I==ΐ 一相對之錯誤更正碼，經由檢核錯誤更 ”、、I時疋否有異即可辨識資料是否有所錯誤，並 “省次%I正产如此不僅可提高資料存取之可靠度，亦可 存或儲存裝置層次複雜，f料可能在儲 取_祕!Ϊ時起發性地錯誤，如此tf料欲被讀 A鼠舌 S料之錯誤訊息，影響資料之讀取正確性頗 I、^，更甚者將影f到#料之正常運算，使整個資料 成為無用之物，讓使用者十分困擾。 為預防上述錯誤賴之發生，相關#相發一種錯 側與更正碼或錯誤更正碼（ERR0R—C0RRECTING ，ECC)來對此現象作改善，而習用技術主要係利用 資料的位元組(W_為單位，在每單位後面附加 夕重檢查位元之錯誤更正碼（同位元，p服ιτγΒΐ丁）， 同位元將連同資料儲存於記憶儲存裝置中 取時，則同位元將連同資料一起被讀取，且; 與讀出#料之新檢查位元相互崎，若檢查位元相同則 表示資料無誤；相反地，當檢查位元並不相同時，則產 生一特別“併發症狀，，（SYNDROM)模式，可用來辨熾錯嗜 的位元及相對的錯誤資料，並藉此而將資决 但此種以資料之位元組O10RD)為單位以附加同位元的方 --------1^.-- (請先閲讀背面之注意事項再填寫本頁}Elimination of A stagger = there are _ " devices and methods of data thorns. The data to be stored is divided into a plurality of data blocks by using two or two i. Each — I == ΐ a relative error correction code, which is checked by inspection. More nuclear errors ”, I can identify whether there is an error in the data at the same time, and“ Province% I is being produced so that not only can improve the reliability of data access, but also the complexity of the storage or storage device level, f The material may be incorrectly stored at the time of storage and retrieval! So the error message of tf material is to be read by A mouse tongue S material, which affects the correctness of the reading of the data. I, ^, and even affects f to # 料 的 NORMAL OPERATION makes the entire data useless and makes users very troubled. In order to prevent the above errors, related #phase sends a wrong side and correction code or error correction code (ERR0R-C0RRECTING, ECC) to improve this phenomenon, and the conventional technology mainly uses the data bytes (W_ As a unit, the error correction code of the recheck bit (parity bit, p server) is appended to each unit. When the parity bit is stored in the memory storage device along with the data, the parity bit is read together with the data. And; and the new check bit that reads the # material is different from each other. If the check bits are the same, the data is correct; on the contrary, when the check bits are not the same, a special "complication condition," (SYNDROM ) Mode, which can be used to identify the bit and the relative error data, and use it to add the same bit as the unit of data bit O10RD) --- --1 ^ .-- (Please read the notes on the back before filling this page}

-1T ---? t----------- -u ff 1/ · 本紙張尺度璉用中國_家標率（（，NS ) Λ4規格 (2】0><297公浚）-1T ---? T ----------- -u ff 1 / · This paper size uses China _ house standard rate ((, NS) Λ4 specifications (2) 0 > < 297 public Jun

I 柯"—部中次枒準扃兵工消費合作社印製 46 1 9 93 Α7 Β7 五、發明説明（） 式’將大幅增加資料之位元數量，而佔據太大之記憶儲 存裝置容量，不僅降低記憶儲存裝置可使用之容量，且 檢測每一位元組亦浪費太多之運算時間，而相對降低資 料之運算速度。 此外，由於現今半導體工業之發達，使得半導體之 製程越來越精良，因此現今之快閃記憶體(FLASH MEMORY) 大都不附加一多重檢查位元之錯誤更正碼（同位元， PARITY BIT) ’故不具有錯誤檢測及更正之功效。而使用 紗碟機(FLASHDISK)時，如不使用錯誤更正碼，則會使資 料不夠準確’但如使用多重檢查位元之錯誤更正碼，則 會使記憶儲存容量減小。 故如何使用另一種之錯誤自動檢測及更正裝置與方 法’此夠同樣達到資料檢測及更正之目的’亦可節省資 料之存取時間及提昇記憶儲存裝置使用容量，長久以來 直疋使用者殷切盼望及本發明欲行解決之困難點所 在’而本發明人基於多年從事於資訊產製品研究、開發、 及銷售之實務經驗，乃思及改良之意念，窮其個人之專 業知識，經多方設計、探討，並經無數次試作樣品及改 良後，終能創出本發明一種可提高資料存取可靠度 制裝置及方法。妥是， 土本發明之主要目的，在於提供一種可提高資料存取 可靠度的控制裴置及方法，利用資料交鉍分割之方式分 割成複數個資料欄，並在每一資料攔後附加有一錯誤更 正碼，藉此以達到檢測資料存取時是否有偶發性^誤之 _ 4 本紙張尺料用中國( 210X297公漦)--—一 I _***\ ·~J <裝 I I ί ^ {請先聞讀背面之注項再填寫本頁) 46 19 93 A7 B7 五'發明説明（） 訊息發生，而可適時予以更正，不僅可預防資料存取時 一連’所發生之錯誤，亦可相對提高資料存取之可靠度 者。 本發明之次要目的，在於提供一種可提高資料存取 可罪度的控制裝置及方法，利用資料交錯分割之方式分 割成複數個資料搁，並在每一資料攔後附加有一錯誤更 正碼，藉此可相對降低資料之存取時間，而可提高系統 之運算速率者。 土本發明之又一目的，在於提供一種可提高資料存取 y靠度的控制裝置及方法，湘資料交錯分割之方式分 剎成複數個資料攔，並在每一資料攔後附加有一錯誤更 正碼，相對可降低記憶儲存裝置之使用容量，而可增加 記憶儲存裝置之真正資料儲存量者。 、紅為使貝審查委員對本發明之結構、特徵及所達 成之功效有更進-步之瞭解與職，佐啸佳之實施圖 例及詳細說明如后： 恕滴部中-^榡丰局只工消贽合作私印 (讳先閱讀背面之注意事項再填寫本K ) I I 1·-! . · 立請參閱第1圖’係為本發明控制裝置之主要構造示 思圖；如圖所示，本伽之主要架構係包财—資料緩 衝器2 1、資料處理!i23、控觸輯電路27、編碼 /解碼器2 8、錯誤更正邏輯電路2 9、及至少一個之 ，誤更正碼記錄器2 5所組合而成。其中該資料緩衝器 1分別連接有一主機10及一記憶儲畚裝置15，可 作為主機10及記憶儲存裝置15内之資料在欲轉存時 之暫時存放之用；而可作為#料相關處理之f料處理号 __ 5 本紙張尺細 461993 五 、發明説明 A7 B7 "滴部中央桴準局負-x消费合作社印繁 23則連接於該資料緩衝器21，其受控於控制邏輯電 路2 7以對存放於該資料緩衝器2 χ内之資料依據其磁 區(SECTOR ’ 256職DS)作交錯分割處理而成複數個資料 搁/而每—資料欄後則利用該編碼/解碼器2 8應用如 ，德-所羅fK_)~SGL_N曜)之運算方法加以編列 ，、相對之錯誤更正碼（其運算方式容後述），而所編列 好^錯誤更正碼則依照其控觸輯電路2 7内之磁區存 取和不器2 7 5指示而找出其相對應之資料襴，並暫時 存放於錯誤更正碼記錄器2 5(2 5 1〜2 5 4)中，且 透過資料處理器2 3之作用而可附加於每一相對的資料 ，後’並齡於如記麟存裝置1 5内；例，當欲讀取 f放於記懦錄置1 5内之資料時，麟編碼/解碼 器2 8將^:控於控制邏輯電路2 7而可對附加於資料搁 後f錯=更正碼抑解碼處理，並相對械該錯誤更正 碼圮錄器2 5中，且藉由錯誤更正邏輯電路2 g之檢 測’，照貧料儲存及讀取時之錯誤更正碼是否為特定 碼？疋否相同？若否，則該錯誤更正邏輯電路2 9將控 制資料處理H 2 3對錯誤之資侧抑更正，並再將資 料輸出至主機1 Q讀出，而:歸_由此檢麻更正之 動作，以提高資料存取之可靠度功效。 再者’請參閱第2圖’係經由本剌控制裝置編碼 儲存後之資料磁區示意圖，由前述得知，本發明主要係 利用交錯分割之方式將資料分割成複數個資料攔，在此 最佳實施例中，主要係將一磁區3 〇 (SECT〇R，256 w〇RDS) 6 >紙張尺度ίί用中國®家梯嘩U'NS ) A4im ( 2)0X297^iT-----—-— ("'先閱讀背面之注意事項再填寫本頁j 1—---T i-----—ΐτ------^ ^---------------- 161993 A7 B7 五、發明説明（ ^澇部中央標淖局貝工消費合作.社印^ 本紙張尺度诚__ 之容量劃分成第一位元組3 1 (HIGH BYTE)、及第二位元 組3 5 (LOW BYTE)兩大部分，而每一位元組3 1、3 5則I Ke " —Printed by the Ministry of Economy and Social Welfare Cooperative Cooperatives 46 1 9 93 Α7 Β7 V. Description of the invention () The type will greatly increase the number of data bits and occupy too much memory storage device capacity, Not only reduces the usable capacity of the memory storage device, but it also wastes too much computing time to detect each byte, and relatively reduces the computing speed of the data. In addition, due to the development of the current semiconductor industry, the semiconductor process is becoming more and more sophisticated. Therefore, most FLASH MEMORY today do not attach a multiple check bit error correction code (parity bit). Therefore, it does not have the function of error detection and correction. When using a FLASHDISK, if the error correction code is not used, the data will be inaccurate. But if the error correction code of multiple check bits is used, the memory storage capacity will be reduced. Therefore, how to use another type of automatic error detection and correction device and method 'this is enough to achieve the purpose of data detection and correction' can also save data access time and increase the capacity of memory storage devices, users have long been eagerly looking forward to it And the difficulties that the present invention intends to solve are based on the many years of practical experience in the research, development, and sales of information products. After discussion, and after numerous trial samples and improvements, the invention can finally create a device and method for improving the reliability of data access. In fact, the main purpose of the present invention is to provide a control method and method that can improve the reliability of data access. It is divided into a plurality of data columns by using the method of dividing data into bismuth, and an additional one is added after each data block. The error correction code is used to detect whether there are occasional errors during data access. _ 4_ This paper ruler is made in China (210X297cm) --- I _ *** \ · ~ J < 装 II ί ^ {Please read the notes on the back before filling out this page) 46 19 93 A7 B7 Five 'Invention () Information occurs, and can be corrected at the appropriate time, not only to prevent the errors that occur in the process of data access, Can also relatively improve the reliability of data access. A secondary object of the present invention is to provide a control device and method capable of improving the guilty degree of data access. The data is divided into a plurality of data shelves by means of data interleaving and division, and an error correction code is added after each data block. This can relatively reduce the access time of data, and can increase the operating speed of the system. Another object of the present invention is to provide a control device and method that can improve the reliability of data access. The method of staggered division of Hunan data is divided into a plurality of data blocks, and an error correction is added after each data block. The code can relatively reduce the capacity of the memory storage device and increase the true data storage capacity of the memory storage device. In order to make the review committee better and better understand the structure, characteristics and effectiveness of the invention, Zuo Xiaojia's implementation legend and detailed description are as follows: Shudi Buzhong-^ Fengfeng Bureau only works Eliminate co-operation private seal (please read the notes on the back first and then fill in this K) II 1 ·-!. · Please refer to Figure 1 for the main structure of the control device of the present invention; as shown in the figure, Benjamin's main architecture is the data package—data buffer 2 1. data processing! I23, touch control circuit 27, encoder / decoder 2 8. error correction logic circuit 2 9 and at least one of them, error correction code recorder 2 5 combination. The data buffer 1 is connected to a host 10 and a memory storage device 15, respectively, which can be used for temporary storage of the data in the host 10 and the memory storage device 15 when they are to be transferred; f 料 处理 号 __ 5 The size of this paper is 461993 V. Description of the invention A7 B7 " Dribu Central Central quasi-station negative-x consumer cooperatives Yinfan 23 is connected to the data buffer 21, which is controlled by the control logic circuit 2 7 The data stored in the data buffer 2 χ is divided into a plurality of data according to its magnetic zone (SECTOR '256 DS). The encoder / decoder is used after each data column. 2 8 Applications such as, German-Solo fK_) ~ SGL_N 曜) are used to compile, the relative error correction code (the operation method is described later), and the programmed ^ error correction code is based on its control touch circuit The magnetic field access within 2 7 and 2 7 5 instructions to find its corresponding data 襕, and temporarily stored in the error correction code recorder 2 5 (2 5 1 ~ 2 5 4), and through the data The role of processor 2 3 can be attached to each relative data, after ' For example, if you want to read the data that f puts in the record setting 15, the Lin encoder / decoder 2 8 will control ^: in the control logic circuit 2 7 After the error is added to the data, f error = correction code and decoding processing, and the error correction code is recorded in the recorder 25, and the error correction logic circuit 2 g 'is used to detect and store the data as poor data. Is the error correction code a specific code?相同 Is it the same? If not, the error correction logic circuit 29 will control the data processing H 2 3 to suppress the correction of the error data, and then output the data to the host 1 Q to read it out, and return to the action of correcting the line, To improve the reliability of data access. Furthermore, "Please refer to Fig. 2" is a schematic diagram of the magnetic domain of the data after being encoded and stored by the control device of the present invention. From the foregoing, it is known that the present invention mainly divides the data into a plurality of data blocks by means of interleaved division. In the preferred embodiment, a magnetic field 3 0 (SECTOR, 256 WRDS) 6 > Paper Scale (U.S. China Home Furnishing U'NS) A4im (2) 0X297 ^ iT ---- -—-— (" 'Read the precautions on the back before filling in this page j 1 ---- T i ------- ΐτ ------ ^ ^ --------- ------- 161993 A7 B7 V. Description of the invention (^ Shellfish consumer cooperation of the Central Bureau of Waterlogging of the Ministry of Waterlogging and Printing ^ The capacity of this paper is divided into the first byte 3 1 (HIGH BYTE ), And the second byte 3 5 (LOW BYTE), and each byte 3 1, 3 5

依其奇偶性細分成第一資料欄3 1 1 (3 5 1 )(ZER0THSubdivide into the first column according to its parity 3 1 1 (3 5 1) (ZER0TH

DATA FIELD)、及第二資料欄 3 1 5 ( 3 5 5 XFIRST DATA FIELD)，故每一磁區資料3 〇可被交錯分成四大塊，而 所相對增加之同位元組4 〇的錯誤更正碼4丄（4 2、4 y二4 4)則亦只需要相對增加四組而已，分別放置於磁 料3 0之後。如此，在同位元組與資料同時儲存於 裝置時’則無需過多額外增加之記憶儲存 ^置^里’故可提高記憶儲存袋置真正之使用儲存效 相#’亦無需花費過多之錯誤更正碼檢測時間，而 相對提向系統之存取速率。 加以’係為本發明在欲儲存資料而 下：】錯*更正碼時之流程示意圖，其主要步驟如 步驟9 η 1 而、£4 j，控制邏輯電路接獲欲儲存資料之訊息， 步備接收㈣； 存資料2，資料處理器控制資料緩衝器開始暫時儲 步冑3 π q 之蒈=’细資料處理11將暫存於資料緩衝器内 步驟？η 1照磁區交錯分割成複數個（四個）資料欄； 緩衝器及〜 =邏輯電路内之磁區_示器指出資料 制邏輯電2理器目前所處理之資料位址’且該控 路控制編碼/解碼器以雷德一所羅門運算 7 Λ4規格（2)0x297公釐} (#先閲讀背面之注意事項再填寫本頁)DATA FIELD) and the second data column 3 1 5 (3 5 5 XFIRST DATA FIELD), so each magnetic field data 〇 can be interleaved into four large blocks, and the relative increase in parity group 〇 error correction The code 4 丄 (4 2, 4 y 2 4 4) only needs to increase the number of four groups, which are placed after the magnetic material 30. In this way, when the parity and data are stored on the device at the same time, 'there is no need to add extra memory storage ^ ^ ^', so the memory storage bag can be improved to use the actual storage effect phase # ', and there is no need to spend too much error correction code Detection time and relative access rate to the system. "Add" is the following for the data to be stored in the present invention:] Schematic diagram of the flow when the code is wrong * corrected. The main steps are as follows: step 9 η 1 and £ 4 j. The control logic circuit receives the information of the data to be stored. Receive ㈣; Store data 2. The data processor controls the data buffer to temporarily store steps 胄 3 π q of 细 = 'fine data processing 11 will temporarily store in the data buffer step? η 1 The magnetic field is divided into a plurality of (four) data columns alternately; the buffer and the magnetic field in the logic circuit _ indicator indicates the address of the data currently processed by the data logic processor 2 and the control The control encoder / decoder uses Reid-Solomon to calculate 7 Λ4 specifications (2) 0x297 mm} (#Read the precautions on the back before filling this page)

A7 B7 Λ61993 五、發明説明（ 對每1料欄編列相對應之錯誤更正碼，並 暫存於相對的錯誤更正碼記錄器中；％並 料處理器將錯誤更正碼附加於已暫存 丰挪貝夏衝器内之資料後面’以完成加碼工作；及 、铋將已附加錯誤更正碼之資料由資料緩衝 =存於s己憶儲存裝置中，而完成資料之儲存工作。 穿置it 4圖，絲本發明在欲從記憶儲存 裝置裡讀取貝料輪出時之流程示意圖，其主要步驟如 下· 步驟4 01，控制邏輯電路接獲欲讀取資料之訊自， 而通知㈣處理器準收從記㈣存裝置讀i資 料， ' 步驟4 0 2 ’資料處理器控制資料緩衝器開始接收來 自記憶儲存裝置之資料並予以暫時儲存； 步驟4 0 3 ’控制邏輯電路内之磁區指示器指出資料 緩衝器及資料處理器目前所處理之資料位址，且該控 制邏輯電路控制編碼//解碼器針對每―諸攔編列 所相對應之錯誤更正碼而予以解碼處理； 步驟4 0 4 ’將已解碼處理過之錯誤更正碼暫時儲存 於相對應之錯誤更正碼記錄器中； 步驟4 0 5，控制邏輯電路將通知錯誤更正邏輯電路 開始比較該已解碼處理之錯誤更正碼是否為正確之 特定碼，若是，則執行步驟4 〇 6，若否，則執行步 驟 4 0 8 ’· 本紙張尺度ii/fl中國周家標準（（，NS ) Μ規格（2〗〇Χ297公廣 (諳^·閱讀背面之注意事項再填寫本頁)A7 B7 Λ61993 V. Description of the invention (the corresponding error correction code is listed for each column and temporarily stored in the corresponding error correction code recorder; the% processor adds the error correction code to the temporarily stored code Bezier punches the data behind the 'to complete the coding work; and, bismuth will buffer the data to which the error correction code has been added from the data buffer = stored in the sjiyi storage device, and complete the data storage work. Wear it 4 Figure The process flow diagram of the present invention when the shell material wheel is to be read from the memory storage device. The main steps are as follows: Step 4 01: The control logic circuit receives the information from the data to be read and notifies the processor To read the data from the storage device, 'Step 4 2' The data processor controls the data buffer to start receiving the data from the memory storage device and temporarily store it; Step 4 0 3 'The magnetic field indicator in the control logic circuit Indicate the data address currently being processed by the data buffer and data processor, and the control logic circuit controls the encoder / decoder for each error correction code corresponding to each block sequence. Step 4 0 4 'Temporarily store the decoded and processed error correction code in the corresponding error correction code recorder; Step 4 0 5 The control logic circuit will notify the error correction logic circuit to start comparing the decoded processing Whether the error correction code is the correct specific code. If it is, go to step 4 〇6; if not, go to step 4 0 8 ′ · This paper size ii / fl China Zhoujia Standard ((, NS) M specifications (2 〖〇Χ297 公 广 (谙 ^ · Read the notes on the back and fill in this page)

461993 五、發明説明（ 步驟4 0 6，判斷資料是否可更正，若是 驟4 〇 7 ’若否，則執行步驟4 8 ; 仃步 步=0 7 ’由於發現資料在儲存時可能有任 i位故通知資料處理器將相對資料攔内之i 予以更正，並將㈣更正後，接續執行步驟 步=4 0 8 ’資料處理器將正確之資料 輸出，完成資料之讀取動作。 顺衝為 步驟4 0 9，發出不可更正資料錯誤之 料之讀取動作。 、·‘。朿貝 本發明主要係利用如雷德-所羅門（REED-S0L0M0N CODE)之運算方法，而對欲存取之資料予以編相對之 錯誤更正碼，故茲對本發明所運用之雷德—所羅門運算 方法做更進一步之解釋： # 首先’定義一本原多項式(PRIMITIVE POLYNOMIAL)， 如下： P(x) = X8 + X4 + X3 + χ2 + 1 經清部中史掠隼局Μ1,消资合竹社印粼 來構成編碼/解碼器之有限域(GAL〇IS FIELD)GF(2S)， 若α為本原多項式尸(X)的一個根，則在此有限域GFP8) 的所有元素’均可由α來產生，故稱α為本原元素 (PRIMITIVE ELEMENT)並可表示成β，其中/為自然數。 又’為了說明與計算上的方便，亦定義t一個伴隨矩陣 (COMPANION MATRIX)Γ ： 本紙張尺度適用中國固家標窣（CNS ) Λ4規格（210X297公釐）461993 V. Description of the invention (Step 4 06, judging whether the data can be corrected, if it is step 4 〇7 'If not, go to step 4 8; 仃 步步 = 0 7' Because it is found that the data may have any position Therefore, the data processor is notified to correct i in the data block, and after the correction is made, the steps are executed in steps = 4 0 8 'The data processor outputs the correct data and completes the reading of the data. 4 0 9 ， Reading action for sending out uncorrectable data errors.… '. This invention is mainly based on the use of calculation methods such as Reed-Solomon (REED-S0L0M0N CODE) to the data to be accessed The relative error correction code is compiled, so the Redd-Solomon operation method used in the present invention is explained further: # First 'define a primitive polynomial (PRIMITIVE POLYNOMIAL), as follows: P (x) = X8 + X4 + X3 + χ2 + 1 is composed of the GAL (IS FIELD) GF (2S) of the encoder / decoder by the Bureau of History and History of the Qing Dynasty Bureau M1, and printed by the Zhuhe Society, if α is the original polynomial ( X) a root, then in this finite field GFP8) Element 'can be produced by the α, so called [alpha] is a primitive element (PRIMITIVE ELEMENT) can be represented as β, where / is a natural number. For the convenience of explanation and calculation, a companion matrix (COMPANION MATRIX) Γ is also defined: This paper size is applicable to the Chinese solid standard (CNS) Λ4 specification (210X297 mm)

6 A 19 93 A7 B7 五、發明説明（6 A 19 93 A7 B7 V. Description of the invention (

T 0 0 0 0 0 0 0 1' 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 本發明之編碼/解碼器，係將128個位元組之資料， 加上兩個同位檢查位元組組合而成，故可稱之為 (130,128)擴充式雷德—所羅門瑪，因此，本創作之生成 多項式可定義為： G⑴= (χ + 1)(λ + ΰί)...... 故若用矩陣表示，則可表示成： (讀先閱讀背面之注意事項再填寫本頁)T 0 0 0 0 0 0 0 1 '1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 The encoder / decoder of the present invention is a combination of 128 bytes of data and two parity check bytes, so it can be called It is (130,128) extended Red-Solomonma. Therefore, the generator polynomial in this creation can be defined as: G⑴ = (χ + 1) (λ + ΰί) ... So if it is represented by a matrix, then Expressed as: (Read the precautions on the back before filling in this page)

G 丁'2Ί 丁 126G Ding'2Ί Ding 126

T 經湞部屮泱摞準局貝Jr.消资合作社印I?. P〇 ~ I /·..//— A — J.127 j\26 _ γ j 的轉置矩陣。 (一）首先，就本發明之編碼過程而言： 若將資料以矩陣方式表示，則可表示成：T The Ministry of Economic Affairs, the Bureau of Standards, Jr. Consumer Cooperatives, and I I .. P0 ~ I /·..//— A — J.127 j \ 26 _ γ j transpose matrix. (1) First, as far as the encoding process of the present invention is concerned: If the data is represented in a matrix manner, it can be expressed as:

Dr=[A27 化6 …A A)] 其中同位檢查位元組/^及巧，可由生成矩陣與資料矩 陣相乘而得： r τ Ι-Ί ·Ζ)Γ ’而為矩陣Z) 10 本紙張尺廋谪州中國S；家標肀（CNS ) Λ4規格（210X 297公釐） Λ 6 1 9 93 Α7 Β7 五、發明説明（ 若表示成算術演算式則為： 127 127 /=0 上述演算式之加法運算，係為有限域之加法運算，運 用於電路設計上則為互斥或閘（EXCLUSIVE 0R GATE)，故可將上述演算式表示成： (^0)/+1 = (^o), + A (户1)/+1 = (Ο, + 尸.D;. ')再者，就本發明之解碼過程而言： 首先，定義一同位檢查位元組矩陣（p紐ity—check MATRIX)//： Η ^ ^ 其中尸為伴 隨矩陣 若將編碼過之資料以矩陣方式表示，則可表示成：B = [〇ni Dm ... /)〇 pQ pj 則讀出資料之解碼過程可表示成：X] 夕—//.5 ，其中方5"為矩陣召的轉置矩陣。 *— *— 而解碼電路所產生的\及&位元組，則稱為該解瑪 過程所產生的併發症狀(SYNDROME)，' 若以運算式表示，則可表示為： Τ Τ Τ 11 { (’NS ) Λ4^ίΜ 210x297公釐} ----叫装-- (請先閱讀背面之注意事項再填寫本頁) -1Τ Δ 19 93 A7 B7 五、發明説明（Dr = [A27 Hua6… AA)] where the parity check byte / ^ and coincidence can be obtained by multiplying the generator matrix and the data matrix: r τ Ι-Ί · Z) Γ 'and the matrix Z) 10 papers Chinzhou China S; House Standard (CNS) Λ4 specification (210X 297 mm) Λ 6 1 9 93 Α7 Β7 V. Description of the invention (if expressed as an arithmetic calculation formula: 127 127 / = 0 above calculation formula The addition operation is an addition operation in a finite field, and it is mutually exclusive or gate (EXCLUSIVE 0R GATE) in circuit design, so the above calculation formula can be expressed as: (^ 0) / + 1 = (^ o) , + A (House 1) / + 1 = (0, + Corpse. D ;. ') Furthermore, in terms of the decoding process of the present invention: First, define a parity check byte matrix (pnewity-check MATRIX) //: Η ^ ^ where the corpse is the adjoint matrix. If the encoded data is expressed in a matrix, it can be expressed as: B = [〇ni Dm ... /) 〇pQ pj The decoding process of the read data It can be expressed as: X] xi — //. 5, where square 5 " is a matrix transpose matrix. * — * — The \ and & bytes generated by the decoding circuit are referred to as the complication symptoms (SYNDROME) generated by the solution process, and 'If expressed by an arithmetic expression, it can be expressed as: Τ Τ Τ 11 {('NS) Λ4 ^ ίΜ 210x297 mm} ---- Calling-(Please read the notes on the back before filling this page) -1Τ Δ 19 93 A7 B7 V. Description of the invention (

127 S':t^Di+PY /=0 上述演算式之加法運算，係為有限域之加法運算。 Ξ·)就本發明之資料錯誤檢查與更正運算而言：(1)若資料沒有錯誤，則： 127 127 127 Ϊ-0 127 i=0 i=0 127 127 127 127^=ΣΓί*Α+^=ΣΓ·Α+ΣΓ·Α i=0 /=0 故無需對資料予以更正動作(2) 若檢查位元組巧發生錯誤，則由（1)可得：0但\ = 0(3) 若檢查位元組乃發生錯誤，則由（1)可得： S0 = 0 ^(4) 若資料有任一位元組發生錯誤，如錯誤資料之樣 式為，且其錯誤位元組之位置為/，則由（1)可 Λ& 付. 127 127 127 ti^tt ^nt ^ ^^^^1 i \ .· ^ 一Av ,¾ (讀先閱讀背面之注意事項再填寫本頁) 經消部中决標準局吳T;消费含作社印來 _!·=〇 127 .j:0 '127 +户〇 ΣΓ_Α+α i=0 m+i Σα +α， i=0127 S ': t ^ Di + PY / = 0 The addition operation of the above calculation formula is an addition operation of a finite field. Ξ ·) As far as the data error checking and correction operation of the present invention is concerned: (1) if there is no error in the data, then: 127 127 127 Ϊ-0 127 i = 0 i = 0 127 127 127 127 ^ = ΣΓί * Α + ^ = ΣΓ · Α + ΣΓ · Α i = 0 / = 0, so there is no need to correct the data (2) If an error occurs in checking the bytes, then (1) can be obtained: 0 but \ = 0 (3) if Checking the byte is an error, then it can be obtained from (1): S0 = 0 ^ (4) If there is an error in any byte of the data, for example, the format of the error data is, and the position of the error byte is /, Will be paid by (1) 可 Λ & 127 127 127 ti ^ tt ^ nt ^ ^^^^ 1 i \. · ^ A Av, ¾ (read the precautions on the back before filling this page) Wu T, the standard decision bureau of the ministry; Consumption is printed by the company _! · = 〇127 .j: 0 '127 + house 〇ΣΓ_Α + α i = 0 m + i Σα + α, i = 0

+ R 127 Σα i=0 Όέ=αΜ+ι i=0 a 12 本纸浓尺度適用中國國家標嗱（CNS ) Λ4規格（2!〇Χ 297公釐） 1993 A7 B7 五、發明説明（ 故可叫=W運算即可求得錯誤位元組之位置 ί ’且由上述之運算式可知，&恰好為錯誤資料之 樣式’ ’故可將錯誤之倾位元纟績所求得之錯 誤樣式做互斥或之運算，就可輕易更 確之資料。 而上述ECC (錯誤更正碼）之編碼/解碼程式設計電 路，如附件所示。 、在本發明裡’主要係利用如雷德—所羅門之運算方 法對欲存取之資料相編列其相對之錯誤更正碼，而立 記憶儲存裝置係可為是-快閃記憶體(FLASHMEM ;夕 碟機(FLASHMSK)、或磁碟機、或一些具有儲存資料訊號 之記憶儲存裝置。 綜上所述’當知本發明係提供可提高資料存取可靠 度的控制裝置及綠，不僅可提高資料存取之可靠度， 亦可節省㈣之存取時間，並可增加記憶儲存裝置之真 正資料儲存量者。故本發明實為一富有新穎性、進步性' 及可供產業利用功效者，應符合發明專利申請要件無 疑’妥依法提出發明專射請，賴局早日賜准專利’，、 至為感禱。 、惟以上所述者，僅為本發明之一較佳實施例而已， 並非用來限定本發明實施之範圍。即凡依本發明申請專 利範圍所述之形狀、構造、特徵及精神七為之均等變化 與修飾，均應包括於本發明之申請專利範圍内。 (―)圖示簡單說明： 13 K n n - --->f<·I--- i^i --- nf T -- 一 ，V ,1 (¾先閱讀背面之注意事項再填寫本頁) 本紙怵八反通川肀國國家標率, 461993 A7 五、發明説明（ ） 〜--— 係為本發明控制裝置之主要構造示意圖。 弟2圖：係經由本發明控制裝置編碼儲存後之資料磁區 示意圖。 第3圖：係為本發明在欲儲存資料時之流程示意圖。 第4圖：係為本發明在欲讀取資料時之流程示意圖。 (二）圖號簡單說明： ^消部屮"標"局負-τ消於合作社印努 10 主機 15 記憶儲存裝置 2 1 資料緩衝器 2 3 資料處理器 2 5 錯誤更正碼記錄器 2 5 1 錯誤更正碼記錄器 2 5 2 錯誤更正碼記錄器 2 5 3 錯誤更正碼記錄器 2 5 4 錯誤更正碼記錄器 2 7 控制邏輯電路 2 7 5 磁區存取指示器 2 8 編碼/解碼器 2 9 錯誤更正邏輯電路 3 0 資料磁區 3 1 第一位元組 3 11 第一資料攔 3 15 第二資料攔 3 5 第二位元組 3 5 1 第一資料爛 3 5 5 第二資料攔 40 同位元組 4 1 第一錯誤更正碼 4 3 第二錯誤更正碼 4 5 第三錯誤更正瑪 47 第四錯誤更正碼 14 本紙張尺度適用中國囷家標率（（:NS M4礼格（210X297公楚 (¾先閱讀背而之注意事項再填寫本頁} 裝 Ή+ R 127 Σα i = 0 Όέ = αΜ + ι i = 0 a 12 The thick scale of this paper is applicable to China National Standard (CNS) Λ4 specification (2! 〇 × 297 mm) 1993 A7 B7 V. Description of the invention The position of the error byte can be obtained by calling = W operation. 'From the above expression, & happens to be the style of the error data' 'Therefore, the error style obtained from the error's bitwise result can be obtained. The mutual exclusion or operation can easily correct the data. The above-mentioned ECC (Error Correction Code) encoding / decoding programming circuit is shown in the annex. In the present invention, 'the main use is such as Reid-Solomon The operation method arranges the relative error correction code for the data to be accessed, and the stand-alone memory storage device can be-flash memory (FLASHMEM; FLASHMSK), or a disk drive, or some have storage Memory storage device for data signals. In summary, when the invention is known, the present invention provides a control device and a green device that can improve the reliability of data access, which can not only improve the reliability of data access, but also save the access time. And increase the true value of memory storage devices The amount of storage. Therefore, the present invention is truly a novel and progressive person and can be used by the industry, should meet the requirements of the invention patent application, undoubtedly submit the patent for the invention in accordance with the law, and the Bureau will grant a quasi-patent at an early date. It ’s my prayer. However, the above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. That is, the shapes, structures, and characteristics described in the scope of the patent application for the present invention Equal changes and modifications should be included within the scope of the patent application of the present invention. (―) The diagram illustrates briefly: 13 K nn---- > f < · I --- i ^ i- -nf T-I, V, 1 (¾Read the notes on the back before filling in this page) This paper is the national standard of the eight anti-pass and Sichuan countries, 461993 A7 V. Description of the invention () ~ ----- Schematic diagram of the main structure of the control device of the invention. Figure 2 is a schematic diagram of the magnetic field of the data encoded and stored by the control device of the invention. Figure 3: Schematic diagram of the flow of the invention when data is to be stored. Figure 4: Schematic diagram of the process of the present invention when reading data (2) Brief description of drawing number: ^ 消 部 屮 " 标 " Passive -τ is eliminated in the cooperative Innu 10 Host 15 Memory storage device 2 1 Data buffer 2 3 Data processor 2 5 Error correction code recorder 2 5 1 Error correction code recorder 2 5 2 Error correction code recorder 2 5 3 Error correction code recorder 2 5 4 Error correction code recorder 2 7 Control logic circuit 2 7 5 Magnetic field access indicator 2 8 Encoding / decoding Device 2 9 Error correction logic circuit 3 0 Data sector 3 1 First byte 3 11 First data block 3 15 Second data block 3 5 Second byte 3 5 1 First data block 3 5 5 Second Data block 40 Parity group 4 1 The first error correction code 4 3 The second error correction code 4 5 The third error correction code 47 The fourth error correction code 14 This paper standard applies to the Chinese family standard rate ((: NS M4 courtesy （210X297 公 楚 (¾Read the precautions before filling in this page)

Claims (1)

申請專利範固 AS B8 C8 D8 經 部 中 央 準 貝 合 作 杜 袋 461993 二種降低記憶儲存裝置使用量之資料存取控制裝 置’^、主要構造係包括有： 衝器，至少連接有一主機及—記憶儲存裝 之用而可作為該兩者間資料欲轉存時之暫時存放 —資料處理器，連接於該資料緩衝器； -電路，可姉及_該#料處理器，而 二子緩衝器内之資料以交錯分割處理 方式成複數個資料欄者； 一，碼器，受控於該控制邏輯電路，而針對 貝料緩衝器内之複數個資料欄適時 ^ 之錯誤更正碼； 個 至更正碼記錄器’可暫時儲存來自於該編 碼裔之錯誤更正碼； 受控於雜侧輯電路，㈣對附加於 ^枓欄叙錯誤Μ舒畴碼_，並存放於 垓錯誤更正碼記錄器中；及 —f,正邏輯電路，分別連接於該錯誤U碼記 資料處理間’受控於該控制邏輯電路而判 別吳更正碼疋否為特定碼，並可控制該資料處 理器對錯誤之資料欄予以更正者。 、 申π專利範圍第1項所述之資料存取控制裝置， ς中該控制邏輯電路内尚包括有—磁區指示器，分別 連接於該資料緩衝器及資料處理器。 用中理理家梂準（CNS )八峨^ ( 21〇Χ297公兼 cs D8 4 ο 1 9 9 3 、申請專利範圍 3如申請專利範圍第1項所述之資料存取控制裝置 “中忒5己憶儲存裝置係可為一快閃記憶體。 如申^青專利範圍第1項所述之資料存取控制裝置： "、中邊5己憶儲存裝置係可為一石夕碟機。 ·=申請專利範圍帛丄項所述之資料存取控制裝置， '、中5亥§己憶儲存裝置係可為一磁碟機。 5::月ί利範圍第1項所述之資料存取控制裝置， ^遠資料處理器受控於該控制邏輯電路而對存友 於，資料緩衝器内之資料作分段處理時係以分割成 四段為最佳。 7如申凊專利範圍第5項所述之資料存取控制裝置， 其中該錯誤更正碼記錄器亦以四個為最佳。、 、種降低圮憶儲存裝置使用量之資料存取控制方 法，其主要係包括有下列之步驟： (a) .，資料欲儲存時，利用資料處理器將資料磁區 交錯分成複數個資料攔； (b) .利用編碼器對每一資料欄後附加有相對之至 —個錯誤更正碼； (c) .將附加有錯誤更正碼之資料儲存於記憶儲 置中； (d) .田 > 料欲碩取時，將每一錯誤更正碼經解碼處 理而存放於記錄器中； (e) · f誤更正邏輯電路將比較該解碼之錯誤更正碼 是否為正'確之特定碼； 16 本紙張尺度適用中國國家樣牟（CNS )八4乳格（210Χ：297公羹） f j . I 1*^-- ('請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 ir------Mr.線--------- A r · 1 A6 1 993 A8 B8 C8 D8 、申請專利範圍 (f) .若是，則控制資料處理器將正確之資料讀取輪 出；及 (g) .若否，則控制資料處理器作相對之錯誤資料欄更 正，且接續動作（f)。 9·如申請專利範圍第8項所述之資料存取控制方法，其 中該步驟(a)之後尚可包括有一步驟(ai)i利用一磁區 指示器可指出正在存取及處理之資料欄。 1 0·如申請專利範圍第8項所述之資料存取控制方法， 其中該步驟(a)中將交錯分割之資料欄係以四個為 最佳。 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央揉準局負工消費合作社印製 17 本紙張尺度適用中國國家揉準（CNS ) A4规格（210X；297公釐）Applying for a patent Fan Gu AS B8 C8 D8 Ministry of Economics Central Junbei cooperation du bag 461993 Two types of data access control devices to reduce the use of memory storage devices' ^, the main structure includes: a punch, at least one host and-memory It can be used for storage and can be used as a temporary storage when the data between the two is to be transferred—data processor, connected to the data buffer;-circuit, which can be connected to the _ # processor, and The data is divided into a plurality of data columns in a staggered and divided processing manner. First, the encoder is controlled by the control logic circuit, and corrects the error correction codes of the plurality of data columns in the shell buffer timely. The error correction code from the encoding source can be temporarily stored; it is controlled by the miscellaneous editing circuit, and the error correction code __ is added to the column and stored in the error correction code recorder; and —F, positive logic circuit, respectively connected to the error U code record data processing room 'is controlled by the control logic circuit to determine whether the Wu correction code is a specific code and can control the data Processor to be corrected by the error column. The data access control device described in item 1 of the patent application scope includes a magnetic field indicator in the control logic circuit, which is connected to the data buffer and the data processor, respectively. Use the Zhongli Lijia Standard (CNS) Ba'e ^ (21〇 × 297 public and cs D8 4 ο 1 9 9 3, the scope of patent application 3 as described in the scope of the patent application of the data access control device "Zhongyi" The 5 Jiyi storage device can be a flash memory. The data access control device described in the first item of the patent scope of the Shenqing patent: ", the middle side 5 Jiyi storage device can be a stone evening disc player. · = The data access control device described in the item (1) of the scope of the patent application, "Zhong 5 Hai § Ji Yi storage device can be a disk drive. Take the control device, the remote data processor is controlled by the control logic circuit, and the data in the data buffer is divided into four segments when it is processed in sections. The data access control device described in item 5, wherein the error correction code recorder is also the best of four. The data access control method for reducing the amount of memory storage device use mainly includes the following: Steps: (a). When data is to be stored, use the data processor to transfer the data sectors Divided into a plurality of data blocks; (b). Use an encoder to append an error correction code to each data column; (c). Store the data with the error correction code in the memory; d). Tian > When it is expected to obtain, each error correction code is decoded and stored in the recorder; (e) · f error correction logic circuit will compare whether the decoded error correction code is positive. Specific code; 16 This paper size applies to China National Samples (CNS) 8 4 milk grid (210 ×: 297 cm) fj. I 1 * ^-('Please read the notes on the back before filling this page) Economy Printed by the Consumers' Cooperative of the Ministry of Standards of the People's Republic of China -------- Mr. Line -------- A r · 1 A6 1 993 A8 B8 C8 D8, patent application scope (f). If yes, then The control data processor reads out the correct data in rotation; and (g). If not, the control data processor corrects the relative error data column and continues the action (f). 9 · If the patent application scope item 8 The data access control method, wherein the step (a) may further include a step (ai) i using a magnetic field indication It can indicate which data columns are being accessed and processed. 10. The data access control method as described in item 8 of the scope of the patent application, wherein in step (a), four data columns are optimally divided into four. (Please read the notes on the back before filling out this page) Printed by the Central Consumers ’Bureau of the Ministry of Economic Affairs, Printed by the Consumers’ Cooperatives 17 This paper size is applicable to China ’s National Union (CNS) A4 specification (210X; 297 mm)