TW459342B - Semiconductor integrated circuit apparatus with copper wiring layer and its manufacturing method - Google Patents
Semiconductor integrated circuit apparatus with copper wiring layer and its manufacturing method Download PDFInfo
- Publication number
- TW459342B TW459342B TW087112907A TW87112907A TW459342B TW 459342 B TW459342 B TW 459342B TW 087112907 A TW087112907 A TW 087112907A TW 87112907 A TW87112907 A TW 87112907A TW 459342 B TW459342 B TW 459342B
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- wiring
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- integrated circuit
- semiconductor integrated
- circuit device
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 356
- 239000010949 copper Substances 0.000 title claims abstract description 166
- 229910052802 copper Inorganic materials 0.000 title claims abstract description 73
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title claims abstract description 50
- 238000004519 manufacturing process Methods 0.000 title claims description 61
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
經濟部智慧財產局員X消費合作社印製 4 b 9 3 4 2 a? __B7_ 五、發明說明（i ) 〔發明所靥之技術領域〕 本發明係關於一種具有銅配線層之半導體積體電路裝 置及其製造技術·特別是，關於一種適用於半導體積體電 路裝置之配線形成技術上有效之技術者。 (以往之技術） 作爲半導體積體電路裝置之配線形成方法，有例如稱 爲達馬新（Damascene )法的方法。該方法係在絕緣膜形成 配線形成用之溝後，在半導體基板全面堆積配線形成用之 導體膜，又藉由化學、機械性硏磨法（CMP : Chemical Mechanical Polishing )予以除去該溝以外之領域的導體膜 ，俾在配線形成用之溝內形成埋入配線的方法。該方法之 情形*特別是，被檢討作爲微細之蝕刻加工困難的銅系（ 銅或銅合金）之導體材料所形成的埋入配線的形成方法- 又，作爲達馬新法之應用有雙達馬新（Dual-Damascene )法。該方法係在絕緣膜形成用以實行配線形成 用之溝及下層配線之連接的連接孔之後，在半導體基板全 面堆積配線形成用之導體膜，又藉由CMP予以除去該溝 以外之領域的導體膜，俾在配線形成用之溝由形成埋入配 線，同時在連接孔內形成插塞之方法。該方法時，特別是 ，在具有多層配線構造的半導體積體電路裝置，可刪減工 程數，並可減低配線成本。 對於此種配線形成技術有例如記載於曰本特開平8-78410' 1996* Symp, VLSI Tech, Digest pp48-49 !!!* ^^ . I I I I I I ^^ ·11! — 1· ^^ <請ib.w讀背面之注意事項再{ 1本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -4- A7 B7 4ο^34·2 五、發明說明（2 ) (請λ-閱讀背面之注意事項再{Λ1Ρ本頁吣 電子材料3月號pp22 — 27，1996年，特開平8 - 1 4 8 5 6 0，或 IBM J· RES. DEVELOP，VOL, 39 NO 4, pp419-435 July 1995 * (發明欲解決之課題） 然而，在上述之埋入配線之形成技術，本案發明人發 現有以下之課題》 經濟部智慧財產局員工消費合作社印製 亦即，具有將埋入配線技術適用於半導體積體電路裝 置時之構造上及製造上之整體像並不完全地確立之課題》 特別是，在上述之雙達馬新法，將配線形成溝與連接孔以 同一導體膜同時地埋入，惟將此配線形成用溝更微細之連 接孔與配線形成用溝同時地，充分地且以確保良好之電氣 式特性之狀態下埋入，隨著配線或連接孔之微細化成爲困 難。一方面，在使用電鍍法時，雖埋入能力高，惟以該方 法所形成的銅之剛成膜後之結晶粒較小，有無法得到充分 之電氣式特性之情形。又，雖電鍍法之埋入能力較高惟也 有界限，而在高縱橫比之微細連接孔之埋入也有困難。該 問題係在相同之埋入配線層，在有縱橫比不同之配線用溝 時也產生。 本發明之目的係在具有埋入配線構造的半導體積體電 路裝置，提供一種不使用高度之技術，可以將埋入配線用 之導體膜良好地埋入的技術。 又，本發明之目的係在具有埋入配線構造的半導體積 體電路裝置，提供一種可以推進配線用溝或連接孔或其雙 本紙張尺度適用中國國家標準（CNS)A4規格（210 * 297公釐） A7 4 6 9 342 ___B7__ 五、發明說明（3 ) 方之微細化的技術》 又，本發明之其他目的，係在於提供一種可提高埋入 配線之可靠性的技術。 又，本發明之其他目的，係在於提供一種將使用銅系 導體材料之埋入配線，在不產生不方便下，可裝進在半導 體積體電路裝置之整體構造的技術。 本發明之上述及其他之目的與新穎之特徵，係由本說 明書之記述及所附圖式即可明瞭。 (解決課題所用之手段） 在本發明所揭示之發明中，簡單地說明代表性者如下 0 本發明的半導體稹體電路裝置之製法，係具有埋入在 半導體基板上層之配線層之配線的半導體稹體電路裝置之 製法，其特徵爲具有： (a )在上述半導體基板上層之絕緣膜開連接孔.的製 程，及 ％ (b )在上述絕緣膜上，埋入上述連接孔地形成連接 用之導體膜的製程，及 (c )上述連接用之導體膜之形成製程後，對於上述 連接用之導體膜施以平坦化處理，介經除去連接孔內以外 之連接用的導體膜，在上述連接孔內形成連接用導體部的 製程，及 (d )在形成上述連接用導體部後之絕緣膜的配線形 !!1 — ！裝 illltl — 訂 *lt — — — — — _線 (請λΜ讀背面之沒意事項再本頁) 經濟部智慧財產局員工消費合作社印5衣 本紙張尺度適用t國國家標準（CNS)A4規格（210 X 297公釐） -6- ^ 59 34-2 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（4 ) 成領域形成配線用溝的製程，及 (e )在上述絕緣膜上，埋入上述配線用溝地形成配 線用之導體膜的製程，及 (f )上述配線用之導體膜之形成製程後•對於上述 配線用之導體膜施以平坦化處理，介經除去配線用溝以外 之配線用之導體膜，在上述配線用溝形成埋入配線的製程 〇 又，本發明的半導體積體電路裝置之製法，係上述配 線用之導體膜由銅或銅合金所構成•以濺射法形成該導體 膜時，在上述配線用之導體膜之平坦化處理製程後具有施 加熱處理之製程者。 又，本發明的半導體積體電路裝置之製法，係在半導 體基板上層之配線層具有埋入配線的半導體積體電路裝置 之製法，在形成於相同之埋入配線層之尺寸不同的配線用 溝內埋入導體膜時，在上述尺寸不同之配線用溝內分別個 別地埋入導體膜者。 又，本發明的半導體積體電路裝置之製法，係在半導 體基板上層之配線層具有埋入配線的半導體積體電路裝置 之製法，其.特徵爲具有： (a )在上述半導體基板上層的絕緣膜開配線用溝與 連結孔的製程，及 (b )在上述絕緣膜上，埋入上述配線用溝與連接孔 地介經濺射法形成銅或銅合金所構成之導體膜的製程，及 (c )對於上述銅或銅合金所構成的導體膜施以平坦Printed by member of the Intellectual Property Bureau of the Ministry of Economic Affairs, X Consumer Cooperative, 4 b 9 3 4 2 a? __B7_ V. Description of the Invention (i) [Technical Field of the Invention] The present invention relates to a semiconductor integrated circuit device having a copper wiring layer and The manufacturing technology and, in particular, it relates to a technically effective technique suitable for wiring formation of a semiconductor integrated circuit device. (Conventional technology) As a method for forming a wiring of a semiconductor integrated circuit device, there is a method called a Damascene method, for example. In this method, after a groove for wiring formation is formed on an insulating film, a conductor film for wiring formation is deposited on a semiconductor substrate in its entirety, and areas outside the groove are removed by chemical and mechanical honing (CMP: Chemical Mechanical Polishing). A method for forming a buried film in a trench for wiring formation. The situation of this method * In particular, the method of forming buried wirings formed of copper-based (copper or copper alloy) conductor materials that are difficult to be finely etched is reviewed-and double-dama is used as an application of the new Dama method New (Dual-Damascene) method. This method is to form a conductive film for wiring formation on a semiconductor substrate after the insulating film has formed a connection hole for connecting a groove for wiring formation and a lower-layer wiring, and then remove the conductors outside the groove by CMP. A method of forming a buried wiring in a trench for forming a film and forming a plug in a connection hole. In this method, in particular, in a semiconductor integrated circuit device having a multilayer wiring structure, the number of processes can be reduced, and wiring costs can be reduced. Such wiring formation technology is described in, for example, Japanese Patent Laid-Open No. 8-78410 '1996 * Symp, VLSI Tech, Digest pp48-49 !!! * ^^. IIIIII ^^ · 11! — 1 · ^^ < Please ib.w Read the notes on the back again {1 page) This paper size is applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm) -4- A7 B7 4ο ^ 34 · 2 V. Description of the invention (2) (Please read λ-Notes on the back page. {Λ1Ρ This page 吣 Electronic Materials March issue pp22-27, 1996, JP 8-8 1 4 8 5 60, or IBM J. RES. DEVELOP, VOL, 39 NO 4, pp419-435 July 1995 * (Invention to solve the problem) However, in the above-mentioned embedded wiring formation technology, the inventor of this case found the following problems: "Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. "The problem that the overall image of the structure and manufacturing when the embedded wiring technology is applied to a semiconductor integrated circuit device is not completely established" In particular, in the above-mentioned double-dama method, the groove formation of the wiring is the same as the connection hole. The conductor film is embedded at the same time, but the connection hole and wiring for the wiring formation groove are more fine. Simultaneously, the trenches are embedded fully and in a state of ensuring good electrical characteristics. With the miniaturization of wiring or connection holes, it becomes difficult. On the one hand, when the plating method is used, although the embedding capacity is high, The crystal grains of copper formed by this method are small immediately after film formation, and there may be cases where sufficient electrical characteristics cannot be obtained. In addition, although the embedding ability of the electroplating method is high, there are limits, but at high aspect ratios It is also difficult to embed fine connection holes. This problem occurs when the same buried wiring layer is used and there are wiring grooves with different aspect ratios. The object of the present invention is a semiconductor integrated circuit device having a buried wiring structure. Provides a technology that can well embed a conductor film for embedded wiring without using a height technology. Furthermore, an object of the present invention is to provide a semiconductor integrated circuit device having an embedded wiring structure and provide a wiring advancement The groove or connection hole or its double paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 * 297 mm) A7 4 6 9 342 ___B7__ V. Detailed description of the invention (3) [Technology] Another object of the present invention is to provide a technique that can improve the reliability of buried wiring. Another object of the present invention is to provide a buried wiring using a copper-based conductor material in Without inconvenience, the technology can be incorporated into the overall structure of a semiconductor integrated circuit device. The above and other objects and novel features of the present invention can be understood from the description of the present specification and the attached drawings. (Means for Solving the Problems) In the invention disclosed in the present invention, the representative ones are briefly described as follows. The method for manufacturing a semiconductor body circuit device of the present invention is a semiconductor having wirings embedded in a wiring layer on a semiconductor substrate. A method for manufacturing a body circuit device, comprising: (a) a process of opening a connection hole in an insulating film on the semiconductor substrate; and (b) embedding the connection hole in the insulation film to form a connection. After the process of forming the conductor film and (c) the process of forming the conductor film for connection, the conductor film for connection is subjected to a flattening treatment, and the conductor film for connection other than the inside of the connection hole is subjected to the above The process of forming the connection conductor portion in the connection hole, and (d) the wiring shape of the insulating film after the above-mentioned connection conductor portion is formed !! 1 —! Install illltl — order * lt — — — — — _line (please read the unintentional matters on the back of λM) (210 X 297 mm) -6- ^ 59 34-2 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (4) The process of forming wiring trenches in the field, and (e) the above insulation On the film, the process of forming the conductor film for wiring is buried in the above-mentioned trench for wiring, and (f) After the process of forming the conductor film for wiring, the conductor film for wiring is subjected to a flattening treatment and removed through A process for forming a conductor film for wiring other than a wiring groove, and forming a buried wiring in the wiring groove, and the method for manufacturing a semiconductor integrated circuit device of the present invention is such that the conductor film for wiring is composed of copper or a copper alloy. • When the conductor film is formed by a sputtering method, there is a process of applying a heat treatment after the planarization process of the conductor film for the above wiring. In addition, the method for manufacturing a semiconductor integrated circuit device of the present invention is a method for manufacturing a semiconductor integrated circuit device having embedded wiring in a wiring layer above a semiconductor substrate, and forming wiring grooves having different sizes in the same embedded wiring layer When the conductor film is embedded, the conductor film is individually embedded in each of the wiring grooves having different sizes. The method for manufacturing a semiconductor integrated circuit device according to the present invention is a method for manufacturing a semiconductor integrated circuit device having embedded wiring in a wiring layer above a semiconductor substrate, and is characterized by having: (a) an insulation layer on the semiconductor substrate; A process of film opening wiring grooves and connection holes, and (b) a process of forming a conductor film composed of copper or a copper alloy by sputtering method to embed the wiring grooves and connection holes on the insulating film, and (c) Flattening the conductor film made of the above copper or copper alloy
先-閲 讀 背 面 之 注 意 事 項 再I I 裝 訂 ▲ 本紙張尺度適用中國國家標準（CNS〉A4規格（210 X 297公釐） A7 4 5 9 34 2 B7 五、發明說明（5) 化處理，並介經除去上述配線用溝與連接孔以外之銅或銅 合金所構成的導體膜，在上述配線用溝與連接孔內埋入導 體膜的製程，及 (d )在上述銅或銅合金所構成之導體膜的平坦化處 .理製程後施以熱處理的製程。 又，本發明的半導體積體電路裝置，係在半導體基板 上層之配線層具有埋入配線層的半導體積體電路裝置，其 特徵爲：上述埋入配線與半導體基板所接觸之部分的配線 材料，係至少使用由鎢、鎢合金、鈦、鈦氮化物、鋁或鋁 合金之一種所構成，而其上層之配線層的埋入配線係由銅 或銅合金所構成者。 又，本發明之半導體積體電路裝置，係在半導體基板 之上層的配線層中之至少一層以上具有埋入配線的半導體 積體電路裝置，其特徵爲：上述配線層中之最上配線層的 配線材料以鋁或鋁合金所構成，而其下層之配線層的埋入 配線以銅或銅合金者。 又，本發明的半導體積體電路裝置，係在半導體基板 上層的配線層具有埋入配線的半導體積體電路裝置，其特 徵爲：在連接鋁或鋁合金所構成之配線，及銅或銅合金所 構成的配線時，在此等接合部介裝阻障導體膜者。 又，本發明的半導體積體電路裝置，係在半導體基板 上層之配線層具有埋入配線的半導體積體電路裝置，其特 徵爲：在電氣式地連接比上述配線層中之所定埋入配線層 更上層的配線與比上述所定之埋入配線之配線層更下層的 ------ - - ----_· ^---— l· — II 訂------1 — 線 ί請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作杜印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -8 - A7 B7 ^〇9 34 2 五、發明說明（6 ) 配線時，具備將設置於從上述上層之配線延伸至上述所定 埋入配線之配線層之連接孔內的連接用導體部，及設置於 從上述下層之配線延伸至上述所定埋入配線之配線層之連 接孔內的連接用導體部，經由設置於上述所定埋入配線之 配線層之連接用溝內的中繼用連接用導體部電氣式連接之 構造，上述中繼用連接用導體部係至少其所定之埋入配線 延伸方向的長度•形成比上述連接孔之上述配線延伸方向 的長度較長者》 (發明之實施形態） 以下，依照圖式詳述本發明之實施形態（又，在用以 說明實施形態之全國中具有相同功能著附與相同記號，而 省略重複之說明）。 請 先 閱 讀 背 面 之 項 再I I Ϊ裝 頁 訂 經濟部智慧財產局員工消费合作杜印製 ▲ (實施例1 ) 第1圖係表示本 裝置的要部剖面圖， 路裝置之第_1配線層 示第2圖之配線構造 1圖之半導體積體電 第7圖係表示第1圖 接的變形例之半導體 第1 2圖係表示第1 要部剖面圖，第1 3 發明之一實施形態之半 第2圖係表示第1圖之 的要部剖面圖，第3圖 之變形例的剖面圖，第 路裝置之第2配線層的 之半導體積體電路裝置 積體電路裝置的要部剖 圖之半導體積體電路裝 圖至第1 8圖係表不第 導體積體電路 半導體積體電 至第5圖係表 6圖係表示第 要部剖面圖， 之配線層間連 面圖，第8至 置之製程中的 1圖之半導體 本纸張尺度適用中國國家標準（CNS)A4規格（2】0*297公釐〉 -9- A7 d5 9 34 2 B7___ 五、發明說明（7 ) 積體電路裝置之製程中之要部的局部切剖斜視圖。 首先，藉由第1圖至第7圖說明本實施形態1的半導 體積體電路裝置之構造。半導體基板1係由例如P —型矽 (s 1 )單晶所構成，在其上部形成有P并p w及η井 NW。在該Ρ井PW，含有例如Ρ型雜質之硼（Β )，而 在η井NW含有例如η型雜質之磷（Ρ)或砷（AS)。 又，在該半導體基板1之上部形成有元件分離部2， 該元件分離部2係在開擴於半導體基板1之上部的分離用 溝2 a內，埋入有例如氧化矽等所構成的分離用絕緣膜 2 b所形成。該文件分離部2之上面係與半導體基扳1之 主面大約一致地被平坦化。 在圍繞於文件分離部2之P井PW及η井NW的領域 '形成有例如η通道型之1^08?[1'(1\/^&1〇1丨(^-Semiconductor Field Effect Transistor ’ 以下簡稱爲 η M〇S) 3η及ρ通道型之MOSFET (以下簡稱爲 pM〇S) 3p 。藉由該打1^〇331^及？]\4〇33?形 成有C Μ 0 S ( Complimentary MOS )。但是，形成於半導 體基板1之積體電路元件係並不限定於Μ 0 S F E T或 Μ I S F E T (Metal Insulator Semicondutor Fileld effect Transistor)者而可作各種變更，雙極電晶體’ 一極體或電阻 元件或是此等之積體電路元件形成在相同半導體基板上之 構造也可以。 nM〇 S 3 η係具有：互相隔離地形成在P#PW上 部的一對半導體領域，及形成在半導體基板1上的閘極絕 ------------一 衣·----„----訂·---- ----一 (諳先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 * 297公釐） -10- 9 34 2 A7 B7 五、發明說明（8 ) 緣膜3 n i ，及形成在其上面閘極電極3 n g又， nMO S 3 η之通道領域係在p井PW內形成在一對之半 導體領域3 n d之間。 該半導體領域3 n d係用以形成nMO S 3 η之源極 、汲極領域的領域，含有例如η型雜質之磷或砷。又，半 導體領域3 n d係具有配置於通道領域側之相對地低濃度 的半導體領域，及配置於其外側之相對地高濃度的半導體 領域之構造也可以。 閘極絕緣膜3 η 1係例如氧化矽所構成。形成於其上 面的閘極電極3 n g ，係例如低電阻多晶矽之單體膜所構 成。但是，閘極電極3 n g係並不被限定於低電阻多晶矽 之單體膜者。例如在低電阻多晶矽之單體膜上形成如鎢矽 化物等之矽化物膜的作爲所謂多矽化物構造也可以，或是 ，例如在低電阻多晶矽之單體膜上經由如氮化鈦等之阻障 金屬膜形成如鎢等金屬膜的所謂多晶矽化金屬構造也可以 〇 一方面，pMO S 3 P係具有：互相隔離地形成在η 井NW上部的一對半導體領域3 p d，及形成在半導體基 板1上的閘極絕緣膜3 P 1 ’及形成在其上面的閘極電極 3 p g。又，pMOS 3 P之通道領域係在η井NW內形 成在一對半導體領域3 P d之間。 該半導體領域3 P d係用以形成pMO S 3 ρ之源極 汲極領域的領域’含有例如P型雜質之硼。又半導體領域 3 p d係具有配置於通道領域側之相對地低濃度的半導體 本紙張尺度適用“ @1家標準（CNS)A4規格（21G x 297公髮)~ --------— — IX ^ ---I l· I--^ I I----- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消费合作社印製 經濟部智慧財產局員工消費合作社印製 59 34 2 A7 ^ _B7__ 五、發明說明（9 ) 領域，及配置於其外側之相對地高濃度的半導體領域之構 造也可以。 閘極絕緣膜3 p i係例如氧化矽所構成。形成於其上 面的閘極電極3 pg，係例如低電阻多晶矽之單體膜所構 成。但是，閘極電極3 n g係並不被限定於低電阻多晶矽 之單體膜者。例如在低電阻多晶矽之單體膜上形成如鎢矽 化物等之矽化物膜的作爲所謂多矽化物構造也可以，或是 ，例如在低電阻聚矽之單體膜上經由如氮化鈦等之阻障金 屬膜形成如鎢等金屬膜的所謂多晶矽化金靥構造也可以* 在此種半導體基板1上，其表面形成有介經例如 CMP法被平坦化的例如氧化矽所構成的層間絕緣膜4 a ，由此，覆蓋有nM0S3n及pM0S3p »在該層間 絕緣膜4 a上部，形成有寬度或長度不同的配線用溝5 a ，5b。配線用溝5a ，5b之深度係相同，例如約 0 _ 3〜1 . Oym，較佳爲〇 . 5em。又，配線用溝 5 a之縱橫比係例如約〇 . 1〜1 . 〇考慮良好地埋入配 線用導體膜時，小於0 . 7較佳。配線用溝5 b之縱橫比 係例如約0 . 5〜2 . 5，而考慮埋入配線用導體膜時， 小於1 . 5較佳。 在該配線用溝5 a ，5b，如第1圖及第2圖所示· 形成有第1配線層6 L成爲埋入狀態。該第1配線層6 L 係由下部與側部之相對地較薄的導體膜6 L 1，及園繞於 該較薄導體膜6 L 1之相對地較厚的導體膜6 L 2所構成First-read the precautions on the back before binding II ▲ This paper size applies to Chinese national standards (CNS> A4 size (210 X 297 mm) A7 4 5 9 34 2 B7 V. Description of the invention (5) Chemical treatment, and introduced A process of removing a conductor film made of copper or a copper alloy other than the wiring groove and the connection hole, embedding the conductor film in the wiring groove and the connection hole, and (d) a conductor made of the copper or copper alloy The flattening part of the film. The process of applying heat treatment after the manufacturing process. The semiconductor integrated circuit device of the present invention is a semiconductor integrated circuit device having a buried wiring layer on a wiring layer above a semiconductor substrate, and is characterized by: The wiring material of the part where the buried wiring contacts the semiconductor substrate is made of at least one of tungsten, tungsten alloy, titanium, titanium nitride, aluminum, or aluminum alloy, and the buried wiring system of the upper wiring layer is used. It is made of copper or copper alloy. The semiconductor integrated circuit device of the present invention has at least one half of the wiring layer above the semiconductor substrate having a half of the embedded wiring. The bulk body circuit device is characterized in that the wiring material of the uppermost wiring layer among the wiring layers is made of aluminum or aluminum alloy, and the buried wiring of the lower wiring layer is made of copper or copper alloy. A semiconductor integrated circuit device is a semiconductor integrated circuit device having embedded wiring on a wiring layer above a semiconductor substrate, and is characterized in that when a wiring composed of aluminum or an aluminum alloy and a wiring composed of copper or a copper alloy are connected, A barrier conductor film is interposed at these joints. The semiconductor integrated circuit device of the present invention is a semiconductor integrated circuit device having embedded wiring in a wiring layer above a semiconductor substrate, and is characterized in that: Ground connection between the wiring layer higher than the embedded wiring layer specified above and the wiring layer lower than the wiring layer specified above ------------ — L · — Order II ------ 1 — Line ί Please read the notes on the back before filling out this page) Consumption cooperation between employees of the Intellectual Property Bureau of the Ministry of Economic Affairs Du printed This paper applies Chinese National Standard (CNS) A4 Specifications (210 X 297 mm) -8-A7 B7 ^ 〇9 34 2 V. Description of the invention (6) For wiring, it is provided for connection in the connection hole provided in the wiring layer extending from the upper wiring to the predetermined buried wiring layer. The conductor portion and the connection conductor portion provided in the connection hole extending from the wiring of the lower layer to the wiring layer of the predetermined buried wiring are passed through the relay provided in the connection groove of the wiring layer of the predetermined buried wiring. The structure of the electrical connection by the connecting conductor portion is such that the relay connecting conductor portion has at least a predetermined length in the direction in which the embedded wiring extends. • It is formed longer than the length in the direction in which the wiring extends in the connection hole. (Embodiment) Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings (in addition, the same function is attached to the same symbol throughout the country used to describe the embodiment, and repeated description is omitted). Please read the item on the back first and then print it out. II Printed booklet printed by consumer cooperation of the Intellectual Property Bureau of the Ministry of Economic Affairs ▲ (Embodiment 1) Figure 1 is a cross-sectional view of the main part of the device. Fig. 7 shows the wiring structure of Fig. 2. Semiconductor integrated circuit of Fig. 7. Fig. 7 shows a modified example of the semiconductor connected to Fig. 1. Fig. 12 shows a cross-sectional view of the first main part. The second half diagram is a cross-sectional view of the main part of FIG. 1, a cross-sectional view of a modification of FIG. 3, and a cross-sectional view of a main part of the semiconductor integrated circuit device of the second wiring layer of the first circuit device. The semi-conductor integrated circuit assembly drawing to FIG. 18 is a diagram showing a conducting volume circuit. The semi-conductor integrated circuit to FIG. 5 is a table. FIG. 6 is a cross-sectional view of the main part. The 1-size semiconductor paper in the manufacturing process applies the Chinese national standard (CNS) A4 specification (2) 0 * 297 mm> -9- A7 d5 9 34 2 B7___ 5. Description of the invention (7) Integrated circuit Partial cut-away perspective view of main parts in the manufacturing process of the device. Fig. 7 illustrates the structure of a semiconductor integrated circuit device according to the first embodiment. The semiconductor substrate 1 is composed of, for example, a P-type silicon (s1) single crystal, and P, pw, and n-well NW are formed on the upper portion. The P well PW contains, for example, boron (B) of a P-type impurity, and the n well NW contains, for example, phosphorus (P) or arsenic (AS) of an η-type impurity. Further, an element isolation portion is formed on the upper portion of the semiconductor substrate 1. 2. The element separation portion 2 is formed by separating a separation insulating film 2 b made of, for example, silicon oxide in a separation groove 2 a which is spread over an upper portion of the semiconductor substrate 1. The document separation portion 2 The upper surface is flattened approximately uniformly with the main surface of the semiconductor substrate 1. In the area surrounding the P-well PW and the η-well NW of the file separation section 2, for example, 1 ^ 08? [1 '( 1 \ / ^ & 1〇1 丨 (^ -Semiconductor Field Effect Transistor 'hereinafter referred to as η M〇S) 3η and ρ channel type MOSFET (hereinafter referred to as pM〇S) 3p. With this hit 1 ^ 〇 331 ^ and?] \ 4〇33? C M 0 S (Complimentary MOS) is formed. However, the integrated circuit element system formed on the semiconductor substrate 1 is not limited Various changes can be made in the M 0 SFET or M ISFET (Metal Insulator Semicondutor Fileld effect Transistor). The structure of a bipolar transistor 'a pole or resistance element or an integrated circuit element formed on the same semiconductor substrate. Yes. The nMoS 3 η system includes a pair of semiconductor regions formed on the upper portion of P # PW in isolation from each other, and a gate electrode formed on the semiconductor substrate 1. --- „---- Order · ---- ---- 1 (谙 Please read the notes on the back before filling in this page) The paper printed by the Employee Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs applies the Chinese national standard ( CNS) A4 specification (210 * 297 mm) -10- 9 34 2 A7 B7 V. Description of the invention (8) Edge film 3 ni and gate electrode 3 ng formed on it, nMO S 3 η channel area It is formed between a pair of semiconductor fields 3 nd in the p-well PW. The semiconductor field 3 nd is used to form the source and drain regions of nMO S 3 η and contains, for example, phosphorus or arsenic of n-type impurities. The semiconductor field 3 nd may have a structure having a relatively low-concentration semiconductor field arranged on the channel field side and a relatively high-concentration semiconductor field arranged on the outer side thereof. The gate insulating film 3 η 1 is, for example, a structure It is made of silicon oxide. The gate electrode 3 ng formed on it is made of a single film of low-resistance polycrystalline silicon, for example. However, the gate electrode 3 ng system is not limited to a low-resistance polycrystalline silicon monomer film. For example, a silicide film such as tungsten silicide is formed on the low-resistance polycrystalline silicon monomer film as a so-called polysilicide. The structure can also be, or, for example, a so-called polycrystalline silicide metal structure in which a metal film such as tungsten is formed on a single film of low-resistance polycrystalline silicon through a barrier metal film such as titanium nitride or the like. On the one hand, pMO S 3 P It has a pair of semiconductor regions 3 pd formed on the upper part of the n-well NW in isolation from each other, and a gate insulating film 3 P 1 ′ formed on the semiconductor substrate 1 and a gate electrode 3 pg formed thereon. The channel field of pMOS 3 P is formed between a pair of semiconductor fields 3 P d in the n-well NW. The semiconductor field 3 P d is a field used to form the source-drain field of pMO S 3 ρ. Boron of type impurity. In the semiconductor field, 3 pd is a semiconductor with a relatively low concentration arranged on the channel field side. This paper is suitable for "@ 1 家 标准 (CNS) A4 size (21G x 297)) ~ ---- ----— — IX ^ --- I l · I-^ I I ----- ( Please read the notes on the back before filling out this page) Printed by the Employees 'Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 59 34 2 A7 ^ _B7__ V. Description of Invention (9) Field A relatively high-concentration semiconductor structure in its outer side is also possible. The gate insulating film 3 p i is made of, for example, silicon oxide. The gate electrode 3 pg formed thereon is made of, for example, a single film of low-resistance polycrystalline silicon. However, the gate electrode 3 n g is not limited to a single film of low-resistance polycrystalline silicon. For example, a so-called polysilicide structure in which a silicide film such as tungsten silicide is formed on a low-resistance polycrystalline silicon monomer film, or, for example, a low-resistance polysilicon monomer film is passed through, for example, titanium nitride, etc. The so-called polycrystalline silicon silicide structure of the barrier metal film forming a metal film such as tungsten can also be formed on the surface of such a semiconductor substrate 1. An interlayer insulation made of, for example, silicon oxide is planarized by, for example, the CMP method. The film 4 a is thereby covered with nM0S3n and pM0S3p »On the interlayer insulating film 4 a, wiring grooves 5 a and 5b having different widths or lengths are formed. The depths of the wiring grooves 5a and 5b are the same, for example, about 0_3 ~ 1. Oym, and preferably 0.5em. The aspect ratio of the wiring trench 5a is, for example, about 0.1 to 1.0. When the conductor film for wiring is satisfactorily embedded, it is preferably less than 0.7. The aspect ratio of the wiring groove 5 b is, for example, about 0.5 to 2.5, and when the conductor film for wiring is considered to be embedded, it is preferably less than 1.5. As shown in FIGS. 1 and 2, the wiring grooves 5 a and 5 b are formed with the first wiring layer 6 L in a buried state. The first wiring layer 6 L is composed of a relatively thin conductive film 6 L 1 at a lower portion and a side portion, and a relatively thick conductive film 6 L 2 wound around the thin conductive film 6 L 1.
It n if n 1· n 一81，* 1 n n n n I (請先《讀背面之i£意事項再{ 本頁) 本纸張又度適用中國固家標準（CNS)A4規格（210 X 297公釐） -12- 經濟部智慧財產局員工消費合作社印製 j 3 4 2 A7 _____B7____ 五、發明說明（10 ) 較薄導體膜6 L 1係由具有提高第1配線層6 L與層 間絕緣膜4 a的密接性之功能或抑制較厚導體膜6 L 2之 構成原子之擴散的阻障功能的材料所構成，例如由鎢（W )，氮化鈦（TiN)，鈦（Ti)，鉅（Ta)，氮化 鎢（WN) •氮化鎢矽化物（WSiN)，氮化鈦矽化物 (TiSiN) *氮化鉅（TaN)或氮化耝矽化物（ T a S i N )等所構成。 以鎢等構件較薄導體膜6L1時，與以TiN，Ti ，Ta ，双1^，贾31^，丁1311^，丁31^或 Ta S i N等所構成者相比較，成爲可降低配線電阻。雖 未特別加以限定，惟在本實施形態1 ，較薄導體膜6 L 1 係由例如T i N所構成。 又，較厚導體膜6 L 2係構成第1層配線層6 L之本 體的構成，例如鋁（A1)，鋁合金，鎢，鎢合金，銅（ C u )，琛銅合金等之低電阻材料所構成。作爲鋁合金之 .· 一例子，有在鋁所構成之導體膜添加如S i ，Cu，Ge 等元素中所選擇之一種或一種以上之元素者。作爲C u合 金之一例子'，有在C u所構成之導體膜添加如Mg，S i ’ T i等元素中所選擇之一種或一種以上之元素者。作爲 鎢合金之一例子，有在鎢所構成導體膜添加如S i ，N等 元素中所選擇之一種或一種以上之元素者。又，在以下之 記載，對於鋁合金，鎢合金及銅合金，基本上成爲與上述 者相同。在以銅或銅合金構成該較厚導體膜6 L 2時，與 以鋁或鎢構成者相比較，可大幅度降低配線電阻，且與以 本紙張尺度通用中國國家標準（CNS)A4規格（210*297公茇） -13- llllt — — — — — — — — . 1 I I — I — I ·111111__ '^^ <請先間讀背面之注意事項再{ Γ本頁) 4 59 34 2 五、發明說明（) 鋁或鋁合金構成者相比較，成爲可提高第1層配線6 L之 電子遷移（EM)耐性。雖未特別加以限定，在本實施例 之形態1中，較厚導體膜6L2以例如銅所構成。 但是第1層配線6 L之構造係並不被限定於表乖在第 1圖及第2圖之構造者而可作各種變更，作成表示於例如 第3圖至第5圖之構造者也可以。第3圖係覆蓋較薄導體 膜6 L 1及較導體膜6 L 2地設置帽蓋導體膜6 L 3之構 造。帽蓋導體膜6L3係例如W，TiN'Ti ，Ta， WN，WSiN，TiSiN，TaN或TaSiN等所 構成。該構造係特別適用於以C u或C u合金構成較厚導 體膜6 L 2時，由於可更抑制C u原子之擴散*因此，成 爲可更提高半導體積體電路裝置之可靠性，又，雖並未特 別加以限定，惟與上層配線材料之關係，也可適用於直接 接觸該配線材料與較厚導體膜6 L 2時會形成高電阻係數 之合金等之情形。又，將帽蓋導體膜之上面形成與層間絕 緣膜4 a上面大約一致地而將帽蓋導體膜只設在較厚導體. 膜6 L 2之上面的構造也可以》 第4圖係表示僅以較厚導體膜6 L 2構成第1層配線 6 L的構造。亦即，沒有較薄導體膜之構造。第5圖係表 示在第4圖之構造中，在較厚導體膜6 L 2之上面設置帽 蓋導體膜6 L 3的構造。該構造係並未特別限定，惟以與 上層配線材料之關係，適用於直接接觸該配線材料與較厚 導體膜6 L 2時會形成高電阻係數之合金的情形。 配線用溝5 a內之第1層配線6 L係經連接用導體部It n if n 1 · n a 81, * 1 nnnn I (please read the "I'm on the back side first, then {this page) This paper is again applicable to China Solid Standard (CNS) A4 (210 X 297) (12%) -12- Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs j 3 4 2 A7 _____B7____ V. Description of the invention (10) Thinner conductor film 6 L 1 is made of the first wiring layer 6 L and interlayer insulation film 4 The function of a tightness of a or a material for inhibiting the diffusion of atoms constituting a thicker conductor film 6 L 2 is composed of materials such as tungsten (W), titanium nitride (TiN), titanium (Ti), giant ( Ta), tungsten nitride (WN) • tungsten nitride silicide (WSiN), titanium nitride silicide (TiSiN) * giant nitride (TaN) or hafnium nitride silicide (T a S i N) . When the thin conductor film 6L1 is made of tungsten and other components, it can reduce wiring compared with those made of TiN, Ti, Ta, double 1 ^, Jia 31 ^, Ding 1311 ^, Ding 31 ^, or Ta S i N. resistance. Although not particularly limited, in the first embodiment, the thin conductive film 6 L 1 is made of, for example, T i N. In addition, the thicker conductor film 6 L 2 is the structure of the body of the first wiring layer 6 L, such as low resistance of aluminum (A1), aluminum alloy, tungsten, tungsten alloy, copper (Cu), and chen copper alloy. Made of materials. As an example of aluminum alloys, there is a case where one or more elements selected from Si, Cu, Ge and the like are added to a conductor film made of aluminum. As an example of Cu alloy, there is one in which one or more elements selected from elements such as Mg, Si'Ti, etc. are added to a conductor film composed of Cu. As an example of a tungsten alloy, one or more elements selected from elements such as Si and N are added to a conductor film made of tungsten. In the following description, aluminum alloys, tungsten alloys, and copper alloys are basically the same as those described above. When the thicker conductor film 6 L 2 is made of copper or copper alloy, compared with those made of aluminum or tungsten, the wiring resistance can be greatly reduced, and it is in accordance with the Chinese National Standard (CNS) A4 standard commonly used in this paper standard 210 * 297 public address) -13- llllt — — — — — — — —. 1 II — I — I · 111111__ '^^ < Please read the precautions on the back first {Γ This page) 4 59 34 2 5. Description of the invention () Compared with those made of aluminum or aluminum alloy, it can improve the electron migration (EM) resistance of 6 L of the first layer wiring. Although not particularly limited, in the first embodiment of the present embodiment, the thick conductive film 6L2 is made of, for example, copper. However, the structure of the first layer wiring 6 L is not limited to the structure shown in Figures 1 and 2 and can be changed in various ways. The structure shown in, for example, Figures 3 to 5 may be used. . Fig. 3 shows a structure in which a thin conductive film 6 L 1 is covered and a cap conductive film 6 L 3 is provided in comparison with the conductive film 6 L 2. The cap conductor film 6L3 is made of, for example, W, TiN'Ti, Ta, WN, WSiN, TiSiN, TaN, or TaSiN. This structure is particularly suitable for thicker conductor films 6 L 2 made of Cu or Cu alloys, because the diffusion of Cu atoms can be more suppressed *. Therefore, the reliability of semiconductor integrated circuit devices can be further improved. Although it is not particularly limited, the relationship with the upper wiring material can also be applied to the case where an alloy with a high resistivity is formed when the wiring material and the thick conductor film 6 L 2 are directly contacted. In addition, the upper surface of the cap conductor film is formed approximately the same as the upper surface of the interlayer insulating film 4a, and the cap conductor film is provided only for a thicker conductor. The structure on the film 6 L 2 is also possible. The structure of the first-layer wiring 6 L is formed by the thick conductive film 6 L 2. That is, there is no construction of a thinner conductive film. Fig. 5 shows a structure in which a cap conductor film 6 L 3 is provided on the thicker conductor film 6 L 2 in the structure of Fig. 4. This structure is not particularly limited, but in terms of the relationship with the upper wiring material, it is suitable for the case where an alloy with a high resistivity is formed when the wiring material and the thick conductor film 6 L 2 are directly contacted. The first-layer wiring 6 L in the wiring groove 5 a is a conductor portion for connection
請 先- U 讀 背 S) 之 注 意 事 項 * 本 I 裝 訂 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210*297公爱） -14- 4 59 34 2 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（I2 ) 7 C電氣式連接nMOS 3 η之半導體領域3 n d或 pMOS3p之半導體領域3pd。連接用導體部7C係 其大部分埋入於從配線用溝5 a之底面向半導體基板1之 上面而穿孔於層間絕緣膜4 a的連接孔8 a內，惟連接用 導體部7 C之上部係貫穿第1層配線6 L之上下面地突出 於第1配線6 L中。連接孔8 a之直徑係例如約〇 . 2〜 1 . 〇//m’較理想爲例如約〇 . 4#m。又，連接孔 8 a之縱橫比係例如約2〜6 *而考慮良好地實行連接用 導體部時低於約4較理想。又，連接用導體部7 C之上面 高度係與第1層配線6 L之上面高度大約一致。 連接用導體部7 C係由其下部與側部之相對地較薄的 導體膜7 C 1 ，及被較薄導體膜7 C 1所圍繞之相對地較 厚的導體膜7 C 2所構成《較薄導體膜7 C 1係由具有提 高ί接用導體部7 C與層間絕緣膜4 a之密接性的功能或 抑制較厚導體膜7 c 2之構成原子之擴散的阻障功能的材 料所構成，例如W，TiN，Ti ，Ta，WN， WS iN，Ti S iN，Ta 或TaS iN等所構成》 以W等構成較薄導體膜Cl時，與以TiN，Ti ， Ta，WN，WSiN，TiSiN，TalS^ T a S i N等所構成時相比較，成爲可降低配線電阻。雖 並未特別限定，惟在本實施形態1 ，較薄導體膜7 C 1由 例如W所構成。 又，較厚導體膜7 C 2係構成連接用導體部7 C之本 體的構件，例如由A 1，A 1合金，W或W合金等之低電 闓 讀 背 面Please read first-U Read S) Note * This booklet is printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, and is printed by the Consumer Cooperatives. The paper size is applicable to China National Standard (CNS) A4 (210 * 297 public love) -14- 4 59 34 2 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the Invention (I2) 7 C Electrically connected to nMOS 3 η in the semiconductor field 3 nd or pMOS3p in the semiconductor field 3pd. The connection conductor portion 7C is mostly buried in the connection hole 8 a which is perforated into the interlayer insulating film 4 a from the bottom of the wiring groove 5 a to the upper surface of the semiconductor substrate 1, but the upper portion of the connection conductor portion 7 C The first wiring 6L penetrates the first wiring 6L above and below the first wiring 6L. The diameter of the connection hole 8a is, for example, about 0.2 to 1.0 // m ', and is preferably about 0.4 #m, for example. The aspect ratio of the connection hole 8a is, for example, about 2 to 6 *, and it is preferable that it is less than about 4 when the conductor portion for connection is well implemented. The height of the upper surface of the connecting conductor portion 7C is approximately the same as the height of the first layer wiring 6L. The connecting conductor portion 7 C is composed of a relatively thin conductor film 7 C 1 at a lower portion and a side portion, and a relatively thick conductor film 7 C 2 surrounded by the thinner conductor film 7 C 1 " The thinner conductive film 7 C 1 is made of a material having a function of improving the adhesion between the conductive portion 7 C for interposing and the interlayer insulating film 4 a or a barrier function of suppressing the diffusion of constituent atoms of the thicker conductive film 7 c 2. Structure, such as W, TiN, Ti, Ta, WN, WS iN, Ti S iN, Ta, or TaS iN, etc. "When forming a thin conductive film Cl with W, etc., and TiN, Ti, Ta, WN, WSiN In comparison with TiSiN, TalS ^ T a Si N, etc., the wiring resistance can be reduced. Although not particularly limited, in the first embodiment, the thin conductive film 7 C 1 is made of, for example, W. Further, the thicker conductor film 7 C 2 is a member constituting the body of the conductor portion 7 C for connection, and is made of, for example, low electric power such as A 1, A 1 alloy, W, or W alloy. 读 Read Back
意 事 項 再I I 頁 裝 訂 私纸張尺度適用中國國家標準（CNS)A4規格（210 * 297公釐） 15- A7 B7 459342 五、發明說明（is ) 阻的材料所構成。在較厚導體膜7 C 2之構成材料並未使 Cu或C u合金。亦即，在未實施形態1中，即使在第1 層配線6 L之埋入導體膜6 L 2之構成材料使用C u或 C u合金等，在與半導體基板1直接接觸之連接用導體部 7 C之構成材料未使用C u或C u合金。由此，成爲減低 第1層配線6 L之配線電阻，且可抑制起因於C u原子擴 散至半導體基板側之連接不良。 在以A 1或A 1合金構成較厚導體膜7C2時，與以 W或W合金所構成時相比較，成爲可降低連接用導體部 7 C之電阻。又，在以W或W合金構成埋入導體膜7 C 2 時，與以A I或A 1合金構成埋入埋入導體膜7C2時相 比較時，成爲可提高連接用導體部7 C之EM耐性及SM 耐性。雖並未被限定，惟在本實施形態1，較厚導體膜 7 C 2例如以W所構成。因此，在本實施形態1中，在第 1層配線6 L之高度位置的平面內，成爲存有異種之導體 膜（第1層配線6 L形成用之C u等及連接用導體部7 C 之W等）的構造。又•連接用導體部也構成者。 又，在上述之說明係說明配線用溝5a ，5b內之第 1層配線6 L以相同材料所構成的情形，惟並未被限定者 。例如，埋入於配線用溝5 b之較厚導體膜6 L 2及較薄 導體膜6 L 1之構成材料，係與埋入於配線用溝5 a之較 厚導體膜6 L 2及較薄導體膜6 L 1之構成材料作成異種 之導體材料也可以。例如在例如寬廣之配線用溝5 a及寬 窄之配線用溝5 b內同時地埋入C u等時，因寬窄之配線 !!!!裝--- (請t闉讀背面之注意事項再{ ί本頁) 訂- -線· 經濟部智慧財產局貝工消費合作社印製 本紙張尺度過用中國國家標準（CNS)A4規格（210 *297公t) - 16- A7 B7 五、發明說明（Μ ) 用溝5 b有無法充分地埋入之情形，因此，在此時，寬廣 之配線用溝5 a係以C u埋入，而寬窄之配線用溝5 b係 介經C VD法埋入W等之情形的構造例•又，對於此時之 形成方法係如下所述' 在層間絕緣膜4 a上，例如於矽氮化膜4 6 1上形成 有比矽氮化膜較厚的氧化矽4 4 2的層間絕緣膜4 b。矽 氮化膜4 b l係以C U系導電材料構成較厚導體膜6 L 2 或埋入導體膜7 C 2時，功能作爲防止C u之擴散之緩衝 膜。又，形成下述之連接孔8d時，將矽氮化膜4b 1使 用作爲蝕刻止動件，蝕刻氧化矽4 b 2，然後蝕刻矽氮化 膜4 b 2加以除去。又，以C u系以外之導電材料構成較 厚導體膜6 L 2或埋入導體膜7 C 2時，不用矽氮化膜 4 b 1也可以。在該層間絕緣膜4 b之上部，形成有寬度 不同之配線用溝5c ，5d»配線用溝5c ，5d之深度 係相同，例如約0 . 3〜1 . ，較理想爲約〇 , 6 β m。又，配線用溝5 c之縱横比係例如約〇 . 1〜 1 . 0，考慮良好地埋入配線用導體膜時小於0 . 7者較 理想。又，配線用溝5 d之縱橫比係例如約0 . 5〜 2 · 5，考慮良好地埋入配線用導體膜時小於1 . 5者較 理想。 氧化矽膜4b 2係例如以CVD法所形成的TEOS 膜或SOG膜所構成。使用低介會係數之S 0 G ( Spin on Glass )膜，可減低配線間的電容，並可提高電路之動作速 度。 本紙張尺度適用中囷國家標準（CNS)A4規格（210 X 297公t ) 請 先-閱 讀 背 面 之 注 意 事 項 t裝 頁 訂 線 經濟部智慧財產局具工消費合作社印製 -17- Λ ) J 3 4· ^ A7 _B7__ 五、發明說明（15 ) 在該配線用溝5 c ’ 5d內，如第1圖及第6圓所.示 ，以埋入狀態形成有第2層配線9 L ·該第2層配線9 L 係由下部與側部之相對地較薄的導體膜9 L 1，及被該較 薄導體膜9 L 1所圍繞之相對地較厚的導體膜9 L 2所構 成。 較薄導體膜9 L 1係由具有提高第2層配線9 L與層 間絕緣膜4 b之密接性的功能或抑制較厚導體膜9 L 2之 構成原子之擴制的阻障功能的材料所構成，例如由W， TiN，Ta，WN，WSiN，TiSiN，TaI^ T a S i N等所構成。 以W等構成薄膜導體膜9L1時，與以TiN，Ti ，Ta ，"\^1''1,'\^811''1，1'1811^，丁31''1或 T a S i N等所構成之情形相比較，成爲可降低配線電阻 。雖並未特別地被限定，惟在本實施例1中，較薄導體膜 9 L 1係以例如T i N所構成。 又，較厚導體膜9 L 2係構成第2層配線9 L之本體 的構件，例如A1 ，A1合金，W，以合金，Cu或Cu 合金之低電阻之材料所構成。以C u或C合金構成該較厚 導體膜9 L 2時，與以A 1或W構成時相比較，成爲可大 幅度降低配線電阻。又，與A i或A 1合金構成較厚導體 膜9 L 2時相比較，也成爲可提高第2層配線9 L之EM 耐性。雖並未特別地被限定，惟在本實施形態中，較厚導 體膜9L2以例如Cu所構成。 但是，第2層配線9 L之構造也並未被限定在表示於 -------------裝 i I! 訂· ！ ! I 線 <請先W讀背面之注意事項再t vr本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準<CNS)A4規格（210 X 297公；g ) -18- 4 5 '9 3 4 2 A7 B7 五、發明說明（仍） 第1圖及第6圖之構造者而可做各種欒更。例如表示於以 上述第1層配線6 L所說明之第3圖至第5圖的構造也可 以。亦即，在較厚導體膜9 L 2及較薄導體膜9 L 1之上 面設置帽蓋導體膜之構造也可以*該帽蓋導體膜係例如W 等之低電阻材料或具有TiN，Ti ，Ta，WN， WS iN，Ti S iN，TaN 或 Ta S iN等之阻障功 能的材料所構成。該構造係特別適用在以C ii或C ii合金 構成較厚導體膜9 L 2時，由於可更抑制Cii原子之擴散 ，因此，成爲可更提高半導體積體電路裝置之可靠性。又 ，雖並未特別被限定，惟與上層之配線材料之關係。適用 於直接接觸該配線材料與較厚導體膜9 L 2時會形成較高 電阻係數之合金等的情形·>又將帽蓋導體膜之上面與層間 絕緣膜4 a之上面大約一致地將帽蓋導體膜僅設在較厚導 體膜9 L 2之上面的構造也可以。 作爲其他構造，僅以較厚導體膜9 L 2構成第2層配 線9 L之構造也可以。亦即，沒有較薄之導體膜的構造， 又，作爲其他之構造，在沒有該較薄導體膜之構造下，在 較厚導體膜9 L 2之上面設置帽蓋導體膜之構造也可以。 該構造係並未特別被限定，惟與上層之配線材料之關係， 適用於直接接觸該配線材料與較厚導體膜9 L 2時會形成 高固有電阻値之合金等的情形。 形成於該配線用溝5 c內的第2層配線9 L係經連接 用導體部1 0 C而與第1層配線6 L電氣式地連接。連接 用導體部1 0 C係其大部分埋入在從配線用溝5 C之底面 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） — — — — — — — I* 裝 i I (請先閱讀背面之沒意事項再(、本頁) 訂· *線· 經濟部智慧財產局員工消费合作社印製 •19- 經濟部智慧財產局員工消費合作社印製 4 59 34 2 五、發明說明（]7) 向第1層配線6 L上面且穿孔於層間絕緣膜4 b之連接孔 8 b內，惟連接用導體部1 〇 c之上部係突出於第2層配 線9 L中成爲貫穿第2層配線9 L之上下面之狀態。連接 孔8b之直徑係例如約〇 . 2〜1 . ，較理想爲例 如約0 4vm。又，連接孔8b之縱橫比係約2〜6， 考慮良好地實行連接用導體部之埋入時，則小於4較理想 。又，連接用導體部1 0 C之上面高度係與第2層配線 9 L之上面高度大約一致，亦即，與層間絕緣膜4 b之上 面闻度大約一致* 連接用導體部1 0 C係由在其下部與側部之相對地較 薄導體膜1 0 C 1 ，及被較薄導體膜1 0 C 1所圍繞之相 對地較厚導體膜1 〇 C 2所構成。較薄導體膜1 0 c 1係 具有提高連接用導體部1 0 C與層間絕緣膜4 b密接性的 功能或抑制較厚導體膜1 〇 C 2之構成原子之擴散的阻障 功能的材料所構成，例如W，TiN，Ti ，Ta ，WN ，WS iN，Ti S iN，TaN 或 Ta S iN 等所構成 ο 以w等構成較薄導體膜loci時，與以TiN »Matters I Ⅰ Page Binding Binding The size of the private paper is applicable to the Chinese National Standard (CNS) A4 (210 * 297 mm) 15- A7 B7 459342 5. The invention is composed of materials that are resistant to resistance. The constituent material of the thicker conductor film 7 C 2 is not made of Cu or Cu alloy. That is, in the first embodiment, even if the constituent material of the buried conductor film 6 L 2 of the first layer wiring 6 L is Cu or Cu alloy, the connection conductor portion that is in direct contact with the semiconductor substrate 1 is used. 7 C is not made of Cu or Cu alloy. This reduces the wiring resistance of the first-layer wiring 6 L, and suppresses the connection failure due to the diffusion of Cu atoms to the semiconductor substrate side. When the thick conductor film 7C2 is made of A 1 or A 1 alloy, the resistance of the connection conductor portion 7 C can be reduced compared with the case where it is made of W or W alloy. In addition, when the buried conductor film 7 C 2 is formed of W or W alloy, the EM resistance of the conductor portion 7 C for connection can be improved when compared with the case where the buried conductor film 7C 2 is formed of AI or A 1 alloy. And SM patience. Although not limited, in the first embodiment, the thick conductive film 7 C 2 is made of, for example, W. Therefore, in the first embodiment, a different type of conductor film (Cu and the like for forming the first layer wiring 6 L, and a connecting conductor portion 7 C) is formed on the plane of the height position of the first layer wiring 6 L. Of W, etc.). Also, the conductor part for connection is also constituted. In the above description, the case where the first-layer wiring 6L in the wiring grooves 5a and 5b is made of the same material is not limited. For example, the constituent materials of the thicker conductor film 6 L 2 and the thinner conductor film 6 L 1 buried in the wiring groove 5 b are the same as the thicker conductor film 6 L 2 and the buried conductor groove 5 a. The constituent material of the thin conductive film 6 L 1 may be a different conductive material. For example, when Cu is buried in a wide wiring groove 5 a and a narrow wiring groove 5 b at the same time, it is because of the narrow wiring !!!! Install --- (Please read the precautions on the back again {ί This page) Order--Line · Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperatives, this paper is used in Chinese National Standards (CNS) A4 (210 * 297 g)-16- A7 B7 V. Description of the invention (M) The trench 5 b may not be sufficiently embedded. Therefore, at this time, the wide wiring trench 5 a is buried with Cu, and the narrow wiring trench 5 b is passed through the C VD method. Structure example for the case of embedding W, etc. Also, the formation method at this time is as follows' On the interlayer insulating film 4a, for example, a silicon nitride film 4 6 1 is formed thicker than the silicon nitride film Interlayer insulating film 4 b of silicon oxide 4 4 2. The silicon nitride film 4 b l is a buffer film that prevents the diffusion of Cu when the thick conductor film 6 L 2 or the buried conductor film 7 C 2 is made of a C U-based conductive material. When the following connection hole 8d is formed, the silicon nitride film 4b 1 is used as an etching stopper, the silicon oxide 4 b 2 is etched, and then the silicon nitride film 4 b 2 is etched and removed. When the thick conductive film 6 L 2 or the buried conductive film 7 C 2 is formed of a conductive material other than the Cu-based material, the silicon nitride film 4 b 1 may not be used. On the upper part of the interlayer insulating film 4b, wiring grooves 5c and 5d with different widths are formed. The depths of the wiring grooves 5c and 5d are the same, for example, about 0.3 to 1., and more preferably about 0, 6 β. m. The aspect ratio of the wiring trench 5 c is, for example, about 0.1 to 1.0, and it is preferable to consider that the wiring trench 5 c is less than 0.7 when well embedded in the wiring conductor film. The aspect ratio of the wiring groove 5 d is, for example, about 0.5 to 2 · 5, and it is preferable to consider that the wiring groove film is less than 1.5 when well embedded in the wiring conductor film. The silicon oxide film 4b 2 is composed of, for example, a TEOS film or an SOG film formed by a CVD method. The use of a S 0 G (Spin on Glass) film with a low dielectric coefficient can reduce the capacitance between wirings and increase the speed of the circuit. This paper size applies the China National Standard (CNS) A4 specification (210 X 297 g t). Please read the note on the back first. T Binding Line Printed by the Industrial Property Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs -17- Λ) J 3 4 · ^ A7 _B7__ V. Description of the invention (15) Within the wiring trench 5 c '5d, as shown in Fig. 1 and the sixth circle, a second-layer wiring 9 L is formed in a buried state. · The second-layer wiring 9 L is composed of a relatively thin conductor film 9 L 1 at the lower portion and a side portion, and a relatively thick conductor film 9 L 2 surrounded by the thin conductor film 9 L 1. The thinner conductive film 9 L 1 is made of a material having a function of improving the adhesion between the second-layer wiring 9 L and the interlayer insulating film 4 b or a barrier function that suppresses the expansion of the constituent atoms of the thicker conductive film 9 L 2. The structure is composed of, for example, W, TiN, Ta, WN, WSiN, TiSiN, TaI ^ T a S i N and the like. When the thin film conductor film 9L1 is formed with W or the like, it is different from TiN, Ti, Ta, " \ ^ 1''1, '\ ^ 811''1, 1'1811 ^, D31''1, or T a S i Compared with the case of N, the wiring resistance can be reduced. Although not particularly limited, in the first embodiment, the thinner conductive film 9 L 1 is made of, for example, T i N. Further, the thicker conductor film 9 L 2 is a member constituting the body of the second-layer wiring 9 L, such as A1, A1 alloy, W, and is made of a low-resistance material of alloy, Cu, or Cu alloy. When the thick conductive film 9 L 2 is made of Cu or C alloy, the wiring resistance can be reduced significantly compared to when it is made of A 1 or W. In addition, it is possible to improve the EM resistance of the second-layer wiring 9 L as compared with the case where the A i or A 1 alloy constitutes a thicker conductor film 9 L 2. Although not particularly limited, in this embodiment, the thick conductive film 9L2 is made of, for example, Cu. However, the structure of the second-layer wiring 9 L is not limited to that shown in ------------- install i I! Order! I-line < Please read the precautions on the back before t vr page) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Employee Consumer Cooperatives This paper is printed in accordance with Chinese National Standards < CNS) A4 (210 X 297 male; g) -18- 4 5 '9 3 4 2 A7 B7 V. Description of the invention (still) The constructors of Figure 1 and Figure 6 can make various changes. For example, the structures shown in FIGS. 3 to 5 described with the first layer wiring 6L may be used. That is, a structure in which a cap conductor film is provided on the thicker conductor film 9 L 2 and the thinner conductor film 9 L 1 may also be used. The cap conductor film is a low-resistance material such as W or has TiN, Ti, Ta, WN, WS iN, Ti S iN, TaN or Ta S iN. This structure is particularly suitable when the C ii or C ii alloy is used to form a thicker conductor film 9 L 2. Since the diffusion of Cii atoms can be more suppressed, the reliability of the semiconductor integrated circuit device can be further improved. Also, although it is not particularly limited, it has a relationship with an upper wiring material. Applicable to the case where the wiring material and the thicker conductor film 9 L 2 are directly in contact with each other, and an alloy with a higher resistivity will be formed. A structure in which the cap conductor film is provided only on the thicker conductor film 9 L 2 is also possible. As another structure, a structure in which the second-layer wiring 9 L is composed of only the thick conductive film 9 L 2 may be used. That is, there is no structure having a thinner conductor film, and as another structure, without the thinner conductor film structure, a structure in which a cap conductor film is provided on the thicker conductor film 9 L 2 may be used. This structure is not particularly limited, but the relationship with the upper wiring material is suitable for the case where an alloy with a high specific resistance is formed when the wiring material and the thick conductor film 9 L 2 are directly contacted. The second-layer wiring 9 L formed in the wiring groove 5 c is electrically connected to the first-layer wiring 6 L via the connection conductor portion 10 C. The connection conductor part 10 C is mostly embedded in the bottom surface of the wiring groove 5 C. The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) — — — — — — — I * Install i I (please read the unintentional matter on the back before (, this page)) Order * * Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs • 19- Printed by the Employee Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 59 34 2 V. Description of the invention () 7) The first layer of wiring 6 L is perforated in the connection hole 8 b of the interlayer insulating film 4 b, but the upper part of the connecting conductor portion 10 c protrudes from the second layer of wiring 9 L The middle is a state penetrating above and below the second-layer wiring 9 L. The diameter of the connection hole 8b is, for example, about 0.2 to 1. More preferably, it is, for example, about 0 to 4 vm. The aspect ratio of the connection hole 8b is about 2 to 6. When the embedding of the connection conductor portion is considered to be good, it is preferably less than 4. The height of the upper surface of the connection conductor portion 10 C is approximately the same as the height of the second layer wiring 9 L, that is, It is approximately the same as the upper surface of the interlayer insulating film 4 b. The relatively thinner conductor film 1 0 C 1 on the side and the relatively thicker conductor film 1 0C 2 surrounded by the thinner conductor film 1 0 C 1. The thinner conductor film 1 0 c 1 has A material that improves the adhesion between the conductor portion 10 C for connection and the interlayer insulating film 4 b or a barrier function that suppresses the diffusion of constituent atoms of a thicker conductor film 10 C 2, such as W, TiN, Ti, Ta , WN, WS iN, Ti S iN, TaN or Ta S iN, etc. ο When thin conductor film loci is formed by w, etc., with TiN »
Ti，Ta，WN，WSiN，TiSiN，TalS^ T a S i N等構成時相比較，成爲可降低配線電阻。雖並 未特別被限定，惟在本實施形態1中，較薄導體膜 1 0 C 1係以例如W所構成。 又，較厚導體膜1 〇 C 2係構成連接用導體部1 〇 c 之本體的構件。例如A1 ，A1合金’W’W合金’Cu 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公楚） -20 " — — — — — — ί — — — ^ — — — —11— « — — — — — — It (請it.閲讀背面之注意事項再{ 6本頁) 經濟部智慧財產局員工消費合作社印製 五、發明說明（I8 ) 或c U合金等之低電阻的材料所構成•介經以例如c υ或 Cu合金構成較厚導體膜10C2,與以A1 ，Ai合金 ，W或W合金所構成之情形相比較，可降低連接用導體部 1 ◦ C之電阻，且可提高連接用導體部1 0 C之EM耐性 。以A 1或A 1合金構成較厚導體膜1 0C2時，與以W 或W合金構成時相比較，成爲可降低連接用導體部1 0 C 之電阻。又，以W或W合金構成較厚導體膜10C2時， 與以A 1或A 1合金構成較厚導體膜1 0 C2時相比較， 成爲可提高連接用導體部1 0 C之EM耐性及SM耐性。 雖並未特別被限定，惟在本實施形態1中，較厚導體膜 1 0 C 2係由例如W所構成。 又，在層間絕緣膜4b，從其上面向第1層配線6L 上面穿孔而穿孔有使第1層配線6 L之一部露出的連接孔 8 C，而在該連接孔8 C以埋入狀態形成有連接用導體部 1 0 C。該連接孔8 C之直徑係例如約0 . 2〜1 · 2 /zm，較理想爲例如約〇 · 4//m。又，連接孔8C之縱 橫比係約2〜6，而考慮良好地實行連接用導體部之埋入 時，小於約4較理想。該連接用導體部1 0 C係構造與上 述者相同，惟在第1圖中》與第2層配線9 L並未直接連 接。但是，將埋入於連接孔8C之連接用導體部10C之 較厚導體膜1 0 C 2及較薄導體膜1 0 C 1的構成材料， 與埋入於連接孔8 b之連接用導體部1 0 C之較厚導體膜 1 0 C 2及較薄導體膜1 0 C 1之構成材料係以異種之導 體材料所構成也可以。 本紙張尺度適用中國國家標準（CNS)A4規格（2〗0* 297公a ) — — —— — — — — — — — — — — — — — — — « — —If— — — * (請Λ..]»讀背面之注意事項再1···.本頁) 經濟部智慧財產局員工消f合作杜印5衣 4. b tj 34 c- μ __B7____ 五、發明說明（I9 ) 又，在上述之說明針對配線用溝5 c，5 d內之第2 層配線9 L以相同材料所構成時加以說明，惟並未被限定 於此者，例如將埋入於配線用溝5 d之較厚導體膜9 L 2 及較薄導體膜9 L 1之構成材料與埋入於配線用溝5 C之 較厚導體膜9 L 2及較薄導體膜9 L 1之構成材料以異種 之導體材料所構成較理想。此乃若將C u等同時地埋入例 如寬廣之配線用溝5 C及寬窄之配線用溝5 d內時，由於 有無法充分地埋入寬窄之配線用溝5 d，因此，在此時， 寬廣之配線用溝5 C係以C u埋入，而寬窄之配線用溝 5 d係介經C VD法等埋入W等之情形的構造例·又此時 之形成方法將如下述。 在層間絕緣膜4 b上，形成有例如與層間絕緣膜4 b 同樣地以氮化矽膜4 C 1與氧化矽膜4 C 2所構成的層間 絕緣膜4 C。在該層間絕緣膜4 C之上部，形成有寬度不 同之配線用溝5e ，5ί ，配線用溝5e ，5f之深度係 相同。例如約0 · 3〜1 . 0//m，較理想是約〇 · 6 /zm。又，配線用溝5e之縱橫比係例如約〇 . 1〜 1 . 0 *考慮良好地埋入配線用導體膜時•比0 . 7小者 較理想。又，配線用溝5 f之縱橫比係例如約0 . 5〜 2 . 5，考慮良好地埋入配線用導體膜時，比1 . 5小者 較理想。 在該配線用溝5e * 5f內，如第1圖所示，以埋入 狀態形成有第3層配線1 1L。該第3層配線1 1L係下 部與側部之相對地較薄導體膜1 1 L 1，及被該較薄導體 — — — — — — — — — — — — — * — — — — — — — ·11111111 (請先閱讀背面之注意事項再'心本頁> 本紙張尺度適用中國國家標準（CNS)A4規格（2〗0 X 297公釐） -22- 4 5 9 34 2 a? B7 五、發明說明（2〇) 膜11L1所圍繞之相對地較厚導體膜11L2所構成· 較薄導體膜11L1係具有提高第3層配線11L與 層間絕緣膜4 C之密接性的功能或抑制較厚導體膜 1 1 L 2之構成原子之擴散的阻障功能的材料所構成，例Ti, Ta, WN, WSiN, TiSiN, TalS ^ TaSiN, etc. can reduce wiring resistance when compared. Although not particularly limited, in the first embodiment, the thin conductive film 10 C 1 is made of, for example, W. The thicker conductive film 10 C 2 is a member constituting the body of the connecting conductor portion 10 c. For example, A1, A1 alloy 'W'W alloy' Cu This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 Gongchu) -20 " — — — — — — ί — — — ^ — — — — 11— «— — — — — — — It (please read the notes on the back and then {6 pages) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Low resistance of invention (I8) or c U alloy Made of a material made of a thicker conductor film 10C2 with, for example, c υ or Cu alloy, compared to the case of A1, Ai alloy, W, or W alloy, which can reduce the resistance of the conductor portion 1 ◦ C , And can improve the EM resistance of the conductor portion 10 C for connection. When the thicker conductor film 10C2 is made of A1 or A1 alloy, the resistance of the conductor portion 10C for connection can be reduced compared to when it is made of W or W alloy. When the thicker conductor film 10C2 is formed of W or W alloy, the EM resistance and SM of the conductor portion 10 C for connection can be improved compared to when the thicker conductor film 10 C2 is made of A 1 or A 1 alloy. patience. Although not particularly limited, in the first embodiment, the thick conductive film 10 C 2 is made of, for example, W. Further, a connection hole 8C is exposed in the interlayer insulating film 4b from above to the first layer wiring 6L, and a part of the first layer wiring 6L is exposed, and the connection hole 8C is buried. A connection conductor portion 10 C is formed. The diameter of the connection hole 8 C is, for example, about 0.2 to 1 · 2 / zm, and more preferably, it is, for example, about 0.4 // m. In addition, the aspect ratio of the connection hole 8C is about 2 to 6, and it is preferable that it is less than about 4 when the embedding of the connection conductor portion is performed well. The structure of the connecting conductor portion 10 C is the same as that described above, but in the first figure, the second-layer wiring 9 L is not directly connected. However, the constituent materials of the thicker conductor film 1 0 C 2 and the thinner conductor film 10 C 1 buried in the connection conductor portion 10C of the connection hole 8C and the connection conductor portion buried in the connection hole 8 b are used. The thicker conductive film 1 0 C 2 of 1 0 C and the thinner conductive film 10 C 1 may be made of different conductive materials. This paper size applies to China National Standard (CNS) A4 specifications (2〗 0 * 297 公 a) — — — — — — — — — — — — — — — — — — — — — — — — — (* Λ ..] »Read the notes on the back again ... 1. This page) The staff of the Intellectual Property Bureau of the Ministry of Economic Affairs has cooperated with Du Yin 5 clothing 4. b tj 34 c- μ __B7____ 5. Explanation of the invention (I9) In the above description, when the second layer wiring 9 L in the wiring trench 5 c, 5 d is made of the same material, it is not limited to this. For example, it is buried in the wiring trench 5 d. The constituent materials of the thicker conductor film 9 L 2 and the thinner conductor film 9 L 1 and the constituent materials of the thicker conductor film 9 L 2 and the thinner conductor film 9 L 1 embedded in the wiring groove 5 C are different types of conductors The composition of the material is ideal. This is because if Cu and the like are buried simultaneously in, for example, a wide wiring groove 5 C and a narrow wiring groove 5 d, it is impossible to fully bury the narrow wiring groove 5 d. Therefore, at this time, The wide wiring trench 5 C is buried with Cu, and the narrow wiring trench 5 d is buried in the W etc. via the C VD method. The formation method at this time will be as follows. On the interlayer insulating film 4b, for example, an interlayer insulating film 4C composed of a silicon nitride film 4C1 and a silicon oxide film 4C2 is formed similarly to the interlayer insulating film 4b. On the upper part of the interlayer insulating film 4C, wiring grooves 5e, 5ί having different widths are formed, and the wiring grooves 5e, 5f have the same depth. For example, about 0.3 to 1.0 // m, and preferably about 0.6 / zm. The aspect ratio of the wiring groove 5e is, for example, about 0.1 to 1.0. * When the wiring conductor film for wiring is considered to be well buried, it is more desirable than 0.7. The aspect ratio of the wiring trench 5 f is, for example, about 0.5 to 2.5. When the wiring conductor film is considered to be well embedded, it is preferable to be smaller than 1.5. In this wiring groove 5e * 5f, as shown in Fig. 1, a third layer wiring 11L is formed in a buried state. The third layer wiring 1 1L is a relatively thin conductor film 1 1 L 1 at the lower portion and the side portion, and is connected by the thinner conductor — — — — — — — — — — — — — — — — — — — — — — · 11111111 (Please read the precautions on the back of the page before 'Heart Page> This paper size is applicable to China National Standard (CNS) A4 specifications (2〗 0 X 297 mm) -22- 4 5 9 34 2 a? B7 V. Description of the invention (20) The relatively thick conductive film 11L2 surrounded by the film 11L1 is made of a thinner conductive film 11L1, which has the function of improving the adhesion between the third layer wiring 11L and the interlayer insulating film 4 C or suppressing A thick conductor film 1 1 L 2 is made of a material constituting the barrier function of the diffusion of atoms, for example
Ti S iN，TaN或Ta S iN等所構成。 在以W等構成較薄導體膜1 1 L 1時，與以T i N， Ti ，Ta，WN，WSiN，TiSiN*Tal^ T a S i N等所構成時相比較成爲可降低配線電阻。又， 在以TiN，Ti ，Ta ，WN，WSiN，TiSiN ，丁 aN或TaS iN等構成較薄導體膜1 1L1時，成 爲特別是提高與層間絕緣膜4 C之密接性。雖並不被特別 限定，惟在本實施形態1，較薄導體膜11L1·係由例 如T i N所構成。 又，較厚導體膜11L2係構成第3層配線11L之 本體的構件，例如A 1 ，A 1合金，W，W合金，Cu或 C u合金之低電阻的材料所構成。在以C u或C u合金構 成該較厚導體膜1 1 L 2時，與以A 1或W構成時相比較 1成爲可大幅地降低配線電阻。又|在以A 1或A 1合金 構成較厚導體膜1 1 L 2時相比較，成爲可提高第3層配 線1 1L之EM耐性。雖並不被特別限定，惟在本實施形 態1，較厚導體膜1 1L2 *係由例如Cii所構成。 但是，第3層配線1 1 L之構造也並未被限定在表示 於第1圖之構造者而可做各種變更。例如表示於以上述第 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） — It — — — — —— — — — — ' I I {請it.M讀背面之注意事項再本I) 訂： ’·線· 經濟部智慧財產局員工消費合作社印製 -23- 4 5 Β 34 2 Α7 Β7 五、發明說明（.21 ) 1層配線6 L所說明之第3圖至第5圖的構造也可以。亦 即’在較厚導體膜11L2及較薄導體膜11L1之上面 設置帽蓋導體膜之構造也可以。該帽蓋導體膜係例如W等 之低電阻材料或具有TiN，Ti ’Ta，WN’ ws i N，Ti S i N * TaN或 Ta S iN 等之阻障功 能的材料所構成。該構造係特別適用在以C u或C u合金 構成較厚導體膜1 1 L 2時，由於可更抑制C u原子之擴 散，因此，成爲可更提高半導體積體電路裝置之可靠性· 又，雖並未特別被限定，惟與上層之配線材料之關係。適 用於直接接觸該配線材料與較厚導體膜1 1 L 2時會形成 較高電阻係數之合金等的情形。又將帽蓋導體膜之上面與 層間絕緣膜4 a之上面大約一致地將帽蓋導體膜僅設在較 厚導體膜1 1 L 2之上面的構造也可以。 作爲其他構造，僅以較厚導體膜1 1 L 2構成第3層 配線1 1 L之構造也可以。亦即，沒有較薄之導體膜的構 造，又，作爲其他之構造，在沒有該較薄導體膜之構造下 ，在配線用溝5 a之上面設置帽蓋導體膜之構造也可以》 該構造係並未特別被限定，惟與上層之線材料之關係* 適用於直接接觸該配線材料與較厚導體膜1 1 L 2時會形 成高固有電阻値之合金等的情形。 形成於該配線用溝5 e ，5 f內的第2層配線1 1 L 係經連接用導體部1 2 C而與第2層配線9 L電氣式地連 接》連接用導體部1 2 C係其大部分埋入在從配線用溝 5 e，5 ί之底面向第2層配線9 L上面且穿孔於層間絕 本紙張尺度適用中囤國家標準（CNS)A4規格（2】0 X 297公爱） -------------裝—— 請先W讀背面之注意事項再C.S本頁) 訂· -線. 經濟部智慧財產局員工消費合作杜印製 ^ 6 9 34 2 五、發明說明（22) 緣膜4 c之連接孔8 d內，惟連接用導體部1 2 C之上部 係突出於第3層配線1 1 L中成爲貫穿第3層配線1 1 L 之上下面之狀態·連接孔8d之直徑係例如約0.2〜 1 _ 較理想爲例如約0 . 4#m。又，連接孔 8 d之縱橫比係約2〜6，考慮良好地實行連接用導體部 之埋入時，則小於4較理想。又，連接用導體部1 2C之 上面高度保與第3層配線1 1 L之上面高度大約一致，亦 即，與層間絕緣膜4 c之上面高度大約一致。 連接用導體部1 2 C係由在其下部與側部之相對地較 薄導體膜12C1，及被較薄導體膜12C1所圍繞之相 對地較厚導體膜1 2 C 2所構成。較薄導體膜1 2 C 1係 具有提高連接用導體部1 2 C與層間絕緣膜4 c密接性的 功能或抑制較厚導體膜1 2 C 2之構成原子之擴散的阻障 功能的材料所構成，例如W，TiN，Ti ，Ta ’WN ，WS iN，Ti S iN，TaN 或 TaS iN 等所構成 ο 以w等構成較薄導體膜1 2 c 1時，與以τ i N，Ti S iN, TaN or Ta S iN. When the thin conductive film 1 1 L 1 is made of W or the like, the wiring resistance can be reduced compared with the case where it is made of T i N, Ti, Ta, WN, WSiN, TiSiN * Tal ^ T a S i N or the like. When the thin conductor film 11L1 is made of TiN, Ti, Ta, WN, WSiN, TiSiN, butan or TaSiN, etc., the adhesion to the interlayer insulating film 4C is particularly improved. Although not particularly limited, in the first embodiment, the thin conductive film 11L1 · is made of, for example, T i N. Further, the thicker conductor film 11L2 is a member constituting the body of the third layer wiring 11L, for example, a material having a low resistance such as A 1, A 1 alloy, W, W alloy, Cu, or Cu alloy. When the thick conductor film 1 1 L 2 is formed of Cu or Cu alloy, the wiring resistance 1 can be significantly reduced as compared with the case of A 1 or W. In addition, when the thicker conductor film 1 1 L 2 is made of A 1 or A 1 alloy, the EM resistance of the third layer wiring 11 1 can be improved. Although not particularly limited, in the first embodiment, the thicker conductor film 11L2 * is made of, for example, Cii. However, the structure of the third layer wiring 1 1 L is not limited to the structure shown in FIG. 1 and various changes can be made. For example, it is indicated that the Chinese National Standard (CNS) A4 specification (210 X 297 mm) is applied to the above paper size. — It — — — — — — — — — 'II {Please read the precautions on the back again Book I) Order: '· Line · Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs-23- 4 5 Β 34 2 Α7 Β7 V. Description of the invention (.21) 1 layer wiring 6 L 3rd to 3rd illustrations The structure of Fig. 5 is also possible. That is, a structure in which a cap conductor film is provided on the thicker conductor film 11L2 and the thinner conductor film 11L1. The cap conductor film is made of a low-resistance material such as W or a material having a barrier function such as TiN, Ti'Ta, WN 'ws i N, Ti S i N * TaN, or Ta S iN. This structure is particularly suitable when Cu or Cu alloy is used to form a thicker conductor film 1 1 L 2. Since the diffusion of Cu atoms can be more suppressed, the reliability of a semiconductor integrated circuit device can be further improved. Although not particularly limited, it has a relationship with the wiring material of the upper layer. It is suitable for the case where the wiring material and the thicker conductor film 1 1 L 2 are in direct contact with each other, which will form an alloy with a higher resistivity. A structure in which the upper surface of the cap conductor film and the upper surface of the interlayer insulating film 4a are approximately the same and the cap conductor film is provided only on the thicker conductor film 1 1 L 2 may be used. As another structure, a structure in which the third-layer wiring 1 1 L is composed of only a thick conductive film 1 1 L 2 may be used. That is, there is no structure with a thinner conductor film, and as another structure, without the thinner conductor film structure, a structure in which a cap conductor film is provided on the wiring groove 5a may be used. The system is not particularly limited, but the relationship with the upper wire material * is applicable to the case where an alloy with high intrinsic resistance is formed when the wiring material and the thick conductor film 1 1 L 2 are directly contacted. The second-layer wiring 1 1 L formed in the wiring grooves 5 e and 5 f is electrically connected to the second-layer wiring 9 L via the connection conductor portion 1 2 C. The connection conductor portion 1 2 C system Most of it is buried from the bottom of the wiring groove 5 e, 5 liter to the second layer wiring 9 L and perforated between the layers. The paper standard is applicable to the national standard (CNS) A4 specification (2) 0 X 297. Love) ------------- Installation—— Please read the precautions on the back before CS page) Order · -line. Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs for consumer cooperation DU 6 9 34 2 V. Description of the invention (22) In the connection hole 8 d of the edge film 4 c, the upper part of the connecting conductor portion 1 2 C protrudes from the third layer wiring 1 1 L to become the third layer wiring 1 1 L The diameter of the connection hole 8d is, for example, about 0.2 to 1 _, and is preferably about 0.4 #m, for example. The aspect ratio of the connection hole 8 d is about 2 to 6, and it is preferable that the connection conductor portion be embedded well, and it is preferably less than 4. The height of the upper surface of the connecting conductor portion 12C is approximately the same as that of the third layer wiring 1 1L, that is, approximately the same as the height of the upper surface of the interlayer insulating film 4c. The connecting conductor portion 1 2 C is composed of a relatively thin conductor film 12C1 at a lower portion and a side portion thereof, and a relatively thick conductor film 1 2 C 2 surrounded by the thinner conductor film 12C1. The thinner conductor film 1 2 C 1 is a material having a function of improving the adhesion between the conductor portion 1 2 C for connection and the interlayer insulating film 4 c or a barrier function of suppressing the diffusion of constituent atoms of the thicker conductor film 1 2 C 2. For example, W, TiN, Ti, Ta'WN, WS iN, Ti S iN, TaN, or TaS iN, etc. When a thin conductor film 1 2 c 1 is formed with w or the like, and τ i N,
Ti ，Ta，WN，WSiN，TiSiN，TaN* T a S i N等構成時相比較，成爲可降低配線電阻。雖並 未特別被限定，惟在本實施形態1中，較薄導體膜 1 2 C 1係以例如w所構成。 又，較厚導體膜1 2 C 2係構成連接用導體部1 2 c 之本體的構件。例如A1 ，A1合金，W’W合金’Cu 或C u合金等之低電阻的材料所構成。介經以例如C u或 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐> --------------裝— {請先《讀背面之注意事項再{*·.本頁) 訂·· •線 經濟部智慧財產局員工消费合作社印製 -25- 4 5^3^2 A7 B7 五、發明說明（23)Ti, Ta, WN, WSiN, TiSiN, TaN * Ta Si N, etc. can reduce wiring resistance when compared. Although not particularly limited, in the first embodiment, the thin conductive film 1 2 C 1 is made of, for example, w. The thick conductor film 1 2 C 2 is a member constituting the body of the connection conductor portion 1 2 c. For example, A1, A1 alloy, W'W alloy 'Cu or Cu alloy and other low resistance materials. Through the application of, for example, Cu or this paper size, the Chinese National Standard (CNS) A4 specification (210 X 297 mm) is installed. -------------- Installation — {Please read the Matters needing attention again (* .. This page) Order ·· • Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs -25- 4 5 ^ 3 ^ 2 A7 B7 V. Description of Invention (23)
Cu合金構成較厚導體膜1 2C2，與以A 1，A 1合金 ，界或，合金所構成之情形相比較，可降低連接用導體部 1 2 C之電阻，且可提高連接用導體部1 2 C之EM耐性 。以A 1或A 1合金構成較厚導體膜1 2C2時，與以W 或W合金構成時相比較，成爲可降低連接用導體部1 2 C 之電阻。又，以W或W合金構成較厚導體膜1 2 C 2時， 與以A 1或A 1合金構成較厚導體膜1 2C2時相比較， 成爲可提高連接用導體部1 2 C之EM耐性及S M ( Stress Migration )耐性。雖並未特別被限定，惟在本實施形態1 中，較厚導體膜1 2 C 2係由例如W所構成。 又，在層間絕緣膜4 c，從其上面向第2層配線9 L 上面穿孔而穿孔有使第2層配線9 L之一部露出的連接孔 8 e ，而在該連接孔8 e以埋入狀態形成有連接用導體部 12C »該連接孔8e之直徑係例如約〇 · 2〜1 . 2 //m，較理想爲例如約〇 . 又，連接孔8e之縱 橫比係約2〜6，而考慮良好地實行連接用導體部之埋入 時，小於約4較理想。該連接用導體部1 2 C係構造與上 述者相同，惟在第1圖中，與第3層配線1 1 L並未直接 連接。又，該連接用導體部1 2 c係與形成於下層連接孔 8 c內的連接用導體部1 〇 c連接而電氣式地連接。亦即 ，在本實施形態1中，在具有埋入配線構造的配線層中· 具有連接用導體部1 0 c ，1 2 c彼此間以貫穿所定配線 層之狀態下互相地電氣式地連接的構造- 介經將連接用導體部1 2 c以與連接用導體部1 〇 c 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -26- -----裝 ί· <請先《讀背面之注意事項再f寫本頁) 訂·· -線 經濟郤智慧財產局員工消費合作社印製 A7 459 34 2 ___B7___ 五、發明說明（24) 相同構成材料所形成·故可降低連接限力。亦即，由於將 連接用導體部1 0 C與1 2 c間，與經由以不同導體材料 所構成之第2層配線9 L連接時相比較•可降低接觸電阻 等，因此，可降低連接電阻。 但是，將欲埋入於連接孔8 e之連接用導體部1 2 c 之較厚導體膜1 2 C 2與較薄導體膜1 2 C 1的構成材料 ，與埋入於連接孔8 e之連接用導體部1 2 C之較厚導體 膜1 2 C 2與較薄1 2 C 1的構成材料，以異種之導體材 料所構成也可以。 又，第1圖右邊之連接用導體部l〇C，12C彼此 間的連接構造係如第7圖所示，經貫穿層間絕緣膜4 c， 4 b之連接孔8 e 1內之一個連接用導體1 2 c直接電氣 地連接第3層配線1 1 L與第1層配線6 L的構造也可以 。€此，可降低連接電阻。 在層間絕緣膜4 c上，形成有與層間絕緣膜4 b同樣 地以氮化矽膜4 d 1與氧化矽4 d 2所構成的層間絕緣膜 4 d。在該層間絕緣膜4 d之上面，形成有第4層配線 1 3L。第4層配線1 3L，1 3L係由例如A 1或A 1 合金所構成，經貫穿於層間絕緣膜4 d之連接孔8 f， 8 f 1分別與下層之第3層配線1 1 L與連接用導體部 1 2 c電氣式地連接。 作爲最上面之第4層配線1 3 L的構成材料，介經使 用例如A 1或A 1合金等，仍直接使用以往就有之搭接線 端的連接技術或***電極的形成技術。亦即，最上面之配 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐〉 閱 讀 背 面 之 注 意The Cu alloy has a thicker conductor film 1 2C2, which can reduce the resistance of the connection conductor portion 1 2 C and increase the connection conductor portion 1 as compared with the case of A 1, A 1 alloy, boundary or alloy. 2 C EM resistance. When the thick conductor film 1 2C2 is made of A 1 or A 1 alloy, the resistance of the conductor portion 1 2 C for connection can be reduced compared with the case where it is made of W or W alloy. In addition, when the thicker conductor film 1 2 C 2 is made of W or W alloy, the EM resistance of the conductor portion 1 2 C for connection can be improved compared to when the thicker conductor film 1 2 C 2 is made of A 1 or A 1 alloy. And SM (Stress Migration) resistance. Although not particularly limited, in the first embodiment, the thick conductive film 1 2 C 2 is made of, for example, W. Further, a connection hole 8 e is formed in the interlayer insulating film 4 c from above to face the upper surface of the second layer wiring 9 L, and a portion of the second layer wiring 9 L is exposed, and the connection hole 8 e is buried. The connection conductor portion 12C is formed in the inserted state. The diameter of the connection hole 8e is, for example, about 0.2 to 1.2 [m], and preferably, for example, about 0.2. The aspect ratio of the connection hole 8e is about 2 to 6. However, when the embedding of the connection conductor portion is considered to be well performed, it is preferably less than about 4. The structure of the connecting conductor portion 12C is the same as that described above, but in the first figure, it is not directly connected to the third-layer wiring 1 1L. The connection conductor portion 12c is electrically connected to the connection conductor portion 10c formed in the lower-layer connection hole 8c. That is, in the first embodiment, in a wiring layer having a buried wiring structure, there are connecting conductor portions 1 0 c and 1 2 c electrically connected to each other in a state of penetrating a predetermined wiring layer. Structure-Connect the connecting conductor part 1 2 c to the connecting conductor part 1 〇 This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -26- ----- · ≪ Please read the notes on the back before writing this page) Order ·· -Printed by the Consumer Economics Cooperative of the Online Economics and Intellectual Property Bureau A7 459 34 2 ___B7___ V. Description of the invention (24) Formed by the same constituent materials Therefore, the connection limit force can be reduced. In other words, the connection resistance between the 10 C and 1 2 c conductors can be reduced compared to when connecting via the second layer wiring 9 L made of a different conductive material. . However, the constituent materials of the thicker conductor film 1 2 C 2 and the thinner conductor film 1 2 C 1 to be buried in the connection conductor portion 1 2 c of the connection hole 8 e and the connection material 8 2 e The constituent materials of the thicker conductor film 1 2 C 2 and the thinner 1 2 C 1 of the connection conductor portion 1 2 C may be made of different types of conductor materials. The connection structure between the connection conductor portions 10C and 12C on the right side of FIG. 1 is as shown in FIG. 7, and is connected through one of the connection holes 8 e 1 penetrating the interlayer insulating films 4 c and 4 b. The conductor 1 2 c may have a structure in which the third-layer wiring 1 1 L and the first-layer wiring 6 L are directly and electrically connected. This reduces the connection resistance. On the interlayer insulating film 4c, an interlayer insulating film 4d composed of a silicon nitride film 4d1 and a silicon oxide 4d2 is formed in the same manner as the interlayer insulating film 4b. On the interlayer insulating film 4d, a fourth layer wiring 13L is formed. The fourth layer wiring 1 3L is composed of, for example, A 1 or A 1 alloy, and passes through the connection holes 8 f and 8 f 1 penetrating through the interlayer insulating film 4 d and the lower layer wiring 1 1 L and The connection conductor portion 1 2 c is electrically connected. As a constituent material of the uppermost fourth layer wiring 1 3 L, for example, A 1 or A 1 alloy is directly used, and the connection technology of the conventional terminal connection or the formation technique of the bump electrode is directly used. That is, the top paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm). Read the note on the back
項 h ! I裝 I 訂 經濟部智慧財產局員工消費合作社印製 ΎΓItem h! I Pack I Order Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs ΎΓ
A7 B7 五、發明說明（25) 線層係連接有搭接線端或***電極，惟介經將最上面之配 線材料作爲以往就使用A 1或A 1合金，成爲可仍然使用 搭接線端或***電極之接合上的以往技術•因此，不會隨 著裝配製程（線接合過程或***電極形成過程）之技術上 變更，成爲可將具有C u系材料所構成之埋入配線構造的 半導體積體電路裝置導入在裝配線。因此，可減低具有 C u系材料所構成之埋入配線的半導體積體電路裝置之成 本，並可縮短製造與開發時間。 該連接孔8f之直徑係例如約0 . 2〜1 . 2vm， 較理想是例如約0 . 5 // m »又，連接孔8 f之縱橫比係 約2〜6。考慮良好地實行連接用導體部1 4 c之埋入。 比4小較理想。在連接孔8 f，埋入有連接用導體部 1 4 c。連接用導體部1 4 c係由其下部與側部之相對地 較薄導體膜1 4 C 1 ，及被較薄導體膜1 4 C 1所圍繞之 相對地較厚導體膜1 4 C 2所構成*又，該連接用導體 1 4C係未貫穿第4層配線1 3L » 較薄導體膜1 4 C 1係由具有提高連接用導體部 1 4 C與層間絕緣膜4 d之密接性的功能或抑制較厚導體 膜1 4 C 2之構成原子之擴散的阻障功能的材料所構成， 例如例如W，TiN’Ti ，Ta ’WN’WSiN， T i S i N，Ta或丁 a S i N等所構成。以W等構成較 薄導體膜14C1時’與以TiN’Ti ，Ta ，WN· WSiN，TiSiN，TaN或TaSiN等所構成時 相比較，成爲可降低配線電阻·雖並未特別限定，惟在本 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公t > --------------裝.-- (請先閱讀背面之注意事項再 1,.¾本頁) 訂： --線· 經濟部智慧財產局員工消費合作社印製 -28- A7 4 59 34 2 B7_ 五、發明說明（26) 實施形態1，較薄導體膜14C1由例如W所構成· 又，較厚導體膜1 4 C 2係構成連接用導體部1 4 C 之本體的構件，例如A 1，A 1合金，W或W合金之低電 阻的材料所構成。以A 1或A 1合金構成較厚導體膜 1 4 C 2時，與以W或W合金所構成時相比較，成爲可降 低連接用導體部1 4 C之電阻。又，在以W或W合金構成 較厚導體膜1 4C2時，與以A i或A 1合金構成較厚導 體膜1 4 C 2時相比較，成爲可提高連接用導體部1 4 C 之EM耐性及SM耐性。又，以W或W合金構成較厚導體 膜1 4 C 2時。由於以較厚阻障金靨可隔離構成第3層配 線1 1 L之Cu與構成第4層配線1 3L之A 1或A 1合 金，因此，容易防止因兩者之反應所產生之電阻上昇。亦 即，介經在連接孔8 f埋入具有阻障性能的材料，由於可 隔離以C u系材料所構成的第3層配線，與以A 1系材料 所構成的第4層配線1 3 L之距離，故可減低兩者之反應 。雖並未特別被限定，惟在本實施形態1中，較厚導體膜 1 4 C 2係由例如W所構成》 在層間絕緣膜4 d上，形成有表面保護膜1 5。由此 ，覆蓋第4層配線1 3 L之表面。表面保護膜1 5係例如 在保護膜1 5 a上重疊保護膜1 5b所形成。保護膜 1 5 a係例如S i 〇2所構成，而其上層之之保護膜1 5 b 係例如氮化矽所構成。在表面保護膜T 5之一部分，形成 有露出第4層配線1 3 L之一部分的開口部1 6。在第4 層配線1 3 L中，從該開口坪1 6所露出的部分，係形成 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱> ill-------裝--- <請先閲讀背面之注意事項再1?萁本頁) 訂· •線- 經濟部智慧財產局員工消費合作社印製 469 34 2 ：； 經濟部智慧財產局員工消費合作社印製 五、發明說明（ 27) 搭接襯墊部B P。亦即，在該搭接襯墊部B P，直接連接 有搭接線端，並經該線，構成半導體稹體電路裝置之封裝 之導線成爲電氣式地連接。又，在該結合片部B P上經由 底質金屬層作成設置鉛-錫合金或金等所構成的***電極 之構造也可以。又，上述之層間絕緣膜4 a〜4 d係例如 以S 0 G ( Spin on Glass )法所形成的塗布膜，有機膜， 添加氟之CVD膜，氮化矽膜或重疊此等所形成的叠層膜 也可以。 以下’依照第8圖至第1 8圇說明本實施形態1的半 導體積體電路裝置之製法》 首先’依照第8圖至第1 2圖說明相同材料所形成的 埋入配線之形成方法。又’在此，由於第1層配線6L， 第2層配線9 L及第3層配線1 1 L之構造係相同，而爲 了簡化說明，因此’以第1層配線6 L作爲代表例說明入 配線之形成方法。 第8圖係表示製程中之半導體積體電路裝置的要部剖 面圖。在形成於半導體基板1上的層間絕緣膜4 a，藉由 光刻法技術及乾蝕刻法技術已經被穿孔能露出半導體基板 1之主面（半導體領域3nd)的連接孔8a。又，層間 絕緣膜4 a係以例如矽氧化膜，以S 0G法所形成的氧化 矽膜，有機膜，添加氟之C VD膜，氮化矽膜或重叠此等 所形成之疊層膜等所構成。層間絕緣膜4 a係將介經例如 C V D ( Chemical Vapor Deposition )法所堆稹之砂氧化膜 ，介經CMP法等施以硏摩，使其表面成爲平坦化》 (請先閱讀背面之注意事項再f爲本頁) --裝 訂. --線· 本紙張又度適用中國國家標準(CNS)A4規格（210*297公«) -30- A7 4 5 9 342 B7_ 五、發明說明（28) 然後，如第9圖所示，在層間絕緣膜4 a之上面，連 接孔8 a之側面及底面•藉由濺射法等覆蓋例如W等所構 成的較薄導體膜7 C 1。該較薄導體膜7 C 1係具有提高 連接用導體部與層間絕緣膜4 a之密接性的功能或抑制較 厚導體膜7 C 2之形成時的材料氣體等之擴散或較厚導體 膜7 C 2之構成原子之擴散的阻障功能的材料所構成，並 不被限定於W者而可施以各種變更，例如TiN，Ti ， Ta，WN，WSi^f，TiSiN，Ta或TaSiN 等也可以《 然後，在薄導體膜7 C 1上，藉由CVD法等覆蓋例 如W等所構成之較厚導體膜7 C 2。由此，在微細之連接 孔8 a內可良好地塡充導體膜。較厚導體膜7 C 2係並不 被限定於W等者而可施以各種變更，例如A 1或A合金等 之低電阻材料也可以9又，較厚導體膜7 C 2之形成方法 係並不被限定於CVD法者，例如組合濺射法，CVD法 ，電鍍法者等也可以。 但是，在第2層配線及第3層配線中，作爲連接用導 體部1 0 C，‘ 1 2 C (參照第1圖）之較厚導體膜之形成 材料，除了上述之材料外，也可以使用C u或C u合金。 作爲此時之C u的成膜方法，例如使用CVD或電鍍法等 即可以。 然後，對於半導體基板1介經施以例如CMP處理， 介經除去連接孔8 a以外之領域的層間絕緣膜4 a上之較 厚導體膜7 C 2及較薄導體膜7 C 1，如第1 0圖所示’ 1紙張尺度適用中國园家標準（CNS)A4規格（210 X 297公藿) -幻： -------^---I------ (請先閱讀背面之注意事項再Jr-寫本頁) 訂· 線 經濟部智慧財產局員工消費合作社印製 A7 4 5 9 34 2 B7____ 五、發明說明（界） 在連接孔8 a內形成連接用導體部7 C。 I-------- I (請先Μ讀背面之注意事項再 1,¾本I) 然後，如第1 1圖所示，在層間絕緣膜4 a上，形成 配線用溝形成用之光阻圖案1 7 a ，將此作爲蝕刻掩蔽· 介經從該光阻圖案1 7 a除去露出的層間絕緣膜4 a部分 ，在層間絕緣膜4 a之上部形成配線用溝5 a及配線用溝 5b (參照第1圖）。此時，在配線用溝5a中突出事先 所形成之連接用導體部7 c之上部。 .線· 然後，除去光阻圖案1 7 a之後，如第1 2圖所示。 在包含配線用溝5 a之層間絕緣膜4 a之表面及連接用導 體部7 C之露出表面，藉由濺射法覆蓋例如T i N等所構 成的較薄導體膜6 L 1。該較薄導體膜6 L 1係具有提高 第1層配線與層間絕緣膜4 a之密接性的功能或抑制較厚 導體膜之構成原子之擴散的阻障功能的材料所構成，並不 被限定於T i N者，可施以各種變更，例如W，T i N， Ti，Ta，WN，WSiN，TiSiN，TaI^ TaSiN等也可以。 經濟部智慧財產局員工消费合作社印製 然後，在較薄導體膜661上，藉由CVD法，濺射 法或電鍍法 '，或組合此等等覆蓋例如C u等所構成的較厚 導體膜6 L 2 »在該C u等之成膜時，儘可能採用伸出（ Over hang )較小之階梯覆蓋（Step Coverage )優異之方法 。例如在濺射法，適用靶與半導體晶圓之間的距離隔間半 導體晶圓之半徑以上的濺射裝置。該較厚導體膜6 L 2係 並不被限定於C u者，可施以各種變更，例如C u合金， A 1、A 1合金，W或N合金也可以。 -32 本紙張尺度適用中國國家標準（CNS)A4規格（210 * 297公« ) 4 53 34 2 a? B7 五、發明說明（30) 以濺射法成膜上述之配線用導體膜時，特別是，繼續 地介經對於半導體基板1施以熱處理，流動較厚導體膜 6 L 2之構成原子（例如C u )而將該構成原子充分地供 給並埋入在配線用溝5 a內。此時，熱處理氣氛係作爲惰 性氣體氣氛，氧化性氣體氣氛或還原氣體氣氛中之任何一 種，或是組合該兩種以上的氣氛•又*採用在C u之濺射 期間施行該熱處理的所謂反流濺射法也可以。由此，可提 高Cu配線之EM特性。 之後，介經對於半導體基板1施以CMP處理，介經 除去配線用溝5a ，5b (參照第1圖）以外之領域的層 間絕緣膜4 a上之較厚導體膜6 L 2及較薄導體膜6 L 1 ，形成表示於第2圖等的第1層配線6 L。 在該CMP處理後或處理前對於半導體基板1施以熱 處理也可以。此時，熱處理氣氛係作爲惰性氣體氣氛，氧 化性氣體氣氛或還元氣體氣氛中之任何一種，或是組合該 兩種以上的氣氛。在該CMP處理後之熱處理過程，促進 較厚半導體基板6 L 2的C u之粒子成長並提高EM耐性 ，同時在C M P處理時避免產生在較薄導體膜6 L 1及較 厚導體膜6 L 2之表面的損傷或氧化膜而得其表面成爲平 滑。同時除去減低絕緣膜4 a的表面污染。由此，成爲可 提高配線之可靠性。 以下，藉第1 3圖至第1 8圖說明在相同之埋入配線 層形成異種導體材料所構成的埋入配線之方法。此乃相當 於在上述相同配線層內存有異種導體材料所構成之配線時 本紙張尺度適用中國國家標準（CNS)A4規格（210 * 297公釐） 請 先-閱 讀 背 面 之 注 意 I h |裝 頁 訂 經濟部智慧財產局員工消費合作社印*J<f A7 4 5 9 34 2 B7_ 五、發明說明（31 ) 的形成方法例子。又，在本實施形態1，將在配線用溝 5a，5b內形成異種導體材料所構成的第1層配線6 L 之情形作爲代表例子加以說明。 第1 3圖係表示半導體積體電路裝置之製程中之層間 絕緣膜4 a的要部斜視圖•在層絕緣膜4 a之上部，配線 用溝5 a藉由光刻法技術及乾蝕刻技術所形成。 然後，如第1 4圖所示，在包括配線用溝5 d的層間 絕緣膜4 a之表面，藉由濺射法覆蓋例如T i N等所構成 的較薄導體膜6 L 1。該較薄導體膜6 L 1係具有提高第 1層配線與層間絕緣膜4 a之密接性的功能或抑制較厚導 體膜之構成原子之擴散的阻障功能的材料所構成*並不被 限定於T i N者，可施以各種變更，例如W，T i N，A7 B7 V. Description of the Invention (25) The wire layer is connected with a splice terminal or a raised electrode, but the A1 or A1 alloy can still be used through the use of the top wiring material. Conventional technology for bonding of bumps or bumps • Therefore, it will not change with the technology of the assembly process (wire bonding process or bump formation process), and will become a semiconductor with a buried wiring structure made of Cu-based materials Integrated circuit devices are introduced at the assembly line. Therefore, it is possible to reduce the cost of a semiconductor integrated circuit device having embedded wiring made of a Cu-based material, and to shorten manufacturing and development time. The diameter of the connection hole 8f is, for example, about 0.2 to 1.2 vm, and preferably, for example, about 0.5 // m. The aspect ratio of the connection hole 8f is about 2 to 6. It is considered to perform the embedding of the connection conductor portion 1 4 c well. Smaller than 4 is ideal. A connection conductor portion 1 4 c is buried in the connection hole 8 f. The connecting conductor portion 1 4 c is formed by a relatively thin conductor film 1 4 C 1 at a lower portion and a side portion, and a relatively thick conductor film 1 4 C 2 surrounded by the thinner conductor film 1 4 C 1. Structure * Also, the connection conductor 1 4C is not penetrated through the fourth layer wiring 1 3L »The thinner conductor film 1 4 C 1 has a function of improving the adhesion between the connection conductor portion 1 4 C and the interlayer insulation film 4 d. Or a material that inhibits the thicker conductor film 1 4 C 2 from constituting the barrier function of the diffusion of atoms, such as W, TiN'Ti, Ta'WN'WSiN, T i S i N, Ta or D a S i N, etc. When the thin conductive film 14C1 is formed with W or the like, it is possible to reduce the wiring resistance compared to when it is formed with TiN'Ti, Ta, WN · WSiN, TiSiN, TaN, or TaSiN. Paper size applies to China National Standard (CNS) A4 specifications (210 X 297 male t > -------------- installed.-(Please read the precautions on the back before 1 ,. ¾ (This page) Order:-Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economy -28- A7 4 59 34 2 B7_ V. Description of the Invention (26) Embodiment 1, the thinner conductive film 14C1 is composed of, for example, W Further, the thick conductor film 1 4 C 2 is a member constituting the body of the connection conductor portion 1 4 C, for example, a low resistance material of A 1, A 1 alloy, W, or W alloy. A 1 or A 1 When the alloy is composed of a thicker conductor film 1 4 C 2, the resistance of the connection conductor portion 1 4 C can be reduced compared to when it is composed of W or a W alloy. Also, when a thicker conductor film is formed of a W or W alloy. In the case of 1 4C2, it is possible to improve the EM resistance and SM resistance of the conductor portion 1 4 C for connection compared with the case where the thick conductor film 1 4 C 2 is made of A i or A 1 alloy. Also, W or W When gold is used to form a thicker conductor film 1 4 C 2. A thicker barrier metal layer can separate Cu that constitutes the third layer wiring 1 1 L from A 1 or A 1 alloy that constitutes the fourth layer wiring 1 3 L. Therefore, It is easy to prevent the resistance from increasing due to the reaction between the two. That is, by embedding a material with barrier properties in the connection hole 8 f, the third-layer wiring made of Cu-based material can be isolated from the The distance of the third layer wiring 1 3 L made of A 1 series material can reduce the reaction between the two. Although it is not particularly limited, in this Embodiment 1, the thicker conductor film 1 4 C 2 is formed by For example, W is formed> A surface protective film 15 is formed on the interlayer insulating film 4 d. As a result, the surface of the fourth layer wiring 1 3 L is covered. The surface protective film 15 is, for example, superposed on the protective film 15 a The protective film 15b is formed. The protective film 15a is made of, for example, Si02, and the upper protective film 15b is made of, for example, silicon nitride. A part of the surface protective film T5 is formed with An opening portion 16 that exposes a portion of the fourth layer wiring 1 3 L. In the fourth layer wiring 1 3 L, a portion exposed from the opening plate 16 Form this paper standard applicable to China National Standard (CNS) A4 specification (210 X 297 Public Love > ill ------- install --- < please read the precautions on the back before 1? 萁 this page) Order · • Line-Printed by the Consumers 'Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 469 34 2: Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (27) Overlapping the pad BP. That is, the bonding pad portion B P is directly connected with a bonding terminal, and the conductive wire constituting the package of the semiconductor body circuit device is electrically connected through the wire. Further, a structure in which a bump electrode made of lead-tin alloy, gold, or the like is provided on the bonding piece portion B P through the ground metal layer may be used. The interlayer insulating films 4 a to 4 d are formed by, for example, a coating film formed by the S 0 G (Spin on Glass) method, an organic film, a CVD film with fluorine added thereto, a silicon nitride film, or a film formed by superimposing these. A laminated film is also possible. The method of manufacturing a semiconductor volumetric circuit device according to the first embodiment will be described hereinafter with reference to FIGS. 8 to 18. First, a method of forming buried wirings made of the same material will be described with reference to FIGS. 8 to 12. Also here, because the structure of the first layer wiring 6L, the second layer wiring 9 L and the third layer wiring 1 1 L are the same, but to simplify the description, 'the first layer wiring 6 L is used as a representative example. Method of forming wiring. Fig. 8 is a sectional view of a main part of a semiconductor integrated circuit device in a manufacturing process. The interlayer insulating film 4a formed on the semiconductor substrate 1 has been perforated by photolithography and dry etching to expose the connection hole 8a on the main surface (semiconductor field 3nd) of the semiconductor substrate 1. The interlayer insulating film 4 a is, for example, a silicon oxide film, a silicon oxide film formed by the S 0G method, an organic film, a fluorine-added C VD film, a silicon nitride film, or a laminated film formed by superimposing these. Made up. The interlayer insulating film 4 a is a sand oxide film stacked through, for example, a CVD (Chemical Vapor Deposition) method, and rubbed through a CMP method to make the surface flat. (Please read the precautions on the back first (F is again on this page)-Binding.-Thread · This paper is again applicable to China National Standard (CNS) A4 specification (210 * 297 male «) -30- A7 4 5 9 342 B7_ V. Description of the invention (28) Then, as shown in FIG. 9, on the upper surface of the interlayer insulating film 4 a, the side surface and the bottom surface of the connection hole 8 a • A thin conductive film 7 C 1 made of, for example, W is covered by a sputtering method or the like. The thinner conductive film 7 C 1 has a function of improving the adhesion between the connecting conductor portion and the interlayer insulating film 4 a or suppressing the diffusion of material gas or the like when the thicker conductive film 7 C 2 is formed or the thicker conductive film 7 C 2 is composed of a material that constitutes the barrier function of atomic diffusion, and is not limited to W. Various changes can be made, such as TiN, Ti, Ta, WN, WSi ^ f, TiSiN, Ta, or TaSiN. Then, the thin conductor film 7 C 1 may be covered with a thicker conductor film 7 C 2 made of, for example, W or the like by a CVD method or the like. Accordingly, the conductive film can be filled in the fine connection hole 8a satisfactorily. The thicker conductor film 7 C 2 is not limited to those such as W and can be modified in various ways. For example, a low-resistance material such as A 1 or A alloy can also be used. The method for forming the thicker conductor film 7 C 2 is The method is not limited to a CVD method. For example, a combination sputtering method, a CVD method, or a plating method may be used. However, in the second-layer wiring and the third-layer wiring, in addition to the above-mentioned materials, as a material for forming a thicker conductor film of the connecting conductor portion 10 C, '1 2 C (see Fig. 1), Use Cu or Cu alloy. As a method for forming Cu at this time, for example, CVD, plating, or the like may be used. Then, the semiconductor substrate 1 is subjected to, for example, a CMP process, and the thicker conductor film 7 C 2 and the thinner conductor film 7 C 1 on the interlayer insulating film 4 a in areas other than the connection hole 8 a are applied, as in the first section. 1 0 shown in the picture '1 The paper size applies to the Chinese Gardener's Standard (CNS) A4 specification (210 X 297 cm)-Magic: ------- ^ --- I ------ (please first Read the notes on the back, and write this page again.) Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. A7 4 5 9 34 2 B7____ 5. Description of the Invention (Boundary) A conductor for connection is formed in the connection hole 8 a 7 C. I -------- I (please read the precautions on the back first, and then ¾ this I). Then, as shown in Fig. 11, on the interlayer insulating film 4a, a groove for wiring formation is formed. The photoresist pattern 17a is used as an etching mask. The exposed part of the interlayer insulation film 4a is removed through the photoresist pattern 17a, and a wiring groove 5a and a wiring are formed above the interlayer insulation film 4a. Use groove 5b (see Figure 1). At this time, an upper portion of the connection conductor portion 7c formed in advance is protruded into the wiring groove 5a. Line · After removing the photoresist pattern 17a, it is shown in Fig. 12. On the surface of the interlayer insulating film 4a including the wiring groove 5a and the exposed surface of the connection conductor portion 7C, a thin conductive film 6 L 1 made of, for example, T i N is covered by a sputtering method. The thinner conductor film 6 L 1 is not limited to a material having a function of improving the adhesion between the first layer wiring and the interlayer insulating film 4 a or a barrier function of suppressing the diffusion of constituent atoms of the thicker conductor film. Various changes can be made to T i N, such as W, Ti N, Ti, Ta, WN, WSiN, TiSiN, TaI ^ TaSiN, etc. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs and then on a thinner conductive film 661, by CVD method, sputtering method or electroplating method, or a combination of these to cover a thicker conductive film composed of Cu, etc. 6 L 2 »In the film formation of Cu, etc., it is better to use a method with excellent step coverage with a small overhang. For example, in the sputtering method, a sputtering device having a semiconductor wafer with a distance greater than the radius of the semiconductor wafer from the target is used. The thicker conductor film 6 L 2 is not limited to Cu, and various modifications can be made, such as Cu alloy, A1, A1 alloy, W or N alloy. -32 This paper size is in accordance with Chinese National Standard (CNS) A4 specification (210 * 297 male «) 4 53 34 2 a? B7 V. Description of the invention (30) When the above-mentioned conductor film for wiring is formed by sputtering, it is particularly important If the semiconductor substrate 1 is subjected to a heat treatment, the constituent atoms (for example, Cu) of the thick conductive film 6 L 2 continue to flow, and the constituent atoms are sufficiently supplied and buried in the wiring trench 5 a. At this time, the heat treatment atmosphere is any one of an inert gas atmosphere, an oxidizing gas atmosphere, or a reducing gas atmosphere, or a combination of the two or more kinds of atmospheres. Also, the so-called reaction atmosphere that performs the heat treatment during the sputtering of Cu is used. Stream sputtering is also possible. This can improve the EM characteristics of Cu wiring. After that, the semiconductor substrate 1 is subjected to a CMP process, and the thicker conductor film 6 L 2 and the thinner conductor on the interlayer insulation film 4 a are removed except for the wiring grooves 5 a and 5 b (see FIG. 1). The film 6 L 1 forms the first layer wiring 6 L shown in FIG. 2 and the like. The semiconductor substrate 1 may be thermally treated after or before the CMP process. At this time, the heat treatment atmosphere is any one of an inert gas atmosphere, an oxidizing gas atmosphere, or a reducing gas atmosphere, or a combination of two or more of them. The heat treatment process after the CMP treatment promotes the growth of Cu particles of the thicker semiconductor substrate 6 L 2 and improves the EM resistance, and avoids the occurrence of the thinner conductor film 6 L 1 and the thicker conductor film 6 L during the CMP treatment. The surface of 2 is damaged or oxidized to make the surface smooth. At the same time, the surface contamination of the insulating film 4 a is reduced. This improves the reliability of the wiring. Hereinafter, a method of forming an embedded wiring composed of a different type of conductive material on the same embedded wiring layer will be described with reference to FIGS. 13 to 18. This is equivalent to the wiring made of dissimilar conductor materials in the same wiring layer mentioned above. This paper applies the Chinese National Standard (CNS) A4 specification (210 * 297 mm). Please read the note on the back I h | Ordered by the Intellectual Property Bureau of the Ministry of Economic Affairs, Employee Consumption Cooperative Association * J < f A7 4 5 9 34 2 B7_ 5. An example of the method of forming the invention description (31). In the first embodiment, a case where a first-layer wiring 6L made of a different conductive material is formed in the wiring grooves 5a and 5b will be described as a representative example. Fig. 13 is a perspective view showing a main part of the interlayer insulating film 4a in the manufacturing process of the semiconductor integrated circuit device. Above the layer insulating film 4a, the wiring groove 5a is subjected to a photolithography technique and a dry etching technique. Formed. Then, as shown in FIG. 14, a thin conductive film 6 L 1 made of, for example, T i N is covered on the surface of the interlayer insulating film 4 a including the wiring groove 5 d by a sputtering method. The thinner conductor film 6 L 1 is made of a material having a function of improving the adhesion between the first layer wiring and the interlayer insulating film 4 a or a barrier function of suppressing the diffusion of constituent atoms of the thicker conductor film * is not limited For T i N, various changes can be made, such as W, T i N,
Ti，Ta，WN，WSiN，TiSiN，Tal·^ T a S i N等也可以》 然後，在較薄導體膜661上，藉由CVD法，濺射 法或電鍍法等覆蓋例如C u等所構成的較厚導體膜6 L 2 。在該C u等之成膜時，儘可能採用伸出較小之分步敷層 優異之方法。例如在濺射法，適用靶與半導體晶圓之間的 距離隔間半導體晶圓之半徑以上的濺射裝置。該較厚導體 膜6 L 2係並不被限定於C u者，可施以各種變更，例如 Cu合金，Al、 Ai合金，W或N合金也可以。 以濺射法成膜上述之配線用導體膜時，特別是，繼續 地介經對於半導體基板1施以熱處理，流動較厚導體膜 6 L 2之構成原子（例如C u )而將該構成原子充分地供 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公；g )Ti, Ta, WN, WSiN, TiSiN, Tal · T a S i N, etc. may be used. Then, a thin conductor film 661 is covered by a method such as CVD, sputtering, or electroplating. The thicker conductor film 6 L 2 is formed. In the film formation of the Cu and the like, a method that is excellent in a stepwise coating with a small extension is used as much as possible. For example, in the sputtering method, a sputtering device having a radius greater than the radius of the semiconductor wafer between the target and the semiconductor wafer is used. The thicker conductor film 6 L 2 is not limited to Cu, and various modifications can be made, such as Cu alloy, Al, Ai alloy, W or N alloy. When the above-mentioned conductor film for wiring is formed by a sputtering method, in particular, the constituent atoms (for example, Cu) of a thicker conductor film 6 L 2 are continuously flowed through a heat treatment of the semiconductor substrate 1 to pass the constituent atoms Fully available for this paper size Applies to Chinese National Standard (CNS) A4 specifications (210 X 297 male; g)
— — — — 11— — — — —— — - — — lull ^ --- ----- (請先閱讀背面之注意事項再f"本頁J 經濟部智慧財岌局貝工消費合作社印製 -34- 459342 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（32) 給並埋入在配線用溝5 a內•此時，熱處理氣氛係作爲惰 性氣體氣氛，氧化性氣體氣氛或還原氣體氣氛中之任何一 種，或是組合該兩種以上的氣氛。又，採用在C u之濺射 期間施行該熱處理的所謂反流濺射法也可以。由此，可提 高C u配線之E Μ特性。 之後，介經對於半導體基板1施以CMP處理，介經 除去配線用溝5 a，以外之領域的層間絕緣膜4 a上之較 厚導體膜6 L 2及較薄導體膜6 L 1，如第.1 5圖所示， 在配線用溝5 a內形成第1層配線6L。 在該CMP處理後或處理前對於半導體基板1施以熱 處理也可以。此時，熱處理氣氛係作爲惰性氣體氣氛，氧 化性氣體氣氛'或還元氣體氣氛中之任何一種，或是組合該 兩種以上的氣氛。在該CMP處理後之熱處理過程，促進 較厚半導體基板6 L 2的（：u之粒子成長並提高EM耐性 ，同時在CMP處理時避免產生在較薄導體膜6 L 1及較 厚導體膜6 L 2之表面的損傷或氧化膜而得其表面成爲平 滑。同時除去減低絕緣膜4 a的表面污染》由此*成爲可 提高配線之可靠性。 然後，如第1 6圖所示*在層間絕緣膜4 a上部藉由 光刻法技術及乾蝕刻技術形成比配線用溝5 a寬窄或長度 短的配線用溝5 b。此時，配線用溝5 b之深度係與配線 用溝5 a相同也可以，惟設定與配線用溝5 a之深度不同 深度也可以。例如第1 7圇所示，將配線用溝5 b之深度 比配線用溝5 a之深度較深也可以》此時，配線用溝5 b C請先閲讀背面之注意事項再f寫本頁) i裝 訂· .線- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公藿〉 4 59 34 2 A7 B7 五、發明說明（ 33) 係寬度係狹窄，惟較深，因此，成爲可降低埋入在配線用 溝5 I)內的導體膜之配線電阻。或將配線用溝5 b形成較 深，達到下層配線層或半導體基板，也可使用於連接用· 然後，與上述同樣地，在配線用溝5 a內之第1層配 線6 L之上面及包括配線用溝5 b之層間絕緣膜4 a之表 面，藉由濺射法等覆蓋例如W等所構成的較薄導體膜•該 較薄導體膜係具有提高第1層配線與層間絕緣膜4 a之密 接性的功能或抑制較厚導體膜之構成原子之擴散的阻障功 能的材料所構成，並不被限定於W者而可施以各種變更， 例如 TiN，Ti ，Ta，WN，WSiN，TiSiN ，丁aN或TaSiN等也可以。 然後，在薄導體膜上，藉由CVD法等覆蓋例如W等 所構成之較厚導體膜。在該W等之成膜時，儘可能採用伸 出較小之分步敷層優異之方法較理想。由此，即使在寬窄 之配線用溝5b，又，如第17圖所示地，即使比配線用 溝5 a較深之配線用溝5 b，也成爲在其內部可良好地塡 充配線用導體。該較厚導體膜，係並不被限定於W者：可 施以各種變k，例如W合金，A 1或A 1合金也可以。 然後，對於半導體基板1介經施以CMP處理，介經 除去配線用溝5 b以外之領域的較厚導體膜及較薄導體膜 ，如第1 8圖所示，在比配線用溝5 a寬窄之配線用溝 5 b內。形成與配線用溝5 a內之較薄導體膜6 L 1及較 厚導體膜6 L 2係異種導體材料所構成之較厚導體膜 6 L 1及較厚導體膜6 L 2所構成的第1層配線6 L。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ---------------裝--- (請先Μ讀背面之注意事項再Cr為本頁) 訂· -線_ 經濟部智慧財產局員工消費合作杜印製 -36 - (1 )在微細連接孔 充導體膜之後，形成比連 配線用溝5a〜5f ，在 體膜，介經形成埋入構造 部7C，第2層配線9L 配線1 1 L及連接用導體 〜5 f及比其較微細之連 充導體膜。 (2 )在相同配線層 擇以微細之配線用溝等與 之方法來埋入導體膜，成 埋入導體膜· (3 )介經上述（1 間之連接上的可靠性。因 裝置之良品率及可靠性》 (4 )介經上述（1 線之微細化*因此，成爲 型化或高積體化》 (5 )介經上述（1 在配線用溝5 a至5 f及 導體膜。 (6 )介經上述（1 經濟部智慧財產局員工消貲合作社印製 4 5 9 342 五、發明說明（Μ) 如此，依照本實施形態1 *成爲可得到以下之效果· 8 3〜8【內使用（：¥0法等塡 接孔8 a〜8 f平面尺寸較大之 該配線用溝5 a〜5 ί內塡充導 之第1配線層6 L，連接用導體 ，連接用導體部10C，第3層 部1 2 C，成爲在配線用溝5 a 接孔8a〜8f雙方可良好地塡 具有不同配線用溝等時，介經選 比其更大之配線用溝等容易埋入 爲在雙方之配線用溝內可良好地 )或（2)，成爲可提高配線層 此，成爲可提高半導體積體電路 )或（2 )，成爲可推動埋入配 可推動半導體積體電路裝置之小 )或（2)，不必採用難技術· 連接孔8 a至8 ί可良好地埋入 )或（2)，成爲作爲埋入配線 本紙張尺度適用中國國家標準（CNS)A4規格（2]〇χ 297公爱） 闓 讀 背 面 之 注 意 Ϊ 卜！ I裝 頁 訂 五、發明說明（35) 材料即使使用c u或C u合金等時也可良好地實施其埋入 狀態。 (7 )與半導體基板1直接接觸之連接用導體部7 C 係以W係（W或W合金）之導髋材料所構成，且與連接用 導體部7 C連接之第1層配線6 L係介經以C u系之導體 材料所構成，一面良好地保持導體膜對於連接孔8 a內之 埋入狀態，一面防止C U原子對於半導體基扳1側之擴散 ，能避免起因於其擴散現象的連接不良，且減低第1層配 線6 L之配線電阻而成爲可提高信號之傳播速度。 (8)介經以A 1系（A 1或A 1合金）之導體材料 構成最上之第4層配線1 3 L，仍可沿用以往之線接合技 術或***電極之形成技術等之裝配技術。因此，成爲可將 C u系之埋入配線的半導體積體電路裝置容易地導入在裝 配過程。 (9 )介經在A 1系之導體材料所構成的第4層配線 1 3 L與其下層之C u系之導體材料所構成的第3層配線 1 1 L之間，設置W系之導體材料所構成的連接用導體部 1 4 C，由於以較厚阻障金屬隔離A系之導體材料與C u 系之導體材料，防止直接接觸A i系之導體材料與C u系 之導體材料時於其接觸部形成高電阻係數之合金層，因此 ，成爲可降低配線層間之電阻。 (1 0 )介經在用以形成C U系導體材料所構成之埋 入配線的CMP處理後對於半導體基板1施以熱處理，由 於促進C u之粒子成長而提高EM耐性，而且在CMP處 本紙張尺度適用中國國家標準（CNS)A4規格（210 * 297公釐） !!!* 裝--- <請λ.Μι*背面之注意事項再CV?本頁} 訂· •線. 經濟部智慧財產局員工消貲合作社印製 -38- 0 9 34 2 經濟部智慧財產局具工消費合作杜印製 五、發明說明（36) 理時可避免產生在配線用導體膜之表面的損傷或氧化膜等 將其表面成爲平滑*或可除去減低CMP時所露出的絕緣 膜之表面污染，因此，成爲可提高C u系之導體材料所構 成的埋入配線之可靠性。 (實施形態2 ) 第1 9圖至第2 3圖係表示本發明之其他實施形態的 半導體積體電路裝置之製程的要部剖面圖，第2 4圖係表 示半導體積體電路裝置的要部剖面圖* 在本實施形態2,係連接用導體部之構造及其形成方 法與上述實施形態1不同* 首先，如第1 9圖所示，在層間絕緣膜4 a之上面形 成配線用溝形成用之光阻圖案1 7 b後，將該光阻圖案 1'7 b作爲蝕刻掩蔽而介經施以蝕刻處理，在層間絕緣膜 4 a上部形成配線用溝5 a。 然後，除去光阻圖案1 7b之後，如第20圖所示， 在層間絕緣膜4 a上形成連接孔形成用之光阻圖案1 7 C 之後，將該光阻圖案1 7 C作爲蝕刻掩蔽施以蝕刻處理， 將如從配線用溝5 a之底面向半導體基板1延伸，且能露 出半導體基板1上面之一部分的連接孔8 a穿孔在層間絕 緣膜4 a。 然後，除去光阻圖案1 7 C之後，如第2 1圖所示， 在連接孔8 a內，藉選擇CVD法等形成例如W等所構成 之連接用導體部7 C 此時，連接用導體部7 C之上部突— — — — 11 — — — — — — — — — lull ^ --- ----- (Please read the notes on the back before f " on this page. -34- 459342 A7 B7 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (32) It is buried in the wiring trench 5a. At this time, the heat treatment atmosphere is an inert gas atmosphere and an oxidizing gas. Either an atmosphere or a reducing gas atmosphere, or a combination of two or more of these atmospheres. Also, a so-called counter-current sputtering method in which the heat treatment is performed during the sputtering of Cu may be used. This can increase Cu The EM characteristics of the wiring. After that, the semiconductor substrate 1 is subjected to a CMP treatment, and the wiring groove 5 a is removed, and the thicker conductive film 6 L 2 and the thinner conductor on the interlayer insulating film 4 a are excluded. As shown in FIG. 15, the film 6 L 1 forms a first layer wiring 6L in the wiring groove 5 a. The semiconductor substrate 1 may be heat-treated after the CMP process or before the process. In this case, the heat treatment The atmosphere is an inert gas atmosphere, an oxidizing gas atmosphere ' Reduce any one of the gas atmospheres, or combine two or more of these atmospheres. The heat treatment process after the CMP treatment promotes the growth of the (: u) particles of the thicker semiconductor substrate 6 L 2 and improves the EM resistance. Avoid damage or oxidation on the surface of the thinner conductor film 6 L 1 and the thicker conductor film 6 L 2 during processing, so that the surface becomes smooth. At the same time, the surface contamination of the insulating film 4 a is reduced, thereby making it * possible Improve the reliability of the wiring. Then, as shown in Figure 16 *, a trench 5 b that is narrower or shorter in length than the wiring trench 5 a is formed on the interlayer insulating film 4 a by photolithography and dry etching. At this time, the depth of the wiring groove 5 b may be the same as that of the wiring groove 5 a, but it may be set to a depth different from the depth of the wiring groove 5 a. For example, as shown in FIG. The depth of b may be deeper than the depth of wiring groove 5a. At this time, wiring groove 5 b C, please read the precautions on the back before writing this page) i Binding ·. Thread-This paper size is applicable to China Standard (CNS) A4 size (210 X 297 public housing) 4 59 34 2 A7 B7 V. Description of the invention (33) The width is narrow but deep, so it can reduce the wiring resistance of the conductor film buried in the wiring trench 5 I). Or the wiring trench 5 b can be formed deeper. It can also be used for connection after reaching the lower wiring layer or semiconductor substrate. Then, as above, on the first layer wiring 6 L in the wiring groove 5 a and the interlayer insulating film including the wiring groove 5 b The surface of 4 a is covered with a thinner conductive film made of, for example, W by a sputtering method. The thinner conductive film has the function of improving the adhesion between the first layer wiring and the interlayer insulating film 4 a or suppressing the thickness. The conductor film is made of a material that prevents the diffusion of atoms. It is not limited to W and can be modified in various ways. For example, TiN, Ti, Ta, WN, WSiN, TiSiN, butaN, or TaSiN can also be used. . Then, a thin conductive film is covered with a thick conductive film made of, for example, W or the like by a CVD method or the like. In the film formation of the W and the like, it is preferable to use a method that is excellent in stepwise coating with a small extension as much as possible. Therefore, even in the wide and narrow wiring groove 5b, as shown in FIG. 17, even if the wiring groove 5b is deeper than the wiring groove 5a, it can be used to fill the wiring well inside. conductor. The thicker conductor film is not limited to W: various changes can be made to k, for example, W alloy, A 1 or A 1 alloy may be used. Then, the semiconductor substrate 1 is subjected to a CMP process through a thicker conductor film and a thinner conductor film in a region other than the trench 5 b for wiring, as shown in FIG. Within the narrow wiring groove 5b. Form and connect the thinner conductor film 6 L 1 and the thicker conductor film 6 L 2 in the trench 5 a for wiring. The thicker conductor film 6 L 1 and the thicker conductor film 6 L 2 composed of dissimilar conductor materials. 1 L wiring 6 L. This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) --------------- Packing --- (Please read the precautions on the back before Cr is (This page) Order ·-Line _ Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperation Du Yin -36-(1) After the fine connection hole is filled with the conductor film, the grooves 5a to 5f for the interconnect wiring are formed. The embedded structure portion 7C, the second layer wiring 9L, the wiring 1 1 L, and the connecting conductors ~ 5 f and a finer continuous charge conductor film are formed. (2) Use the same wiring layer to embed the conductive film with a fine wiring groove or the like to form the embedded conductive film. (3) Reliability of the connection through the above (1). Because of the good quality of the device "Ratio and reliability" (4) Through the above (1 line miniaturization * Therefore, it becomes a type or high-integralization "(5) Through the above (1 in the wiring grooves 5 a to 5 f and the conductor film. (6) Through the above (1 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 5 9 342 V. Description of Invention (M) In this way, according to this embodiment 1 * The following effects can be obtained. 8 3 ~ 8 [ For internal use (: ¥ 0 method, etc., contact holes 8 a to 8 f, the wiring trench 5 a to 5 with a larger plane size, 1 litter for the first wiring layer, 6 L, connection conductor, connection conductor part 10C, the third layer part 1 2 C, when the wiring grooves 5 a and the contact holes 8 a to 8 f can be well connected with different wiring grooves, etc., it is easy to embed the wiring grooves which are larger than them. In order to make the wiring grooves on both sides good) or (2), the wiring layer can be improved, and the semiconductor integrated circuit can be improved) or (2), which can be improved. Promote embedded distribution can promote the small size of semiconductor integrated circuit devices) or (2), do not need to use difficult technology · Connection holes 8 a to 8 (can be embedded well) or (2), become the paper standard for embedded wiring Applicable to China National Standard (CNS) A4 specification (2) 〇χ 297 (Public Love) 背面 Read the note on the backΪ ！! I Binding Ⅴ. Description of the invention (35) Materials can be good even when using cu or Cu alloy (7) The connecting conductor portion 7 C which is in direct contact with the semiconductor substrate 1 is made of a W-based (W or W alloy) hip material and is connected to the connecting conductor portion 7 C. The first layer of wiring 6 L is composed of a Cu-based conductor material, while maintaining the buried state of the conductor film in the connection hole 8 a, while preventing the diffusion of CU atoms to the semiconductor substrate 1 side, Avoids poor connection due to its diffusion phenomenon, and reduces the wiring resistance of the first layer of wiring 6 L, which can increase the speed of signal propagation. (8) Conductor material via A 1 series (A 1 or A 1 alloy) It constitutes the uppermost layer 4 wiring 1 3 L, which can still be connected with the previous wire Assembly technology such as bonding technology or bump electrode formation technology. Therefore, a semiconductor integrated circuit device capable of embedding Cu-based wiring can be easily introduced in the assembly process. (9) Conductor material through A 1 series Between the formed fourth layer wiring 1 3 L and the third layer wiring 1 1 L composed of a Cu-based conductor material, a connection conductor portion 1 4 C composed of a W-based conductor material is provided. A thick barrier metal is used to isolate the A-based conductor material and the Cu-based conductor material to prevent direct contact with the Ai-based conductor material and the Cu-based conductor material to form a high-resistance alloy layer at the contact portion. It can reduce the resistance between wiring layers. (1 0) The semiconductor substrate 1 is subjected to a heat treatment after the CMP treatment to form the buried wiring composed of the CU-based conductor material, and the EM resistance is improved because the particle growth of Cu is promoted. Standards are applicable to China National Standard (CNS) A4 specifications (210 * 297 mm) !!! * Packing --- < Please note on the back of λ.Μι * CV? This page} Order · • Line. Ministry of Economy Wisdom Printed by the staff of the Property Bureau and printed by cooperatives -38- 0 9 34 2 Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, printed by industrial and consumer cooperation. V. Description of the invention (36) It can avoid damage or oxidation on the surface of the conductor film for wiring. The surface of the film can be smoothed or can be removed to reduce the surface contamination of the insulating film exposed during CMP. Therefore, it is possible to improve the reliability of buried wiring made of Cu-based conductor materials. (Embodiment 2) Figures 19 to 23 are cross-sectional views of main parts of a semiconductor integrated circuit device manufacturing process according to other embodiments of the present invention, and Figures 24 and 4 are main parts of a semiconductor integrated circuit device Sectional view * In the second embodiment, the structure and forming method of the connection-use conductor portion are different from those in the first embodiment * First, as shown in FIG. 19, a wiring groove is formed on the interlayer insulating film 4a. After using the photoresist pattern 17b, the photoresist pattern 1'7b is used as an etching mask and an etching process is performed to form a wiring groove 5a on the interlayer insulating film 4a. Then, after removing the photoresist pattern 17b, as shown in FIG. 20, a photoresist pattern 17C for forming a connection hole is formed on the interlayer insulating film 4a, and the photoresist pattern 17c is used as an etching masking application. By an etching process, the connection hole 8 a extending from the bottom of the wiring groove 5 a toward the semiconductor substrate 1 and exposing a part of the upper surface of the semiconductor substrate 1 is perforated into the interlayer insulating film 4 a. Then, after removing the photoresist pattern 1 7 C, as shown in FIG. 21, a connection conductor portion 7 C made of, for example, W is formed by a CVD method or the like in the connection hole 8 a. At this time, the connection conductor 7 C
請 先-I» 讀 背 面 之 注 意 事 項 再· >*· I t 裝 訂 本紙張尺度適用中國國家標準<CNS)A4規格（210 X 297公釐） -39- 經濟部智慧財產局員工消費合作社印製 9 34 2 a? _；___B7__ 五、發明說明（37 ) 出於配線用溝5 a中也無妨•又*連接用導體部7 C之材 料係並不被限定於W者，可施以各種變更，例如W合金， A 1、A 1合金也可以。 然後，如第2 2圖所示，在包括配線用溝5 a之層間 絕緣膜4 a之表面及連接用導體部7 C之露出表面，藉由 濺射法覆蓋例如T i N等所構成的較薄導體膜6 L 1 >該 較薄導體膜6 L 1係具有提高第1層配線與層間絕緣膜 4 a之密接性的功能或抑制較厚導體膜之構成原子之擴散 的阻障功能的材料所構成，並不被限定於T i N者，可施 以各種變更，例如W，TiN，Ti ，Ta，WN* WS iN，Ti S iN，TaN或TaSiN等也可以。 然後，在較薄導體膜661上，藉由CVD法，濺射 法或電鍍法等覆蓋例如C u等所構成的較厚導體膜6 L 2 。在該C u等之成膜時，儘可能採用伸出較小之分步敷層 優異之方法。例如在濺射法，適用靶與半導體晶圓之間的 距離隔間半導體晶圓之半徑以上的濺射裝置。該較厚導體 膜6 L 2係並不被限定於C u者，可施以各種變更，例如 1Please -I »Read the precautions on the back. ≫ * · I t The size of the bound paper is applicable to the Chinese national standard < CNS) A4 specification (210 X 297 mm) Printed 9 34 2 a? _; _B7__ V. Description of the invention (37) It is not necessary for the wiring groove 5a. • Also * The material of the connection conductor 7 C is not limited to W, but can be applied. Various changes are possible, such as W alloy, A1, and A1 alloy. Then, as shown in FIG. 22, the surface of the interlayer insulating film 4a including the wiring groove 5a and the exposed surface of the connection conductor portion 7C are covered with, for example, T i N by a sputtering method. Thinner conductor film 6 L 1 > The thinner conductor film 6 L 1 has a function of improving the adhesion between the first layer wiring and the interlayer insulating film 4 a or a barrier function of suppressing the diffusion of constituent atoms of the thicker conductor film. The composition of the material is not limited to T i N, and various changes can be made, such as W, TiN, Ti, Ta, WN * WS iN, Ti S iN, TaN, or TaSiN. Then, the thinner conductive film 661 is covered with a thicker conductive film 6 L 2 made of, for example, Cu or the like by a CVD method, a sputtering method, or a plating method. In the film formation of the Cu and the like, a method that is excellent in a stepwise coating with a small extension is used as much as possible. For example, in the sputtering method, a sputtering device having a radius greater than the radius of the semiconductor wafer between the target and the semiconductor wafer is used. The thicker conductor film 6 L 2 series is not limited to those of Cu, and various changes can be made, such as 1
Cu合金，A 1、A 1合金，W或W合金也可以。 以濺射法成膜上述之配線用導體膜時，特別是，繼續 地介經對於半導體基板1施以熱處理•流動較厚導體膜 6 L 2之構成原子（例如C u )而將該構成原子充分地供 給並埋入在配線用溝5 a內。此時，熱處理氣氛係作爲惰 性氣體氣氛，氧化性氣體氣氛或還原氣體氣氛中之任何一 種，或是組合該兩種以上的氣氛。又，採用在C u之濺射 — — III — — — — — — — — ·1111111 illlll· — —— (請λ.Μ讀背面之注意事項再本頁) 本紙張尺度適用中S國家標準（CNS)A4規格（210 X 297公釐） -40- A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（) 期間施行該熱處理的所謂反流濺射法也可以•由此，可提 高C u配線之E Μ特性· 之後，介經對於半導體基板1施以CMP處理，介經 除去配線用溝5a ，5b (參照第1圖）以外之領域的層 間絕緣膜4 a上之較厚導體膜6 L 2及較薄導體膜6 L 1 ，如第2 3圖所示，在配線用溝5 a內形成第1配線層 6 L。 在該CMP處理後或處理前對於半導體基板1能以熱 處理也可以。此時，熱處理氣氛係作爲惰性氣體氣氛，氧 化性氣體氣氛或還元氣體氣氛中之任何一種•或是組合該 兩種以上的氣氛。在該CMP處理後之熱處理過程，促進 較厚半導體基板6 L 2的C u之粒子成長並提高EM耐性 ，同時在CMP處理時避免產生在較薄導體膜6 L 1及較 厚導體膜6 L 2之表面的損傷或氧化膜而得其表面成爲平 滑。同時除去減低絕緣膜4 a的表面污染。由此，成爲可 提高配線之可靠性。 又，此等埋入配線構造係如第2 4圖所示，也可適用 於第2層配線9 L *亦即，連接用導體部1 〇 C成爲以例 如選擇CVD法所形成之W，W合金，A1 ，A1合金， C U或C u合金等的導體膜所構成之構造。 依照此等本實施形態2，成爲可得到與上述實施形態 1同樣之效果。 ·‘ (實施形態3 ) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公笼） -41 - 請 先. 閱 讀 背 St 之 注 意 事 項 再I | i 裝 訂 ▲ 4 69 34 2 五、發明說明（39) 第2 5圖至第2 8圖及第2 9圖至第3 2圖係本發明 之其他實施形態的半導體積體電路裝置之製程中的要部剖 面圖，第3 3圖係表示半導體積體電路裝置之要部剖面圖Cu alloy, A1, A1 alloy, W or W alloy are also possible. When the above-mentioned conductor film for wiring is formed by a sputtering method, in particular, the constituent atoms (for example, Cu) of the semiconductor substrate 1 which is subjected to a heat treatment and a thicker flowing conductor film 6 L 2 are continuously passed through to form the constituent atoms. It is fully supplied and buried in the wiring trench 5a. At this time, the heat treatment atmosphere is any one of an inert gas atmosphere, an oxidizing gas atmosphere, or a reducing gas atmosphere, or a combination of two or more of them. In addition, the sputtering in Cu — — III — — — — — — — — 1111111 illlll · — — — (Please read the precautions on the back of λ.M on this page) The national standard of this paper applies ( CNS) A4 specification (210 X 297 mm) -40- A7 B7 Printed by the Consumers ’Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention The so-called counter-current sputtering method which performs this heat treatment during () is also possible After improving the EM characteristics of the Cu wiring, a thicker interlayer insulating film 4a is applied to the semiconductor substrate 1 through a CMP process, and the wiring grooves 5a and 5b are removed (see FIG. 1). The conductor film 6 L 2 and the thinner conductor film 6 L 1 have a first wiring layer 6 L formed in the wiring groove 5 a as shown in FIG. 23. The semiconductor substrate 1 may be thermally treated after the CMP process or before the process. At this time, the heat treatment atmosphere is any one of an inert gas atmosphere, an oxidizing gas atmosphere, or a reducing gas atmosphere, or a combination of two or more of these atmospheres. The heat treatment process after the CMP treatment promotes the growth of Cu particles of the thicker semiconductor substrate 6 L 2 and improves the EM resistance, and avoids the occurrence of the thinner conductor film 6 L 1 and the thicker conductor film 6 L during the CMP treatment. The surface of 2 is damaged or oxidized to make the surface smooth. At the same time, the surface contamination of the insulating film 4 a is reduced. This improves the reliability of the wiring. These buried wiring structures are also applicable to the second-layer wiring 9 L as shown in FIG. 24. That is, the connection conductor portion 10 C becomes W, W formed by, for example, a selective CVD method. Alloy, A1, A1 alloy, CU or Cu alloy conductor film structure. According to the second embodiment, the same effects as those of the first embodiment can be obtained. · '(Embodiment Mode 3) This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 male cage) -41-Please first. Read the notes on the back of St before I | i Binding ▲ 4 69 34 2 V. Explanation of the invention (39) FIGS. 25 to 28 and FIGS. 29 to 32 are cross-sectional views of main parts in the process of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention, and FIGS. 3 to 3 Is a sectional view of a main part showing a semiconductor integrated circuit device
Q 第2 5圖係表示製程中的半導體稹體電路裝置。在層 間絕緣膜4 a ，藉由在上述實施形態2所說明之方法，形 成有配線用溝5 a及連接孔8 a。 首先，在本實施形態3中，如第2 6圖所示，在連接 孔8 a內•藉由選擇CVD法形成例如W等所構成之連接 用導體部7C。此時，在本實施形態3中，實行成膜處理 使連接用導體部7 C之上部突出於配線用溝5 a之外側的 程度。又，連接用導體部7 C之材料係並不被限定於W者 ，可施以各種變更，例如W合金，A 1 ，A 1合金也可以 〇 然後，如第2 7圖所示，在包括配線用溝5 a之層間 絕緣膜4 a之表面及連接用導體部7 C之表面，藉由濺射 法覆蓋例如T i N等所構成的較薄導體膜6 L 1 »該較薄 導體膜6 L1係具有提高第1層配線與層間絕緣膜4 a之 密接性的功能或抑制較厚導體膜之構成原子之擴散的阻障 功能的材料所構成，並不被限定於T i N者，可施以各種 變更，例如W，TiN，Ti ，Ta ，WN，WSiN， T i S i N，TaN或TaS iN等也可以》 然後，在較薄導體膜661上，藉由CVD法，濺射 法或電鍍法等覆蓋例如C u等所構成的較厚導體膜6 L 2 本紙張又度適用中园國家標準<CNS)A4規格（210 *297公釐） —111 — — — — — —— — · <ttit.wtk背面之;i意事項再{>»本頁》 訂.· ,線· 經濟部智慧財產局具工消費合作社印製 -427 Α7 Β7 4 2 五、發明說明（40) 。在該C U等之成膜時，儘可能採用伸出較小之分步敷層 優異之方法。例如在濺射法，適用靶與半導體晶圓之間的 距離隔間半導體晶圓之半徑以上的濺射裝置。該較厚導體 膜6 L 2係並不被限定於C u者，可施以各種變更，例如 C u合金，A 1、A 1合金，W或Ν合金也可以》 以濺射法成膜上述之配線用導體膜時，特別是，繼續 地介經對於半導體基板1施以熱處理，流動較厚導體膜 6 L 2之構成原子（例如C u )而將該構成原子充分地供 給並埋入在配線用溝5 a內。此時，熱處理氣氛係作爲惰 性氣體氣氛，氧化性氣體氣氛或還原氣體氣氛中之任何一 種，或是組合該兩種以上的氣氛。又，採用在C u之濺射 期間施行該熱處理的所謂反流濺射法也可以。由此，可提 高Cu配線之EM特性。 之後，介經對於半導體基板1施以CMP處理》介經 除去配線用溝5a ，5b (參照第1圖）以外之領域的層 間絕緣膜4 a上之較厚導體膜6 L 2及較薄導體膜6 L 1 ，如第2 8圖所示，在配線用溝5 a內形成第1層配線 6 L *同時i形成連接用導體部7 C ^ 在該C.Μ P處理後或處理前對於半導體基板1施以熱 處理也可以。此時，熱處理氣氛係作爲惰性氣體氣氛，氧 化性氣體氣氛或還元氣體氣氛中之任何一種，或是組合該 兩種以上的氣氛。在該CMP處理後之熱處理過程，促進 較厚半導體基板6 L 2的C u之粒子成長並提高ΕΜ耐性 ，同時在CMP處理時避免產生在較薄導體膜6 L 1及較 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 1 — — — — — — — — — — — — - 1111111 ^0 — — — — — — — (請it.閱讀背面之注意事項再t、本頁) 經濟部智慧財產局員工消費合作社印製 -43- Α7 Β7 34 2 五、發明說明（41 ) 雇導體膜6 L 2之表面的損傷或氧化膜而得其表面成爲平 滑。同時除去減低絕緣膜4 a的表面污染。由此，成爲可 提高配線之可靠性- 又，欲形成如第2 8圖之構造之埋入配線，例如.如下 地實行也可以。 首先，如第2 9圖所示，在層間絕緣膜4 a藉由先刻 法技術及乾蝕刻技術形成使半導體基板1上面之一部分露 出的連接孔8 a。 然後，如第3 0圖所示，在連接孔8 a內，藉由選擇 CVD法形成例如W等所構成連接用導體部7 C。此時， 實行成膜處理使連接用導體部7 C之上面與層間絕緣膜 4 a之上面大約一致》又，連接用導體部7 C之材料係並 不被限定於W者，可施以各種變更，例如W合金，A 1 ， A 1合金也可以《 然後，如第3 1圖所示，在層間絕緣膜4 a藉由光刻 法技術及乾蝕刻技術形成配線用溝5 a。此時，在配線用 溝5 a中露出連接用導體部7 C之上部。 然後，如第3 2圖所示，在包括配線用溝5 a之層間 絕緣膜4 a之表面及連接用導體部7 C之露出表面，藉由 濺射法覆蓋例如T i N等所構成的較薄導體膜6 L 1。該 較薄導體膜6 L 1係具有提高第1層配線與層間絕緣膜 4 a之密接性的功能或抑制較厚導體膜之構成原子之擴散 的阻障功能的材料所構成，並不被限定於T i N者，可施 以各種變更，例如W，TiN，Ti，Ta，WN’ -------------裝 * If n- n- tt aa_v 訂------!線 (請L閱讀背面之注意事項再i:.s本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用争囤國家標準（CNS)A4規格（210 χ 297公釐> -44- 4 b 9 3 4· ^ A7 B7_____ 五、發明說明（42 ) WS iN，Ti S iN，TaN或TaSiN等也可以 * <請先閱讀背面之注意事項再1,、本頁) 然後，在較薄導體膜6 6 1上，藉由CVD法，濺射 法或電鍍法，或組合此等等覆蓋例如C u等所構成的較厚 導體膜6L2。在該Cu等之成膜時，儘可能採用伸出較 小之分步敷層優異之方法。例如在濺射法，適用靶與半導 體晶圓之間的距離隔間半導體晶圓之半徑以上的濺射裝置 。該較厚導體膜6 L 2係並不被限定於C u者，可施以各 種變更，例如Cu合金，Al、 A1合金，W或N合金也 可以。 以濺射法成膜上述之配線用導體膜時，特別是，繼續 地介經對於半導體基板1施以熱處理，流動較厚導體膜 6 L 2之構成原子（例如C u )而將該構成原子充分地供 給並埋入在配線用溝5 a內。此時•熱處理氣氛係作爲惰 性氣體氣氛，氧化性氣體氣氛或還原氣體氣氛中之任何一 種，或是組合該兩種以上的氣氛。又，採用在C u之濺射 期間施行該熱處理的所謂反流濺射法也可以。由此，可提 高Cu配線之EM特性。 經濟部智慧財產局員工消費合作社印製 之後，介經對於半導體基板1施以CMP處理，介經 除去配線用溝5 a ，5b (參照第1圖）以外之領域的層 間絕緣膜4 a上之較厚導體膜6 L 2及較薄導體膜6 L 1 ，如第2 8圖所示，在配線用溝5 a內形成第1層配線 6L，同時，形成連接用導體部7C。 在該CMP處理後或處理前對於半導體基板1施以熱 處理也可以。此時，熱處理氣氛係作爲惰性氣體氣氛，氧 本紙張尺度iS用中國國家標準<CNS)A4規格（210 X 297公;g ) • 46 - 9 34 2 A7 B7 五、發明說明（43 ) 化性氣體氣氛或還元氣體 兩種以上的氣氛i在該C 較厚半導體基板6 L 2的 ，同時在CMP處理時避 厚導體膜6 L 2之表面的 滑。同時除去減低絕緣膜 提高配線之可靠性。 又，此等埋入配線構 第2層配線9L。亦即， 選擇CVD法所形成之W 導體膜所構成的構造》 如此，依照本實施形 態1同樣之效果/ 氣氛中之任何一種，或是組合該 MP處理後之熱處理過程，促進 C II之粒子成長並提髙EM耐性 免產生在較薄導體膜6 L 1及較 損傷或氧化膜而得其表面成爲平 4 a的表面污染。由此，成爲可 造，如第3 3圖所示，也適用於 連接用導體部1 0 C，成爲例如 ，W合金，A1 ，A1合金等之 態3，成爲可得到與上述實施形 請 先 閲 讀 背 面 之 注 訂 經濟部智慧財產局員工消費合作社印«衣Q Figure 25 shows the semiconductor body circuit device in the manufacturing process. In the interlayer insulating film 4a, a wiring groove 5a and a connection hole 8a are formed by the method described in the second embodiment. First, in the third embodiment, as shown in Fig. 26, a connection conductor portion 7C made of, for example, W is formed in the connection hole 8a by a selective CVD method. At this time, in the third embodiment, a film forming process is performed so that the upper portion of the connection conductor portion 7C protrudes to the outside of the wiring groove 5a. The material of the connecting conductor portion 7 C is not limited to W, and various changes may be made. For example, W alloy, A 1, and A 1 alloy may be used. Then, as shown in FIG. The surface of the interlayer insulating film 4 a of the wiring groove 5 a and the surface of the connection conductor portion 7 C are covered with a thin conductor film 6 L 1 made of, for example, T i N by a sputtering method. 6 L1 is composed of materials that have the function of improving the adhesion between the first layer of wiring and the interlayer insulating film 4 a or the barrier function of suppressing the diffusion of constituent atoms of thicker conductor films, and are not limited to T i N, Various changes can be made, such as W, TiN, Ti, Ta, WN, WSiN, TiSiN, TaN or TaSiN, etc. "Then, on a thinner conductor film 661, by CVD, sputtering Method or electroplating method to cover a thicker conductor film made of, for example, Cu, etc. 6 L 2 This paper is again applicable to the National Standard of the Park < CNS) A4 specification (210 * 297 mm) —111 — — — — — — — — · ≪ ttit.wtk on the back of the page; I will re-item the {> »page" order. ·, · Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Industrial Cooperatives System -427 Α7 Β7 4 2 V. Description of the invention (40). In the film formation of the C U and the like, it is preferable to use a method that is excellent in a stepwise coating with a small extension as much as possible. For example, in the sputtering method, a sputtering device having a radius greater than the radius of the semiconductor wafer between the target and the semiconductor wafer is used. The thicker conductor film 6 L 2 is not limited to Cu, and various changes can be made, such as Cu alloy, A 1, A 1 alloy, W or N alloy can also be formed by the sputtering method. In the case of a conductor film for wiring, in particular, the semiconductor substrate 1 is further subjected to a heat treatment to flow the constituent atoms (for example, Cu) of the thicker conductor film 6 L 2, and the constituent atoms are sufficiently supplied and buried in the conductor film. Wiring groove 5 a. At this time, the heat treatment atmosphere is any one of an inert gas atmosphere, an oxidizing gas atmosphere, or a reducing gas atmosphere, or a combination of two or more of them. It is also possible to use a so-called counter-current sputtering method in which the heat treatment is performed during the sputtering of Cu. This can improve the EM characteristics of Cu wiring. After that, the semiconductor substrate 1 is subjected to a CMP process. The thicker conductor film 6 L 2 and the thinner conductor on the interlayer insulation film 4 a are removed except for the wiring grooves 5 a and 5 b (see FIG. 1). The film 6 L 1, as shown in FIG. 28, forms the first layer wiring 6 L in the wiring groove 5 a * At the same time i forms the connection conductor portion 7 C ^ After the C.MP treatment or before The semiconductor substrate 1 may be heat-treated. At this time, the heat treatment atmosphere is any one of an inert gas atmosphere, an oxidizing gas atmosphere, or a reducing gas atmosphere, or a combination of two or more of them. The heat treatment process after the CMP treatment promotes the growth of Cu particles of the thicker semiconductor substrate 6 L 2 and improves the EM resistance. At the same time, during the CMP treatment, the thinner conductor film 6 L 1 and the paper size applicable to China are applicable to China. National Standard (CNS) A4 Specification (210 X 297 mm) 1 — — — — — — — — — — — — 1111111 ^ 0 — — — — — — — (Please read the notes on the back and then t, (This page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs-43- Α7 Β7 34 2 V. Description of the invention (41) The surface of the conductor film 6 L 2 is damaged or oxidized so that its surface becomes smooth. At the same time, the surface contamination of the insulating film 4 a is reduced. This makes it possible to improve the reliability of the wiring-and to form a buried wiring having a structure as shown in Fig. 28, for example, it may be performed as follows. First, as shown in FIG. 29, a connection hole 8a is formed in the interlayer insulating film 4a so that a part of the upper surface of the semiconductor substrate 1 is exposed by a pre-etching technique and a dry etching technique. Then, as shown in FIG. 30, in the connection hole 8a, a connection conductor portion 7C composed of, for example, W is formed by a selective CVD method. At this time, the film forming process is performed so that the upper surface of the connecting conductor portion 7 C and the upper surface of the interlayer insulating film 4 a are approximately the same. The material system of the connecting conductor portion 7 C is not limited to W, and various materials can be applied. For example, W alloy, A 1, and A 1 alloy may be modified. Then, as shown in FIG. 31, a trench 5 a for wiring is formed on the interlayer insulating film 4 a by a photolithography technique and a dry etching technique. At this time, the upper portion of the connection conductor portion 7C is exposed in the wiring groove 5a. Then, as shown in FIG. 32, on the surface of the interlayer insulating film 4a including the wiring groove 5a and the exposed surface of the connection conductor portion 7C, for example, Ti N is formed by sputtering. Thinner conductor film 6 L 1. The thinner conductor film 6 L 1 is not limited to a material having a function of improving the adhesion between the first layer wiring and the interlayer insulating film 4 a or a barrier function of suppressing the diffusion of constituent atoms of the thicker conductor film. For T i N, various changes can be applied, such as W, TiN, Ti, Ta, WN '------------- install * If n- n- tt aa_v order ---- -! Line (please read the notes on the back and then i: .s this page) printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperatives, this paper is printed with the national standard (CNS) A4 specification (210 x 297 mm & gt -44- 4 b 9 3 4 · ^ A7 B7_____ V. Description of the invention (42) WS iN, Ti S iN, TaN or TaSiN etc. can also be used * < Please read the precautions on the back first, 1, this page) Then, the thinner conductor film 6 61 is covered with a thicker conductor film 6L2 made of, for example, Cu or the like by a CVD method, a sputtering method, or a plating method, or a combination thereof. In the film formation of Cu and the like, a method that is excellent in a stepwise coating with a small extension is used as much as possible. For example, in the sputtering method, a sputtering device having a distance greater than the radius of the semiconductor wafer between the target and the semiconductor wafer is applicable. The thicker conductor film 6 L 2 is not limited to Cu, and various modifications can be made. For example, Cu alloy, Al, A1 alloy, W or N alloy may be used. When the above-mentioned conductor film for wiring is formed by a sputtering method, in particular, the constituent atoms (for example, Cu) of a thicker conductor film 6 L 2 are continuously flowed through a heat treatment to the semiconductor substrate 1 to pass the constituent atoms. It is fully supplied and buried in the wiring trench 5a. At this time, the heat treatment atmosphere is any one of an inert gas atmosphere, an oxidizing gas atmosphere, or a reducing gas atmosphere, or a combination of two or more of them. It is also possible to use a so-called counter-current sputtering method in which the heat treatment is performed during the sputtering of Cu. This can improve the EM characteristics of Cu wiring. After printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, the semiconductor substrate 1 is subjected to a CMP process, and the interlayer insulating film 4 a on the area other than the wiring grooves 5 a and 5b (see FIG. 1) is removed. As shown in FIG. 28, the thicker conductor film 6 L 2 and the thinner conductor film 6 L 1 form a first layer wiring 6L in the wiring groove 5 a, and at the same time, a connection conductor portion 7C is formed. The semiconductor substrate 1 may be thermally treated after or before the CMP process. At this time, the heat treatment atmosphere is an inert gas atmosphere, and the paper size iS uses the Chinese national standard < CNS) A4 specification (210 X 297 g; g) • 46-9 34 2 A7 B7 V. Description of the invention (43) Two or more kinds of atmospheres i, i.e., a gaseous gas atmosphere or a reduced gas atmosphere, on the C thick semiconductor substrate 6 L 2, and at the same time, the surface of the thick conductor film 6 L 2 is prevented from slipping during the CMP process. At the same time, the reduced insulation film is removed to improve the reliability of the wiring. These buried wiring structures have a second layer wiring 9L. That is, the structure of the W conductor film formed by the CVD method is selected. Thus, in accordance with any of the same effects / atmospheres as in Embodiment 1, or combining the heat treatment process after the MP treatment, the particles of C II are promoted Grow and improve EM resistance to avoid surface contamination on the thinner conductor film 6 L 1 and the more damaged or oxidized film, resulting in a flat surface. As a result, it can be manufactured. As shown in FIG. 33, it can also be applied to the connecting conductor portion 10 C, and becomes, for example, state 3 of W alloy, A1, A1 alloy, and the like. Read the note on the back of the book, printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs
(實施形態4 ) 第3 4圖及第3 5圖係表示本發明之其他實施形態之 半導體積體電路裝置的要部剖面圖《 在本實施形態中，如第3 4圖及第3 5圖所示，連接 用導體部7C，10C以較薄導體膜7C1 * 10C1所 構成。亦即，連接孔8a，8b以較薄導體膜7C1， 10C1埋入之構造。 較薄導體膜7 C 1，1 0 C 1係具有提高連接用導體 部7C，10C與層間絕緣膜4a，4b之密接性的功能 或抑制配線之構成原子的阻障功能的材料所構成，例如W 線 本紙張尺度適用中囷國家棵準（CNS)A4規格<210 X 297公S ) -46 - 4 59 34 2 A7 B7__ 五、發明說明（44 ) ，TiN，Ti，Ta，WN，WSiN，TiSiN， TaN或TaSiN等所構成。 連接孔8a之直徑係例如約Ο · 1〜Ο · 4/im，較 理想係例如0 · 2 /zm"又，連接孔8 a之縱横比係約2 〜1 0，考慮良好地實行連接用導體部之埋入時，比約3 小較理想。 又，連接孔8b之直徑係例如約〇 . 1〜0 . 4gm ，較理想係例如約0.2#m。又，連接孔8b之縱橫比 係約2〜1 0，考慮良好地實行連接用導體部之埋入時， 比約5小較理想。 又|配線構造係並不被限定於表示於第3 3圖及第 3 4圖之構造者，可施以各種變更*表示於例如以上述實 施形態1所說明之第3圖至第5圖之構造也可以* 此等埋入配線之形成方法，與使用上述實施形態1的 第8圖至第1 2圖所說明相同。亦即，將第1層配線6 L 之形成方法作爲一例子係如下。 首先，在層間絕緣膜4 a穿孔連接孔8 a之後，在該 層間4 a上藉由濺射法等覆蓋埋入連接孔8 a的較薄導體 膜7 C 1。然後·介經對於半導體基板1施以CMP法等 ，在該較薄導體膜7 C 1除去連接孔8 a之領域以外的部 分，而在連接孔8 a內，形成僅由較薄導體膜7 C 1所構 成的連接用導體部7 C。然後，在層間絕緣膜4 a形成配 線用溝5 a之後，在該層間絕緣膜4 a上藉由濺射法或電 鍍法等覆蓋埋入配線用溝5 a的配線用導體膜。然後，介 本紙張尺度適用中因國家標準（CNS)Α4規格（210 X 297公茇> !!li 〃裝-----11_ 訂.！ I ·線 (請L閱讀背面之注意事項再ι,Η本頁) 經濟部智慧財產局員工消費合作杜印製 -47- 經濟部智慧財產局員工消費合作社印製 五、發明說明（45 ) 經對於半導體基板1施以CMP法等，在該記線用導體膜 除去配線用溝5 a之領域以外的部分，而在配線用溝5 a 內形成第1層配線6L。 在較厚導體膜6 L 1之成膜後或CMP處理後對於半 導體基板1施以熱處理也可以。此時，熱處理氣氛係作爲 惰性氣體氣氛，氧化性氣體氣氛或還元氣體氣氛中之任何 一種，或是組合該兩種以上的氣氛。介經施以熱處理，促 進較厚半導體基板6 L 2的C u之柱子成長並提高EM耐 性，同時在CMP處理時避免產生在較薄導體膜6 L 1及 較厚導體膜6 L 2之表面的損傷或氧化膜而將其表面成爲 平滑，及除去減低絕緣膜4 a的表面污染，因此，成爲可 提高配線之可靠性β 依照此等本實施形態4，成爲可得到與上述實施形態 1同樣之效果。 (實施形態5 ) 第3 6圖係表示本發明之其他實施形態之半導體積體 電路裝置的要部剖面圖，第3 7圖係表示第3 6圖之半導 體積體電路裝置的要部放大剖面圖，第3 8圖係表示於第 3 7圖之半導體積體電路裝置之要部之變形例的要部放大 剖面圖，第3 9圖係表示於第3 7圖之半導體積體電路裝 置的要部放大剖面圖，第4 0圖係模式地表示第3 9圖之 半導體積體電路裝置之要部的說明圖’第41圖係模式地 表示第4 0圖之變形例的說明圖，第4 2圖及第4 3圖係 本紙張尺度適用中园國家標準（CNS)A4規格（210 X 297公t ) -48- — 111111 — 1_1_ ^^ · I I I I I I I (請先M'讀背面之注意事項再产·'·.本頁) A7 B7 4 5b 34 2 五、發明說明（4ό) 模式地表示第4 0圖之變形例的說明圖，第4 4圖至第 4 8圖係表示第3 6圖之半導體積體電路裝置之要部之變 形例的要部放大剖面圖《 首先，藉由第3 6圖至第4 8圖說明本實施形態5的 半導體積體電路裝置之構造•本實施形態5之基本上的整 體構造，係例如如下。 第1，在第1層配線6L之構成材料，使用例如W， W合金，A 1或A 1合金等的Cu或Cu合金以外的導體 材料。由此，由於可將C u配線直接接觸於半導體基板1 之構造，因此，可抑制起因於C u原子擴散半導體基板1 側之元件不良，成爲可提高半導體積體電路裝置之可靠性 。又，介經隔離以C u配線所構成之第2，第3層配線 9L，11L與半導體基板1之距離，可減低Cu原子對 於半導體基板1之擴散。 第2，.在最上之第4層配線1 3 L之構成，使用例如 A 1或A 1合金等《由此，可仍然沿用以往就有的接合線 之連接技術或***電極之形成技術。亦即，雖然最上之配 線層係連接有接合線或***電極，惟將最上之配線材料作 爲以往就使用的A 1或A 1合金，成爲可仍然使用接合線 或***電極之接合上的以往技術》因此，不會隨著裝配過 程（線接合過程或***電極形成過程）的技術上之變更等 ，成爲可將具有C u系材料所構成的埋入配線構造旳半導 體積體電路裝置導入在裝配線。因此，可推動減低具有 C u系材料之埋入配線的半導體積體電路裝置之成本。成 --------------裝 * κι ϋ <請先‘Μ讀背面之注意事項再i .本頁) 訂. •線 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 x297公釐） -49- 經濟部智慧財產局具工消費合作社印製 ^ 34 2 a? _'_ B7 _ 五、發明說明（47 ) 爲可推動製造與開發時間之短期化。 第3，在最上之配線層與最下配線層之間的中間配線 層（第2層配線9L及第3層配線1 1L)的構成*例如 C u或C u合金》由此，可減低配線電阻或配線電容.，成 爲可提高半導體積體電路裝置之信號傳播速度，並成爲可 提高其動作速度· 第4，將連接以Cu系材料所構成之配線層間的連接 用導體部18C，19C，以例如W，TiN，Ti ，(Embodiment 4) Figures 34 and 35 are cross-sectional views of main parts of a semiconductor integrated circuit device according to other embodiments of the present invention. In this embodiment, as shown in Figures 34 and 35 As shown, the connecting conductor portions 7C, 10C are formed of thinner conductor films 7C1 * 10C1. That is, the connection holes 8a, 8b are embedded with thinner conductor films 7C1, 10C1. The thinner conductive film 7 C 1, 10 C 1 is made of a material having a function of improving the adhesion between the connecting conductor portions 7C, 10C and the interlayer insulating films 4a, 4b, or a function of suppressing the atomic barrier function of the wiring. The size of the W-line paper is applicable to the China Standard (CNS) A4 specification <210 X 297 male S) -46-4 59 34 2 A7 B7__ 5. Description of the invention (44), TiN, Ti, Ta, WN, WSiN , TiSiN, TaN or TaSiN. The diameter of the connection hole 8a is, for example, about 0. 1 to 0. 4 / im, and ideally, for example, 0. 2 / zm " The aspect ratio of the connection hole 8a is about 2 to 10, and it is considered to perform well for connection. When the conductor is buried, it is preferably smaller than about 3. The diameter of the connection hole 8b is, for example, about 0.1 to 0.4 gm, and more preferably, about 0.2 #m. The aspect ratio of the connection hole 8b is about 2 to 10, and it is preferable that it is smaller than about 5 when the embedding of the connection conductor portion is performed well. Also, the wiring structure system is not limited to those shown in FIGS. 33 and 34, and various changes can be made. * For example, shown in FIGS. 3 to 5 described in the first embodiment. The structure may also be formed. * The method of forming such buried wirings is the same as that described using FIGS. 8 to 12 of the first embodiment. That is, a method of forming the first-layer wiring 6 L as an example is as follows. First, after the interlayer insulating film 4a is perforated with the connection hole 8a, a thin conductive film 7C1 buried in the connection hole 8a is covered with the interlayer 4a by a sputtering method or the like. Then, by applying a CMP method or the like to the semiconductor substrate 1, the thinner conductor film 7 C 1 is removed from the area other than the area of the connection hole 8 a, and within the connection hole 8 a, only the thinner conductor film 7 is formed. C 1 is a connecting conductor portion 7 C. Then, after the wiring groove 5a is formed on the interlayer insulating film 4a, the wiring conductor film buried in the wiring groove 5a is covered with the interlayer insulating film 4a by a sputtering method or an electroplating method or the like. Then, the paper standards apply to the national standard (CNS) Α4 specification (210 X 297 males > !! li outfit ----- 11_ order.! I · line (please read the precautions on the back again) ι, Η this page) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs on the Consumer Consumption Du-47- Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs of the Consumer Consumption Cooperative V. Invention Description (45) After applying the CMP method to semiconductor substrate 1, The conductor film for wiring is removed from the area outside the wiring groove 5a, and the first layer wiring 6L is formed in the wiring groove 5a. For the semiconductor after the film formation of the thicker conductor film 6L1 or after the CMP treatment, The substrate 1 may be heat-treated. At this time, the heat-treatment atmosphere is any one of an inert gas atmosphere, an oxidizing gas atmosphere, or a reduced gas atmosphere, or a combination of two or more of these atmospheres. The Cu pillars of the thick semiconductor substrate 6 L 2 grow and improve the EM resistance. At the same time, during the CMP process, damage to the thinner conductor film 6 L 1 and the thicker conductor film 6 L 2 or damage to the oxide film is prevented. The surface becomes smooth and the insulation film is removed 4 The surface contamination of a can improve the reliability of the wiring β According to the fourth embodiment, the same effect as that of the first embodiment can be obtained. (Embodiment 5) Figures 3 and 6 show other aspects of the present invention. The main part sectional view of the semiconductor integrated circuit device according to the embodiment, FIG. 37 is an enlarged cross-sectional view showing the main part of the semiconductor integrated circuit device of FIG. 36, and FIG. 38 is the semiconductor shown in FIG. 37. An enlarged sectional view of an essential part of a modified example of an essential part of the integrated circuit device, FIG. 39 is an enlarged sectional view of an essential part of the semiconductor integrated circuit device shown in FIG. 37, and FIG. Illustrative diagrams of the main parts of the semiconductor integrated circuit device shown in Figs. 9 and 9 'Fig. 41 is an explanatory diagram schematically showing a modification of Fig. 40, and Figs. 4 2 and 43 are drawings applicable to this paper. National Standard (CNS) A4 Specification (210 X 297 Gt) -48- — 111111 — 1_1_ ^^ IIIIIII (Please read M'Notes on the back before re-production · '. This page) A7 B7 4 5b 34 2 V. Description of the invention (4th) An explanatory diagram schematically showing a modified example of Fig. 40, Fig. 4 4 to 48 are enlarged cross-sectional views of main parts showing a modification of the main part of the semiconductor integrated circuit device of Fig. 36. "First, this embodiment will be described with reference to Figs. 36 to 48 Structure of a semiconductor integrated circuit device • The basic overall structure of the fifth embodiment is, for example, as follows. First, as a constituent material of the first layer wiring 6L, for example, W, W alloy, A 1 or A 1 alloy is used. Conductive materials other than Cu or Cu alloys. Accordingly, since the Cu wiring can be directly contacted to the semiconductor substrate 1, it is possible to suppress component failures due to the Cu atom diffusion semiconductor substrate 1 side and improve the reliability of the semiconductor integrated circuit device. In addition, the distance between the second and third layer wirings 9L, 11L formed by Cu wiring through the isolation and the semiconductor substrate 1 can reduce the diffusion of Cu atoms into the semiconductor substrate 1. Second, the structure of the uppermost layer 4 wiring 1 3 L uses, for example, A 1 or A 1 alloy, etc., and thus the conventional connection wire connection technology or bump formation technology can be used. That is, although the uppermost wiring layer is connected with a bonding wire or a raised electrode, the uppermost wiring material is conventionally used as A 1 or A 1 alloy, and it is a conventional technology that can still use a bonding wire or a raised electrode for bonding. 》 Therefore, it will not be possible to introduce buried wiring structures made of Cu-based materials and semiconductor integrated circuit devices into the assembly line due to technical changes in the assembly process (wire bonding process or bump formation process). . Therefore, it is possible to promote a reduction in the cost of a semiconductor integrated circuit device having a buried wiring of a Cu-based material. Into -------------- equipment * κι ϋ < Please read the precautions on the back before i. This page) Order. • Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper size applies to China National Standard (CNS) A4 (210 x 297 mm) -49- Printed by the Industrial and Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ^ 34 2 a? _'_ B7 _ V. Description of Invention (47) is Can promote short-term manufacturing and development time. Third, the configuration of the intermediate wiring layer (the second layer wiring 9L and the third layer wiring 1 1L) between the uppermost wiring layer and the lowermost wiring layer * For example, Cu or Cu alloy can reduce the wiring. Resistors or wiring capacitors are used to increase the signal transmission speed of semiconductor integrated circuit devices and increase their operating speed. Fourth, connecting conductor portions 18C, 19C that connect wiring layers made of Cu-based materials, Take for example W, TiN, Ti,
Ta，WN，WSiN，TiSiN，TaI^ T a S i N等所構成之材料所構成。由此，由於在微細連 接孔8 g，8 h內可良好地埋入導體膜，因上，成爲可提 高配線層間的電氣式連接的可靠性。 第5，未直接接觸A 1系所構成的第4層配線1 3 L ，及C u系材料所構成的第3層配線1 1 L，而在其中間 介裝阻障層（連接用導體部2 0 C等）。由此，直接接觸 A 1系材料與C u系材料時，由於可抑制高電阻係數之合 金層的環境，因此，成爲可提高流在配線之信號的傳播速 度。 第6，在位於連接用導體部1 9 C與連接用導體部 2 0 C所連接之部分的配線層中，設置至少沿著配線之長 度方向比連接用導體部1 9 C，2 0 C平面地較長所形成 的連接用導體部（中繼用之連接用導體部）2 1 C ·並電 氣式地連接上述之連接用導體部2 0 C。由此’由於可將 連接用導體部2 1 C所形成之配線用溝5 g之平面積成爲 本紙張尺度適用中國1家標準（CNS>A4規格（210 X 297公发） -50- -------------裝 * I ft— n I* 訂---------線 (請先閱讀背面之沒意事項艮内本頁) 459 34 2 五、發明說明（48) 較大，因此，成爲在該溝內良好地埋入配線用導體膜。又 ，成爲可增大連接用導體部1 9 C與連接用導體部2 0 C 之配線的長度方向之平面性對位的餘量。因此，成爲可提 高上下之連接用導體部1 9 C，2 0 C之連接上的可靠性 〇 以下，詳述本實施形態5之半導體積體電路裝置的各 構成部。 埋入於配線用溝5 a，5b內所形成的第1層配線 6 L，係由下部與側部之相對地較薄導體膜6 L 1，及被 該較薄導體膜6 L 1所圍繞之相對地較厚導體膜6 L 2所 構成。較薄導體膜6 L 1係具有提高第1層配線6 L與層 間絕緣膜4 a之密接性的功能或抑制較厚導體膜6 L 2之 構成原子之擴散的阻障功能的材料所構成，例如W， T i' N - T i，Ta，WN，WSiN，TiSiN， TaN或TaSiN等所構成》 以W等構成較薄導體膜6 L 1時，與以T i N，T i ，Ta，WN，WSiN，TiSiN，TaI^ T a S i N等所構成時相比較，成爲可降低配線電阻。雖 並不被特別限定，惟在本實施形態5，較薄導體膜6 L 1 係例如以W所構成。 又，較厚導體膜6 L 2係構成第1層配線6 L之本體 的構件，例如A 1 ，A 1合金，W或W合金之低電阻之材 料所構成》雖並不被特別限定，惟在本實施形態5，較厚 導體膜6 L 2係例如以W所構成。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --------I-----裝 i — <請先闓讀背面之注意事項再本頁) 訂-· .線 經濟部智慧財產局員工消費合作社印製 -51 - A7 B7 五、發明說明（49) 但是，第1層配線6 L之構造係並不被限定於表示於 第3 6圖及第3 7儸之構造者而可施以各種變更，作成在 上述實施形態1中使用第3圖至第5圖所說明的構造也可 以。亦即，有在較厚導體膜6 L 2與較薄導體膜6 L 1上 設置帽蓋導體膜之構造；在較厚導體膜6 L 2上設置帽蓋 導體膜，且將帽蓋導體膜之上面與層間絕緣膜4 a之上面 成爲大約一致的構造；僅在較厚導體膜6 L 2構成配線的 構造；僅在較厚導體膜6 L 2構成配線時在其上面設置帽 蓋導體膜的構造等。帽蓋導體膜係例如W，T i N，T i ，Ta，WN，WSiN，TiSiN，TaI^ TaSiN等所構成。 配線用溝5 a之第1層配線6 L係經連接孔8 a與 nMO S 3 η之半導體領域3 n d或pMO S 3 P之半導 體領域3 p d電氣式地連接》在本實施形態5中，在配線 用溝5 a與連接孔8 a內一體地埋入有配線形成用導體膜 請 先. 闓 讀 背 面Ta, WN, WSiN, TiSiN, TaI ^ T a S i N and other materials. As a result, the conductor film can be buried well within 8 hours of the fine connection hole, thereby improving the reliability of the electrical connection between the wiring layers. Fifth, the fourth layer wiring 1 3 L made of A 1 series and the third layer wiring 1 1 L made of Cu material are not directly contacted, and a barrier layer (connection conductor portion) is interposed therebetween. 2 0 C, etc.). Therefore, when directly contacting the A1-based material and the Cu-based material, the environment of the alloy layer with a high resistivity can be suppressed, and thus the propagation speed of a signal flowing in the wiring can be increased. Sixth, the wiring layer located at a portion where the connecting conductor portion 19 C and the connecting conductor portion 20 C are connected is provided at least along the length of the wiring than the connecting conductor portion 19 C, 2 0 C plane The connection conductor portion (relay connection conductor portion) 2 1 C formed by a long ground is electrically connected to the connection conductor portion 2 C described above. As a result, since the flat area of 5 g of the wiring groove formed by the connecting conductor portion 2 1 C can be used as one paper standard in China (CNS > A4 specification (210 X 297)) -50-- ----------- install * I ft— n I * order --------- line (please read the unintentional items on the back page on this page first) 459 34 2 V. Invention Explanation (48) is large, so that the conductor film for wiring is well embedded in the groove. It also becomes a lengthwise increase in the length of the wiring between the connection conductor portion 19 C and the connection conductor portion 20 C. Flatness alignment margin. Therefore, it is possible to improve the reliability of the connection between the upper and lower connection conductor portions 19 C, 20 C. Hereinafter, each structure of the semiconductor integrated circuit device of the fifth embodiment will be described in detail The first layer of wiring 6 L formed by being buried in the wiring grooves 5 a and 5 b is formed by a relatively thin conductor film 6 L 1 from the lower portion to the side portion, and the thin conductor film 6 L 1 The relatively thick conductive film 6 L 2 surrounds it. The thinner conductive film 6 L 1 has the function of improving the adhesion between the first layer wiring 6 L and the interlayer insulating film 4 a or suppressing the thicker conductive film 6. L 2 is made of a material that forms the barrier function of atomic diffusion, for example, W, T i 'N-T i, Ta, WN, WSiN, TiSiN, TaN, or TaSiN, etc. At 6 L 1, the wiring resistance can be reduced compared to the case of T i N, T i, Ta, WN, WSiN, TiSiN, TaI ^ Ta Si N, etc. Although it is not particularly limited, but In the fifth embodiment, the thinner conductive film 6 L 1 is composed of, for example, W. The thicker conductive film 6 L 2 is a member constituting the body of the first layer wiring 6 L, such as A 1, A 1 alloy, W or W alloy with low resistance material composition "is not particularly limited, but in this embodiment 5, the thicker conductor film 6 L 2 is composed of, for example, W. This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -------- I ----- install i — < please read the precautions on the back before reading this page) Order- ·. Intellectual Property Bureau, Ministry of Economic Affairs Printed by Employee Consumption Cooperatives -51-A7 B7 V. Description of Invention (49) However, the structure of the first-layer wiring 6 L is not limited to those shown in Figures 36 and 37. To Various changes may be made to the structure described in the first embodiment using Figs. 3 to 5. That is, there is a structure in which a cap conductor film is provided on the thicker conductor film 6 L 2 and a thinner conductor film 6 L 1; a cap conductor film is provided on the thicker conductor film 6 L 2, and the cap conductor film is provided The upper surface and the upper surface of the interlayer insulating film 4 a have approximately the same structure; the structure of the wiring is formed only by the thicker conductor film 6 L 2; and the capped conductor film is provided thereon only when the thicker conductor film 6 L 2 constitutes the wiring. The construction and so on. The cap conductor film is composed of, for example, W, TiN, Ti, Ta, WN, WSiN, TiSiN, TaI ^ TaSiN, and the like. The first layer wiring 6 L of the wiring groove 5 a is electrically connected to the semiconductor field 3 nd of nMO S 3 η or the semiconductor field 3 pd of pMO S 3 P via the connection hole 8 a. In the fifth embodiment, The wiring formation conductor film is embedded in the wiring groove 5 a and the connection hole 8 a integrally. 闿 Read the back
意 事 項 再I I 本 頁 裝 訂 線 經濟部智慧財產局員工消費合作社印製 此等第1層配線6 L之形成方法，係例如與以下之以 往之埋入配線的形成方法相同。亦即*將配線用溝5 a， 5 b與連接孔8 a藉由各該之光刻法技術及乾蝕刻技術形 成層間絕緣膜4 a之後，藉由濺射法覆蓋例如W等所構成 的較薄導體膜6L1，又，在該較薄導體膜6L1上，藉 由CVD法等形成例如W等所構成的較厚導體膜6 L 2 » 由此，成爲在微細連接孔8 a內也可良好地埋入導體膜。 然後，施以CMP處理，除去配線用溝5a，5b及連接 本紙張尺度適用中國國家標準（CNS)A4規格（210 * 297公釐） -52- 4 6 9 34 2 A7 B7 五、發明說明（抝）Matters Reprinted on this page Binding line Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs The method of forming these first-layer wiring 6 L is the same as, for example, the following method of forming buried wiring. That is, * the wiring grooves 5 a, 5 b and the connection holes 8 a are formed by the respective photolithography and dry etching techniques to form an interlayer insulating film 4 a, and then are covered with, for example, W by sputtering. A thinner conductor film 6L1 is formed on the thinner conductor film 6L1 by a CVD method or the like, and a thicker conductor film 6 L 2 made of, for example, W is formed. Well buried conductor film. Then, CMP treatment is applied to remove the wiring grooves 5a, 5b and the connection. This paper applies the Chinese National Standard (CNS) A4 specification (210 * 297 mm) -52- 4 6 9 34 2 A7 B7 V. Description of the invention ( bend)
孔8 a以外的導體膜，俾形成埋入構造之第1層配線6 L 〇 埋入於配線用溝5 c，5 d內所形成的第2層配線 9 L，係下部與側部之相對地較薄導體膜9 L 1 ，及被該 較薄導體膜9 L 1所圍繞之相對地較厚導體膜9 L 2所構 成。較薄導體膜9 L 1，係具有提高第2層配線9 L與層 間絕緣膜4 b之密接性的功能或抑制較厚導體膜9 L 2之 構成原子之擴散的阻障功能的材料所構成，例如W | T i N > T i，Ta，WN，WSiN，TiSiN， TaN或Ta S i N等所構成》 以W等構成較薄導體膜9 L 1時，與以T i N » 丁 i ，Ta，WN，WSiN*TiSiN，Tar^ T a S i N等所構成時相比較，成爲可降低配線電阻》雖 並未被特別限定，惟在本實施形態5中，較薄導體膜 9 L 1係例如以T i N所構成。 又，較厚導體膜9 L 2係構成第2層配線9 L之本體 的構件，例如C u或C u合金等之低電阻材料所構成•但 是，第2層配線9 L之構造係並不被限定於表示在第3 6 圖構造者而可施以各種變更，作成在上述實施形態1中使 用第3圖至第5圖所說明之構造也可以》亦即，有在較厚 導體膜9 L 2與較薄導體膜9 L 1上設置帽蓋導體膜之構 造：在較厚9 L 2上設置帽蓋導體膜；且將帽蓋導體膜之 上面與層間絕緣膜4 b之上面成爲大約一致的構造；僅以 較厚導體膜9 L 2構成配線的構造；僅在以較厚導體膜 本紙張尺度適用中國國家標準（CNS)A4規格（210 * 297公釐） ---------------裝--- (請先閲讀背面之注意事項再pi本頁) 訂· -線. 經濟部智慧財產局員工消费合作社印製 -53- 4b9 34 2 A7 B7 _ _ 五、發明說明（51 ) 9 L 2構成配線時在其上面設置帽蓋導體膜的構造等*帽 蓋導體膜係例如W，TiN，Ti ，Ta，WN， 配線用溝5 c之第2層配線9 L係經連接孔8 g與第 1層配線9L電氣式地連接。連接扎8 g係從配線用溝 5 c之底面向第1層配線6 L之上面，使其第1層配線 6 L之上面一部分露出地彤成，而在該孔內，設有例如w ，W合金，A 1或A 1合金所構成的連接用導體部1 8 c 〇 又’埋入於配線用溝5 e內所形成的第3層配線 1 1 L ’係與第2層配線9 L之構造相同，下部與側部之 相對地較薄導體膜1 1 L 1，及被該較薄導體膜1 1 L 1 所圍繞之相對地較厚導體膜1 1 L 2所構成。較薄導體膜 1 1 L 1係具有提高第3層配線1 1 L與層間絕緣膜4C 之密接性的功能或抑制較厚導體膜1 1 L 2之構成原子之 擴散的阻障功能的材料所構成，例如W，T i N , T i，The conductor film other than the hole 8 a forms the first layer wiring 6 L of the buried structure. The second layer wiring 9 L formed by being buried in the wiring trench 5 c, 5 d is the opposite of the lower part to the side. The thinner ground conductor film 9 L 1 and the relatively thicker conductor film 9 L 2 surrounded by the thinner conductor film 9 L 1. The thinner conductive film 9 L 1 is made of a material having a function of improving the adhesion between the second layer wiring 9 L and the interlayer insulating film 4 b or a barrier function of suppressing the diffusion of constituent atoms of the thicker conductive film 9 L 2. For example, W | T i N > T i, Ta, WN, WSiN, TiSiN, TaN or Ta S i N, etc. "When a thin conductive film 9 L 1 is formed with W or the like, and T i N» D i, Ta, WN, WSiN * TiSiN, Tar ^ T a S i N, etc., can reduce wiring resistance when compared. Although not particularly limited, in the fifth embodiment, the thinner conductor film 9 L 1 is composed of, for example, T i N. Also, the thicker conductor film 9 L 2 is a member constituting the body of the second layer wiring 9 L, such as a low resistance material such as Cu or Cu alloy. However, the structure of the second layer wiring 9 L is not It is limited to the structure shown in FIG. 3 and can be modified in various ways, and the structure described in FIGS. 3 to 5 in the first embodiment may be used. That is, there is a thicker conductor film 9 L 2 and the thinner conductor film 9 L 1 are provided with a cap conductor film structure: a thicker 9 L 2 is provided with a cap conductor film; and the top of the cap conductor film and the top of the interlayer insulating film 4 b are approximately Consistent structure; only the thick conductor film 9 L 2 constitutes the wiring structure; the Chinese National Standard (CNS) A4 specification (210 * 297 mm) is only applicable to the paper size of the thick conductor film ------ --------- Install --- (Please read the precautions on the back before pi this page) Order · -line. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs -53- 4b9 34 2 A7 B7 _ _ V. Description of the invention (51) 9 L 2 Structure for providing a cap conductor film on the wiring when forming wiring * Cap conductor film systems such as W, TiN, Ti, Ta, WN The second-layer wiring 9 L of the wiring groove 5 c is electrically connected to the first-layer wiring 9L through the connection hole 8 g. The connection 8 g is formed from the bottom of the wiring groove 5 c to the upper surface of the first layer wiring 6 L, so that a part of the upper surface of the first layer wiring 6 L is exposed, and in the hole, for example, w is provided, The connecting conductor portion 1 8 c made of W alloy, A 1 or A 1 alloy is also 'the third layer wiring 1 1 L' formed by being buried in the wiring groove 5 e and the second layer wiring 9 L The structure is the same, which is composed of a relatively thin conductor film 1 1 L 1 at the lower portion and a side portion, and a relatively thick conductor film 1 1 L 2 surrounded by the thinner conductor film 1 1 L 1. The thinner conductor film 1 1 L 1 is a material having a function of improving the adhesion between the third-layer wiring 1 1 L and the interlayer insulating film 4C or a barrier function of suppressing the diffusion of constituent atoms of the thicker conductor film 1 1 L 2. Composition, such as W, T i N, T i,
Ta，WN，WSiN，TiSiN，TaNS T a S i N等所構成。 以W等構成較薄導體膜1 1 L 1時，與以T i N，Ta, WN, WSiN, TiSiN, TaNS Ta Si N, etc. When a thin conductive film 1 1 L 1 is formed with W or the like, and T i N
Ti ，Ta ，WN，WSiN，丁iSiN'TaN或 T a S i N等所構成時相比較，成爲可降低配線電阻。雖 並未被特別限定，惟在本實施形態5中，較薄導體膜 1 1 L 1係例如以T i N所構成。 又，較厚導體膜1 1 L 2係構成第3層配線1 1 L之 本紙張尺度適用中因困家標準（CNS)A4規格（210 X 297公釐） -------------裝----- ϋ it ϋ · IP n n I 線 (請先'閲讀背面之泫意事項再1{,本頁) 經濟部智慧財產局員工消費合作社印製 -54- 459342 ； 五、發明說明（52) 本體的構件，例如C u或C u合金等之低電阻材料所構成 •但是，第3層配線1 1 L之構造係並不被限定於表示在 第3 6圖構造者而可施以各種變更，作成在上述實施形態 1中使用第3圖至第5圇所說明之構造也可以。亦即，有 在較厚導體膜1 1 L 2與較薄導體膜1 1 L 1上設置帽蓋 導體膜之構造；在較厚1 1 L 2上設置帽蓋導體膜，且將 帽蓋導體膜之上面與層間絕緣膜4 b之上面成爲大約一致 的構造：僅以較厚導體膜1 1 L 2構成配線的構造：僅在 以較厚導體膜1 1 L 2構成配線時在其上面設置帽蓋導體 膜的構造等。帽蓋導體膜係例如W，T i N，T i ，Ta 所構成。 配線用溝5 e之第3層配線1 1 L係經連接孔8 h與 第2層配線9 L電氣式地連接。連接孔8 h係從配線用溝 5 e之底®向第2層配線9 L之上面，使其第2層配線 9 L之上面一部分露出地形成，而在該孔內，設有例如W ，W合金，A 1或A 1合金所構成的連接用導體部1 9 c c 如下述第39 (A)圖所示*第2層配線9L係設成 例如向Y方向延伸，而第2層配線9 L間的節距係向X方 * 向以所定値被設計。又，第3層配線1 1 L係設成例如向 垂直於Y方向之X方向延伸，而第3層配線1 1 L間的節 距係向Y方向以所定値被設計6 此等第2層配線9 L與第3層配線1 1 L之形成方法 本紙張尺度適用_國國家標準（CNS)A4規格（210 * 297公釐> I I I— ϋ ϋ n. I— 1_ * 1. n 請L閲讀背面之注意事項再本頁) 訂· _線· 經濟部智慧財產局員工消費合作社印製 -55- 4 59 34 2 五、發明說明（53 ) *係與例如以往之埋入配線的形成方法相同。亦即*將第 2層配線9 L之彤成方法作爲例子加以說明如下。 首先，將配線用溝5 c，5 d及連接孔8 g分別藉由 光刻法技術及乾蝕刻技術形成在層間絕緣膜4 b之後，將 例如W等所構成之導體膜藉由選擇CVD法等選擇性地成 長於連接孔8 g內以形成連接用導體部1 8 c · 然後，藉由濺射法覆蓋例如T i N等所構成之較薄導 體膜9L1 ，又，在該較薄導體膜9L1上，藉由濺射法 ，CVD法或電鍍等形成例如Cu或Cu合金等所構成的 較厚導體膜9 L 2。該過程後，施以熱處理而將C u原子 良好地塡充於配線用溝5c ，5d內也可以。由此，成爲 在微細連接孔8 g內良好地埋入導體膜》 然後，對於半導體基板1施以CMP處理俾除去配線 用溝5 c，5 d以外的導體膜，形成埋入構造之第2層配 線9 L。在較厚導體膜9 L 2之成膜後或CMP處理後對 於半導體基板1施以熱處理也可以。此時，熱處理氣氛係 作爲惰性氣體氣氛，氧化性氣體氣氛或還元氣體氣氛中之 任何一種*或是組合該兩種以上的氣氛。介經施以熱處理 ，促進較厚半導體基板9 L 2的C u之粒子成長並提高 EM耐性，同時在CMP處理時避免產生在較薄導體膜 6 L 1之表面的損傷或氧化膜而將其表面成爲平滑，又除 去減低絕緣膜4 a的表面污染，因此，成爲可提髙配線之 可靠性。 但是，連接孔8 g，8 h之埋入構造，係並不被限定 本紙張尺度適用中國國家標準（CNS)A4規格（210 * 297公釐） --------------裝— <請*..闓讀背面之注意事項再(、本頁) 訂· .線 經濟部智慧財產局員工消費合作社印製 -56- 經濟部智慧財產局員工消費合作社印製 459 34 2 五、發明說明（δ4) 於表示在第3 6圖等之構造者而可施以各種變更，例如作 爲表示於第3 8圖之構造也可以。亦即，在第3 8圖中， 連接孔8g，8h以較薄導體膜9L1，11L1埋入。 此時之較薄導體膜11L1之構成材料也與上述之材料相 同，例如W，TiN，Ti ，Ta，WN，WSiN，When compared with Ti, Ta, WN, WSiN, but iSiN'TaN or Ta Si N, the wiring resistance can be reduced. Although not particularly limited, in the fifth embodiment, the thin conductive film 1 1 L 1 is made of, for example, T i N. In addition, the thicker conductor film 1 1 L 2 is the paper size that constitutes the third layer of wiring 1 1 L. Applicable Standards (CNS) A4 (210 X 297 mm) --------- ---- Install ----- ϋ it ϋ · IP nn I line (please 'read the notice on the back and then 1 {, this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs-54- 459342; V. Description of the invention (52) The main body components are made of low resistance materials such as Cu or Cu alloys; however, the structure of the third layer wiring 1 1 L is not limited to the structure shown in Figure 36 Alternatively, various modifications may be made, and the structures described in FIGS. 3 to 5 (a) may be used in the first embodiment. That is, there is a structure in which a cap conductor film is provided on the thicker conductor film 1 1 L 2 and a thinner conductor film 1 1 L 1; a cap conductor film is provided on the thicker 1 1 L 2 and the cap conductor The upper surface of the film and the upper surface of the interlayer insulating film 4 b have approximately the same structure: a structure in which wiring is constituted only by a thicker conductor film 1 1 L 2: provided only when a wiring is constituted by a thicker conductor film 1 1 L 2 Structure of cap conductor film, etc. The cap conductor film is made of, for example, W, T i N, T i, Ta. The third-layer wiring 1 1 L of the wiring groove 5 e is electrically connected to the second-layer wiring 9 L through the connection hole 8 h. The connection hole 8 h is formed from the bottom 5 e of the wiring groove to the upper surface of the second-layer wiring 9 L so that a part of the upper surface of the second-layer wiring 9 L is exposed, and, for example, W is provided in the hole. W 9 alloy, A 1 or A 1 alloy connection conductor portion 9 cc as shown in the following figure 39 (A) * The second layer wiring 9L is provided to extend in the Y direction, for example, and the second layer wiring 9 The pitch between L is designed in the X direction * direction with a predetermined pitch. In addition, the third layer wiring 1 1 L is provided to extend in the X direction perpendicular to the Y direction, for example, and the pitch between the third layer wiring 1 1 L is designed in the Y direction at a predetermined angle. 6 These second layers Forming method of wiring 9 L and layer 3 wiring 1 1 L This paper size applies _ National Standard (CNS) A4 specification (210 * 297 mm > III— ϋ ϋ n. I— 1_ * 1. n Please L (Please read the notes on the back, and then this page.) Order _ Line · Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs-55- 4 59 34 2 V. Description of the invention (53) the same. That is, * The method of forming the second-layer wiring 9 L is described as an example below. First, the wiring grooves 5 c, 5 d, and the connection hole 8 g are formed on the interlayer insulating film 4 b by a photolithography technique and a dry etching technique, respectively, and then a conductor film made of, for example, W is selected by a CVD method. And selectively grow in the connection hole 8 g to form a connection conductor portion 1 8 c. Then, a thin conductor film 9L1 made of, for example, T i N is covered by a sputtering method. On the film 9L1, a thick conductive film 9L2 made of, for example, Cu or a Cu alloy is formed by a sputtering method, a CVD method, or plating. After this process, heat treatment may be performed to sufficiently fill the Cu atoms into the wiring grooves 5c and 5d. Thereby, a conductive film is satisfactorily buried in the fine connection hole 8 g. Then, the semiconductor substrate 1 is subjected to CMP treatment, and the conductive film other than the wiring grooves 5 c and 5 d is removed to form a second buried structure. Layer wiring 9 L. The semiconductor substrate 1 may be heat-treated after the thick conductor film 9 L 2 is formed or after the CMP process. At this time, the heat treatment atmosphere is any one of an inert gas atmosphere, an oxidizing gas atmosphere, or a reducing gas atmosphere *, or a combination of two or more of them. The heat treatment promotes the growth of Cu particles in the thicker semiconductor substrate 9 L 2 and improves the EM resistance. At the same time, during the CMP treatment, it avoids damage or oxide film on the surface of the thinner conductor film 6 L 1 and makes it The surface becomes smooth, and the surface contamination of the insulating film 4 a is reduced, thereby improving the reliability of the wiring. However, the buried structure of the connection holes 8 g and 8 h is not limited. The paper size is applicable to the Chinese National Standard (CNS) A4 (210 * 297 mm) ------------ --Installation— < Please * .. 闿 Read the notes on the back and then (, this page) Order.. 34 2 V. Description of the Invention (δ4) Various changes may be made to the structure shown in Fig. 36 and the like, for example, the structure shown in Fig. 38 may be used. That is, in FIG. 38, the connection holes 8g, 8h are buried with the thinner conductor films 9L1, 11L1. The constituent material of the thinner conductor film 11L1 at this time is also the same as that described above, such as W, TiN, Ti, Ta, WN, WSiN,
Ti S iN，TaN或Ta S iN等所構成，較厚導體膜 9L2，11L2係例如Cu或Cu合金所構成。 又，連接孔8 g，8 h係其下部與側部之相對地較薄 導體膜，及被較薄導體膜所圍繞之相對地較厚導體膜所構 成也可以。此時，較薄導體膜係例如W，T i N等所構成 ，而較厚導體膜係例如W等所構成。 一方面，在層間絕緣膜4 c之上部[第3配線層〕， 與上述之配線用溝5 e —起，形成有與其相同之深度的連 接用溝5 g。連接用溝5 g係與配線用溝5 e同時地形成 0 該連接用溝5 g係如上所述，形成沿著配線之長度方 向較長之狀態。由此，成爲在連接用溝5 g內可良好地埋 入導體膜。亦即，在配線用溝5 e內埋入導體膜時，即使 在相同配線層中之連接用溝5 g同時地埋入導體膜，若將 連接用溝5 g之平面形狀與尺寸作爲下層之連接用導體部 1 9 c之上面之平面形狀與尺寸，由於連接用溝5 g係微 細，因此產生無法充分地埋入導體膜之情形β爲了避免此 等不方便，由此連接用溝5 g係其平面形狀沿著配線之長 度方向較長的形狀，可防止降低配線之實裝密度，並成爲 本紙張尺度適用中國國家標準（CNS)A4規格（2〗0 * 297公釐） -57- — — — 1IIII1I1I — * — — — — — — — illlllt <請t閱讀背面之注意事項再{·'-·本頁) 459 34 2 ' e； 五、發明說明（55) 可良好地連接該導體膜者•因此，成爲可良好地連接上下 之配線層間。 (請51.«讀背面之注意事項再c.i頁) 在連接用溝5g ，如第36圖，第39圖及第40圖 所示，設有連接用導體部2 1 c。第39 (A)圖係表示 第2層配線9 L至第4層配線1 3 L之一部的要部平面圖 ，第39 (B)圖係表示沿著第39 (A)圖之B—B線 的要部剖面圖，第39 (C)圖係表示沿著第39 (A) 圖之C — C線的要部剖面圖。又，第39 (B)圖係表示 在紙面同垂直方向切剖第3 6圖之右側的第2層配線9 L 至第4層配1 3 L部分時的剖面圖。 經濟部智慧財產局員工消費合作杜印¾The thick conductor films 9L2 and 11L2 are made of Ti S iN, TaN or Ta S iN, and are made of, for example, Cu or Cu alloy. The connection holes 8g and 8h may be formed by a relatively thin conductive film at the lower portion and the side portion, and a relatively thick conductive film surrounded by the thinner conductive film. At this time, a thinner conductor film is composed of, for example, W, T i N and the like, and a thicker conductor film is composed of, for example, W and the like. On the other hand, a connecting groove 5 g having the same depth as the above-mentioned wiring groove 5 e is formed on the upper part of the interlayer insulating film 4 c [the third wiring layer]. The connection groove 5 g is formed at the same time as the wiring groove 5 e. The connection groove 5 g is formed in a long state along the length of the wiring as described above. As a result, the conductor film can be satisfactorily buried in 5 g of the connection groove. That is, when the conductor film is buried in the wiring groove 5e, even if the connection groove 5g in the same wiring layer is simultaneously buried in the conductor film, if the planar shape and size of the connection groove 5g are used as the lower layer The planar shape and size of the connecting conductor portion 19 c are 5 g for the connection groove, which is fine, so that the conductor film cannot be fully embedded. Β To avoid these inconveniences, the connection groove 5 g It is a shape whose plane shape is longer along the length of the wiring, which can prevent the density of the wiring from being reduced, and becomes the paper standard applicable to the Chinese National Standard (CNS) A4 specification (2〗 0 * 297 mm). — — — 1IIII1I1I — * — — — — — — — illlllt < Please read the notes on the back and then {· '-· this page) 459 34 2' e; V. Description of the invention (55) Can be well connected to this Conductor film • As a result, it becomes a good connection between the upper and lower wiring layers. (Please read the 51. «Notes on the back page and page c.i) 5 g of connection grooves, as shown in Figs. 36, 39, and 40, are provided with connection conductors 2 1 c. Figure 39 (A) is a plan view of the main part of the second layer wiring 9 L to the fourth layer wiring 1 3 L, and Figure 39 (B) is a view along B-B along Figure 39 (A) A cross-sectional view of the main part of the line. FIG. 39 (C) is a cross-sectional view of the main part taken along line C-C of FIG. 39 (A). Fig. 39 (B) is a cross-sectional view when the second layer wiring 9L to the fourth layer are disposed with 1 3L portions on the right side of Fig. 36, cut on the same plane as the paper surface. Consumption Cooperation of Employees of Intellectual Property Bureau, Ministry of Economic Affairs
連接用導體部21C係成爲與第3層配線11L相同 之構造，下部與側部之相對地較薄導體膜2 1 C 1，及被 該較薄導體膜21C1所圍繞之相對地較厚導體膜 2 1 C2所構成。亦即，連接用導體部2 1 C係與第3層 配線1 1 L相同之配線所構成。較薄導體膜2 1 C 1係具 有提高連接用導體部2 1 C與層間絕緣膜4 C之密接性的 功能或抑制較厚導體膜2 1 C 2之構成原子之擴散的阻障 功能的材料—構成，例如W，TiN，Ti ，Ta’WN ，WSiN，Ti S iN，TaN或 TaSiN 等所構成 « 以W等構成較薄導體膜2 1 C 1時，與以T i N ’The connecting conductor portion 21C has the same structure as the third-layer wiring 11L. The lower portion and the side portion are relatively thinner conductor film 2 1 C 1 and the relatively thicker conductor film is surrounded by the thinner conductor film 21C1. 2 1 C2. That is, the connection conductor portion 2 1 C is composed of the same wiring as the third layer wiring 1 1 L. The thinner conductive film 2 1 C 1 is a material having a function of improving the adhesion between the connecting conductor portion 2 1 C and the interlayer insulating film 4 C or a barrier function of suppressing the diffusion of constituent atoms of the thicker conductive film 2 1 C 2 —Composition, such as W, TiN, Ti, Ta'WN, WSiN, Ti SiN, TaN, or TaSiN, etc. «When thin conductor film 2 1 C 1 is composed of W, and T i N '
Ti，Ta，WN，WSiN，TiSiN，Tal·^ T a S i N等所構成時相比較，成爲可降低配線電阻•雖 並未被特別限定，惟在本實施形態5中’較薄導體膜 -58 - 本紙張尺度適用中因因家標準（CNS)A4規格（210 X 297公釐） 4 59 34 2 A7 B7 _ 五、發明說明（δό ) 2 1 C 1係與第3層配線1 1 L之較薄導體膜1 1 L 1同 時地以相同材料所形成，例如以T i N所構成· 又，較厚導體膜2 1 C 2係構成連接用導體部2 1 C 之本體的構件，例如C u或C u合等之低電阻材料所構成 。但是，連接用導體部2 1 C之構造係並不被限定於表示 在第3 6圖至第4 1圖之構造者而可施以各種變更，作成 在上述實施形態1中使用第3圖至第5圖所說明之構造也 可以。 亦即，有在較厚導體膜2 1 C 2與較薄導體膜 2 1 C 1上設置帽蓋導體膜之構造，在較厚導體膜. 2 1 C 2上設置帽蓋導體膜，且將帽蓋導體膜之上面與層 間絕緣膜4 C之上面成爲大約一致的構造；僅以較厚導體 膜2 1 C 2構成配線的構件；僅在以較厚導體膜2 1 C 2 構成配線時在其上面設置帽蓋導體膜的構造等。帽蓋導體 膜係例如W，TiN，Ti ，Ta ，WN，WSiN， T i S i N，TaN或Ta S i N等所構成。如第39圖 及第4 0圖所示，連接用導體部2 1 C之平面形狀介經配 線之長度方向（X方向）構成比Y方向之配線寬度較大， 可將上下之連接用導體部1 9 C，2 0 C之對位餘童在X 方向較大。由此，即使欲增大第3層配線11L之Y方向 的配線節距P，也由於可將上下之連接用導體部1 9 C， 2 0 C之對位餘量在X方向成爲較大·，故可得到配線之高 密度化及高積體化《又，由於配線之長度方向的配線長度 係在配線寬度以上，成爲配線寬度之約南倍以下，而不用 本紙張尺度適用中國國家標準（CNS)A4規格<210 X 297公:g ) — — — — — — — —--i* 裝·！！11 訂 t請先閱讀背面之注意事項再一、本頁) 經濟部智慧財產局員工消費合作社印製 -59- 9 5 4.. 經濟部智慧財產局員工消費合作社印製 五、發明說明（57) 對接架，因此，可增大對位餘量，同時可增大埋入邊緣· 不必增大配線節距，即可成爲髙積體化· 又，如第4 1圖所示，將連接用導體部2 1 c之平面 形狀，形成配線之長度方向及對於其方向呈交叉方向（配 線寬度方向，亦即Y方向）較長之形狀也可以*但是*此 時，配線之長度方向（X方向）構成比Y方向之配線寬度 較大者。此時，可將上下之連接用導體部19C，20C 之對位餘量在配線之長度方向及寬度方向之雙方較大。所 以，由於可緩和埋入連接用導體部2 0 C之連接孔8 f形 成時的對位精度，成爲可容易地形成連接孔8 f。又，即 使連接孔8 f之平面位置稍偏離設計値，也成爲將連接用 導體部2 0 C與連接用導體部2 1 C可良好地連接之狀態 〇 又，如第4 2圖及第4 3圖所示，作爲在上述實施形 態1所說明之構造者也可以。亦即，連接用導體部1 9 C 之上部突出於連接用導體部2 1 C中之構造。此時，與在 上述實施形態1等所說明者相同方法所形成•亦即，在形 成於層間絕緣膜4 C之連接孔8 h (參照第3 6圖）內埋 入形成連接用導體部1 9 C之後，形成連接用溝5 g (參 照第36圖），然後，堆積導體膜，又施以CMP處理， 在該連接用溝5 g內形成連接用導體部2 1 C » 第4層配線1 3 L，係與上述實施形態1同樣地成爲 —般之配線構造。第4層配線1 3 L係經連接孔8 f內之 連接用導體部2 0 C與第3層配線1 1 L或連接用導體部 本紙張尺度通用中國固家標準（CNS)A4規格（2〗0 X 297公笼〉 -60- iliii* . il — t ί I 訂 * ! I I ! {請先«讀背面之沒意事項再{>:本頁) 4 5 9'34 2 A7 B7 五、發明說明（58 ) 2 1C電氣式地連接。連接用導體部2 0 C係例如以選擇 CVD法所形成之W或W合金等所構成。 亦即*在本實施形態5，係未直接接觸A 1系材料所 構成之第4層配線1 3L，及Cu系材料所構成之第3層 配線1 1 L或連接用導體部2 1 C，經由W系材料所構成 的連接用導體部2 0 C成爲電氣式地連接之構造。由此， 防止A 1與C 1之直接接觸，成爲可防止在該接觸部形成 高電阻係數之合金層的構造。 但是，作爲防止此等合金層所形成之構造，並不被限 定於表示於第3 6圖之構造而可施以各種變更，作成表示 於第4 4圖至第5 2圖之構造也可以。亦即，第4 4圖係 表示第4層配線1 3 L由較薄導體膜1 3 L 1與重疊於該 上層之較厚導體膜13L2所構成的構造。較薄導體膜 1 3 L 1係具有提高第4層配線1 3 L與層間絕緣膜4 d 之密接性昨功能或抑制較厚導體膜1 3 L 2之構成原子之 擴散的阻障功能的材料所構成，例如W，T i N，T i ， Ta，WN，WSiN，TiSiN，TaN 或 Ta S i N等所構成。又，較厚導體膜1 3L 2係例如 A 1或A .1.合金等所構成。 在第4 5圖之構造中，在從連接孔8 ί露出之第3層 配線1 1 L的露出面上*設有例如以選擇CVD法等所形 成之W或W合金等所構成的連接用導體部2 0 C 1 ·且在 連接孔8 f內的連接用導體部2 0 C 1上，設有例如A 1 或A 1合金等所構成的連接用導體部2 0 C 2。第3層配 本紙張尺度適用中國國家標準（CNS)A4規格（210 * 297公釐） ---------------裝.-- (請齩閱讀背面之注意事項再本頁) 訂· -線 經濟部智慧財產局員工消費合作社印製 -61 - 'b 4 9 34 2 μ _' _B7____ 五、發明說明（59 ) 線13L係經該連接用導體部20C (20C2， 20C1)與第3層配線11L電氣式地連接*又， 1 3 L與2 0 C係同時地形成也可以。亦即，在該構造成 爲A 1系材料所構成之第4層配線1 3 L與連接用導體部 20C2，及Cu系材料所構成之第3層配線1 1L的接 觸部設置W等所構成之連接用導體部2 0 C 1的構造•由 此，在該接觸部可防止形成高電阻係數之合金層。又，由 於將構成連接用導體部2 0 C之大部分的連接用導體部 2 0 C 2以低電阻之A 1系材料所構成，因此，成爲可降 低以W等構成所有該連接用導體部之第3 6圖之構造相比 較的連接用導體部2 0 C之電阻。 在第4 6圖之構造中，在第2層配線1 1 L之上部設 置帽蓋導體膜1 1L3。帽蓋導體膜1 1L3係例如W， TiN，Ti ，Ta 'WN，WSiN，TiSiN， TaN或Ta S i N等所構成。又，較厚導體膜1 3L2 係例如A 1或A 1合金等所構成。在連接孔8 f內埋入有 與第4層配線1 3L —體地形成之A 1或A 1合金等所構 成的導體膜•此時，也由於A 1系材料所構成之第4層配 線1 3L，及Cu等材料所構成之第3層配線1 1L的接 觸部設置W等所構成的較薄導體膜1 1 L 3，因此，可防 止在該接觸部形成高電阻係數之合金層，且由於連接孔 8 f內係以低電阻之A 1系材料埋入，因此，與第3 6圖 之情形相比較成爲可降低層間連接部之電阻。 在第4 7圖之構造中，連接孔8 f以較薄導體膜 本紙張尺度適用中國國家標準（CNS)A4規格（210 * 297公S )~ -62: -------------裝 * n n n n n k ϋ ϋ n i I 線 {請先Μ'讀背面之注意事項再C..S本頁) 經濟部智慧財產局員工消費合作杜印製 A7 A7 4 59 34 2 B7____ 五、發明說明（60) 1 3 L 1埋入•此時之較薄導體膜1 3 L 1的構成材料係 與上述之材料相同，例如W，T i N，T i ，Ta，WN ，WS i’ ，Ti S iN，TaN或TaS iN 等所構成 。較厚導體膜1 3L2係例如A 1或A 1合金所構成。 第4 8圖之構造，係在第4 7圖之構造中，有較厚導 體膜13L2a，13L2b由下層依順序重叠在較薄導 體膜1 3 L 1上，下層側之較厚導體膜1 3 L 2 a係例如 W或W合金所構成，例如以CVD法或濺射法等所形成。 上層側之較厚導體膜1 3 L 2 b係例如A 1或A 1合金所 構成，例如以C V D法或濺射法所形成。 在第4 9圖之構造，將連接A 1系所構成之第4層配 線1 3 L，及C u系所構成之第3層配線1 1 L的連接用 導體部14C，以濺射法所形成的W，TiN等阻障（較 薄導體膜）1 4 C 1，及以CVD法所形成的W等之插頭 (較厚導體膜）1 4 C 2所構成。由該構造，可減低接觸 電阻。 該構造係介經濺射法堆積阻障金屬之後，以C VD法 將W埋入堆積於連接孔8 f，然後，介經CMP或反複蝕 刻，可將阻障金屬14C1，插頭14C2僅形成在連接 孔8 f內。 又，連接用導體部1 4 C僅以CVD法埋入T i N之 插頭1 4 C 2所構成也可以。 第5 0圖之構造，係在第4 9圖之構造中，將第4層 配線1 3L，BP，以A 1系所構成之較厚導體膜 本紙張尺度適用中國S家標準（CNS>A4規格（210 * 297公芨） I!--------*裝--------訂-----！1·線 {請先«讀背面之泫意事項再产、本頁> 經濟部智慧財產局員工消費合作社印製 -63- A7 A7 459342 B7_ 五、發明說明（61 ) 1 3 L 2，及成膜T i N或W等之髙融點金屬或金屬化合 物之較薄導體膜13 L 1所構成。由此*可更提髙可靠性 〇 第5 1圖之構造，係在第4 9圖之構造中，在連接孔 8 f內堆積阻障金屬及W之後，未施以插頭加工，而堆積 A 1系材料，以w，T iN等的阻障金屬（較薄導體膜） 13L1，及W所構成的較厚導體膜13L2a ，及A1 系所構成的較厚導體膜1 3 L 2 b構成第4層配線1 3 L 。如此，未施加插頭加工地留下，成爲與A 1合金之叠層 配線，可提高依廢止插頭硏磨過程所產生之簡化與依疊層 構造所產生之可靠性。 第5 2圖之構造，係在第5 1圖之構造中。未設置阻 障金屬（較薄導體膜）13L1，以CVD法形成之 TiN所構成的較厚導體膜13L2a，及A1系所構成 的較厚導體膜1 3 L 2 b構成第4層配線1 3 L。因以 CVD法所形成之T i N膜1 3 L 2 b係與層間絕緣膜之 黏接性比以膜優異，因此，不必設置阻障金屬1 3 L 1， 而可減低製程•與第5 1圖之構造同樣地，未施加插頭加 工地留下|成爲與A 1合金之叠層配線，可提高依廢止插 頭硏磨過程所產生之簡化與依疊層構造所產生之可靠性。 將表示於連接用導體部1 4 C之構造適用於連接用導 體部 IOC，12C，18C，19C，20C 也可以。 第5 3圖係表示將表示於第4 9圖之連接用導體部1 4 C 之構造適用於表示在第3 9圖，第4 0圖之連接用導體部 — It — — — — ! — —！ . I I I I — I (ifr先《讀背面之注意事項再4;·本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度通用中國國家標準（CNS)A4規格（210 X 297公釐） -64- 5 9 34 2 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（泣） 19C，20C的構造。較薄導體膜19C1，20C1 係與阻障金屬1 4 C同稱地構成，而較厚導體膜1 9 C 2 ，20C2係與插頭14C2同稱地構成。 第5 4圇係表示以雙達馬新形成表示於第5 3圖之第 3層配線1 1 L，2 1 C的構造。該構造係形成連接孔 5g，8h之後，藉濺射法堆積阻障金屬，然後，將Cu 例如藉濺射法較薄地形成後，再使用電解電鍍法埋入地形 成於連接孔5g，8h »然後藉CMP法之形成以阻障金 屬所構成之較薄導體膜2 1 C 1 ，及C U所構成之較厚導 體膜21C2所構成的第3層配線11L，21.C。因將 2 1 C至少沿著配線之長度方向比8 h在平面上較長地形 成，可降低將5 g，8h同時地以Cu埋入時的實效之縱 橫比，成爲可容易實施C u埋入。 第55 (a)圖及第55 (b)圖係表示將表示於第 3 9圖之連接用導體部2 1 C偏向長度方向（X方向）的 變形例。第55 (a)圖係表示第2層配線9L至第4層 配線13L之一部的要部平面圖· 55 (b)圖係表示沿 著第55 (a)圖之C 一 C線的要部剖面圖。由此，即使 在相鄰接之第2層配線9 L的節距P 1之位置形成第2層 配線9 L，也可設計連接用導體部2 1 C。 第5 6圖係表示將表示於第3 9圖之連接用導體部 2 1 C，僅連接孔8 f所配置之部位向垂直於長度方向（ X方向）之方法，在不變更節距P地變粗的變形例。將表 示於第5 6圖之連接用導體部2 1 C適用在表示於第5 5 价先Mtt背面之注意事項再i 裝--- 、本頁) 訂. -線· 本紙張尺度適用中®囷家棵準（CNS)A4規格（210 X 297公釐） -65- 經濟部智慧財產局員工消費合作社印製 a b 9 34 2 a? B7 五、發明說明（63) (a)圖及第55 (b)圖的連接用導體部21C· (實施形態6 ) 第5 7圖係表示本發明之其他實施形態之半導體積體 電路裝置的要部剖面圖。第5 8圖R第5 9圖係表示半導 體積體電路裝置之製程中的要部剖面圖》 首先’使用第5 7圖說明本實施形態6的半導體積體 電路裝置之構造。 第1層配線6 L係以如W之C 11系以外之導體材料所 構成，而第2層配線9L，第3層配線1 1L係與實施形 態5同樣地以C u系之導體材料所構成。 第1層配線6L係使用於例如將以MI SFET所構 成之邏輯電路由予以結線的配線，或結線邏輯電路間的配 線，與第2層配線9 L與第3層配線1 1 L相比較，比較 短之配線長度所構成。 第2層配線9 L與第3層配線1 1 L係使用於例如結 線邏輯電路間之配線，構成其中一方向X方向延伸，而另 —方向Υ方向延伸的構造。 介經以W膜構成第1層配線6 L，可用微細圖案形成 第1層配線6 L，可提高高積體化，同時可提高電子遷移 耐性。 又，由於在第1層配線6 L未使用C u系之導電材料 ，因此，可減低C u對於半導體基板1之擴散’並可提髙 可靠性。 本紙張尺度適用+國國家標準（CNS)A4規格（210 X 297公釐） · 66 — — I — III! — _ ·1111111 »11 — — — — —— (請先·閲«-背面之注意事項再一 本買) 經濟部智慧財產局貝工消費合作社印製 五、發明說明（64) 由於以C U系之導電材料構成第2層配線9 L與第3 層配線1 1 L，因此可減低配線之電阻係數，可成爲高速 動作者。 連接用導體部7C，18C，19C，20C， 2 1 C係分別與表示於第4 9圖之連接用導體部1 4 C同 樣地，以濺射法形成之W所構成的阻障金屬（較薄導體膜 )1 4 C 1，及以W所構成之插頭（較厚導體膜） 1 4 C 2所構成。 第4層配線1 3L，與第5層配線102係例如以 Α1系之導電材料所構成。 第4層配線1 3 L係以W，T i Ν等之阻障金屬（較 薄導體膜）13L1 ，13L3，隔著A1或A1合金所 構成之較厚導體膜1 3 L 2之疊層構造所構成。 介經將以A 1系導電材料所構成的第4層配線1 3 L ，及以C u系導電材料所構成的第3層配線1 1 L，經由 W所構成的連接用導體部2 0 C施以電氣式地連接，成爲 可防止介經A 1與C u有高電阻係數之合金層形成在接觸 部。又，第4層配線1 3L係以表示於第44圖至第52 圖之配線構.造所構成也可以。 又，第5層配線1 0 2係未經由連接用導體部電氣式 地連接於第4層配線1 3 L，惟並不被限定於此者《與第 4層配線1 3 L與第3層1 1 L之間之連接相同地，經由 與連接用導體部2 0 C相同之構造的連接用導體部，電氣 式地連接第5層配線1 0 2與第4層配線1 3 L- - ----------- 裝！ —訂------ -- _線 <請先M-讀背面之注意事項再一.V.本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X297公复） -67- A7 B7 4 5 9 34 2 五、發明說明（65) 又，將第5層配線1 〇 2與第4屠配線1 3 L同樣地 以疊層構造所構成也可以。 在第5層配線1 0 2，形成有例如矽氧化膜所構成的 絕緣膜1 0 4，而在形成於絕緣膜1 〇 4之開口部形.成有 下部電極1 0 6。第5層配線1 0 7係經由下部電極 1 0 6電氣式地連接於軟焊料***所構成的***電極 1 ◦ 8，下部電極1 0 6係例如以阻障金屬所構成。 以下，使用第5 8圖及第5 9圖簡單地說明第1層配 線6 L及連接用導體部7 C之形成方法》 與第8圖同樣地在層間絕緣膜4 a形成連接$8 a之 後，如第5 8圖所示，藉濺射法堆積W所構成之較薄導體 膜7C1，然後以CVD法將W所構成之較厚導體膜 7 C 2埋入地堆積連接孔8 a。 然後，如第5 9圖所示，藉例如CMP法硏磨該堆稹 膜，並在連接孔8 a內埋入W所構成之較薄導體膜7 C 1 ，及W所構成之較厚導體膜7 C 2。 然後，以例如P VD法堆積W膜之後，藉蝕刻使之圖 案化後形成第1層配線6L。在此以依PVD法的W膜形 成6L，惟在以PVD法之W膜上，形成以依CVD法的 W膜之疊層構造等作各種變更。 然後，以例如CVD法堆積矽氧化膜之後，藉CMP 法硏磨矽氧化膜，形成表面被平坦化之層間絕緣膜4 b。 以下之過程|係與上述之實施形態1至5同樣地形成 本紙張尺度適用中國因家標準（CNS)A4規格（210 * 297公« ) — In —-------- 裝 i I 沐先Mtt背面之注意事項再i 本頁) 訂.· 線· 經濟部智慧財產局員工消费合作杜印製 -68- αο9 34 2 α7 Β7 五、發明說明（66 ) 本實施形態6之半導體積體電路裝置係使用***電極 108，惟如第6C圖所示*在以第5層配線1〇2所構 成之搭接襯墊電氣式地連接搭接線端110也可以。 又，本實施形態6之半導體積體電路裝置，係以5層 之配線層所構成，惟以7層之配線層所構成•以C u系之 導電材料構成第2層至第5層配線，而以A 1系之導電材 料構成第6層配線至第7層配線也可以。此時，第2層配 線與第4層配線構成向相向方向延伸而第3層配線與第5 層配線係構成向相同方向延伸，使用作爲連接邏輯電路間 之配線。又|本實施形態6中，在位於連接用導體部 1 9 C與連接用導體部2 0 C所連接之部分的第3層配線 層中，至少設置至少沿著配線之長度方向比連接用導體部 1 9 C，2 0 C平面地較長地形成的連接用導體部2 1 C ，惟將構成連接用導體部2 1 C之構造設於第2，3，4 ，5層也可以。 在第6 1圖，表示於實施形態1至6之半導體積體電 路裝置的平面佈置。 重複地配置閘極陣列2 0 0，而在各閘極陣列2 0 C ，裝配配置有例如MI SFET，雙載子，電阻等之積體 電路元件。 介經變更第1層配線至第5層配線之配線圖案，構成 各種邏輯電路，以形成具有所定邏輯的半導體積體電路裝 置。 在第6 2圖，表示具有閘極陣列2 0 0與作爲記憶體 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公t ) '69- --------------裝--- (請先閲讀背面之注意事項再本頁) δ * --線_ 經濟部智慧財產局員工消費合作社印製 A7 B7 34 2 五、發明說明（67 ) 之RAM4 0 0的半導體積體電路裝置。 又，如第63圖所示，隨著LSI之性能自由地配置 具有各種功能的單元400 * 500，600，700。 如此，依照本實施形態5，6，除了在上述實施形態 1所得到之（8)至（1 0)之效果外，成爲可得到以下 之效果。 (1 )介經在微細連接孔8 a至8 f內使用CVD法 等塡充導體膜之後，在此連接孔8 a至8 f其平面尺寸較 大之配線用溝5 a至5 ί內塡充導體膜而形成埋入構造之 第1層配線6L，第2層配線9L及第3層配線1 1L， 成爲在配線用溝5 a至5 ί及比其微細之連接孔8 a至 8 f之雙方良好地埋入導體膜·>又，在微細連接孔8 a至 8 f與位於其上方之配線用溝5 a至5 ί內，同時地使用 CVD法或電鍍法等塡充導體膜時，介經將配線用溝5 a 至5 f成爲此連接孔8 a至8 f增大平面尺寸，成爲可良 好地埋入導體膜。 (2) 介經上述（1)，成爲可提高配線層間之連接 上的可靠性。因此，成爲可提高半導體積體電路裝置之良 品率及可靠性· (3) 介經上述（1) *成爲可推動埋入配線之微細 化。因此，成爲可推動半導體積體電路裝置之小型化或高 積體化。 (4) 介經上述（1)，不必採用難技術，在配線用 溝5 a至5 f及連接孔8 a至8 f可良好地埋入導體膜。 請 先. 閲 讀 背 面 之 注 意 事 項 •、‘ 裝 訂 經濟部智慧財產局員工消费合作社印製 本紙張尺度適用中國囷家標準（CNS)A4規格（210 * 297公爱） -70- A7 B7 A b 9 34 2 五、發明說明（65) (5) 介經上述（1)，成爲作爲埋入配線材料即使 使用C u或C u合金等時也可良好地實施其埋入狀態。 (6) 與半導體基板1直接接觸之第1層配線6L係 以W系之導體材料所構成，一面良好地保持導體膜對於連 接孔8 a內之埋入狀態，一面成爲可避免起因於C u原子 對於半導體基板1側之擴散現象的元件不良·又，介經W 系之導體材料構成第1層配線6 L，成爲可減低配線電阻 與提高E Μ耐性。 以上，依照實施形態具體地說明藉由本發明者所施行 之發明，惟本發明係並不被限定於上述實施形態者，在未 超出其要旨之範圍內當然可施以各種變更。 例如在半導體基板，與連接用導體部之接觸部•也可 以設置例如鎢矽化物或鈦矽化物等之矽化物層。 又，配線層係並不被限定於4層至7層者而可施以各 種變更，3層或4層以上也可以。 藉由本案所揭示之發明中，簡單地說明籍由代表性者 所得到之效果，如下所述。 (1 )依照本發明的半導體積體電路裝置之製法，介 經以導體膜充分地埋入連接孔之後，形成配線用溝，並以 導體膜埋Λ該溝，成爲在配線用溝及比該溝更微細之連接 孔的雙方良好地埋入導體膜* (2 )依照本發明的半導體積體電路裝置之製法，在 相同配線層具有不同配線用溝等時，介經選擇以微細之配 線用溝等與比其更大之配線用溝等容易埋入之方法來埋入 --------------裝--- (請先Μ讀背面之注意事項再1.·.本頁) 訂‘ ，線 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中囷國家標準（CNS)A4規格（210 X 297公釐） -71 - 459342 A7 B7_ 五、發明說明（69 ) 導體膜，成爲在雙方之配線用溝內可良好地埋入導體膜β (3) 介經上述（1)或（2) ’成爲可提高配線層 間之連接上的可靠性。因此，成爲可提高半導體積體電路 裝置之良品率及可靠性· (4) 介經上述（1)或（2) ’成爲可推動埋入配 線之微細化。因此，成爲可推動半導體積體電路裝置之小 型化或高稹體化。 (5) 介經上述（1)或（2)，不必採用難技術* 在配線用溝及連接孔良好地埋入導體膜。 (6) 介經上述（1)或（2)，成爲作爲埋入配線 材料即使使用C u或C u合金等時也可良好地實施其埋入 狀態。 (7 )依照本發明的半導體積體電路裝置之製法，介 經在包含配線用溝之絕緣膜上平坦化以濺射法等所形成之 C u系導體材料俾除去配線用溝等以外之領域的C u系導 體材料，形成埋入配線後施以熱處理，由於促進C u之粒 子成長而提高ΕΜ耐性 > 同時在平坦化處理時可避免產生 在C u系導體膜之表面的損傷或氧化膜等將其表面成爲平 滑，或可除去減低CMP時所露出的絕緣膜之表面污染， 因此，可提高C U系導體材料所構成的埋入配線之可靠性 〇 (8 )依照本發明之半導體積體電路裝置，再於在半 導體基板上層之配線層具有埋入配線的半導體積體電路裝 置，上述埋入配線與半導體基板接觸部分的配線材料，係 1— ·1 tt n I 1 n ( t It ft— a n I— · ----線 <i*-先IB·讀背面之注意事項再i :本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公S〉 -72- 45 9 34 2 A7 B7 五、發明說明（7〇 ) 以W，W合金，A 1或A 1合金所構成，介經將其上層之 配線層的埋入配線以C u或C u合金所構成，一面良好地 保持導體膜對於連接孔之埋入狀態，一面防止C u原子對 於半導體基板側之擴散俾避免起因於其擴散現象之元件不 良，且可減低半導體積體電路裝置之整體性之配線電阻而 成爲可提高傳播速度。 (9 )依照本發明之半導體積體電路裝置，屬於在半 導體基板上層之配線層具有埋入配線的半導體積體電路裝 置，上述配線層中之最上配線層的配線材料以A 1或A 1 合金所構成，其下層配線層的埋入配線以C u或C u合金 所構成，且仍然沿用以往之搭接線端技術或***電極之形 成技術等之裝配技術。因此，成爲可將具有C u系導體材 料之埋入配線的半導體積體電路裝置容易地導入在裝配過 程。 (10 )依照本發明之半導體積體電路裝置，靥於在 半導體基板上層之配線層具有埋入配線的半導體積體電路 裝置，在連接A 1或A 1合金所構成之配線，及C U或 C 11合金所構成的配線時，介經在此等接合部作爲咀障導 體膜介裝插頭，由於在直接接觸A 1系導體材料與C u系 導體材料時，可防止在其接皤部形成有高電阻係數之合金 層，因此成爲降低配線層間之連接電阻。 (11)介經上述（8)至（10)，成爲可將Cu 系導體材料所構成的埋入配線，不會產生不方便下，裝進 半導體積體電路裝置之整體構造。 本紙張尺度適用中园國家標準（CNS)A4規格（210* 297公S ) --------------裝--- <ΐί·先·閲讀背面之注意事項再i .本頁) 訂： •線. .經濟部智慧財產局員工消費合作杜印製 -73- a d 34 2 A7 __；_ B7___ 五、發明說明（） (1 2 )又，依照本發明之半導體積體電路裝置，介 經上述中繼用之連接用導體部，係至少其所定埋入配線之 配線延伸方向的長度，形成比上述連接孔之上述配線延伸 方向的長度較長，由於可將形成中繼用之連接用導體部的 連接用溝形成較大，因此，在連接用溝的可良好地埋入導 體膜。故可提高上下之配線層間之電氣式地連接上的可靠 性，成爲可提高半導體積體電路裝置之良品率及可靠性* (圖式之簡單說明） 第1圖係表示本發明之一實施形態之半導體積體電路 裝置的要部剖面圖。 第2圖係表示第1圖之半導體積體電路裝置之第1層 配線的要部剖面圖。 第3圖係表示第2圖之配線構造之變形例的剖面圖" 第4圖係表示第2圖之配線構造之變形例的剖面圖β 第5圖係表示第2圖之配線構造之變形例的剖面圖。 第6圖係表示第1圖之半導體積體電路裝置之第2層 配線的要部剖面圖。 第7圖係表示第1圖的半導體積體電路裝置之配線層 間連接之變形例之半導體積體電路裝置的要部剖面®I ° 第8圖係表示第1圖之半導體積體電路裝置之製程中 的要部剖面圖。 第9圖係表示第1圖之半導體積體電路裝置之製程中 的要部剖面圖。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公餐） — lit — — —— — — — — — · 1 I I ! I I I ill— — — — — I (請先閱讀背面之泫意事項再一乂本頁) 經濟部智慧財產局員工消費合作社印製 -74- A7 4 5 9 34 2 B7____ 五、發明說明（72 ) 第1 0圖係表示第1圖之半導體積體電路裝置之製程 中的要部剖面圖。 (請先閱讀背面之注意事項再i λ本頁) 第1 1圖係表示第1圖之半導體積體電路裝置之製程 中的要部剖面圖。 第1 2圖係表示第1圖之半導體積體電路裝置之製程 中的要部剖面圖。 第1 3圖係表示第1圖之半導體積體電路裝置之製程 中之要部的局剖切剖斜視圖。 第14圖係表示第1圖之半導體積體電路裝置之製程 中之要部的局剖切剖斜視圖。 第15圖係表示第1圖之半導體積體電路裝置之製程 中之要部的局剖切剖斜視圖。 第1 6圖係表示第1圖之半導體積體電路裝置之製程 中之要部的局剖切剖斜視圖。 第1 7圖係表示第1圖之半導體積體電路裝置之製程 中之要部的局剖切剖斜視圖。 第1 8圖係表示第1圖之半導體積體電路裝置之製程 中之要部的局剖切剖斜視圖。 經濟部智慧財產局員工消費合作社印製 第1 9圖係表示本發明之其他實施形態之半導體積體 電路裝置之製程中的要部剖面圖。 第2 0圖係表示繼續於第1 9圖之半導體積體電路裝 置之製程中的要部剖面圖》 第2 1圖係表示繼續於第1 9圖之半導體積體電路裝 置之製程中的要部剖面圖° 本紙張尺度適用中國國家標準（CNS)A4規格（210x297公釐） -75- Λ r 0342 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（73) 第2 2圖係表示繼績於第1 9圖之半導體積體電路裝 置之製程中的要部剖面圖。 第2 3圇係表示繼續於第1 9圖之半導體積體電路裝 置之製程中的要部剖面圖。 第2 4圖係表示本發明之其他實施形態之半導體積體 電路裝置的要部剖面圖》 * 第2 5圖係表示本發明之其他實施形態之半導體稹體 電路裝置之製程中的要部剖面圖。 第2 6圖係表示繼續於第2 5圖之半導體積體電路裝 置之製程中的要部剖面圖。 第2 7圖係表示繼續於第2 5圖之半導體積體電路裝 置之製程中的要部剖面圖。 第2 8圖係表示繼續於第2 5圖之半導體積體電路裝 置之製程中的要部剖面圖。 第2 9圖係表示本發明之其他實施形態之半導體積體 電路裝置之製程中的要部剖面圖。 第3 0圖係表示繼續於第2 9圖之半導體積體電路裝 置之製程中的要部剖面圖。 第3 1圖係表示繼續於第2 9圖之半導體積體電路裝 置之製程中的要部剖面圖。 第3 2圖係表示繼續於第2 9圖之半導體稹體電路裝 置之製程中的要部剖面圖。 第3 3圖係表示本發明之其他實施形態之半導體稹體 電路裝置的要部剖面圖》 __— — — — — —— — — — —— - I I I (請先Μ讀背面之ii意事項再c.i頁)： 訂- -線- 本紙張尺度適用中國國家標準（CNS)A4規格（210 * 297公* ) -76- 459342 A7 B7 五、發明說明（74 ) 第3 4圖係表示本發明之其他 電路裝置的要部剖面圖。 第3 5圖係表示本發明之其他 電路裝置的要部剖面圖。 第3 6圖係表示本發明之其他 電路裝置的要部剖面圖。 第3 7圖係表示第3 6圖之半 部放大剖面圖。 第3 8圖係表示於第3 7圖之 要部之變形例的要部放大剖面圖。 第3 9 ( A )圖係表示於第3 裝置之要部之變形例的要部平面圖< 第39 (B) * (C)圖係表 半導體積體電路裝置之要部之變形 0 第4 0圖係模式地表示第3 置之要部的說明圖》 實施形態之半導體積體 實施形態之半導體積體 實施形態之半導體積體 導體積體電路裝置的要 半導體積體電路裝置之 7圖之半導體積體電路 示於第39圖（Α)之 例的要部放放大剖面圖 圖之半導體積體電路裝 先 閲 讀 背 面 意 事 項 再 頁 裝 訂 ▲ 經濟部智慧財產局員工消f合作社印製 第 圖 明 說 說 的 例 形 變 之 圖 ο 4 第 示 表 地 式 模 係 ,圖 圖 明 說 說 的 例 形 變 之 圖 ο 4 第 示 表 地 式 模 係 圖 2 4 第 圖 明 說 說 的 例 形 變 之 圖 ο 4 第 示 表 地 式 模 係 圖 3 4 第 要 之 置 裝 路 -S Ιξ!ΟΓ 體 _積 證 導 半 之 圖 6 3 第 示 表 係 圖 4 4 第 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公芨> -77- 4d 9 34 2 A7 B7____ 五、發明說明（75 ) 部之變形例的要部放大剖面圖。 第4 5圇係表示第3 6圖之半導體積體電路裝置之要 部之變形例的要部放大剖面圖。 第4 6圖係表示第3 6圖之半導體稹體電路裝置之要 部之變形例的要部放大剖面圖》 第4 7圖係表示第3 6圖之半導體積體電路裝置之要 部之變形例的要部放大剖面圖。 第4 8圖係表示第3 6圖之半導體積體電路裝置之要 部之變形例的要部放大剖面圖》 第4 9圖係表示第3 6圖之半導體積體電路裝置之要 部之變形例的要部放大剖面圖。 第5 0圖係表示第3 6圖之半導體積體電路裝置之要 部之變彤例的要部放大剖面圖。 第5 1圖係表示第3 6圖之半導體積體電路裝置之要 部之變形例的要部放大剖面圖。 第5 2圖係表示第3 6圖之半導體積體電路裝置之要 部之變形例的要部放大剖面圖。 第5 3圖係表示第3 9 ( C )圖之半導體積體電路裝 置之變形例的剖面圖。 第5 4圖係表示第3 9 ( C)圖之半導體積體電路裝 置之變形例的剖面圖。 第55 (a)圖係表示第39 (Α)圖之半導體積體 電路裝置之變形例的平面圖。 第55 (b)圖表示於第55 (a)圖之半導體積體 — til — — — — — —•裝 *-------訂！|_線I、 (介先閱讀背面之注意事項再本頁) 一 經濟部智慧財產局員工消費合作社印製 本纸張尺度適用中园國家標準（CNS)A4規格（210 X 297公发） -78- A7 453 34 2 _B7____ 五、發明說明（76 ) 電路裝置的要部放大剖面圖。 第56圖係表示第39 (A)圖之半導體積體電路裝 置之實施例的平剖面圖。 第5 7圖係表示本發明之其他實施形態之半導體積體 電路裝置的要部剖面圖。 第5 8圖係表示第5 7圖之半導體稹體電路裝置之製 程中的要部剖面圖。 第5 9圖係表示第5 7圖之半導體稹體電路裝置之製 程中的要部剖面圖。 .， 第6 0圖係表示第5 7圖之半導體積體電路裝置之變 形例的要部剖面圖。 第6 1圖係表示本發明之實施形態之半導體積體電路 裝置的平面佈置圖。 第6 2圖係表示第6 1圖之半導體積體電路裝置之變 形例的平面佈置圖。 第6 3圖係表示第6 1圖之半導體積體電路裝置之變 形例的平面佈置圖。 、1 (記號之說明） 1 半導體基板，2 元件分離部，2a 分離用溝 -2 b 分離用絕緣膜，4a〜4d 層間絕緣膜， 5a〜5f 配線用溝，6L 第1層配線， 7 C 連接用導體部，8a〜8h 連接孔， 9 L 第2層配線，10C 連接用導體部， 1_1!!!1_ ^^--------訂--I I I I--- <tfr先閱讀背面之注意事項再产·-.本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210x 297公釐） -79- 4 5 9 3 4 2 a? _____B7__ 五、發明說明（77 ) 1 1 L 第3層配線，12C 連接用導體部， 1 3 L 第4層配線，14C 連接用導體部， 15 表面保護膜，15a，15b 保護膜， 17a〜17c 光阻圖案* 19c〜21c 連接用導體部，102 第5層配線， 104 絕緣膜，106 下部電極，108 ***電極 *110 搭接線端，200 閘極陣列|Compared with the composition of Ti, Ta, WN, WSiN, TiSiN, Tal · ^ T a S i N, the wiring resistance can be reduced. • Although not particularly limited, in the fifth embodiment, the thinner conductor film -58-Applicable to China Standard (CNS) A4 (210 X 297 mm) 4 59 34 2 A7 B7 _ V. Description of the invention (δό) 2 1 C 1 series and layer 3 wiring 1 1 The thinner conductor film 1 of L is formed of the same material at the same time, for example, T i N. The thicker conductor film 2 1 C 2 is a member constituting the body of the conductor portion 2 1 C for connection. For example, it is made of low resistance materials such as Cu or Cu. However, the structure of the connecting conductor portion 2 1 C is not limited to those shown in FIGS. 36 to 41 and various changes can be made to use the third embodiment to the first embodiment. The structure illustrated in FIG. 5 is also possible. That is, there is a structure in which a cap conductor film is provided on a thicker conductor film 2 1 C 2 and a thinner conductor film 2 1 C 1, and a cap conductor film is provided on a thicker conductor film. 2 1 C 2 The upper surface of the cap conductor film and the upper surface of the interlayer insulating film 4 C have approximately the same structure; a member that constitutes wiring only with a thicker conductor film 2 1 C 2; only when the wiring is constituted with a thicker conductor film 2 1 C 2 A structure such as a cap conductor film is provided thereon. The cap conductor film is composed of, for example, W, TiN, Ti, Ta, WN, WSiN, TiSiN, TaN, or TaSiN. As shown in Fig. 39 and Fig. 40, the planar shape of the connecting conductor portion 2 1 C through the length direction (X direction) of the wiring is larger than the wiring width in the Y direction, and the upper and lower connecting conductor portions can be formed. The opposite Yu Tong at 1 9 C and 20 C is larger in the X direction. Therefore, even if it is desired to increase the wiring pitch P in the Y direction of the third-layer wiring 11L, the alignment margin of the upper and lower connecting conductor portions 19 C and 20 C can be made larger in the X direction. Therefore, high density and high integration of wiring can be obtained. Also, because the wiring length in the length direction of the wiring is above the width of the wiring, and becomes about south of the width of the wiring, the Chinese national standard does not apply to this paper scale ( CNS) A4 specifications < 210 X 297 Male: g) — — — — — — — —-- i * Install ·! !! 11 Order t, please read the notes on the back first, and then this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs-59- 9 5 4. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ) The docking frame can increase the positioning margin and the embedded edge at the same time. It can be integrated into the product without increasing the wiring pitch. Also, as shown in Figure 41, The planar shape of the conductor portion 2 1 c can be formed in a length direction of the wiring and a shape that crosses the direction (the width direction of the wiring, that is, the Y direction) is longer. However, at this time, the length direction of the wiring (the X direction ) The one with a larger wiring width than the Y direction. In this case, the alignment margins of the upper and lower connection conductor portions 19C and 20C can be made larger in both the length direction and the width direction of the wiring. Therefore, the alignment accuracy at the time of forming the connection hole 8f embedded in the connection conductor portion 20C can be eased, so that the connection hole 8f can be easily formed. In addition, even if the plane position of the connection hole 8 f deviates slightly from the design, it is in a state where the connection conductor portion 2 0 C and the connection conductor portion 2 1 C can be well connected. Also, as shown in FIGS. 4 2 and 4 As shown in FIG. 3, it may be a structure described in the first embodiment. That is, a structure in which the upper portion of the connection conductor portion 19 C protrudes from the connection conductor portion 2 1 C. At this time, it is formed by the same method as that described in the first embodiment and the like, that is, the connection conductor portion 1 is embedded in the connection hole 8 h (see FIG. 36) formed in the interlayer insulating film 4 C to form the connection conductor portion 1. After 9 C, 5 g of connection grooves are formed (refer to FIG. 36), and then a conductor film is deposited and CMP treatment is performed to form a connection conductor portion 2 1 C in the 5 g of connection grooves. Layer 4 wiring 1 3 L has a general wiring structure similar to that of the first embodiment. The 4th layer wiring 1 3 L is the connecting conductor part 2 0 C through the connection hole 8 f and the 3rd layer wiring 1 1 L or the connecting conductor part. This paper is in accordance with the Chinese standard (CNS) A4 specification (2 〖0 X 297 male cage〉 -60- iliii *. Il — t ί Order *! II! {Please «read the unintentional matters on the back {>: this page) 4 5 9'34 2 A7 B7 5 Description of the invention (58) 2 1C is electrically connected. The connection conductor portion 20 C is made of, for example, W or W alloy formed by a selective CVD method. That is, * in the fifth embodiment, the fourth layer wiring 1 3L made of A 1 series material and the third layer wiring 1 1 L made of Cu material or connection conductor 2 1 C are not directly contacted. The connection conductor portion 2 C made of a W-based material has a structure that is electrically connected. This prevents the direct contact between A 1 and C 1, and prevents the formation of an alloy layer with a high electrical resistivity at the contact portion. However, the structure for preventing the formation of these alloy layers is not limited to the structure shown in Fig. 36 and can be variously modified. The structures shown in Fig. 44 to Fig. 52 may be used. That is, Fig. 44 shows a structure in which the fourth-layer wiring 1 3 L is composed of a thinner conductive film 1 3 L 1 and a thicker conductive film 13L2 overlapping the upper layer. The thinner conductive film 1 3 L 1 is a material having the function of improving the adhesion between the fourth layer wiring 1 3 L and the interlayer insulating film 4 d or the barrier function of suppressing the diffusion of constituent atoms of the thicker conductive film 1 3 L 2 For example, W, T i N, T i, Ta, WN, WSiN, TiSiN, TaN, Ta S i N, or the like. The thick conductive film 13L 2 is made of, for example, A 1 or A .1. Alloy. In the structure shown in FIG. 4 and 5, a connection layer made of, for example, W or W alloy formed by a selective CVD method is provided on the exposed surface of the third layer wiring 1 1 L exposed from the connection hole 8. Conductor portion 2 C 1 · The connection conductor portion 20 C 1 in the connection hole 8 f is provided with a connection conductor portion 2 C 2 made of, for example, A 1 or A 1 alloy. The paper size for the third layer is applicable to the Chinese National Standard (CNS) A4 specification (210 * 297 mm) --------------- installed.-(Please read the precautions on the back again (This page)--Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs -61-'b 4 9 34 2 μ _' _B7____ V. Description of the invention (59) The 13L line is connected through the conductor section 20C (20C2, 20C1) is electrically connected to the third-layer wiring 11L *. Alternatively, 1 L and 20 C may be formed simultaneously. That is, the contact layer of the fourth layer wiring 1 3 L made of A 1 series material and the connection conductor portion 20C2 and the third layer wiring 1 1 L made of Cu material is provided with W and the like. Structure of the connection conductor portion 20 C 1 • This prevents the formation of an alloy layer with a high electrical resistivity at the contact portion. In addition, since the connection conductor portion 20 C 2 constituting most of the connection conductor portion 20 C is made of an A 1-based material having a low resistance, it is possible to reduce the configuration of all the connection conductor portions by W or the like. The resistance of the connection conductor portion 20 C is compared with the structure of Fig. 36. In the structure shown in Fig. 46, a cap conductor film 11L3 is provided above the second layer wiring 1 1L. The cap conductor film 11L3 is made of, for example, W, TiN, Ti, Ta'WN, WSiN, TiSiN, TaN, or TaSiN. The thick conductor film 13L2 is made of, for example, A 1 or A 1 alloy. A conductor film made of A 1 or A 1 alloy, which is integrally formed with the fourth layer wiring 1 3L, is embedded in the connection hole 8 f. At this time, the fourth layer wiring made of A 1 series material is also embedded. 1 3L, and the third layer of wiring 1 made of Cu and other materials 1 1L is provided with a thin conductor film 1 1 L 3 made of W and the like. Therefore, it is possible to prevent the formation of a high-resistance alloy layer at the contact portion. And because the connection hole 8 f is embedded with a low-resistance A 1 series material, the resistance of the interlayer connection portion can be reduced compared to the case of FIG. 36. In the structure of Figure 47, the connection hole 8 f is applied to the thinner conductive film. The paper size applies the Chinese National Standard (CNS) A4 specification (210 * 297 male S) ~ -62: --------- ---- Equipment * nnnnnk ϋ I ni I line {Please read the precautions on the back first, and then C..S this page) Consumption cooperation by employees of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed A7 A7 4 59 34 2 B7____ V. Description of the invention (60) 1 3 L 1 embedded • The thinner conductive film 1 3 L 1 at this time is composed of the same material as the above materials, for example, W, T i N, T i, Ta, WN, WS i ' , Ti S iN, TaN or TaS iN. The thicker conductive film 1 3L2 is made of, for example, A 1 or A 1 alloy. The structure of Fig. 48 is based on the structure of Fig. 47. There are thicker conductor films 13L2a and 13L2b, which are sequentially stacked on the thinner conductor film 1 3 L 1 from the lower layer, and the thicker conductor film 1 3 on the lower layer side. L 2 a is made of, for example, W or a W alloy, and is formed by, for example, a CVD method or a sputtering method. The thicker conductor film 1 3 L 2 b on the upper layer side is made of, for example, A 1 or A 1 alloy, and is formed by, for example, the C V D method or the sputtering method. In the structure shown in Fig. 49, the connection conductor portion 14C of the fourth layer wiring 1 1 L constituted by the A 1 system and the third layer wiring 1 1 L constituted by the Cu system is formed by a sputtering method. The barriers (thinner conductive film) 1 4 C 1 formed by W, TiN and the like, and the plugs (thicker conductive film) 1 4 C 2 by W formed by CVD method. With this structure, the contact resistance can be reduced. After the barrier metal is deposited by sputtering, the structure is buried in the connection hole 8 f by the C VD method, and then the barrier metal 14C1 and the plug 14C2 can be formed only through CMP or repeated etching. Within the connection hole 8 f. The connection conductor portion 1 C may be constituted by only the plug 1 4 C 2 in which T i N is embedded by the CVD method. The structure of Fig. 50 is based on the structure of Fig. 49. The thicker conductor film composed of the 4th layer of wiring 1 3L, BP and A 1 series is applied to the Chinese standard SCN (CNS > A4). Specifications (210 * 297 cm) I! -------- * Equipment -------- Order -----! 1 · Line {Please read «Read the intentions on the back and reproduce again» Page > Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs-63- A7 A7 459342 B7_ V. Description of the Invention (61) 1 3 L 2 and film melting point metals such as T i N or W It is composed of a thinner conductive film 13 L 1 of the compound. As a result, reliability can be improved even more. The structure of Fig. 51 is based on the structure of Fig. 49, and barrier metals and After W, no plug processing is applied, but A 1 series materials are stacked with barrier metals (thinner conductive films) 13L1 such as w, T iN, and thicker conductive films 13L2a composed of W, and A1 series. The thicker conductor film 1 3 L 2 b constitutes the fourth layer of wiring 1 3 L. In this way, it is left without plug processing and becomes a laminated wiring with A 1 alloy, which can improve the production of the plug by honing process. Simplified and stacked structures The resulting reliability. The structure in Figure 52 is in the structure in Figure 51. There is no barrier metal (thinner conductor film) 13L1, and a thicker conductor film 13L2a made of TiN formed by CVD. The thicker conductor film 1 3 L 2 b composed of A1 and A1 series constitutes the fourth layer wiring 1 3 L. The T i N film 1 3 L 2 b formed by the CVD method has an adhesion ratio with the interlayer insulating film. The film is excellent. Therefore, it is not necessary to provide a barrier metal 1 3 L 1 and the manufacturing process can be reduced. Like the structure shown in FIG. 51, it is left without plug processing. Improve the simplification of the honing process of the plug by abolition and the reliability of the laminated structure. The structure shown in the connecting conductor section 1 4 C is applicable to the connecting conductor section IOC, 12C, 18C, 19C, 20C. Yes, Fig. 53 shows that the structure of the connecting conductor portion 1 4 C shown in Fig. 49 is applied to the connecting conductor portion shown in Fig. 39 and Fig. 40 — It — — — —! — —!. IIII — I (ifr first read the notes on the back and then 4; · this page) Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs consume Printed by the agency. Paper size: General Chinese National Standard (CNS) A4 specification (210 X 297 mm) -64- 5 9 34 2 A7 B7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 20C structure. The thinner conductor films 19C1 and 20C1 are symmetrically formed with the barrier metal 1 4 C, while the thicker conductor films 19 C2 and 20C2 are symmetrically formed with the plug 14C2. The 54th line is a structure in which the third layer wiring 1 1 L, 2 1 C shown in FIG. 53 is newly formed by Shuang Dama. In this structure, 5 g of connection holes are formed, and after 8 hours, the barrier metal is deposited by sputtering, and then Cu is formed thinly, for example, by sputtering, and then buried in the connection holes by electrolytic plating to form 8 g » Then, a thin conductor film 2 1 C 1 made of a barrier metal and a thick conductor film 21C 2 made of a CU are used to form the third-layer wiring 11L and 21.C by the CMP method. Since 2 1 C is formed on the plane longer than 8 h at least along the length of the wiring, the effective aspect ratio when 5 g and 8 h are simultaneously buried with Cu can be reduced, making it easy to implement Cu buried. Into. Figs. 55 (a) and 55 (b) show modification examples in which the connecting conductor portion 2C shown in Fig. 39 is biased in the longitudinal direction (X direction). Figure 55 (a) is a plan view showing the main part of one part of the second layer wiring 9L to 4th layer wiring 13L. 55 (b) is a main part along the line C-C of Figure 55 (a) Sectional view. Accordingly, even if the second-layer wiring 9 L is formed at a position P 1 adjacent to the second-layer wiring 9 L, the connection conductor portion 2 1 C can be designed. Fig. 56 shows a method of connecting the conductor portion 2 1 C shown in Fig. 39 to only the portion where the connection hole 8 f is arranged perpendicular to the length direction (X direction) without changing the pitch P ground. Thickened variant. Apply the connection conductor 2 1 C shown in Fig. 56 to the precautions shown on the back of Mtt before the 5th price, and then install (-, this page).-Thread · This paper size is applicable ®囷 家 棵 准 (CNS) A4 specification (210 X 297 mm) -65- Printed by employee consumer cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ab 9 34 2 a? B7 V. Description of the invention (63) (a) Figure and page 55 (b) The connecting conductor portion 21C in the figure (Embodiment 6) Figures 5 to 7 are cross-sectional views of main portions of a semiconductor integrated circuit device according to another embodiment of the present invention. Figs. 5 to 8 and Figs. 5 to 9 are cross-sectional views of main parts in the process of manufacturing a semiconductor volumetric circuit device. "First, the structure of the semiconductor integrated circuit device according to the sixth embodiment will be described with reference to Figs. The first layer wiring 6 L is made of a conductive material other than the C 11 series of W, while the second layer wiring 9L and the third layer wiring 1 1L are made of a Cu-based conductive material in the same manner as in Embodiment 5. . The first layer wiring 6L is used for, for example, wiring of a logic circuit composed of MI SFETs, or wiring between the junction logic circuits. Compared with the second layer wiring 9 L and the third layer wiring 1 1 L, It consists of a relatively short wiring length. The second-layer wiring 9 L and the third-layer wiring 1 1 L are used, for example, for wiring between wiring logic circuits, and constitute a structure extending in one direction in the X direction and the other extending in the direction Υ. The first layer of wiring 6 L is formed by a W film, and the first layer of wiring 6 L can be formed in a fine pattern. This increases the buildup and improves the resistance to electron migration. In addition, since the Cu-based conductive material is not used for the first-layer wiring 6L, the diffusion of Cu to the semiconductor substrate 1 can be reduced 'and the reliability can be improved. The size of this paper applies to the national standard (CNS) A4 specification (210 X 297 mm) · 66 — — I — III! — _ • 1111111 »11 — — — — — (Please read«-Note on the back first Please buy another copy) Printed by Shelley Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (64) Since the CU-based conductive material is used to form the second layer wiring 9 L and the third layer wiring 1 1 L, it can be reduced The resistivity of the wiring can become a high-speed operator. The connecting conductor portions 7C, 18C, 19C, 20C, and 2 1 C are barrier metals (compared with W formed by sputtering) similar to the connecting conductor portions 1 4 C shown in FIG. Thin conductor film) 1 4 C 1 and plug (thicker conductor film) made of W 1 4 C 2. The fourth layer wiring 13L and the fifth layer wiring 102 are made of, for example, an A1-based conductive material. The layer 4 wiring 1 3 L is a laminated structure of a thicker conductor film 1 3 L 2 made of barrier metals (thinner conductor films) 13L1 and 13L3 such as W, T i N, and A1 or A1 alloy. Made up. Via a layer 4 wiring 1 3 L made of an A 1 conductive material and a layer 3 wiring 1 1 L made of a Cu conductive material, a connection conductor portion 20 C formed by W Electrical connection is applied to prevent the formation of an alloy layer with a high electrical resistivity through A 1 and Cu through the contact portion. The fourth layer wiring 13L may be a wiring structure shown in Figs. 44 to 52. The fifth layer wiring 102 is electrically connected to the fourth layer wiring 1 3 L without a connection conductor portion, but it is not limited to this "with the fourth layer wiring 1 3 L and the third layer The connection between 1 1 L is the same, and the 5th layer wiring 1 0 2 and the 4th layer wiring are electrically connected via the connection conductor portion having the same structure as the connection conductor portion 2 0 C 1 L--- ---------- Install! --Order -------_ Line < Please read M-Notes on the back side again.V. This page) This paper size is applicable to China National Standard (CNS) A4 (210 X297 public copy) -67- A7 B7 4 5 9 34 2 V. Invention Explanation (65) It should be noted that the fifth-layer wiring 1 0 2 and the fourth-layer wiring 1 3 L may have a laminated structure in the same manner as the fourth wiring 1 3 L. In the fifth layer wiring 102, an insulating film 104 made of, for example, a silicon oxide film is formed, and an opening portion formed in the insulating film 104 is formed with a lower electrode 106. The fifth layer wiring 1 0 7 is a bump electrode 1 ◦ 8 which is electrically connected to a soft solder bump via a lower electrode 106, and the lower electrode 106 is a barrier metal, for example. Hereinafter, the method of forming the first layer wiring 6 L and the connecting conductor portion 7 C will be described briefly using FIGS. 58 and 59. After the connection $ 8 a is formed on the interlayer insulating film 4 a in the same manner as in FIG. 8, As shown in FIG. 58, a thin conductive film 7C1 made of W is deposited by a sputtering method, and then a thick conductive film 7C2 made of W is buried by CVD to deposit the connection holes 8a. Then, as shown in Fig. 59, the stack film is honed by, for example, the CMP method, and a thin conductor film 7 C 1 made of W and a thick conductor made of W are buried in the connection hole 8 a. Membrane 7 C 2. Then, the W film is deposited by, for example, the P VD method, and patterned by etching to form a first layer wiring 6L. Here, 6 L is formed using a W film according to the PVD method, but various changes are made to a laminated structure of the W film using the PVD method and a W film according to the CVD method. After the silicon oxide film is deposited by, for example, the CVD method, the silicon oxide film is honed by the CMP method to form an interlayer insulating film 4 b with a flat surface. The following process | It is the same terrain cost as the above-mentioned Embodiments 1 to 5. The paper size applies the Chinese Standard (CNS) A4 specification (210 * 297 male «) — In —-------- Install i I Mu Note on the back of Mtt before this page) Order. · Line · Consumption Cooperation of Employees of Intellectual Property Bureau of the Ministry of Economic Affairs -68- αο9 34 2 α7 Β7 V. Description of the Invention (66) The semiconductor integrated circuit of Embodiment 6 The circuit device uses the bump electrode 108, but as shown in FIG. 6C * it is also possible to electrically connect the bonding terminal 110 to a bonding pad composed of the fifth layer wiring 102. In addition, the semiconductor integrated circuit device according to the sixth embodiment is composed of five layers of wiring layers, but is composed of seven layers of wiring layers. • The second to fifth layers of wiring are made of a Cu-based conductive material. Alternatively, it is also possible to configure the 6th layer wiring to the 7th layer wiring with an A 1 series conductive material. At this time, the second layer wiring and the fourth layer wiring structure extend in the opposite direction, and the third layer wiring and the fifth layer wiring system structure extend in the same direction, and are used as wiring for connecting logic circuits. In addition, in the sixth embodiment, the third wiring layer located at a portion where the connection conductor portion 19 C and the connection conductor portion 20 C are connected is provided at least along the length of the wiring than the connection conductor. The connection conductor portions 2 1 C formed by the portions 1 9 C, 2 C are longer in the plane, but the structure constituting the connection conductor portions 2 1 C may be provided in the second, third, fourth, and fifth layers. Fig. 61 shows the planar layout of the semiconductor integrated circuit device of the first to sixth embodiments. The gate array 2000 is repeatedly arranged, and each gate array 20 C is equipped with integrated circuit elements such as a MI SFET, a bipolar transistor, and a resistor. Various logic circuits are constituted by changing the wiring patterns of the first layer wiring to the fifth layer wiring to form a semiconductor integrated circuit device having a predetermined logic. In Figure 62, it is shown that the gate array 2 0 0 and the paper size as the memory are applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 g t) '69----------- ---- Equipment --- (Please read the precautions on the back first, then this page) δ * --Line_ Printed by the Consumers' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 34 2 V. Description of the invention (67) RAM 4 0 0 semiconductor integrated circuit device. Also, as shown in Fig. 63, cells 400 * 500, 600, and 700 having various functions can be freely arranged according to the performance of the LSI. As described above, according to the fifth and sixth embodiments, in addition to the effects (8) to (10) obtained in the first embodiment, the following effects can be obtained. (1) After filling the conductive film using a CVD method or the like in the fine connection holes 8a to 8f, the connection holes 8a to 8f have wiring grooves 5a to 5 with a larger plane size. The first-layer wiring 6L, the second-layer wiring 9L, and the third-layer wiring 1 1L are filled with a conductor film to form a buried structure, and the wiring grooves 5 a to 5 and finer connection holes 8 a to 8 f are formed. Both of them are well embedded in the conductor film. Also, in the fine connection holes 8 a to 8 f and the wiring grooves 5 a to 5 d above them, the conductor film is filled with a CVD method or a plating method at the same time. In this case, the wiring grooves 5 a to 5 f are formed into the connection holes 8 a to 8 f to increase the planar size, so that the conductor film can be buried well. (2) Via (1) above, it is possible to improve the reliability of the connection between the wiring layers. Therefore, it is possible to improve the yield and reliability of semiconductor integrated circuit devices. (3) Through the above (1) *, miniaturization of embedded wiring can be promoted. Therefore, miniaturization or higher integration of semiconductor integrated circuit devices can be promoted. (4) Via the above (1), it is not necessary to use a difficult technique, and the conductor grooves 5 a to 5 f and the connection holes 8 a to 8 f can be well buried in the conductor film. Please first. Read the notes on the back •, 'The binding of the paper printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economics is applicable to the Chinese family standard (CNS) A4 specification (210 * 297 public love) -70- A7 B7 A b 9 34 2 V. Description of the invention (65) (5) Via the above (1), even if Cu or Cu alloy is used as the buried wiring material, the buried state can be well implemented. (6) The first-layer wiring 6L that is in direct contact with the semiconductor substrate 1 is made of a W-based conductor material, while maintaining the buried state of the conductor film in the connection hole 8 a, it can be prevented from being caused by Cu Defective elements due to the diffusion phenomenon of atoms to the semiconductor substrate 1 side, and the first layer wiring 6 L is formed by a W-based conductive material, which can reduce the wiring resistance and improve the EM resistance. As mentioned above, the invention made by the present inventors has been specifically described in accordance with the embodiments. However, the present invention is not limited to those described in the above embodiments, and various changes can be made without departing from the scope of the invention. For example, the semiconductor substrate may be provided with a silicide layer such as a tungsten silicide or a titanium silicide at its contact portion with the connection conductor portion. The wiring layer system is not limited to those having 4 to 7 layers, and various changes can be made, and 3 or more layers may be used. In the invention disclosed in this case, the effect obtained by a representative person will be briefly described as follows. (1) According to the method of manufacturing a semiconductor integrated circuit device according to the present invention, a wiring groove is formed after the connection hole is sufficiently buried in the conductor film, and the groove is buried with the conductor film. Both sides of the finer connection grooves are well embedded in the conductive film * (2) According to the method of manufacturing a semiconductor integrated circuit device of the present invention, when the same wiring layer has different wiring grooves, etc., the fine wiring is selected through Trenches, etc., and wirings larger than them are buried by methods such as trenches, which are easy to embed. (Please read the precautions on the back and then 1. ·. This page) Order, the paper printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Employees' Cooperatives, is printed in accordance with the China National Standard (CNS) A4 specification (210 X 297 mm) -71-459342 A7 B7_ V. Description of the invention ( 69) The conductor film can be well embedded in the wiring grooves of both sides of the conductor film β (3) Via the above (1) or (2) ', the reliability of the connection between the wiring layers can be improved. Therefore, it is possible to improve the yield and reliability of semiconductor integrated circuit devices. (4) Through the above (1) or (2) ', miniaturization of embedded wiring can be promoted. Therefore, it is possible to promote the miniaturization or the increase in the size of the semiconductor integrated circuit device. (5) Through the above (1) or (2), it is not necessary to use difficult techniques * The conductor film is well buried in the trenches and connection holes for wiring. (6) Via (1) or (2) above, a buried wiring material can be satisfactorily implemented even when Cu or Cu alloy is used. (7) According to the method for manufacturing a semiconductor integrated circuit device according to the present invention, a Cu-based conductor material formed by a sputtering method or the like is planarized on an insulating film including a wiring groove, and the fields other than the wiring groove are excluded. The Cu-based conductor material is heat-treated after forming the embedded wiring, which improves the EM resistance by promoting the growth of Cu particles. At the same time, it can avoid damage or oxidation on the surface of the Cu-based conductor film during flattening. The surface of the film can be smoothed, or the surface contamination of the insulating film exposed during CMP can be removed. Therefore, the reliability of the embedded wiring composed of the CU-based conductor material can be improved. (8) The semiconductor product according to the present invention The bulk circuit device is a semiconductor integrated circuit device having embedded wiring on a wiring layer above the semiconductor substrate. The wiring material of the buried wiring contacting the semiconductor substrate is 1—1 tt n I 1 n (t It ft— an I— · ---- line < i *-IB · Read the notes on the back then i: This page) Printed on the paper by the Consumers' Cooperative of Intellectual Property Bureau of the Ministry of Economy Standards for Chinese papers (CNS) A4 (210 X 297 male S> -72) -45 9 34 2 A7 B7 V. Description of the invention (70) It is made of W, W alloy, A 1 or A 1 alloy, and the embedded wiring of the upper wiring layer is made of Cu or Cu alloy. The structure prevents the diffusion of Cu atoms to the semiconductor substrate side while maintaining the buried state of the conductor film in the connection hole, avoids the failure of the element due to the diffusion phenomenon, and reduces the integrity of the semiconductor integrated circuit device. (9) The semiconductor integrated circuit device according to the present invention belongs to a semiconductor integrated circuit device having embedded wiring in a wiring layer above a semiconductor substrate. The wiring material is made of A 1 or A 1 alloy, and the buried wiring of the underlying wiring layer is made of Cu or Cu alloy, and the assembly technology such as the past bonding terminal technology or the bump electrode formation technology is still used. Therefore, a semiconductor integrated circuit device having a buried wiring with a Cu-based conductor material can be easily introduced into the assembly process. (10) The semiconductor integrated circuit device according to the present invention is designed to be layered on a semiconductor substrate. The wiring layer has a semiconductor integrated circuit device with embedded wiring. When connecting wirings made of A 1 or A 1 alloy and wirings made of CU or C 11 alloy, these junctions are used as barrier conductor films through these joints. The dielectric plug can reduce the connection resistance between wiring layers because it can prevent the formation of a high-resistance alloy layer at the junction when it directly contacts the A 1-based conductor material and the Cu-based conductor material. Through the above (8) to (10), it becomes an embedded wiring that can be made of Cu-based conductor material, without any inconvenience, and can be integrated into the semiconductor integrated circuit device's overall structure. (CNS) A4 specification (210 * 297 male S) -------------- install --- < ΐ · First, read the notes on the back, and then i. This page) Order: • Lines.... Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs on consumer cooperation. Du-73- ad 34 2 A7 __; _ B7___ 5. Description of the invention ( ) (1 2) Furthermore, according to the semiconductor integrated circuit device of the present invention, the length of at least the predetermined extension direction of the wiring embedded in the wiring is formed through the above-mentioned connection-conducting conductor portion to form the above-mentioned connection hole. The length of the wiring extending direction is long, and since the connecting grooves forming the connecting conductor portions for relays can be formed large, the conductive film can be buried well in the connecting grooves. Therefore, the reliability of the electrical ground connection between the upper and lower wiring layers can be improved, and the yield and reliability of the semiconductor integrated circuit device can be improved. * (Simplified description of the diagram) FIG. 1 shows an embodiment of the present invention A cross-sectional view of a main part of a semiconductor integrated circuit device. Fig. 2 is a cross-sectional view of a main portion of the first layer wiring of the semiconductor integrated circuit device of Fig. 1; Fig. 3 is a cross-sectional view showing a modified example of the wiring structure of Fig. 2 " Fig. 4 is a cross-sectional view showing a modified example of the wiring structure of Fig. 2 Fig. 5 is a view showing a modification of the wiring structure of Fig. 2 Example of a sectional view. Fig. 6 is a cross-sectional view of a main part of a second layer wiring of the semiconductor integrated circuit device of Fig. 1; Fig. 7 is a cross section of a main part of a semiconductor integrated circuit device showing a modified example of the interconnection between the wiring layers of the semiconductor integrated circuit device of Fig. 1 ° I ° Fig. 8 shows a process of the semiconductor integrated circuit device of FIG. The main section cross-sectional view. Fig. 9 is a sectional view of a main part in the process of manufacturing the semiconductor integrated circuit device of Fig. 1; This paper size applies to China National Standard (CNS) A4 specifications (210 X 297 meals) — lit — — — — — — — — 1 II! III ill — — — — — I (Please read the intention on the back first Matters are repeated on this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs -74- A7 4 5 9 34 2 B7____ V. Description of the Invention (72) Figure 10 shows the semiconductor integrated circuit device shown in Figure 1. A cross-sectional view of the main parts in the manufacturing process. (Please read the precautions on the back of this page before i λ page) Figure 11 is a cross-sectional view of the main parts in the process of manufacturing the semiconductor integrated circuit device shown in Figure 1. FIG. 12 is a cross-sectional view of a main part in the manufacturing process of the semiconductor integrated circuit device of FIG. 1. FIG. Fig. 13 is a partially cutaway perspective view showing the main parts of the semiconductor integrated circuit device manufacturing process of Fig. 1; Fig. 14 is a partially cutaway perspective view showing main parts of the semiconductor integrated circuit device manufacturing process of Fig. 1; Fig. 15 is a partially cutaway perspective view showing main parts of the semiconductor integrated circuit device in the manufacturing process of Fig. 1; Fig. 16 is a partially cutaway perspective view showing the main parts of the semiconductor integrated circuit device manufacturing process of Fig. 1; Fig. 17 is a partially cutaway perspective view showing the main parts of the semiconductor integrated circuit device manufacturing process of Fig. 1; Fig. 18 is a partially cutaway perspective view showing main parts of the semiconductor integrated circuit device in the manufacturing process of Fig. 1; Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs. FIG. 19 is a cross-sectional view of a main part in a process of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention. FIG. 20 is a cross-sectional view of a principal part in the process of the semiconductor integrated circuit device continued from FIG. 19. FIG. 21 is a cross-sectional view of the major part in the process of the semiconductor integrated circuit device continued from FIG. 19. Section cross-section ° This paper size applies Chinese National Standard (CNS) A4 (210x297 mm) -75- Λ r 0342 A7 B7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (73) Figure 2 2 It is a cross-sectional view of a main part in the manufacturing process of the semiconductor integrated circuit device following FIG. 19. Fig. 23 is a sectional view of a main part in the process of the semiconductor integrated circuit device continued from Fig. 19; Fig. 24 is a cross-sectional view of a main part of a semiconductor integrated circuit device according to another embodiment of the present invention "* Fig. 25 is a cross-sectional view of a main part in the process of manufacturing a semiconductor body circuit device according to another embodiment of the present invention Illustration. Fig. 26 is a cross-sectional view of a main part in the process of the semiconductor integrated circuit device continued from Fig. 25. Fig. 27 is a cross-sectional view of a principal part in the process of the semiconductor integrated circuit device continued from Fig. 25. Fig. 28 is a cross-sectional view of a principal part in the process of the semiconductor integrated circuit device continued from Fig. 25. Fig. 29 is a cross-sectional view of a main part in a manufacturing process of a semiconductor integrated circuit device according to another embodiment of the present invention. Fig. 30 is a cross-sectional view of a principal part in the process of the semiconductor integrated circuit device continued from Fig. 29. Fig. 31 is a cross-sectional view of a principal part in the process of the semiconductor integrated circuit device continued from Fig. 29. Fig. 32 is a cross-sectional view of a principal part in the process of the semiconductor body circuit device continued from Fig. 29. Fig. 33 is a cross-sectional view of a main part of a semiconductor body circuit device according to another embodiment of the present invention. "__ — — — — — — — — — — (Please read the second notice on the back before proceeding. Page ci): Order--Line-This paper size is applicable to China National Standard (CNS) A4 (210 * 297 mm *) -76- 459342 A7 B7 V. Description of the invention (74) Figure 34 shows the invention Main section cross-sections of other circuit devices. Fig. 35 is a sectional view of a main part showing another circuit device of the present invention. Fig. 36 is a sectional view of a main part showing another circuit device of the present invention. Fig. 37 is an enlarged sectional view showing a half of Fig. 36; Fig. 38 is an enlarged sectional view of a main part showing a modification of the main part in Fig. 37. Figure 3 9 (A) is a plan view of a principal part showing a modification of the principal part of the third device < Figure 39 (B) * (C) shows the deformation of the main part of the semiconductor integrated circuit device 0 Figure 40 is a diagram schematically showing the main part of the third device "Implementation of the semiconductor integrated circuit implementation Form of the semiconductor integrated circuit of the embodiment of the semiconductor integrated circuit volume device of the semiconductor integrated circuit device of the semiconductor integrated circuit shown in Figure 7 of the semiconductor integrated circuit shown in Figure 39 (A) in the main part of the enlarged sectional view Semiconductor integrated circuit assembly First read the notice on the back and then page binding. ▲ Printed by the co-operative society of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed illustrations of the deformation examples. Figure ο 4 The model of the surface model shown in the figure 2 4 The figure of the example of the deformation illustrated in the chart ο 4 The model of the model in the surface shown in figure 3 4 The main installation path -S Ιξ! ΟΓ Figure 6 3 The chart is shown in Figure 4 4 This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 cm > -77- 4d 9 34 2 A7 B7____ V. Description of the invention (75) Modification Enlarged sectional view of the main part. Figs. 4 and 5 are enlarged cross-sectional views of the main parts showing a modified example of the main part of the semiconductor integrated circuit device of Figs. 36 and 46. Figs. 4 and 6 show the semiconductor body circuit of Figs. Enlarged sectional view of the main part of a modification example of the main part of the device "Fig. 4 7 is an enlarged cross-sectional view of the main part of a modification example of the main part of the semiconductor integrated circuit device of Fig. 36. Fig. 4 8 shows the first The enlarged sectional view of the principal part of the modification of the principal part of the semiconductor integrated circuit device of Fig. 3 and 6 "Fig. 4 9 is an enlarged sectional view of the principal part of the modification of the principal part of the semiconductor integrated circuit device of Fig. 36 Fig. 50 is an enlarged sectional view of a main part showing a modified example of the main part of the semiconductor integrated circuit device of Fig. 36. Fig. 51 is a main part of the semiconductor integrated circuit device of Fig. 36. The enlarged sectional view of the main part of the modified example. Fig. 5 2 is an enlarged cross-sectional view of the main part of the modified example of the main part of the semiconductor integrated circuit device of Fig. 36. Fig. 5 3 shows the 3rd part (C 5) is a cross-sectional view of a modified example of the semiconductor integrated circuit device. (C) A cross-sectional view of a modified example of the semiconductor integrated circuit device. Figure 55 (a) is a plan view showing a modified example of the semiconductor integrated circuit device of Figure 39 (A). Figure 55 (b) shows The semiconductor package shown in Figure 55 (a) — til — — — — — — • installation * ------- order! | _ Line I, (refer to the precautions on the back before reading this page) The paper size printed by the Ministry of Intellectual Property Bureau's Consumer Cooperatives is applicable to the National Park Standard (CNS) A4 specification (210 X 297) -78- A7 453 34 2 _B7____ 5. Description of the invention (76) The main parts of the circuit device Enlarged section. Fig. 56 is a plan sectional view showing an embodiment of the semiconductor integrated circuit device of Fig. 39 (A). Fig. 57 is a cross-sectional view of a main part of a semiconductor integrated circuit device according to another embodiment of the present invention. Fig. 58 is a cross-sectional view of a main part in the process of manufacturing the semiconductor body circuit device shown in Fig. 57. Fig. 59 is a sectional view of a main part in the process of manufacturing the semiconductor body circuit device of Fig. 57; Fig. 60 is a cross-sectional view of a principal part showing a modification example of the semiconductor integrated circuit device of Fig. 57. Fig. 61 is a plan view showing a semiconductor integrated circuit device according to an embodiment of the present invention. Fig. 62 is a plan view showing a modification of the semiconductor integrated circuit device shown in Fig. 61. Fig. 63 is a plan view showing a modification of the semiconductor integrated circuit device shown in Fig. 61. , 1 (Description of symbols) 1 Semiconductor substrate, 2 Element separation section, 2a Separation groove-2 b Separation insulation film, 4a ~ 4d Interlayer insulation film, 5a ~ 5f Wiring groove, 6L First layer wiring, 7 C Conductor section for connection, 8a ~ 8h connection hole, 9 L layer 2 wiring, 10C conductor section for connection, 1_1 !!! 1_ ^^ -------- Order --III I --- < tfr First read the notes on the back before re-production.-. This page) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Employee Consumer Cooperatives. 9 3 4 2 a? _____B7__ 5. Description of the invention (77) 1 1 L layer 3 wiring, 12C connection conductor, 1 3 L layer 4 wiring, 14C connection conductor, 15 surface protective film, 15a, 15b Protective film, 17a ~ 17c photoresist pattern * 19c ~ 21c Conductor for connection, 102 Layer 5 wiring, 104 Insulation film, 106 Lower electrode, 108 Bulge electrode * 110 Tap terminal, 200 Gate array |
4 0 0 RAM 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（2〗0 * 297公釐）4 0 0 RAM Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper size applies to China National Standard (CNS) A4 specifications (2〗 0 * 297 mm)
Claims (1)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23423697 | 1997-08-29 | ||
| JP18281398A JP3605291B2 (en) | 1997-08-29 | 1998-06-29 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW459342B true TW459342B (en) | 2001-10-11 |
Family
ID=26501475
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW087112907A TW459342B (en) | 1997-08-29 | 1998-08-05 | Semiconductor integrated circuit apparatus with copper wiring layer and its manufacturing method |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP3605291B2 (en) |
| KR (1) | KR100847921B1 (en) |
| TW (1) | TW459342B (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3651765B2 (en) | 2000-03-27 | 2005-05-25 | 株式会社東芝 | Semiconductor device |
| JP4130621B2 (en) | 2003-10-30 | 2008-08-06 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
| JP2007266073A (en) * | 2006-03-27 | 2007-10-11 | Toshiba Corp | Semiconductor device and its fabrication process |
| US20080290428A1 (en) * | 2007-05-23 | 2008-11-27 | Texas Instruments Incorporated | Use of alloys to provide low defect gate full silicidation |
| JP5214913B2 (en) * | 2007-05-31 | 2013-06-19 | ローム株式会社 | Semiconductor device |
| US7867891B2 (en) * | 2008-12-10 | 2011-01-11 | Intel Corporation | Dual metal interconnects for improved gap-fill, reliability, and reduced capacitance |
| KR102562279B1 (en) | 2018-01-26 | 2023-07-31 | 삼성전자주식회사 | Plating solution and metal composite and method of manufacturing the same |
| KR102027951B1 (en) | 2019-06-07 | 2019-10-04 | 권일수 | Method and apparatus for controlling integrated circuit manufacturing process |
| US11424133B2 (en) | 2019-07-25 | 2022-08-23 | Samsung Electronics Co., Ltd. | Metal structure and method of manufacturing the same and metal wire and semiconductor device and electronic device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09213698A (en) * | 1996-01-31 | 1997-08-15 | Fujitsu Ltd | Formation of wiring |
-
1998
- 1998-06-29 JP JP18281398A patent/JP3605291B2/en not_active Expired - Lifetime
- 1998-08-05 TW TW087112907A patent/TW459342B/en not_active IP Right Cessation
- 1998-08-26 KR KR1019980034549A patent/KR100847921B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR19990023871A (en) | 1999-03-25 |
| JP3605291B2 (en) | 2004-12-22 |
| JPH11135630A (en) | 1999-05-21 |
| KR100847921B1 (en) | 2008-11-11 |
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| GD4A | Issue of patent certificate for granted invention patent | ||
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