TW459320B - Flip-chip soldering structure with stress buffering effect - Google Patents

Flip-chip soldering structure with stress buffering effect Download PDF

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Publication number
TW459320B
TW459320B TW089117749A TW89117749A TW459320B TW 459320 B TW459320 B TW 459320B TW 089117749 A TW089117749 A TW 089117749A TW 89117749 A TW89117749 A TW 89117749A TW 459320 B TW459320 B TW 459320B
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Taiwan
Prior art keywords
flip
chip
scope
substrate
patent application
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TW089117749A
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Chinese (zh)
Inventor
Wei-Sen Tang
Shr-Guan Chiou
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Siliconware Precision Industries Co Ltd
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Publication of TW459320B publication Critical patent/TW459320B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

There is provided a flip-chip soldering structure with stress buffering effect, which is able to solder a flip-chip type semiconductor chip to a substrate. The flip-chip soldering structure is characterized in forming a first conductive stress buffering layer on the chip bonding pad, and forming a second conductive stress buffering layer on the substrate bonding pad. These conductive stress buffering layers not only can reduce the stress to the solder bumps caused by the thermal expansion of the chip and substrate, but also prevent the soldered chip and substrate from deforming due to the difference in thermal expansion coefficients. Therefore, the completed flip-chip type semiconductor device has a better quality and reliability.

Description

A7A7

i、發明說明（i ) 4593 20 經濟部智慧財產局員工消费合作社印製i. Description of the invention (i) 4593 20 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs

[發明領域I 本發明係有關於一種覆晶式半導體製造技術，特別是 有關於一種覆晶銲接結構，其可用以將覆晶式半導趙晶片 銲接至基板上，其特點在於可提供一應力缓衝作用，可於 咼溫狀況中，用以緩衝晶片和基板由於熱膨脹而產生之應 力》 [發明背景] 覆晶式（Flip Chip)半導體封裝技術為一種先進之半導 體封裝技術，其與一般習知之非覆晶式封裝技術的最主要 之不同點在於其所封裝之半導趙晶片係以正面朝下之倒置 方式安置於基板上’並藉由複數個銲塊（s〇lderbumps)而銲 結及電性連接至基板β由於覆晶式封裝結構艎中不需要使 用較佔空間之銲線（bonding wires)來將半導體晶片電性連 接至基板’因此可使得所製成之覆晶封裝式半導體裝置的 整體尺寸作得更為輕薄短小β 然而習知之覆晶銲接結構的一項缺點在於其中之銲塊 易於在後續之尚溫狀況下，由於受到晶片和基板之熱膨脹 所引起之應力的掛壓作用而產生破裂現象，因此而可能對 晶片與基板之間的電性連接造成損壞，使得最後完成之覆 晶封裝式半導體裝置的品質性及可靠度均受到不良影響β 以下即配合所附圖式之第1圖，以圖解方式簡單敘述習知 之復晶銲接結構的基本結構及其缺點a 第1圖顯示一習知之覆晶銲接結構的剖面示意圖，其 係用以將一半導體晶片10以覆晶方式銲接至一基板20。 — —illlllli I I I I I ί 1 — — — ι!ΐί· (諳先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 1 16065 A7[Field of Invention I The present invention relates to a flip-chip semiconductor manufacturing technology, and in particular, to a flip-chip soldering structure that can be used to solder a flip-chip semiconductor wafer to a substrate, and is characterized by providing a stress The buffering effect can be used to buffer the stress caused by thermal expansion of wafers and substrates in high temperature conditions. [Background of the Invention] Flip Chip semiconductor packaging technology is an advanced semiconductor packaging technology, The most important difference of the known non-flip-chip packaging technology is that the packaged semiconductor chip is placed on the substrate in an upside-down manner and is bonded by a plurality of solder bumps. And electrically connecting to the substrate β because the flip-chip package structure 艎 does not require the use of more space-saving bonding wires (bonding wires) to electrically connect the semiconductor wafer to the substrate ', so that the fabricated flip-chip packaged semiconductor can be made The overall size of the device is made lighter, thinner and shorter β. However, a disadvantage of the conventional flip-chip soldering structure is that the solder bumps are easy to maintain in the subsequent temperature conditions. The cracking phenomenon occurs due to the hanging pressure of the stress caused by the thermal expansion of the wafer and the substrate. Therefore, the electrical connection between the wafer and the substrate may be damaged, resulting in the quality and quality of the final flip-chip packaged semiconductor device. Reliability is adversely affected β The following is a diagrammatic description of the basic structure and disadvantages of a conventional multi-crystal welded structure in conjunction with Figure 1 of the attached drawing.a Figure 1 shows a cross-section of a conventional flip-chip welded structure. A schematic diagram for soldering a semiconductor wafer 10 to a substrate 20 in a flip-chip manner. — —Illlllli I I I I I ί 1 — — — ι! Ϊ́ί · (谙 Please read the notes on the back before filling this page) This paper size applies Chinese National Standard (CNS) A4 (210 X 297 mm) 1 16065 A7

五 '發明說明（2 ) 此習知之復晶銲接結構包含一鋁製銲墊1丨，其形成於半導 體晶片10之表面上；一銲塊底部金屬結構層（UnderBu叫 Metallization，UBM)12 ’其形成於鋁製銲墊11上；以及一 銲塊13，其形成於UBM結構層12上。此外，此習知之覆 晶銲接結構亦包含一銅製銲墊21，其形成於基板2〇之表 面上；以及一黏銲性（solder wettable)金屬結構層，例如為 一銅/鎳/金（Cu/Ni/Au)之金屬結構層22，其形成於鋼製輝 墊21上。 經濟部智慧財產局員4消費合作社印製 半導體晶片10係以倒置方式（即覆晶方式）安置於基板 20 ’並使得其上之銲塊13黏結至Cu/Ni/Au金屬結構層22 上，藉此而將半導體晶片10銲接及電性相連至基板20。 然而’上述之覆晶鲜接結構的一項缺點在於其中之銲 塊13易於在後續之高溫狀況下，例如為封裝膠體製程中的 高溫狀況下’由於受到半導體晶片10和基板20之熱膨脹 所引起之應力的擠壓作用而產生破裂現象，因此而可能對 半導體晶片10與基板20之間的電性連接造成損壞，使得 最後完成之覆晶封裝式半導體裝置的品質性及可靠度受到 不良影響。這是由於半導體晶片10、銲塊13、和基板20 具有不同之熱膨骚係數（Coefficient of Thermal Expansion， CTE);且半導體晶片l〇上的鋁製銲墊11和UBM結構層 12’以及基板20上的銅製銲墊21和Cu/Ni/Au金屬結構層 22，均係為具有高剛性模數（m〇dulus of rigidity)之材質所 製成；因此使得半導體晶片10和基板20於受熱時所引起 的膨脹應力可直接傳遞至銲塊13上，因而對銲塊13造成 ----------------訂---1 ------ (請先閱讀背面之泫意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210x297公釐） 2 16065 經濟部智慧財產局員工消f合作社印製 --A593 2Q_b7_ 五、發明說明（3 ) 擠壓作用，使得銲塊13易於產生破裂現象。若銲塊13發 生破裂現象’則將對半導體晶片1〇與基板20之電性連接 造成損壞。 此外，半導體晶片10和基板20於受熱時所引起的膨 脹應力亦同時會使得其本身之結構體易於產生變形*使得 最後完成之覆晶封裝式半導體裝置之品質性及可靠度均受 到不良影響。 目前已有許多不同的專利技術可用來製作覆晶銲接結 構，例如包括以下所列之美國專利： .美國專利第 5,904,859 號"FLIP CHIP METALLIZATION” ； .美國專利第 5,902,686 號”METHODS FOR FORMING AN INTERMETALLIC REGION BETWEEN A SOLDER BUMP AND AN UNDER BUMP METALLURGY LAYER AND RELATED STRUCTURES"； •美國專利第 6,01 5,652 號”MANUFACTURE OF FLIP-CHIP DEVICE” ； •美國專利第 5,137,845 號”METHOD OF FORMING METAL CONTACT PADS AND TERMINALS ON SEMICONDUCTOR CHIPS"； •美國專利第 5,773,359 號"INTERCONNECTION SYSTEM AND METHOD OF FABRICATION"; •美國專利第 5,736,456 號"METHOD OF FORMING CONDUCTIVE BUMPS ON DIE FOR FLIP CHIP APPLICATIONS” ： I-----------i 裝—I-----訂—III---- (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家棵準（CNS)A4規格（210 297公蹵） 3 16065 經濟部智慧財產局員工消费合作社印製 A7 .__B7____ 五、發明說明<4 ) •美國專利第 4,927,505 號"METALLIZATION SCHEME PROVIDING ADHESION AND BARRIER PROPERTIES"； •美國專利第 5,903,058 號”CONDUCTIVE BUMPS ON DIE FOR FLIP CHIP APPLICATION"。 然而，上列之專利技術均未對前述之熱應力問題提供 一有效之解決方法。 [發明概述] 鑒於以上所述習知技術之缺點，本發明之主要目的便 是在於提供一種覆晶銲接結構，其可使得其中之銲塊不易 於在高溫狀況下，因受到晶片和基板之熱膨脹的應力影響 而產生破裂現象β 本發明之另一目的在於提供一種覆晶銲接結構，其可 使得所銲接之晶片及基板不易因熱膨脹係數之差異而產生 變形現象。 本發明之再一目的在於提供一種覆晶銲接結構，其可 使得最後完成之覆晶封裝式半導體裝置具有更佳之品質性 及可靠度》 根據以上所述之目的，本發明即提供了 一種新穎之覆 晶銲接結構。 本發明之覆晶銲接結構係用以將一覆晶式半導艎晶片 銲接至一基板β 廣義而言，本發明之覆晶銲接結構包含以下構件：（a)Five 'Description of the Invention (2) The conventional multi-crystal soldering structure includes an aluminum bonding pad 1 丨 formed on the surface of the semiconductor wafer 10; a metal structure layer (UnderBull Metallization, UBM) at the bottom of the solder block 12' Formed on the aluminum bonding pad 11; and a solder bump 13 formed on the UBM structure layer 12. In addition, the conventional flip-chip soldering structure also includes a copper bonding pad 21 formed on the surface of the substrate 20; and a solder wettable metal structure layer, such as a copper / nickel / gold (Cu) / Ni / Au) metal structure layer 22 is formed on a steel glow pad 21. Member of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 Consumer cooperatives printed semiconductor wafers 10 are placed on the substrate 20 'in an inverted (ie flip-chip) manner and the solder bumps 13 thereon are bonded to the Cu / Ni / Au metal structure layer 22, Accordingly, the semiconductor wafer 10 is soldered and electrically connected to the substrate 20. However, one of the disadvantages of the above-mentioned flip chip structure is that the solder bumps 13 are easily exposed to the subsequent high temperature conditions, such as the high temperature conditions during the sealing process. The cracking phenomenon caused by the stress of the stress may cause damage to the electrical connection between the semiconductor wafer 10 and the substrate 20, which adversely affects the quality and reliability of the final flip-chip packaged semiconductor device. This is because the semiconductor wafer 10, the solder bump 13, and the substrate 20 have different coefficients of thermal expansion (CTE); and the aluminum pads 11 and the UBM structure layer 12 'on the semiconductor wafer 10 and the substrate The copper pads 21 and the Cu / Ni / Au metal structure layer 22 on 20 are both made of a material with a high modulus of rigidity (m0dulus of rigidity); therefore, the semiconductor wafer 10 and the substrate 20 are exposed to heat. The induced expansion stress can be directly transmitted to the solder bump 13, which causes the solder bump 13 to order--1 ------ (Please first Read the intentions on the reverse side and fill out this page) This paper size applies to China National Standard (CNS) A4 (210x297 mm) 2 16065 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs-A593 2Q_b7_ V. Description of the invention ( 3) The squeezing action makes the solder bump 13 prone to cracking. If the solder bump 13 is broken, the electrical connection between the semiconductor wafer 10 and the substrate 20 will be damaged. In addition, the expansion stress caused by the semiconductor wafer 10 and the substrate 20 when heated will also cause its own structure to be easily deformed *, which will adversely affect the quality and reliability of the final flip-chip packaged semiconductor device. There are many different patented technologies that can be used to make flip-chip welded structures, including the following US patents: US Patent No. 5,904,859 " FLIP CHIP METALLIZATION "; US Patent No. 5,902,686" METHODS FOR FORMING AN INTERMETALLIC " REGION BETWEEN A SOLDER BUMP AND AN UNDER BUMP METALLURGY LAYER AND RELATED STRUCTURES "; • US Patent No. 6,01 5,652 “MANUFACTURE OF FLIP-CHIP DEVICE”; • US Patent No. 5,137,845 “METHOD OF FORMING METAL CONTACT PADS AND TERMINALS ON SEMICONDUCTOR CHIPS " • U.S. Patent No. 5,773,359 " INTERCONNECTION SYSTEM AND METHOD OF FABRICATION "; U.S. Patent No. 5,736,456 " METHOD OF FORMING CONDUCTIVE BUMPS ON DIE FOR FLIP CHIP APPLICATIONS ": I -------- --- i Pack—I ----- Order—III ---- (Please read the notes on the back before filling this page) This paper size is applicable to China National Standard (CNS) A4 (210 297 cm) ) 3 16065 A7 printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. __B7____ Explanation < 4) • US Patent No. 4,927,505 " METALLIZATION SCHEME PROVIDING ADHESION AND BARRIER PROPERTIES "; US Patent No. 5,903,058 "CONDUCTIVE BUMPS ON DIE FOR FLIP CHIP APPLICATION ". However, none of the patented technologies listed above are correct The aforementioned thermal stress problem provides an effective solution. [Summary of the Invention] In view of the shortcomings of the conventional techniques described above, the main object of the present invention is to provide a flip-chip welding structure which can make the solder bumps therein difficult. Under high temperature conditions, cracking occurs due to the thermal expansion stress of the wafer and the substrate. Another object of the present invention is to provide a flip-chip soldering structure, which can prevent the soldered wafer and substrate from being easily affected by the difference in thermal expansion coefficient. Deformation occurs. Another object of the present invention is to provide a flip-chip soldering structure, which can make the final flip-chip packaged semiconductor device have better quality and reliability. According to the above-mentioned object, the present invention provides a novel Flip-chip welding structure. The flip-chip welding structure of the present invention is used for welding a flip-chip semiconductor wafer to a substrate β. In a broad sense, the flip-chip welding structure of the present invention includes the following components: (a)

一晶片銲塾，其形成於該半導體晶片之一表面上；（b)—第 一導電性應力緩衝層，其形成於該晶片銲墊上；（c) 一 UBM -------------裝—---訂--I---- - 線 (請先閱讀背面之ii意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 4 16065 經濟部智慧財產局具工消費合作社印製 459320 五、發明說明G ) 結構層，其形成於該第一導電性應力緩衝層上：（d) 一鲜 塊，其黏結於該UBM結構層上；（e)—基板銲墊，其形成 於該基板之一表面上；（0—第二導電性應力緩衝層，其开多 成於該基板銲墊上；以及（g)—黏銲性金屬結構層，其形成 於該第二導電性應力缓衝層上，且黏結至該銲塊。 本發明之覆晶鲜接結構之特點在於其所提供之第_ 第二導電性應力緩衝層，不只可用以減低晶片和基板由於 熱膨脹而對銲塊所產生之應力，且亦可使得所銲接之晶片 及基板不易因熱膨脹係數之差異而產生變形現象，因此其 可使得最後完成之覆晶封裝式半導體裝置具有更佳之品質 性及可靠度。 [圖式簡述] 本發明之實質技術内容及其實施例已用圖解方式詳細 揭露飧製於本說明書所附之圖式之中》此些圖式之内容簡 述如下： 第1圖（習知技術）為一剖面結構示意圖，其中顯示一 習知之覆晶銲接結構；以及 第2A至2E圖為剖面結構示意圖，其中顯示本發明之 覆晶銲接結構之製程中的各個程序步驟。 [圖式標號] 10 覆晶式半導體晶片 11 晶片銲墊 12 UBM結構層 13 !?塊（solder bump) -------------丄^--------訂---------線 (锖先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國圉家標準（CNS)A4規格（210 X 297公楚） 5 16065 A7 B7 發明說明G ) 20 基板 21 基板銲墊 22 Cu/Ni/Au金屬結構層 100 覆晶式半導體晶片 110 晶片銲墊 111 第一導電性應力緩衝層 120 UBM結構層 130 銲塊（solder bump) 200 基板 210 基板銲墊 211 第二導電性應力緩衝層 220. Cu/Ni/Au金屬結構層 [發明實施例] > f— It n n tt I n I (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 以下即配合所附圖式之第2A至2E圖，詳細揭露說明 本發明之覆晶銲接結構之一實施例。第2 A至2E圖為剖面 結構示意圖，其中顯示本發明之覆晶銲接結構之製程t的 各個程序步驟。 請參閱第2A圖，於覆晶製程中，首先需預製出一覆 晶式半導體晶片100和一基板200。 半導體晶片100之表面上形成有一銲墊110，其例如 為一鋁製銲墊，係用以作為半導體晶片100之内部電路（未 顯示）之一個輸出入銲墊（註：實際之半導體晶片係包含複 數個輸出入銲墊；但由於此些輪出入銲墊之結構均大致相 同，因此為了簡化圖式及說明，此處之第2A圖中僅顯示 表紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公餐） 6 16065 經濟部智慧財產局員工消費合作社印製 459320 五、發明說明（7 ) 一個輪出入銲墊作為範例說明）。 相對地，基板200之表面上亦形成有一得墊210，其 例如為一銅製銲墊，係用以作為基板200上之一個電性接 觸點，以對應於半導體晶片100上之輸出入銲墊11〇(註： 實際之基板係包含複數個銅製銲墊；但由於此些銅製銲墊 之結構均大致相同，因此為了簡化圖式及說明，此處之第 2A圖中僅顯示一個銅製銲墊作為範例說明）。 本發明之主要技術特點即在於形成一第一導電性應力 緩衝層111於晶片銲墊110上；並同時形成一第二導電性 應力緩衝層211於基板銲墊210上。此第一及第二導電性 應力緩衝層111、211之材質須為一具有低剛性模數之導電 性材料，例如為一導電性高分子材料（electrically conductive polymer);且其製作方法可例如為採用塗佈製 程（coating)或網印製程（screen printing)而分別形成於晶片 銲墊110及基板銲墊210上。 請接著參閱第2B圖，下一個步碌為進行·一 UBM製 程，藉以形成一 UBM結構層120於第一導電性應力緩衝 層U 1上。此UBM製程為採用習知技術，其中之步驟非 關本發明之實質技術内容與範圍，因此以下將不對其作進 一步詳細之說明。 請接著參閱第2C圖’下一個步驟為進行一銲塊製程， 藉以形成一銲塊（solder bump) 130於UBM結構層120上α 此銲塊製程亦為採用習知技術，其中之步驟非關本發明之 實質技術内容與範圍，因此以下將不對其作進一步詳細之 ------------*,.^--------訂---------線 <請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 7 16065 經濟部智慧財產局員工消費合作社印製 A7 . _B7 _ 五·，發明說明（8~) '" 說明。 請接著參閱第2D圖，基板200上形成第二導電性應 力缓衝層2Π之後’係接著進行一黏銲性金屬化製程， 精 以形成一點鏵性（solder wettable)金屬結構層，例如為— /鎳/金（Cu/Ni/Au)之金屬結構層220，於第二導電性應力 衝層211上。此Cu/Ni/Au金屬結構層220之製作方法例如 可採用電鍍製程（plating)而形成於第二導電性應力緩衝層 211上。此黏銲性金屬化製程亦為採用習知技術，其中之 步鱗非關本發明之實質技術内容與範圍，因此以下將不對 其作進一步詳細之說明。 請接著參閱第2E圖，下一個步驟為將半導體晶片1〇〇 以倒置方式（即覆晶方式）安置於基板200上，並使得其上 之靜塊130黏結至Cu/Ni/Au金屬結構層220上，藉此而將 半導體晶片100銲接及電性相連至基板200。 於後續之高溫狀況下，例如為封裝膠體製程中的高溫 狀況下，由於半導體晶片100之熱膨脹所引起之應力，即 可受到第一導電性應力缓衝層1Π所提供之缓衝作用；而 由於基板200之熱膨脹所引起之應力，即可受到第二導電 性應力緩衝層211所提供之緩衝作用。因此於高溫狀況 下’第一及第二導電性應力緩衝層111、211即可減小銲塊 130所受到的熱應力，使得銲塊130不易因而產生破裂現 象而損壞到半導艘晶片100與基板200之間的電性連接。 此外，第一及第二導電性應力缓衝層111、211亦可使得半 導體晶片100與基板200本身不易因熱應力而發生變形， I * ------ —訂--------- f請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 8 16065 459320 五、發明說明（9 ) 使得最後完成之覆晶封裝式半導體裝置之整體外觀不易產 生變形現象。本發明之覆晶銲接結構因此可使得最後完成 之覆晶封裝式半導體裝置具有更佳之品質性及可靠度。 以上所述僅為本發明之較佳實施例而已，並非用以限 定本發明之實質技術内容的範圍。本發明之實質技術内容 係廣義地定義於下述之申請專利範圍中〇任何他人所完成 之技術實體或方法，若是與下述之申請專利範圍所定義者 為完全相同、或是為一種等效之變更，均將被視為涵蓋於 此專利範圍之中。 ---------^—I 裝--------訂--------- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 χ 297 ------- 16065 9A wafer pad is formed on a surface of the semiconductor wafer; (b) a first conductive stress buffer layer is formed on the wafer pad; (c) a UBM --------- ---- Packing ----- Order--I -----Line (Please read the notice on the back of the page before filling in this page) This paper size applies to China National Standard (CNS) A4 (210 X 297) (%) 4 16065 Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Industrial Cooperative Cooperative 459320 V. Description of the invention G) A structural layer formed on the first conductive stress buffer layer: (d) A fresh piece which is adhered to the UBM On the structural layer; (e) —a substrate pad formed on one surface of the substrate; (0—a second conductive stress buffer layer formed on the substrate pad; and (g) —adhesive welding A conductive metal structure layer is formed on the second conductive stress buffer layer and is bonded to the solder bump. The crystal-covered fresh structure of the present invention is characterized in that it provides the second conductive stress buffer layer , Not only can be used to reduce the stress caused by the thermal expansion of the wafer and the substrate to the solder bump, but also can make the wafer being soldered The substrate is not easily deformed due to the difference in thermal expansion coefficient, so it can make the final flip-chip packaged semiconductor device have better quality and reliability. [Brief Description of the Drawings] The essential technical content of the present invention and its embodiments The content of these drawings, which have been illustrated in the drawings attached to this specification, has been disclosed in detail by way of illustration: Figure 1 (known technique) is a schematic diagram of a cross-sectional structure, which shows a known flip chip Welding structure; and Figures 2A to 2E are schematic cross-sectional structure diagrams showing the various process steps in the manufacturing process of the flip-chip soldering structure of the present invention. [Figure numbering] 10 flip-chip semiconductor wafer 11 wafer pad 12 UBM structure layer 13!? Block (solder bump) ------------- 丄 ^ -------- Order --------- Line (锖 Read the precautions on the back first (Fill in this page again.) This paper size is in accordance with Chinese Standard (CNS) A4 (210 X 297 cm) 5 16065 A7 B7 Invention Description G) 20 Substrate 21 Substrate Pad 22 Cu / Ni / Au Metal Structure Layer 100 Overlay Crystalline semiconductor wafer 110 wafer pad 111 first conductive stress Punching layer 120 UBM structure layer 130 solder bump 200 substrate 210 substrate pad 211 second conductive stress buffer layer 220. Cu / Ni / Au metal structure layer [Invention Example] > f— It nn tt I n I (Please read the precautions on the back before filling out this page) The Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs prints the following figures 2A to 2E, which are used to illustrate the detailed description of the flip chip welding structure of the present invention An embodiment. Figures 2A to 2E are schematic cross-sectional structural diagrams showing the various program steps of the process t of the flip-chip soldering structure of the present invention. Please refer to FIG. 2A. In the flip-chip manufacturing process, a flip-chip semiconductor wafer 100 and a substrate 200 need to be prefabricated. A pad 110 is formed on the surface of the semiconductor wafer 100, for example, an aluminum pad is used as an input / output pad of the internal circuit (not shown) of the semiconductor wafer 100 (Note: The actual semiconductor wafer contains There are several input / output pads; however, because the structure of these input / output pads is almost the same, in order to simplify the diagram and description, the figure in Figure 2A only shows the paper size of the table, which is applicable to China National Standard (CNS) A4 (210 X 297 public meals) 6 16065 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 459320 V. Description of the invention (7) A wheel-out pad is used as an example). In contrast, a pad 210 is also formed on the surface of the substrate 200, which is, for example, a copper pad, which is used as an electrical contact point on the substrate 200 to correspond to the input / output pads 11 on the semiconductor wafer 100. 〇 (Note: The actual substrate contains a plurality of copper pads; but because these copper pads have approximately the same structure, in order to simplify the diagram and description, only one copper pad is shown in Figure 2A here. Example description). The main technical feature of the present invention is that a first conductive stress buffer layer 111 is formed on the wafer pad 110; and a second conductive stress buffer layer 211 is formed on the substrate pad 210 at the same time. The material of the first and second conductive stress buffer layers 111 and 211 must be a conductive material with a low rigidity modulus, such as an electrically conductive polymer material; and the manufacturing method thereof can be, for example, A coating process or a screen printing process is used to form the wafer pads 110 and the substrate pads 210, respectively. Please refer to FIG. 2B. The next step is to perform a UBM process to form a UBM structure layer 120 on the first conductive stress buffer layer U1. This UBM process uses conventional technology, and the steps are not related to the essential technical content and scope of the present invention, so it will not be described in further detail below. Please refer to FIG. 2C. The next step is to perform a solder bump process, so as to form a solder bump 130 on the UBM structure layer 120. This solder bump process also uses conventional techniques, and the steps are not relevant. The essential technical content and scope of the present invention, so it will not be further detailed in the following ------------ *,. ^ -------- order --------- --Line < Please read the notes on the back before filling in this page) This paper size is applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm) 7 16065 Printed by A7, Consumer Cooperatives, Intellectual Property Bureau, Ministry of Economic Affairs. _B7 _ Five, the description of the invention (8 ~) '" Description. Please refer to FIG. 2D. After the second conductive stress buffer layer 2II is formed on the substrate 200, an adhesive soldering metallization process is performed to form a solder wettable metal structure layer. For example,- The nickel / gold (Cu / Ni / Au) metal structure layer 220 is on the second conductive stress layer 211. The method for manufacturing the Cu / Ni / Au metal structure layer 220 can be formed on the second conductive stress buffer layer 211 by using a plating process, for example. This adhesive soldering metallization process also uses conventional techniques, and the steps are not related to the essential technical content and scope of the present invention, so it will not be described in further detail below. Please refer to FIG. 2E. The next step is to place the semiconductor wafer 100 on the substrate 200 in an inverted manner (ie, flip-chip method), and make the static block 130 thereon adhere to the Cu / Ni / Au metal structure layer. 220, thereby soldering and electrically connecting the semiconductor wafer 100 to the substrate 200. Under subsequent high-temperature conditions, such as those during the encapsulation process, the stress caused by the thermal expansion of the semiconductor wafer 100 can be buffered by the first conductive stress buffer layer 1Π. The stress caused by the thermal expansion of the substrate 200 can be buffered by the second conductive stress buffer layer 211. Therefore, under high temperature conditions, the first and second conductive stress buffer layers 111 and 211 can reduce the thermal stress to which the solder bump 130 is subjected, making it difficult for the solder bump 130 to cause cracking and damage to the semiconductor wafer 100 and Electrical connection between the substrates 200. In addition, the first and second conductive stress buffer layers 111 and 211 can also prevent the semiconductor wafer 100 and the substrate 200 themselves from being easily deformed due to thermal stress. I * ------ --Order ------ --- f Please read the notes on the back before filling in this page) This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 8 16065 459320 V. Description of the invention (9) makes the final report The overall appearance of the chip packaged semiconductor device is not prone to deformation. Therefore, the flip-chip soldering structure of the present invention can make the final flip-chip packaged semiconductor device have better quality and reliability. The above descriptions are merely preferred embodiments of the present invention, and are not intended to limit the scope of the essential technical content of the present invention. The essential technical content of the present invention is broadly defined in the scope of the following patent applications. Any technical entity or method completed by another person is the same as or equivalent to the definition of the scope of patent applications below Changes are deemed to be covered by this patent. --------- ^ — I equipment -------- Order --------- (Please read the precautions on the back before filling out this page) Staff of the Intellectual Property Bureau of the Ministry of Economic Affairs The paper size printed by the consumer cooperative is applicable to the Chinese National Standard (CNS) A4 specification (210 χ 297 ------- 16065 9

Claims (1)

經濟部智慧財產局員工消費合作社印製 A8 B8 C8 D8 六、申請專利範圍 L 一種覆晶銲接結構，用以將一覆晶式半導體晶片銲接至 一基板； 此覆晶銲接結構包含： (a) —晶片銲墊’其形成於該半導體晶片之一表面 上； (b) —第一導電性應力緩衝層，其形成於該晶片銲 墊上； (c) 一 UBM結構層，其形成於該第一導電性應力緩 衝層上； (d) —銲塊，其黏結於該UBM結構層上； (e) —基板銲墊，其形成於該基板之一表面上； (f) 一第二導電性應力緩衝層，其形成於該基板銲 墊上；以及 (g) —黏銲性金屬結構層，其形成於該第二導電性 應力緩衝層上，且黏結至該銲塊。 2. 如申請專利範圍第1項所述之覆晶銲接結構，其中該晶 片銲墊為一鋁製銲墊。 3. 如申請專利範圍第1項所述之覆晶銲接結構，其中該第 一及第二導電性應力緩衝層之材質為一導電性高分子 材料。 4. 如申請專利範圍第1項所述之覆晶銲接結構，其中該第 一及第二導電性應力緩衝層係藉由一塗佈製程而形 成。 5. 如申請專利範圍第1項所述之覆晶銲接結構，其中該第 I n 裝 訂 線 (請先M讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家樣準（CNS ) A4说格（2I0X297公釐） 10 16065 A8 B8 C8 D8 459320 六、申請專利範圍 及第一導電性應力緩衝層係藉由一網印製程而形 成。 6.如申請專利範圍第1項所述之覆晶銲接結構，其中該基 板銲墊為一銅製鮮登。 7 如申請專利範圍第1項所述之覆晶銲接結構，其中該黏 銲性金屬結構層為一銅/鎳/金之金屬結構廣。 8.如申請專利範圍第7項所述之覆晶銲接結構，其中該銅 /錄/金之金屬結構層係藉由一電鍍製程而形成。 9- 一種覆晶銲接結構，用以將一覆晶式半導體晶片銲接至 一基板； 此覆晶銲接結構包含： (a) —鋁製銲墊，其形成於該半導體晶片之—表面 上； (b) —第一導電性高分子材料層’其形成於該鋁製 銲墊上； (c) 一 UBM結構層，其形成於該第一導電性高分子 材料層上； (d) —銲塊，其黏結於該UBM結構層上； (e) —銅製銲墊，其形成於該基板之一表面上； (f) 一第二導電性高分子材料層，其形成於該銅製 銲墊上；以及 (g) —銅/鎳/金之金屬結構層’其形成於該第二導電 性高分子材料層上，且黏結至該銲塊。 10.如申請專利範圍第9項所述之復晶銲接結構，其中該第 本紙張又度逋用中國國家揉琅（CNS ) A4規格（210X297公釐） 16065 ί' 4 (請先閲讀背面之注意事項再填寫本頁} -va 經濟部智慧財雇局員工消費合作社印製 11 經濟部智慧財產局員工消費合作社印製 12 A8 Βδ C8 D8 六、申請專利範圍 ^ ^ 一及第一導電性南分子村料層係藉由一塗佈数程而形 成。 11 ·如申請專利範圍第9項所述之覆晶銲接結構，其中該第 一及第二導電性高分子材料層係藉由—網印製程而形 成。 12.如申請專利範圍第9項所述之覆晶銲接結構，其t該鋼 /鎳/金之金屬結構層係藉由一電鍍製程而形成。 1 3 . —種半導體製程，係用來製作一覆晶銲接結構，用以將 一覆晶式半導體晶片銲接至一基板； 此半導體製程包含以下步驟： (υ形成一晶片銲墊於該半導想晶片上； (2) 形成一第一導電性應力緩衝層於該晶片銲墊 上； (3) 形成一 UBM結構層於該第一導電性應力緩衝 層上： (4) 形成一銲塊於該UBM結構層上； (5) 形成一銲墊於該基板上； (6) 形成一第二導電性應力緩衝層於該基板銲墊 上； (7) 形成一黏銲性金羼結構層於該第二導電性應力 緩衝層上；以及 (8) 將該半導體晶片以覆晶方法安置於該基板上； 其中並將該銲塊黏結至該基板上之黏銲性金屬結構 層。 祕…㈣r明家椟率（CNS)A4^( 210X297^) 16065 I - 訂 n [ 線 f請先閎讀背面之注意事項再填寫本頁) ABCD 4593 2 0 六、申請專利範圍 K如申請專利範圍第13項所述之半導體製程，其中該步 驟（1)中所述之晶片銲墊為一鋁製銲墊。 摩 15. 如申請專利範圍第13項所述之半導體製程，其中該步 驟（2)及（6)令所述之第一及第二導電性應力緩衝層，其 材質為一導電性高分子材料。 16. 如申請專利範圍第13項所述之半導體製程，其中於該 步騨（2)及（6)中，該第一及第二導電性應力緩衝層係藉 由一塗佈製程而形成。 17. 如申請專利範圍第13項所述之半導體製程，其中於該 步驟（2)及（6)中，該第一及第二導電性應力緩衝層係藉 由一網印製程而形成。 18. 如申請專利範圍第13項所述之半導體製程，其中該步 驟（5)中所述之基板銲墊為.一銅製銲墊。 19. 如申請專利範圍第13項所述之半導體製程，其中該步 縣（7)中所述之黏銲性金屬結構層為一銅/鎳/金之金属 結構層。 20. 如申請專利範圍第19項所述之半導體製程，其中於該 步驟（7)令，該銅/鎳/金之金屬結構層係藉由一電鍍製程 而形成。 本紙承尺度適用中國國家標準（CNS ) Α4現格（210X297公釐） 13 16065 (請先閲讀背面之注意事項再填寫本頁) 装 •1Τ 經濟部智慧財產局員工消費合作社印製Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A8 B8 C8 D8 6. Scope of patent application L A flip-chip soldering structure for welding a flip-chip semiconductor wafer to a substrate; This flip-chip soldering structure includes: (a) -Wafer pads' formed on a surface of the semiconductor wafer; (b)-a first conductive stress buffer layer formed on the wafer pads; (c) a UBM structure layer formed on the first On a conductive stress buffer layer; (d)-a solder bump, which is bonded to the UBM structure layer; (e)-a substrate pad, which is formed on one surface of the substrate; (f) a second conductive stress A buffer layer formed on the substrate pad; and (g) an adhesive soldering metal structure layer formed on the second conductive stress buffer layer and bonded to the solder bump. 2. The flip-chip welding structure according to item 1 of the patent application scope, wherein the wafer pad is an aluminum pad. 3. The flip-chip soldering structure described in item 1 of the scope of the patent application, wherein the material of the first and second conductive stress buffer layers is a conductive polymer material. 4. The flip-chip soldering structure described in item 1 of the scope of patent application, wherein the first and second conductive stress buffer layers are formed by a coating process. 5. The flip chip welding structure as described in item 1 of the scope of patent application, where the I n gutter (please read the notes on the back before filling this page) This paper size applies to China National Standard (CNS) A4 Grid (2I0X297 mm) 10 16065 A8 B8 C8 D8 459320 6. The scope of patent application and the first conductive stress buffer layer are formed by a screen printing process. 6. The flip-chip welding structure according to item 1 of the scope of the patent application, wherein the substrate pad is made of copper. 7 The flip-chip soldering structure described in item 1 of the scope of patent application, wherein the adhesive metal structure layer is a copper / nickel / gold metal structure. 8. The flip-chip soldering structure according to item 7 of the scope of the patent application, wherein the copper / metal / gold metal structure layer is formed by an electroplating process. 9- A flip-chip soldering structure for soldering a flip-chip semiconductor wafer to a substrate; the flip-chip soldering structure includes: (a) an aluminum bonding pad formed on the surface of the semiconductor wafer; ( b) a first conductive polymer material layer 'formed on the aluminum bonding pad; (c) a UBM structure layer formed on the first conductive polymer material layer; (d) a solder bump, It is bonded to the UBM structure layer; (e) a copper pad formed on one surface of the substrate; (f) a second conductive polymer material layer formed on the copper pad; and ( g)-a copper / nickel / gold metal structure layer 'formed on the second conductive polymer material layer and bonded to the solder bump. 10. The compound crystal welding structure as described in item 9 of the scope of the patent application, wherein the first paper has been re-used in China National Standard (CNS) A4 (210X297 mm) 16065 ί '4 (Please read the Note for refilling this page} -va Printed by the Employees 'Cooperatives of the Ministry of Economic Affairs, Smart Finance and Employment Bureau 11 Printed by the Employees' Cooperatives of the Ministry of Economic Affairs, Intellectual Property Bureau, 12 A8 Βδ C8 D8 VI. Scope of Patent Application ^ ^ First and first conductivity The molecular village material layer is formed by a coating process. 11 · The flip-chip welding structure described in item 9 of the scope of the patent application, wherein the first and second conductive polymer material layers are formed by- It is formed by a printing process. 12. The flip-chip soldering structure described in item 9 of the scope of the patent application, wherein the metal structure layer of steel / nickel / gold is formed by an electroplating process. 1 3. — A semiconductor process Is used to make a flip-chip soldering structure for soldering a flip-chip semiconductor wafer to a substrate; this semiconductor process includes the following steps: (υ) forming a wafer pad on the semiconductor wafer; (2) Form a first guide (3) forming a UBM structure layer on the first conductive stress buffer layer: (4) forming a solder bump on the UBM structure layer; (5) forming a solder pad On the substrate; (6) forming a second conductive stress buffer layer on the substrate pad; (7) forming an adhesive soldering metal structure layer on the second conductive stress buffer layer; and (8) The semiconductor wafer is placed on the substrate by a flip-chip method; wherein the solder bump is bonded to an adhesive soldering metal structure layer on the substrate. ㈣ ... 明明 家 椟 率 (CNS) A4 ^ (210X297 ^) 16065 I-Order n [Please read the precautions on the back of the line f before filling out this page) ABCD 4593 2 0 VI. Patent application scope K The semiconductor process as described in item 13 of the patent application scope, where step (1) The wafer bonding pad is an aluminum bonding pad. 15. The semiconductor process according to item 13 of the scope of patent application, wherein the steps (2) and (6) make the first and second conductivity described. The stress buffer layer is made of a conductive polymer material. The semiconductor process according to item 13 of the scope, wherein in the steps (2) and (6), the first and second conductive stress buffer layers are formed by a coating process. 17. If applying for a patent The semiconductor process according to the scope item 13, wherein in the steps (2) and (6), the first and second conductive stress buffer layers are formed by a screen printing process. The semiconductor process according to item 13, wherein the substrate pad described in step (5) is a copper pad. 19. The semiconductor process according to item 13 of the scope of patent application, wherein the adhesive metal structure layer described in step (7) is a copper / nickel / gold metal structure layer. 20. The semiconductor process as described in item 19 of the scope of patent application, wherein in step (7), the copper / nickel / gold metal structure layer is formed by an electroplating process. This paper bears the standard of China National Standards (CNS) A4 (210X297 mm) 13 16065 (Please read the precautions on the back before filling out this page) Packing • Printed by the Intellectual Property Bureau Employees Cooperative of the Ministry of Economic Affairs
TW089117749A 2000-08-31 2000-08-31 Flip-chip soldering structure with stress buffering effect TW459320B (en)

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