TW456018B

TW456018B - Method for preventing current leakage of embedded memory device

Info

Publication number: TW456018B
Application number: TW89122730A
Authority: TW
Inventors: Ching-Kuen Huang; Jr-Chang Chen; Shian-Jr Peng; Ping-Shiang Chin
Original assignee: Taiwan Semiconductor Mfg
Priority date: 2000-10-27
Filing date: 2000-10-27
Publication date: 2001-09-21

Abstract

The present invention discloses a manufacturing method for embedded memory device in the logic device processing, which includes the following steps: first, defining a gate structure and a conductive plate on the semiconductor substrate; defining the source area and the drain area on the semiconductor substrate on both sides of the gate structure; in which the drain area is located between the gate structure and the conductive plate; next, forming a passivation oxide layer on the surface of the drain area and extending in both sides to the side of part of the gate structure and to the side of part of the conductive plate; and, forming silicide in the exposed source area, the gate structure and the external surface of the conductive plate; then, depositing the dielectric layer on the semiconductor substrate for covering the silicide and the passivation oxide layer; and, forming the conductive plugs in the dielectric to electrically connect to the source area.

Description

4 1 80 18 五、發明說明（1) 發明領域：本發明與一種半導體製程有關，特別是與一種在邏輯元件（logic device)相關製程中’防止内嵌式記憶體元件 (embedded memory)的源/汲極區域發生漏電流（current leakage)之方法。發明背景：隨著半導體工業持續的進展，在超大型積體電路 (ULSI)的開發與設計中，為了符合高密度積體電路之設計趨勢，各式元件之尺寸皆降至次微米以下。並且由於元件不斷的縮小’也導致在進行相關半導體製程時，往往遭遇了前所未有之難題’且製程複雜程度亦不斷提高。例如，為了進一步提昇積體電路的操作性能，往往會在尺寸極小的空間中，製作數以萬計的AND閘、0R閘、或NAND閘…等的邏輯元件，以執行所需的邏輯功能與運算。但是當這歧邏輯元件的尺寸大幅縮小時，如何藉著微影製程將其定義於半導體底材上，便成為極重要的課題。一般而言，在邏輯元件的相關製程中，往往會同時製作内嵌式記憶體（Embedded memory) ’以提供邏輯電路操作所需。典型的内嵌式記憶體元件其製作步驟，如第一圖所示。先在半導體底材1 〇上定義出多晶矽閘極丨2與多晶石夕4 1 80 18 V. Description of the invention (1) Field of the invention: The present invention relates to a semiconductor process, and in particular, to a source that prevents embedded memory in a logic device-related process. / Drain region current leakage (current leakage) method. Background of the Invention: With the continuous progress of the semiconductor industry, in the development and design of ultra large integrated circuits (ULSI), in order to meet the design trend of high density integrated circuits, the size of various components has been reduced to sub-micron. And because of the continuous shrinking of the components ', the related semiconductor process often encounters unprecedented challenges' and the complexity of the process is also increasing. For example, in order to further improve the operating performance of integrated circuits, tens of thousands of logic gates such as AND gates, OR gates, or NAND gates are often made in a very small space to perform the required logic functions and Operation. However, when the size of this discrete logic device is greatly reduced, how to define it on a semiconductor substrate through the lithography process becomes a very important issue. Generally speaking, in the related process of logic elements, embedded memory is often manufactured at the same time to provide logic circuit operation requirements. The manufacturing steps of a typical embedded memory device are shown in the first figure. First define the polycrystalline silicon gate on the semiconductor substrate 10 and polycrystalline silicon

第4頁、發明說明（2) 平板1 4 »其中’多晶矽閘極i 2與多晶矽平板丨4，分別藉著閑極氧化層16與電容介電層18，而貼附於半導體底材1〇上並且’在多晶梦閘極1 2的側壁上具有側壁間隙壁，以提供多晶矽閘極1 2所需的絕緣效果。在使用離子植入程序，定義出位於多晶矽閘極丨2兩側的源極區域20與汲極區域22之後，可再沉積金屬層24於半導體底材1 0、多晶矽閘極1 2、與多晶矽平板1 4的外表面，以便在熱回火程序後，可形成金屬矽化層2 6於多晶矽閘極 12、多晶矽平板η、源極區域2〇、與汲極區域22上表面，如第二圖所示。然後，移除未參與矽化反應的金屬後，且形成介電層28於半導體底材10上方，並使用微影製程，可定義導電插塞30於此介電層28中，且連結至源極區域20 » 如此一來’對多晶矽平板14而言，由於其與下方的半導體底材1 0間’會以電容介電層1 8隔開。是以可將多晶矽平板14視為頂部電極（top plate)，而將下方的半導體底材10視為底部電極（storage node)，而構成一個電容器結構。此底部電極並直接連接至汲極區域22，而可藉著多晶矽閘極12來對電容器結構進行操作。另外，可藉著導電插塞30，使電晶體的源極區域20與位元線產生電性連結，而進行資料的傳遞° 但值得注意的是，製作於汲極區域22表面的矽化金屬Page 4 and description of the invention (2) Flat plate 1 4 »Among them, the polycrystalline silicon gate i 2 and the polycrystalline silicon plate 丨 4 are attached to the semiconductor substrate 1 through the free oxide layer 16 and the capacitor dielectric layer 18, respectively. There is a sidewall spacer on the sidewall of the polycrystalline silicon gate 12 to provide the insulation effect required for the polycrystalline silicon gate 12. After using the ion implantation procedure to define the source region 20 and the drain region 22 located on both sides of the polycrystalline silicon gate 丨 2, a metal layer 24 can be deposited on the semiconductor substrate 10, the polycrystalline silicon gate 12, and the polycrystalline silicon The outer surface of the plate 14 so that after the thermal tempering process, a metal silicide layer 26 can be formed on the polysilicon gate 12, the polysilicon plate η, the source region 20, and the upper surface of the drain region 22, as shown in the second figure. As shown. Then, after the metal not participating in the silicidation reaction is removed, a dielectric layer 28 is formed on the semiconductor substrate 10, and a lithography process is used to define a conductive plug 30 in the dielectric layer 28 and connected to the source electrode. Region 20 »In this way, 'for the polycrystalline silicon flat plate 14, since it is separated from the semiconductor substrate 10 below' by a capacitive dielectric layer 18. The polycrystalline silicon flat plate 14 can be regarded as a top electrode, and the lower semiconductor substrate 10 can be regarded as a storage node, thereby forming a capacitor structure. This bottom electrode is directly connected to the drain region 22, and the capacitor structure can be operated by the polysilicon gate 12. In addition, the conductive plug 30 can be used to electrically connect the source region 20 of the transistor and the bit line to transmit data. However, it is worth noting that the silicided metal fabricated on the surface of the drain region 22

五、發明說明（3) 請層26 ’往往容易與作為電容器頂部電極的多晶矽平板14 間，產生接面漏電流，而造成所儲存資料流失等缺陷參照第三圖，此圖顯示了由MOSYS公司所生產，尺寸為〇· 25 #111的内嵌式記憶體元件1T_SRAM其俯視圖。其t，在長條狀的多晶矽閘極1 2兩側，分別定義了源極區域2〇與汲極區域22。在源極區域20的上方，並定義了導電插塞3〇，以連接至位元線。至於所定義的多晶矽平板丨4，則與汲極區域2 2相鄰。要特別說明的是，在定義上述的各式元件之前，往往會先在半導體底材10上製作隔離結構，以便定義出曝露出部份的半導體底材10上表面，作為製作元件的主動區域4〇使用。然後，再依照第一圖與第二圖的步驟，逐一的形成所需的各式元件。是以，對半導體底材10而言，在進行;金屬矽化程序時，便會在曝露的主動區域40表面，形成矽化金屬層26 ^其中，形成於汲極區域22表面的矽化金屬層 26，便由於過於貼近多晶矽平板14，而容易導致發生面漏電流之問題。發明目的及概述：製作内本發明之目的在提供一種在邏輯元件製程嵌式記憶體之方法。本發明之再一目的在提供一種防止内嵌式記憶體元件五、發明說明（4) 其汲極區域發生漏電流在本發明中揭露了式記憶體元件的方法。上，且形成導電層於絕緣膜層，以定義閘極結後，定義源極區域與；:及材中。其中，汲極區域後，形成防護氧化層於份閘極結構側邊 '以及屬層於曝露的源極區域後，沉積介電層於半導護氧化層。並且，形成結至源極區域。之方法。一種在邏首先，形緣膜層上構與導電極區域於位於閘極汲極區域部份導電、閘極結體底材上導電插塞輯元件製程成絕緣膜層。接著，蝕平板於半導閘極結構兩結構與導電表面，且向平板侧邊。構、導電平，以覆蓋矽於介電層間中，製於半導刻導電體底材側的半平板間兩側延再形成板外表化金屬，以便作内嵌體底材層與絕上0 铁〇、、導體底。隨伸至部 $夕化金面。然層與防電性連發明詳細說明：本發明提供一種在邏輯製程中，製作内嵌式記憶體元件之方法。藉著形成防護氧化層於汲極區域表面，可以防止在後續的製程中’形成矽化金屬於汲極區域上。如此一來’可以有效的防止汲極區域與電容器接面間發生漏電流。有關本發明之詳細說明如下所述。請參照第四圖，首先提供一半導體底材50以便用來沉積所需的膜層。其中，此半導體底材5〇可使用具<1〇〇>晶國 ΗV. Description of the invention (3) Please layer 26 'is often easy to produce contact leakage current between the polycrystalline silicon flat plate 14 serving as the top electrode of the capacitor, resulting in the loss of stored data and other defects. Refer to the third figure. The top view of the produced 1T_SRAM, an embedded memory device with a size of 0.25 # 111. At t, a source region 20 and a drain region 22 are respectively defined on both sides of the strip-shaped polysilicon gate 12. Above the source region 20, a conductive plug 30 is defined to connect to the bit line. As for the defined polycrystalline silicon plate 4, it is adjacent to the drain region 2 2. It should be particularly noted that, before defining the above-mentioned various components, an isolation structure is often first fabricated on the semiconductor substrate 10 in order to define an exposed portion of the upper surface of the semiconductor substrate 10 as an active region 4 for manufacturing the component. 〇Use. Then, follow the steps in the first and second figures to form the required components one by one. Therefore, for the semiconductor substrate 10, during the metal silicidation process, a silicided metal layer 26 is formed on the surface of the exposed active region 40. Among them, the silicided metal layer 26 formed on the surface of the drain region 22, Because it is too close to the polycrystalline silicon flat plate 14, the problem of surface leakage current easily occurs. Purpose and Summary of the Invention: The purpose of the present invention is to provide a method for manufacturing embedded memory in a logic device. Another object of the present invention is to provide an embedded memory device. V. Description of the Invention (4) Leakage current in the drain region of the invention The method of the memory device is disclosed in the present invention. And a conductive layer is formed on the insulating film layer to define the gate junction, and then define the source region and; in the material. After the drain region, a protective oxide layer is formed on the side of the gate structure, and a metal layer is deposited on the exposed source region, and then a dielectric layer is deposited on the semiconductor protective oxide layer. In addition, a junction-to-source region is formed. Method. First, in the logic first, the structure of the edge film layer and the conductive electrode region are partially conductive on the gate drain region and the gate junction substrate is made of conductive plugs. Then, the etched plate is placed on the two structures of the semiconductive gate structure and the conductive surface, and faces the plate side. The structure and conductivity are flat, so as to cover the silicon in the dielectric layer. The two sides of the half-plate between the semiconductive substrate and the conductive substrate are extended to form the surface metal of the board. Iron 0 ,, the bottom of the conductor. With the extension to the $ 夕化金面. However, the layer is connected to the electrical resistance. Detailed description of the invention: The present invention provides a method for manufacturing an embedded memory element in a logic process. By forming a protective oxide layer on the surface of the drain region, it is possible to prevent the formation of silicided metal on the drain region in subsequent processes. In this way, the leakage current between the drain region and the capacitor junction can be effectively prevented. A detailed description of the present invention is as follows. Referring to the fourth figure, a semiconductor substrate 50 is first provided for depositing a desired film layer. Among them, this semiconductor substrate 50 can make appliances < 1〇〇 > crystal country Η

45601B 五、發明說明（5) 向之單晶石夕來加以構成。一般而言’其它種類之半導體材料’諸如砷化鎵（gallium arsenide)、鍺（germanium)或是位於絕緣層上之石夕底材（silicon on insulator, SOI) 亦可應用作為此處的半導體底材50使用。另外，由於晶圓表面的特性對本發明而言’並不會造成特別的影晌，是以其晶向亦可選擇<110〉或<111〉。接著’可形成絕緣膜層52於此半導體底材5〇上表面，以便根據需求作為閘極介電層或電容介電層使用。一般而言’可使用氧化材料來構成此絕緣膜層5 2。例如，可在溫度約700至1100 °C且充滿氧氣的環境中，形成絕緣膜層 52。或著’也可以合適的氧化物其化學組合及程序，諸如化學氣相沈積法，來形成絕緣膜層5 2。然後，可沉積導電層54於此絕緣膜層52表面。在較佳實施例中，可使用多晶矽材料來構成此導電層54。並且，藉著使用低壓化學氣相沈積法（Lpc VD)，將矽曱烷 (si lane, SiH4)加熱解離’可沉積所需的多晶矽層。其中’沉積的溫度約在600至650 X：，且壓力约在0.3至0.6托耳之間。另外’為了降低所形成導電層5 4的電阻值，亦可在多晶石夕沉積反應中進行同步摻雜^^心“ doping)程序’或是在沉積程序完成後，再將摻質植入多晶矽材料中。45601B V. Description of the invention (5) It is composed of single crystal eve. Generally speaking, 'other kinds of semiconductor materials' such as gallium arsenide, germanium, or silicon on insulator (SOI) on the insulating layer can also be used as the semiconductor substrate here.材 50 用。 Material 50 is used. In addition, since the characteristics of the wafer surface do not cause a special influence on the present invention, the crystal orientation can also be selected as < 110> or < 111>. Next, an insulating film layer 52 may be formed on the upper surface of the semiconductor substrate 50 so as to be used as a gate dielectric layer or a capacitor dielectric layer according to requirements. Generally, an insulating material is used to constitute this insulating film layer 52. For example, the insulating film layer 52 may be formed in an environment filled with oxygen at a temperature of about 700 to 1100 ° C. Alternatively, the insulating film layer 52 can be formed by a suitable combination of oxide and its chemical combination and procedures, such as chemical vapor deposition. Then, a conductive layer 54 can be deposited on the surface of the insulating film layer 52. In a preferred embodiment, the conductive layer 54 may be formed using a polycrystalline silicon material. In addition, by using low pressure chemical vapor deposition (Lpc VD), the silicon polysiloxane layer (Si lane, SiH4) is thermally dissociated 'to deposit a desired polycrystalline silicon layer. The temperature of the 'deposition' is about 600 to 650 X :, and the pressure is about 0.3 to 0.6 Torr. In addition, 'in order to reduce the resistance value of the formed conductive layer 54, a simultaneous doping process can be performed in the polycrystalline stone deposition reaction' or after the deposition process is completed, dopants are implanted Polycrystalline silicon material.

ι隨後，再形成光阻層56於導電層54上表面，以作為蝕刻^幂，並依序對導電層54與絕緣膜層5 2進行蝕刻程序，以定義閉極結構58與導電平板60於半導體底材5〇上，如第五圖所示。其中，位於閘極結構58下表面的部份絕緣膜層 52可作為閘極介電層使用。至於，位在導電平板60下表^ 的部份絕緣膜層52，則作為電容介電層使用。請參照第六圖，在製作側壁間隙壁62於閘極結構58的侧壁上後，可對半導體底材50進行離子佈植程序，以便在閘極結構58兩側’定義出源極區域64與沒極區域μ。一般而言，可以藉著化學氣相沈積法，先形成—氮化矽層於閘極結構58表面上。然後，再進行非均向性蝕刻’以移除部份氮化石夕層’並在閘極結構5 8的側壁上形成側壁間隙壁 62。再利用閘極結構5 8作為罩幂’對半導體底材5〇進行離子佈植，可形成源極區域64與汲極區域66 ^其中，汲極區域66位於閘極結構58與導電平板6〇間的半導體底材中，至於源極區域64則位於閘_.極結構58另一侧的半導體底材5〇中。隨後，可形成一防護氧化層（resist protect oxide; RPO)於曝露的汲極區域66表面，並分別向兩側沿伸至閘極結構5 8的部份侧壁間隙壁6 2表面、以及部份導電平板6 〇的側邊表面。並且’沉積金屬層70於半導體底材5〇上，以覆蓋閘極結構58、導電平板60、防護氡化層68與源極區域64Then, a photoresist layer 56 is formed on the upper surface of the conductive layer 54 as an etching power, and an etching process is performed on the conductive layer 54 and the insulating film layer 52 in order to define the closed-electrode structure 58 and the conductive plate 60. On the semiconductor substrate 50, as shown in the fifth figure. Among them, a part of the insulating film layer 52 on the lower surface of the gate structure 58 can be used as a gate dielectric layer. As for the part of the insulating film layer 52 located on the lower surface of the conductive plate 60, it is used as a capacitor dielectric layer. Please refer to the sixth figure. After the sidewall spacer 62 is fabricated on the sidewall of the gate structure 58, an ion implantation process may be performed on the semiconductor substrate 50 so as to define a source region 64 on both sides of the gate structure 58. And immutable area μ. Generally, a silicon nitride layer can be formed first on the surface of the gate structure 58 by a chemical vapor deposition method. Then, anisotropic etching is performed to remove a part of the nitride nitride layer and a sidewall spacer 62 is formed on the sidewall of the gate structure 58. The gate structure 58 is used as a mask power to perform ion implantation on the semiconductor substrate 50, so that a source region 64 and a drain region 66 can be formed. Among them, the drain region 66 is located at the gate structure 58 and the conductive plate 6. Among the semiconductor substrates, the source region 64 is located in the semiconductor substrate 50 on the other side of the gate electrode structure 58. Subsequently, a protective protect oxide (RPO) layer may be formed on the surface of the exposed drain region 66, and may extend to both sides of the surface of the part of the side wall spacer 62 of the gate structure 58 and the part Part of the side surface of the conductive flat plate 60. And ’a metal layer 70 is deposited on the semiconductor substrate 50 to cover the gate structure 58, the conductive plate 60, the protective layer 68 and the source region 64.

表面序，使用。一般而言，可藉由濺鍍等熟知的物理氣相沉積程形成耐熔性金屬材料或重金屬材料，來作為金屬層70 。例如’可使用Ti、pt、co、w、Ni等金屬。請參照第七圖，此圖顯示應用本發明方法，於在 = SYS公司所生產，尺寸為〇25从111的内嵌式記憶體元件 SRAM上之情形。其中，在進行邏輯製程時，往往會先在半導體底材50上方，定義絕緣隔離結構，以曝露部份半導體底=50的上表面，用來作為定義元件的主動區域72使用。接著，便可依照上述步驟，在半導體底材5〇上，定義v 長條狀的閘極結構5 8與導電平板6 〇，且定義出位於閘極結構58兩側的源極區域64與汲極區域66。然後，形成防護氧化層68於汲極區域66上。其中，為了增加遮蔽矽材料的效果’所定義的防護氧化層，會完全覆蓋住位於長條狀導電閘極58與導電平板6〇間的主動區域72 ’以避免曝露的半導體底材5〇表面，在後續的金屬石夕化程序中發生反應。是以，如圖中所示，沉積的防護氧化層68，會沿著閘極結構58與導電平板60間的主動區域邊緣’完全將主動區域包覆住（第七圖中虚線區域）。並且，部份的防護氧化層6 8 ’亦會延伸至汲極區域6 6邊緣的閘極結構58與導電平板60的邊緣上β 請參照第八圖，接著可進行一熱回火程序，以便半導Surface order, use. In general, the metal layer 70 can be formed by forming a refractory metal material or a heavy metal material by a well-known physical vapor deposition process such as sputtering. For example, a metal such as Ti, pt, co, w, and Ni can be used. Please refer to the seventh figure, which shows the application of the method of the present invention on an embedded memory device SRAM produced by SYS Corporation with a size of 025 from 111. Among them, when performing a logic process, an insulating isolation structure is often defined above the semiconductor substrate 50 to expose a part of the upper surface of the semiconductor substrate = 50, which is used as the active area 72 for defining the component. Then, in accordance with the above steps, on the semiconductor substrate 50, a v-shaped gate structure 58 and a conductive plate 60 can be defined, and source regions 64 and drains located on both sides of the gate structure 58 can be defined.极区 66。 Polar region 66. Then, a protective oxide layer 68 is formed on the drain region 66. Among them, in order to increase the shielding effect of the silicon material, as defined by the protective oxide layer, it will completely cover the active area 72 between the long conductive gate 58 and the conductive flat plate 60 to avoid the exposed surface of the semiconductor substrate 50. , The reaction occurs in the subsequent metallization process. Therefore, as shown in the figure, the deposited protective oxide layer 68 completely covers the active area along the active area edge 'between the gate structure 58 and the conductive plate 60 (the dotted area in the seventh figure). In addition, part of the protective oxide layer 6 8 ′ will also extend to the edge of the gate structure 58 on the edge of the drain region 66 and on the edge of the conductive plate 60. Please refer to the eighth figure, and then perform a thermal tempering procedure so that Semiconducting

第10頁 4 5 6 CM 8 五、發明說明（8) 體底材50上方曝露的矽材料，與金屬層70發生矽化反應，而形成矽化金屬層74。其中’所形成的矽化金屬層74會覆蓋於部份導電平板6 0、部份閘極結構5 8、與源極區域6 4表面°至於，在汲極區域6 6上表面’由於有防護氧化層68的遮覆，是以不會產生矽化金屬。隨後，將位於半導體底材 50上，未發生矽化反應的殘餘金屬層7〇移除，而形成第八圖中的截面結構。一般而言’可在溫度約350至700 t，且充滿N2的環境中，進行一快速熱回火（r τ A)，以使該对溶性金屬與多晶矽閘極結構58、以及半導體底材5〇發生反應’並且在這些部份上形成矽化金屬。接著’可沉積介電層76於矽化金屬層74、側壁間隙壁、與防護氧化層上表面，以覆蓋下方的閘極結構μ、導電平板60、源極區域64、汲極區域66。其中，可利用氧化物材料’來構成此處的介電層76。隨後，藉著進行微影製程’可定義接觸孔於此介電層76中，以曝露出部份源極區域64的上表面。然後，再形成導電插塞78於此接觸孔中’以便與源極區域64產生電性連結。其中，可以藉著熟 ^的技術，如物理氣相沈積法（PVD)、濺鍍法等類似製、程’先形成導電層於介電層76上，且填充於接觸孔内。再 $用化學機械研磨程序，對此導電層進行研磨，直至抵達 ^電層76上表面為止。如此，可以得到所需的導電插塞常用的導電材料，包括了紹、鈥、鎢、銅、金、麵、合金或多晶矽等等。或著，也可使用化學氣相沉積法Page 10 4 5 6 CM 8 V. Description of the invention (8) The silicon material exposed above the body substrate 50 undergoes a silicidation reaction with the metal layer 70 to form a silicided metal layer 74. Among them, the formed silicided metal layer 74 will cover part of the conductive plate 60, part of the gate structure 58, and the surface of the source region 64. As for the upper surface of the drain region 66, there is a protective oxidation The layer 68 is masked so as not to generate silicide metal. Subsequently, the residual metal layer 70 on the semiconductor substrate 50, which has not undergone a silicidation reaction, is removed to form a cross-sectional structure in the eighth figure. Generally speaking, a rapid thermal tempering (r τ A) can be performed in an environment full of N2 at a temperature of about 350 to 700 t to make the pair of soluble metal and polycrystalline silicon gate structure 58 and the semiconductor substrate 5 〇Reaction 'and formation of silicided metal on these parts. Next, a dielectric layer 76 may be deposited on the silicide metal layer 74, the sidewall spacer, and the upper surface of the protective oxide layer to cover the gate structure μ, the conductive plate 60, the source region 64, and the drain region 66 below. Among them, an oxide material 'can be used to form the dielectric layer 76 here. Subsequently, by performing a photolithography process, a contact hole can be defined in the dielectric layer 76 to expose a portion of the upper surface of the source region 64. Then, a conductive plug 78 is formed in this contact hole 'so as to be electrically connected with the source region 64. Among them, a conductive layer can be formed on the dielectric layer 76 by filling in a contact hole by a known process such as physical vapor deposition (PVD), sputtering, or the like. Then, the conductive layer is polished by a chemical mechanical polishing procedure until it reaches the upper surface of the electric layer 76. In this way, the required conductive materials commonly used in conductive plugs can be obtained, including Shao, ', tungsten, copper, gold, surface, alloy or polycrystalline silicon and so on. Alternatively, chemical vapor deposition can also be used

45 6〇 t g 五、發明說明（9) (CVD)在溫度約400至500° C的環境下，以WF6與H2作為反應氣體形成鎢金屬層來定義導電插塞78。如此一來，由於在沒極區域66的表面，並未形成石夕化金屬層，並且在與此汲極區域66相鄰的部份導電平板6〇表面上’亦未形成矽化金屬層。因此，可有效的防止汲極區域66與導電平板60發生接面漏電的情形《請參照第十圖，此圖顯示利用本發明方法，所製作内嵌式記憶體元件其良率改善的情形。其中，批次A的邏輯產品利用了本發明方法’形成防護氧化層來降低没極區域發生接面漏電流，至於批次B則是利用傳統方法製作的内嵌式記憶體元件。由圖中可知’未使用防護氧化層的批次B，在所進行的兩次測試中，僅有約4. 8 %與3. 4 %的原始（n a t u r e)良率。即使，在對所製作的内嵌式記憶體元件進行修復後，亦祇能提昇良率至約30. 3%與26. 6%。相對的，使用防護氧化層製作的批次A則具有約70. 3%與63. 2%的良率，且在進行修復後，可提昇良率至83. 0%與74. 2%。顯然，藉著利用本發明方法，確可有效降低汲極區域漏電流發生。本發明雖以一較佳實例闡明如上，然其並非用以限定本發明精神與發明實體，僅止於此一實施例爾。因此，在不脫離本發明之精神與範圍内所作之修改，均應包含在下述之申請專利範圍内。45 6〇 tg 5. Description of the invention (9) (CVD) The conductive plug 78 is defined by forming a tungsten metal layer using WF6 and H2 as a reaction gas in an environment at a temperature of about 400 to 500 ° C. As a result, since the petrified metal layer is not formed on the surface of the electrodeless region 66, and the silicon silicided metal layer is not formed on the surface of the conductive plate 60 adjacent to the drain region 66. Therefore, it is possible to effectively prevent the leakage of the junction area between the drain region 66 and the conductive plate 60. Please refer to the tenth figure. This figure shows that the yield of the embedded memory device is improved by using the method of the present invention. Among them, the logic product of batch A uses the method of the present invention to form a protective oxide layer to reduce the junction leakage current in the non-polar region. As for the batch B, the embedded memory device is manufactured by the traditional method. From the figure, it can be seen that the batch B without the protective oxide layer has only about 4.8% and 3.4% original (n a t u r e) yields in the two tests performed. Even after repairing the fabricated embedded memory device, the yield can only be improved to about 30.3% and 26.6%. In contrast, batch A made with a protective oxide layer has a yield of about 70.3% and 63.2%, and after repair, the yield can be improved to 83.0% and 74.2%. Obviously, by using the method of the present invention, the leakage current in the drain region can be effectively reduced. Although the present invention is explained as above with a preferred example, it is not intended to limit the spirit and the inventive substance of the present invention, but only to this embodiment. Therefore, modifications made without departing from the spirit and scope of the present invention should be included in the scope of patent application described below.

第12頁 5 6 Ο 1 8 圖式簡單綱 " ____ 藉由以下詳細之描述結合所附圖示，將可輕易了上述内容及此項發明之諸多優點，其中：：解第一圖為半導體底材戴面圖，顯示根據像統製程電晶體元件與平行板電容器於半導體底材上之步驟；義第二圖為半導體底材截面圖，顯示根據傳統製程矽化金屬層於曝露的矽材料上之步轉；作第三圖為半導體底材俯視圖，顯示使用傳統製裎的MOSYS 1T-SRAM元件其相關結構； 1乍第四圖為半導體底材截面圖，顯示使用本發明方法形成絕緣膜層與多晶石夕層於半導體底材上之步驟；第五圖為半導體底材截面圖，顯示定義閘極結構與導電平板於半導體底材上之步驟；第六圖為半導體底材載面圖，顯示根據本發明形成防護氧化層於汲極區域表面之步驟；第七圖為半導體底材俯視圖，顯示根據本發明形成防護層於MOSYS 1T-SRAM元件上，所覆蓋之區域；第八圖為半導體底材截面圖，顯示根據本發明形成矽化金屬於曝露的矽材料之步驟；第九圖為半導體底材截面圖，顯示形成導電插塞於半導體底材上之步驟；及第十圖為數據圖，顯示使用本發明万法與傳統方法時，產品間良率的變化情形。Page 12 5 6 Ο 1 8 Schematic Outline " ____ By the following detailed description combined with the attached drawings, the above content and many advantages of this invention can be easily made, of which:: The first figure is a semiconductor Substrate wearing view, showing the steps of the transistor system and the parallel plate capacitor on the semiconductor substrate according to the image processing process; the second figure is a cross-sectional view of the semiconductor substrate, showing the silicided metal layer on the exposed silicon material according to the traditional process The third step is a top view of a semiconductor substrate, showing the related structure of a conventionally made MOSYS 1T-SRAM device. The first and fourth views are cross-sectional views of a semiconductor substrate, showing the use of the method of the present invention to form an insulating film layer. And polycrystalline stone layer on the semiconductor substrate; the fifth figure is a cross-sectional view of the semiconductor substrate, showing the steps to define the gate structure and conductive plate on the semiconductor substrate; the sixth figure is a semiconductor substrate surface view , Which shows the step of forming a protective oxide layer on the surface of the drain region according to the present invention; FIG. 7 is a plan view of a semiconductor substrate, showing the formation of a protective layer on MOSYS 1T-SRAM according to the present invention The area covered by the component; Figure 8 is a cross-sectional view of a semiconductor substrate, showing the steps for forming a silicided metal on an exposed silicon material according to the present invention; Figure 9 is a cross-sectional view of a semiconductor substrate, showing the formation of a conductive plug on a semiconductor The steps on the substrate; and the tenth figure is a data chart showing the change of the yield rate between products when the method of the present invention and the traditional method are used.

第13頁Page 13

Claims

456〇 1 8456〇 1 8

六、申請專利範圍内嵌式記憶體元件 1，一種在邏輯元件製程中，製作之方法’該方法至少包括下列步驟：形成絕緣膜層於半導體底材上，以定義閘極結構與導電形成導電層於該絕緣膜層上；蝕刻該導電層與該絕緣膜層，平板於該半導體底材上；定義源極區域與汲極區域於該閘極結構兩侧的該半導體底材中，其中該汲極區域位於該閘極結構盘芎導電平間； ' 开v成防護氧化層（resist protect oxide; RPO)於該汲極區域表面，且向兩側延伸至部份該閘極結構側邊、以及部份該導電平板側邊；形成矽化金屬層於曝露的該源極區域、該閘極結構、該導電平板外表面；沉積介電層於該半導想底材上’以覆蓋該碎化金屬層與該防護氧化層；且形成導電插塞於該介電層間，以便電性連結至該源極區域。 2.如申請專利範圍第i項之方法’其中上述絕緣膜層是由氧化材料所構成。 3.如申請專利範圍第1項之方法，其中上述導電詹是由多晶妙材料所構成。6. In-memory embedded memory element 1 in the scope of patent application, a method of manufacturing in the process of logic element 'The method includes at least the following steps: forming an insulating film layer on a semiconductor substrate to define a gate structure and conducting electricity Layer on the insulating film layer; etching the conductive layer and the insulating film layer, and flattening on the semiconductor substrate; defining a source region and a drain region in the semiconductor substrate on both sides of the gate structure, wherein the The drain region is located in the conductive structure of the gate structure plate; 'resist protective oxide (RPO) is formed on the surface of the drain region, and extends to both sides to part of the gate structure side, and Part of the side of the conductive plate; forming a silicided metal layer on the exposed source region, the gate structure, and the outer surface of the conductive plate; depositing a dielectric layer on the semiconducting substrate to cover the shattered metal Layer and the protective oxide layer; and a conductive plug is formed between the dielectric layer so as to be electrically connected to the source region. 2. The method according to item i of the scope of patent application, wherein said insulating film layer is made of an oxidizing material. 3. The method according to item 1 of the scope of patent application, wherein the conductive substrate is composed of a polycrystalline material.

第14頁 456〇 ] 8 六、申請專利範圍 4. 如申請專利範圍第丨項之方法，其中在定義結構後，並形成侧壁間隙壁於該閘極結構兩側壁上該側壁間隙壁是由氮化矽材料所構成。 5. 如申請專利範圍第1項之方法，其中上述之化層，用以覆蓋住該閘極結構與該導電平板間導體底材。 6. 如申請專利範圍第1項之方法，其中上述導是由多晶矽材料所構成。 7. 如申請專利範圍第1項之方法，其中上述導可作為電容器頂部電極使用，而位於該導電平板下份該半導體底衬則可作為電容器底部電極使用。 8_ —種在邏輯元件製程中，製作内嵌式記憶骨之方法，該方法至少包括下列步驟· 形成閘極結構與導電平板於半導體底材上；形成側壁間隙壁於該閘極結構的側壁上；，定義源極區域與汲極區域於該閘極結構兩側的體底材中，其中該汲極區域位於該閘極結構與該導該閘極，其中防護氧的該半電插塞電平板方之部元件半導平板形成防護氧化層（resis Protect oxide; RP〇)於該 456〇 t 8 六、申請專利範圍閘極結構與該導電平板間，曝露的該半導體底材上表面；沉積金屬層於該源極區域、該閘極結構、該防護氧化層、該導電平板外表面；進行熱回火程序以形成矽化金屬層於曝露的該源極區域、該閘極結構、該導電平板外表面；移除殘餘的該金屬層；沉積介電層於該半導體底材上，以覆蓋該矽化金屬層與該防護氧化層；且形成導電插塞於該介電層間，以便電性連結至該源極 9.如申請專利範圍第8項極結構前，先形成一閘極氧化之方法，其中在形成上述層於該半導體底材上表面閘中上述閘極結中上述側壁間申請專利範圍第8項之方法，構與該導電平板，是由多a 疋田多日日矽材料所構 12.如申請專利範圍第8 陈壁是由氮化矽材料所構成。之方法Page 14 45 0] 8 VI. Application for Patent Scope 4. For the method of applying for the item No. 丨, after defining the structure, and forming side wall spacers on the two side walls of the gate structure, the side wall spacers are composed of Made of silicon nitride material. 5. The method according to item 1 of the patent application range, wherein the above-mentioned chemical conversion layer is used to cover the conductive substrate between the gate structure and the conductive flat plate. 6. The method according to item 1 of the patent application, wherein the above guide is made of polycrystalline silicon material. 7. For the method of applying for the first item of the patent scope, wherein the above conductor can be used as a capacitor top electrode, and the semiconductor substrate under the conductive plate can be used as a capacitor bottom electrode. 8_ —A method for making an embedded memory bone in a logic element process, the method includes at least the following steps: forming a gate structure and a conductive plate on a semiconductor substrate; forming a sidewall gap on the sidewall of the gate structure ;, Define a source region and a drain region in the body substrate on both sides of the gate structure, wherein the drain region is located in the gate structure and the gate electrode, and the semi-electric plug for protecting oxygen is electrically charged; The semi-conducting plate of the element on the plate side forms a resist protective oxide (RP0) at the 4560 t 8 6. Patent application scope The exposed upper surface of the semiconductor substrate between the gate structure and the conductive plate; deposition A metal layer on the source region, the gate structure, the protective oxide layer, and the outer surface of the conductive plate; a thermal tempering process is performed to form a silicided metal layer on the exposed source region, the gate structure, and the conductive plate An outer surface; removing the remaining metal layer; depositing a dielectric layer on the semiconductor substrate to cover the silicided metal layer and the protective oxide layer; and forming a conductive plug Plugged between the dielectric layers so as to be electrically connected to the source electrode 9. Before applying the patent No. 8 electrode structure, a gate oxidation method is formed, in which the above-mentioned layer is formed on the upper surface of the semiconductor substrate. In the above-mentioned gate junction, the method of applying for item No. 8 in the patent range between the above-mentioned side walls, the structure and the conductive plate are constructed of a multi-day Putian multi-day silicon material. Made of silicon material. Method

六、申請專利範圍 13.如申請專利範圍第8項之方法’其中上述之防護氧化層，用以覆蓋住該閘極結構與該導電平板間的該及極區域》 14.如申請專利範圍第8項之方法，其中上述導電插塞是由多晶矽材料所構成。 15.如申請專利範圍第8項之方法，其中上導板可作為電容器頂部電上工导4十部份該半導體底材則守€十扳下方之〜可作為電容器底部電極使用。6. The scope of patent application 13. The method of item 8 of the scope of patent application 'wherein the above-mentioned protective oxide layer is used to cover the region between the gate structure and the conductive plate' 14. The method according to item 8, wherein the conductive plug is made of polycrystalline silicon material. 15. According to the method of applying for the item No. 8 of the patent scope, the upper guide plate can be used as the electric guide on the top of the capacitor. Some 40% of the semiconductor substrate can be used as the bottom electrode of the capacitor.

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