TW454347B - Manufacturing method for super thin gate insulation layer - Google Patents

Abstract

The present invention provides a manufacturing method for super thin gate insulation layer that while using NH3 to nitridate silicon substrate for growing super thin Si3N4 film in low pressure chemical vapor deposition; and, through rapid annealing process, using a N2O gas to oxidize the layer of super thin silicon nitride film. The layer of super thin silicon nitride film (effective thickness is 28 Å) provides a highly excellent electrical property and reliability which is suitable for replacing the silicon dioxide grown in the traditional furnace tube as the dielectric material for gate, and can be applied to the next generation of super-large integrated circuit, such as deep sub-micron CMOS transistor, erasable and programmable ROM and flash memory.

Description

454347 五、發明說明（1) 發明領域： 本案係有關一種絕緣層之製造方法，尤指一種超薄絕 緣層之製造方法。 發明背景： 在現代積體電路製造中，因要求高容量、速度快及低 功率原則下’電晶體的線寬一定要縮短和閘極厚度一定要 變薄。然而現在積體電路技術都以二氧化矽作為閘極，在 士氧化砂的厚度持續降下#薄時，要當作閑極的介電材料 .有些困難’因為它有不可避奪，高的漏電流，由於它的厚度 太薄導致電子直接穿遂引起。最近幾年，超薄之氮化矽 (s i3 N4 )閘極薄膜具有低漏電流被研究來取代傳統的二氧 化矽’因為它具有高的介電常數和高度防止雜質擴散免疫 能力。在可抹除且程式化唯讀記憶體及快閃記憶體技術中 ，穿遂氧化層（tunneling oxide)厚度被寫入/抹除 (write/erase)循環次數被應力誘發漏電流（stress i nduced 1 eakage cur rent )限制，為了提高寫入/抹除循 環次數，擁有高度可靠性之氮化矽薄膜可取代傳統的二氧 化石夕。但是，在JTD(Jet Vapor Deposition)的Si3N4 薄膜 (由耶魯大學之馬教授（Τ· P. Ma )實驗室研發’請參考資 料：T.P_Ma，’『 Making Silicon Nitride Film a Viable Gate Dielectric," IEEE Electron Devices Vol.45 j p. 680〜690, 1 998 ) ’他有許多缺點及問題，需要昂貴的 JVD儀器設備、低生產力（low throughput)及沉積速率454347 V. Description of the invention (1) Field of the invention: This case relates to a method for manufacturing an insulating layer, especially a method for manufacturing an ultra-thin insulating layer. BACKGROUND OF THE INVENTION In the manufacture of modern integrated circuits, the line width of the transistor must be shortened and the gate thickness must be thin due to the requirements of high capacity, fast speed and low power. However, the integrated circuit technology now uses silicon dioxide as the gate electrode. When the thickness of silicon oxide sand continues to decrease # thin, it must be used as a dielectric material for the idler electrode. It is difficult because of its unavoidable and high leakage current. Due to its too thin thickness, it causes electrons to pass through directly. In recent years, ultra-thin silicon nitride (Si3N4) gate films with low leakage current have been studied to replace traditional silicon dioxide 'because of its high dielectric constant and high immunity to impurities from diffusion. In erasable and stylized read-only memory and flash memory technologies, the thickness of the tunneling oxide is written / erase cycles are stressed i nduced 1 eakage cur rent). In order to increase the number of write / erase cycles, a silicon nitride film with high reliability can replace the traditional dioxide. However, it was developed in the J3 (Jet Vapor Deposition) Si3N4 thin film (developed by Yap University Professor TP Ma) 'Please refer to: T.P_Ma,' "Making Silicon Nitride Film a Viable Gate Dielectric, " IEEE Electron Devices Vol.45 j p. 680 ~ 690, 1 998) 'He has many shortcomings and problems, he needs expensive JVD instruments and equipment, low throughput and deposition rate

1896.ptd 第4頁 45434? 五、發明說明（2) 慢。而傳統低壓化學氣相沈積（LPCVD )爐管只能長出5 0 埃的Si3N4膜，無法成長更薄的Si3N4膜，且它的電性非常 差。氮化矽與矽基材介面不像二氧化矽與矽基材界面這麼 好且它有很高的邊緣缺陷密度（border trap density )〇 職是之故，申請人鑑於習知技術之缺失，乃經悉心試 驗與研究’並一本鍥而不捨之精神，終發明出本案之『― 種超薄閘極絕緣層之製造方法』。 發明簡述： 、 本案之主要目的為提供一種超薄閘極絕緣層之製造方 法 °亥方法係以氨氣（N Hs)來氮化（N i t r i d a t i ο η )石夕基材成 長超薄之氮化矽（SigNJ薄膜在低壓化學氣相沈積中，再經 2速退火過程用一氧化二氮（N20)氣體氧化這層超薄之氮 户石夕薄膜。這層超薄氮化矽薄膜具有高度良好電性及可靠 ^絲非常適合取代用傳統爐管長的二氧化矽當作閘極的介 。 質，可應用於下一代的超大型積體電路。 兮制本案之又一目的為提供一種超薄閘極絕緣層的製法， 叇製法包括下列步驟： 泉汝 )氡化處理.以氨氣（隨3)氮化（Nitridati〇n)矽基 化舉# ί Ϊ長厚度超薄之氮化矽（S丨^)薄膜於高溫低壓 学巩相沈積中成長， # jb) $氧—氮氧化處理：復將該薄膜經快速退火處理 係以一氧化二氮(N2〇)在高溫處理。1896.ptd Page 4 45434? 5. Description of the invention (2) Slow. The traditional low pressure chemical vapor deposition (LPCVD) furnace tube can only grow a Si3N4 film of 50 angstroms, it cannot grow a thinner Si3N4 film, and its electrical properties are very poor. The interface between silicon nitride and silicon substrate is not as good as the interface between silicon dioxide and silicon substrate and it has a high edge trap density. Because of the lack of known technology, the applicant is After careful testing and research, and a spirit of perseverance, he eventually invented the "--a method for manufacturing an ultra-thin gate insulation layer" in this case. Brief description of the invention: The main purpose of this case is to provide a method for manufacturing an ultra-thin gate insulating layer. The method is to use nitrogen gas (N Hs) to nitride (Nitridati ο η) Shi Xi substrate to grow ultra-thin nitrogen. Siliconized (SigNJ thin film in low-pressure chemical vapor deposition, and then through a two-speed annealing process with nitrous oxide (N20) gas to oxidize this ultra-thin Nitolite film. This ultra-thin silicon nitride film has a Good electrical properties and reliable wire are very suitable to replace the traditional silicon dioxide tube long silicon dioxide as the dielectric of the gate. It can be applied to the next generation of ultra-large integrated circuits. Another purpose of this case is to provide a super The manufacturing method of thin gate insulating layer, the manufacturing method includes the following steps: Quan Ru) chemical treatment. Nitriding (Nitridati〇n) silicon-based chemical lifting with ammonia (with 3) # Ϊ Ϊ long thickness ultra-thin silicon nitride (S 丨 ^) The film was grown in high-temperature and low-pressure sclero-deposition. # Jb) Oxygen-nitrogen oxidation treatment: The film was subjected to rapid annealing treatment with nitrous oxide (N20) at high temperature.

454347 五、發明說明（3) 較佳者，其中該步驟（a)所生長之氮化矽薄膜等效厚度 為1 0〜4〇埃。 較佳者’其中該步驟（a)之氮化矽薄膜於6 〇 〇 ~ n 〇 〇度低 壓化學汽相沈積中成長。 較佳者，其中該步驟（a)之氮化矽薄膜於低壓化學氣相 沈積中成長約一小時者。 較佳者，其中該步驟（b)之該薄膜經快速退火處理，需 700〜1100 度。 較佳者，其中該步驟（b)之該薄膜經快速退火處理’需 要時間為5 ~ 3 0 0秒。 較佳者，其中該製法可應用於深次微米互補式金氧電 晶體製程。 較佳者，其中該製法可應用於抹除且程式化唯讀記憶 體及快閃記憶體製程。 本案得藉由下列圖示與符號說明，俾得一更清楚之暸解·· 圖示說明： 7第一圖（a)〜（d):以本案最佳實施例趙薄閘極絕緣層 製法程序實施之元件剖面流程圖。 第二圖：根據本案方法與傳統方法所形成的絕緣層薄 膜之電流密度-電壓（J-V )特性曲線圖； 第三圖：應用本案方法所形成緒構之低與高頻電容對 電壓（C-V )特性曲線圖；以及454347 V. Description of the invention (3) The preferred one, wherein the equivalent thickness of the silicon nitride film grown in step (a) is 10 to 40 angstroms. The preferred one, wherein the silicon nitride film in step (a) is grown in a low pressure chemical vapor deposition at a temperature of 600-n °. Preferably, the silicon nitride film in step (a) is grown for about one hour in a low pressure chemical vapor deposition. Preferably, the thin film in step (b) is subjected to rapid annealing, and the temperature is 700 to 1100 degrees. Preferably, the time required for the step (b) of the thin film to undergo rapid annealing treatment is 5 to 300 seconds. Preferably, the manufacturing method can be applied to the manufacturing process of deep sub-micron complementary metal oxide crystals. Preferably, the method can be applied to erase and program the read-only memory and flash memory system. In this case, you can get a clearer understanding by the following illustrations and symbols: • The first illustration: (a) ~ (d): The procedure of Zhao thin gate insulating layer manufacturing method in the best embodiment of this case Implemented component cross-section flowchart. Figure 2: Current density-voltage (JV) characteristic curve of the insulating layer film formed according to the method of the present case and the traditional method; Figure 3: The low and high frequency capacitor-to-voltage (CV) of the structure formed by applying the method of the case Characteristic graphs; and

第6頁 45434 7 五、發明說明（4) 測試第圖四圖.應用本案方法所形成的絕緣層薄膜之可靠性 圖示符號說明： 2 .氣化發薄膜 4 :鋁膜（上層） 1 : P型基底 3 :—氧化二氮氣體 5 :鋁膜（背面） 實施例說明： ' —明參閱第一圖’其係為以本案超薄閘極絕緣層製造方 法貫碜之兀件剖面流程示意圖。本案方法步驟如下： 首先，，第一圖（a)所示，以氨氣來氮化矽基材1以成 長一厚度超，之氮化矽薄膜2在低壓化學氣相沈積中。其 中所形成之氮化矽層厚度為1〇至4〇埃，以15埃為佳。另外 ’使用之氨氣流量與壓力分別以1〇5sccin與5〇〇1111;〇1^為佳 ’而成長之溫度可控制於6 〇〇至1〇〇〇度，以85〇度下成長一 小時為佳。 接著’如第一圖（b )所示，將氮化矽薄膜2經快速退 火處理’以一氧化二氮氣體3在7〇〇至11〇〇度高溫下氧化處 理5至3 0 0秒。在本案最佳實施例中，以於§ 〇 〇、9 〇 〇以及 1 0 0 0度高溫下處理2 〇秒為最佳。 然後’於上述結構上鍵上一厚度為5 〇 〇 〇埃之紹膜4， 並開圖案’即蝕刻該鋁膜4如第一圖（c )。最後再於矽晶 片之背面锻上5000埃的鋁膜5以形成如第一圖（d)之結構，Page 6 of 45434 7 V. Description of the invention (4) Figure 4 of the test. Reliability of the insulating layer film formed by applying the method of this case: 2. Gasification film 4: Aluminum film (upper layer) 1: P-type substrate 3: Nitrogen oxide gas 5: Aluminium film (back surface) Description of the embodiment: '— Refer to the first figure for details', which is a schematic flow chart of the cross section of the element using the manufacturing method of the ultra-thin gate insulating layer in this case. . The steps of the method in this case are as follows: First, as shown in the first figure (a), the silicon substrate 1 is nitrided with ammonia gas to grow to a thickness that is greater than that of the silicon nitride film 2 in a low-pressure chemical vapor deposition. The silicon nitride layer formed therein has a thickness of 10 to 40 angstroms, preferably 15 angstroms. In addition, 'the flow rate and pressure of the ammonia gas used are preferably 105 sccin and 50000 1111; 〇1 ^ is better', and the growth temperature can be controlled at 6,000 to 10,000 degrees, and the temperature can be increased at 8500 degrees. Hours are better. Next, as shown in the first figure (b), the silicon nitride film 2 is subjected to rapid annealing treatment with a nitrous oxide gas 3 at a temperature of 700 to 1100 ° C for 5 to 300 seconds. In the preferred embodiment of the present case, it is best to process at a high temperature of § 00, 900, and 1000 degrees for 20 seconds. Then "a film of thickness 500 angstroms is formed on the above-mentioned structure and patterned", that is, the aluminum film 4 is etched as shown in the first figure (c). Finally, a 5000 angstrom aluminum film 5 is forged on the back of the silicon wafer to form a structure as shown in the first figure (d).

I896*ptd 第7頁 45434 7 五、發明說明（5) 此時做成可以量測電容。 Μ绍ί ^ Ϊ 一圖’其係為根據本案方法與傳統方法所形成 的、.恩緣層薄膜之電流密度1壓（J_V)特性曲線圖。由第 7 t:應用本案方法所形成之超薄氮化矽薄膜（等效 厚度2 8埃）比使用傳统爐昝士、I ^ ^ , m 1寻跳總s成長的二氣化矽Γ厚埯為2 9埃 )具有更低之漏電流。 >請參閱第三圖，其係為應用本案方法所形成結構之低 與咼頻電容對，壓（C-V )之特性曲線圖。由第三圖可 知，在低頻及高頻之電容與電容與電壓（d )曲線中顯 示氮化砍薄膜具有非常良好的與矽基材界面。在高頻電容 與電壓（C-V)磁滯（hysteresis)曲線中，幾乎可以忽 略它的變化（34mV )，意思指他具有低的界面能階 (interface state)及體積缺陷（bulk trap)密度在這 個薄膜層内。 請參閱第四圖’其係為應用本案方法所形成的絕緣層 薄膜之可靠度測試圖。由第四圖所示結果可知，氮化矽薄 膜層經過定電流為~lmA/cm2及定電場-6. 5MV/cm應力在一 萬秒後’沒有什麼變化，結果顯示它有高可靠性及低的體_ 積缺陷..密度..缺-陷產生率（trap generation rate)。沒有 什麼變化的改變應利誘發漏電流的這層絕緣層薄膜，經過 定電場為-6. 5MV/cm應在一萬秒後。 綜上所述，本案為一種超薄閘極絕緣層之製造方法， 以氨氣（NH3)來氮化（Nitridation)梦基材成長超薄之II化I896 * ptd Page 7 45434 7 V. Description of the invention (5) At this time, the capacitance can be measured. Μ 绍 ί ^ Ϊ A graph 'is a graph of the current density and voltage (J_V) characteristic of the grace layer film formed according to the method of the present case and the conventional method. 7th t: The ultra-thin silicon nitride film (equivalent thickness of 28 angstroms) formed by applying the method of this case is thicker than the two-gassed silicon grown using a traditional furnace maker, I ^ ^, m 1埯 is 2 9 Angstroms) has a lower leakage current. > Please refer to the third figure, which is a characteristic curve diagram of the low and high frequency capacitor pairs and voltage (C-V) of the structure formed by applying the method of the present case. As can be seen from the third figure, the low-frequency and high-frequency capacitance, capacitance, and voltage (d) curves show that the nitrided film has a very good interface with the silicon substrate. In the high frequency capacitance and voltage (CV) hysteresis curve, its change can be almost ignored (34mV), which means that he has a low interface state and bulk trap density. Within the film layer. Please refer to the fourth figure ', which is a reliability test chart of the insulating layer film formed by applying the method of the present case. From the results shown in the fourth figure, it can be seen that the silicon nitride thin film layer has a constant current of ~ lmA / cm2 and a constant electric field of -6.5MV / cm after ten thousand seconds. 'There is no change, and the results show that it has high reliability and Low volume defects .. density .. trap generation rate. There is no change in the change of this insulating layer film which should be favorable for inducing leakage current. After a fixed electric field of -6. 5MV / cm should be in ten thousand seconds. To sum up, this case is a method for manufacturing an ultra-thin gate insulation layer, which uses ammonia (NH3) to nitride (Nitridation) dream substrates to grow ultra-thin II

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Claims (1)

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