TW454277B - Direct heat dissipating type structure of BGA substrate - Google Patents

Direct heat dissipating type structure of BGA substrate Download PDF

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Publication number
TW454277B
TW454277B TW088108336A TW88108336A TW454277B TW 454277 B TW454277 B TW 454277B TW 088108336 A TW088108336 A TW 088108336A TW 88108336 A TW88108336 A TW 88108336A TW 454277 B TW454277 B TW 454277B
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Taiwan
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layer
heat dissipation
substrate
circuit layer
bga substrate
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TW088108336A
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Chinese (zh)
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Shr-Bin Shiu
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Phoenix Prec Technology Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32153—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/32175—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic
    • H01L2224/32188—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic the layer connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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Abstract

The present invention relates to a direct heat dissipating type structure of BGA substrate, which includes a heat sink, an insulating resin layer, an upper circuit layer, a lower circuit layer and a plurality of PTHs. The heat sink has a body portion, a carrying portion and a combination portion. The carrying portion is arranged above the body portion. The combination portion is arranged below the body portion and its periphery is extended outward to form a flange. The body portion of the heat sink is buried into the center of the substrate. The upper circuit layer is formed on the upper surface of the resin layer and has a plurality of bonding pads. The lower circuit layer is formed on the lower surface of the resin layer and has a plurality of solder ball pads. The upper and lower circuit layers are connected via a plurality of PTHs. When packaging the BGA substrate, a chip is directly adhered to the carrying portion of the heat sink and is coupled to the bonding pads on the upper circuit layer by a plurality of gold wires. The surfaces of the solder ball pads on the lower circuit layer are bonded with solder balls and the lower circuit layer is connected to the circuit board via the solder balls. In addition, the combination portion of the heat sink is directly bonded to the circuit board.

Description

經濟部智慧財產局員工消費合作社印製 五、發明說明（/ ) 發明領域： 本發明係有關於一種BGA基板直接散熱型結構及製 程，特別是有關於一種可以提高散熱效率和簡化製程之BGA 基板。 發明背景： 請參閱圖一所示，其係習知技術一之BGA基板10結構 示意圖，該基板10包括一銅板材11、一上樹脂層12、一上 電路餍13、一下樹脂層14、一下電路層15及複數個導重检 16和導熱栓17。 ..... . . .. .. 該銅板材11係位於基板10結構的中間，其主要目的係 做爲該基板10之散熱板，使晶片20所產生之熱量可以藉由 銅板材11散發至外界，又該銅板材11在其表面周圍設有複 數個貫穿之導通孔112 ; 該上樹脂層I2係壓合於該銅板材11之上側表面，而該 下樹脂層14係壓合於該銅板材η之下側表面，在壓合的過 程中該上、下樹脂層12、14之絕緣樹脂膠亦同時將銅板材 11之導通孔112填滿； 該上電路層13係設於上樹脂層12之表面，又該上電路 層I3具有複數個打線墊132其表面鍍有一層鎳金(Ni-Au)， 此外，通常在該上電路層13表面係覆蓋有一層綠漆18(Solder Mask)’該層綠漆18之目的係在於保護上電路層13並使打線 墊132暴露於外界； 該下電路層15係設於下樹脂層14之表面，又該下電路 層14具有複數個鍚球墊152其表面鍍有一層鎳金，此外，通 _______2________ 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閲讀背面之注意事項再填寫本I) 經濟部智慧財產局員工消費合作社印制农 五、發明說明) 常在該下電路層15表面係覆蓋有一層綠漆19，該層綠漆19 之目的係在於保護下電路層15並使鍚球墊152暴露於外界； 上述複數個導電栓16係貫穿上樹脂層12、銅板材11之 導通孔112以及下樹脂層14，使上、下電路層13、15彼此 之間互相導通，其中該導電栓16之孔徑係較銅板材U之導 通孔112小，且該導電栓16與導通孔112之間係利用絕緣樹 脂膠加以阻隔以避免發生短路現象； 上述複數個導熱栓17係貫穿上樹脂層12、銅材2材11 以及下樹脂層14，並使該導熱栓17直接接觸於晶片20之底 部。 習知技術一之基板10在進行封裝時，係將晶片20置於 上樹脂層12表面，且該晶片20之底部係直接與上述導熱栓 Π相接觸，該基板10之上電路層13之打線墊132與晶片20 之電路佈局之間係藉由複數條金線21加以耦合連接，之後再 利用一層封膠(Epoxy)將晶片20與金線21加以保護，又該基 板10之下電路層15之鍚球墊152表面係焊上複數個鍚球 23，並藉由該鍚球23與電路板（圖中未示）之電路相耦合。 然而，習知技術之基板10結構具有導熱提昇有限以及製 程複雜等缺點，究其原因主要係因爲： a.習知技術一之基板10對於晶片20之散熱方式係藉由複數 個導熱栓Π將熱量傳遞至銅板材11和電路板，再傳遞至 外界，但是導熱栓17可供晶片20散熱之截面積有限，而 . * 封膠:22與上樹脂層J2之材料均爲熱之不良導體，因而導 致整體封裝元件之散熱效果不佳，相對地也就影響到晶片 —--------->! L . -----------llri--1 ^ (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） :.¾ 為 § 4 . . . . A7 _ - Β7 經濟部智慧財產局員工消費合作社印製 五、發明說明（々） 20之工作效能與穩定性。 b.習知技術一之基板10在設置導熱栓17時，必須經過鑽孔、 鑛銅以及塞孔等複雜製程，不僅費時且增加製造成本，此 外’若導熱栓17塞孔不完全而有許多殘留的小空隙存在， 將產生Popcorn現象。 因此’對於從事晶片2〇之封裝業者莫不致力於基板10 之散熱效果之改善以提高其產品之品質與市場的競爭力。 請參閱圖二所示，其係習知技術二之BGA基板30結構 示意圖，由於習知技術一係爲Die up型式具有散熱效果不佳 之缺點，因此習知技術二係針辑置知技術一之缺點而提出一 種Cavity Down型式之BGA基板30。 習知技術二之BGA基板30結構包括一散熱板3卜一樹 脂層32以及一電路層33。該散熱板3.1係爲一銅板材，在其 中間具有一方形容置槽312可供晶片40容置於其中;該樹脂 層32係壓合於銅板林31之上，且該樹脂層32具有一形狀與 銅板材31之容置槽312相配合之開口 322 ;該電路層33係 形成於樹脂層32之表面，其中該電路層32更具有複數個打 線墊332和鍚球墊334且在其表面更鍍有一層鎳金，該電路 層33表面係覆蓋上一層綠漆34以保護電路層，並使打線墊 332與鍚球墊334暴露於外界。 習知技術二之BGA基板30結構在進行晶片40之封裝 時，係將晶片40結合於散熱板31之容置槽312上，並利用 複數條金線41將晶片40之電路佈局耦合於電路層33之打線 墊332，此時在晶片40表面與金線41之周圍係利用一層封 (請先閱讀背面之注意事項再填寫本頁) -----if---\裝 訂 ___- _u-«I-1 ——II ί n n 1 n —1 , 本紙張尺度適用中國國家標準（CNS).A4規格（210 X 297公.楚） >4^7 7 A7 _____________B7_______ 五、發明說明（p 膠42加以保護，之後將複數個鍚球43焊於鍚球墊334之表 面再結合於電路板(圖中未示）之電路上。 習知技術二之BGA基板30結構散熱效率較習知技術一 之散熱效率佳，但是仍然有下列之缺點： . ... . ' a. 習知技術二之基板30係爲Cavity Down型式，其特徵係在 於將晶片40與鍚球43設於同一側面，有別於一般傳統的 : I 一Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Invention Description (/) Field of the Invention: The present invention relates to a direct heat dissipation structure and process of a BGA substrate, and particularly to a BGA substrate that can improve heat dissipation efficiency and simplify the process . Background of the Invention: Please refer to FIG. 1, which is a schematic structural diagram of a BGA substrate 10 of the conventional technology 1. The substrate 10 includes a copper plate 11, an upper resin layer 12, an upper circuit 餍 13, a lower resin layer 14, The circuit layer 15 and a plurality of guide re-inspections 16 and a thermally conductive plug 17. ......... The copper plate 11 is located in the middle of the substrate 10 structure. Its main purpose is to serve as a heat sink for the substrate 10 so that the heat generated by the chip 20 can be dissipated through the copper plate 11. To the outside, the copper plate 11 is provided with a plurality of through-holes 112 around the surface; the upper resin layer I2 is pressed on the upper side surface of the copper plate 11 and the lower resin layer 14 is pressed on the surface. The lower side surface of the copper plate η, during the lamination process, the insulating resin glue of the upper and lower resin layers 12 and 14 also fills the through-holes 112 of the copper plate 11 at the same time; the upper circuit layer 13 is provided on the upper resin On the surface of layer 12, the upper circuit layer I3 has a plurality of wire bonding pads 132, and the surface is plated with a layer of nickel gold (Ni-Au). In addition, the surface of the upper circuit layer 13 is usually covered with a layer of green paint 18 (Solder Mask). ) 'The purpose of this green paint 18 is to protect the upper circuit layer 13 and expose the bonding pad 132 to the outside; the lower circuit layer 15 is provided on the surface of the lower resin layer 14, and the lower circuit layer 14 has a plurality of 钖The surface of the ball pad 152 is plated with a layer of nickel and gold. In addition, the paper size applicable to _______2________ National Standard (CNS) A4 Specification (210 X 297 mm) (Please read the notes on the back before filling in this I) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, Agricultural V. Invention Description) Often in this lower circuit layer The surface of 15 is covered with a layer of green paint 19, the purpose of this layer of green paint 19 is to protect the lower circuit layer 15 and expose the ball pad 152 to the outside; the above-mentioned plurality of conductive plugs 16 penetrate the upper resin layer 12, the copper plate 11 The via hole 112 and the lower resin layer 14 allow the upper and lower circuit layers 13 and 15 to communicate with each other. The hole diameter of the conductive pin 16 is smaller than the through hole 112 of the copper plate U, and the conductive pin 16 is connected to the conductive hole. The holes 112 are insulated by an insulating resin glue to avoid short circuit. The above-mentioned plurality of thermally conductive plugs 17 penetrate the upper resin layer 12, the copper material 2 and the lower resin layer 14 and directly contact the thermally conductive plug 17 to The bottom of the wafer 20. When the substrate 10 of the conventional technique 1 is packaged, the wafer 20 is placed on the surface of the upper resin layer 12, and the bottom of the wafer 20 is directly in contact with the above-mentioned thermally conductive plug Π, and the wiring of the circuit layer 13 on the substrate 10 is wired. The circuit layout of the pad 132 and the chip 20 is coupled by a plurality of gold wires 21, and then a layer of epoxy (Epoxy) is used to protect the chip 20 and the gold wire 21, and the circuit layer 15 under the substrate 10 A plurality of ball balls 23 are soldered on the surface of the ball ball pad 152, and the ball balls 23 are coupled to the circuit of a circuit board (not shown) through the ball balls 23. However, the substrate 10 structure of the conventional technology has disadvantages such as limited heat transfer enhancement and complicated manufacturing process. The main reasons are as follows: a. The substrate 10 of the conventional technology uses a plurality of thermally conductive bolts to dissipate the heat from the substrate 20. The heat is transferred to the copper plate 11 and the circuit board, and then to the outside, but the cross-sectional area of the thermal conductive plug 17 for the heat dissipation of the chip 20 is limited, and the sealant: 22 and the upper resin layer J2 are both bad thermal conductors. As a result, the heat dissipation effect of the overall package component is not good, and the chip is relatively affected —--------- >! L. ----------- llri--1 ^ ( Please read the notes on the back before filling out this page) This paper size applies to Chinese National Standard (CNS) A4 (210 X 297 mm): ¾ is § 4... A7 _-Β7 Intellectual Property Bureau of the Ministry of Economic Affairs Printed by Employee Consumer Cooperatives V. Invention Description (々) 20 Work efficiency and stability. b. The substrate 10 of the conventional technology 1 must be subjected to complicated processes such as drilling, ore copper, and plug holes when the thermal plug 17 is provided, which is not only time consuming and increases the manufacturing cost. In addition, if the plug holes of the thermal plug 17 are not complete, there will be many The existence of small residual voids will cause the Popcorn phenomenon. Therefore, the packaging industry that is engaged in the wafer 20 is committed to improving the heat dissipation effect of the substrate 10 to improve the quality of its products and the competitiveness of the market. Please refer to FIG. 2, which is a schematic diagram of the structure of the BGA substrate 30 of the conventional technology 2. Because the conventional technology 1 is a Die up type and has the disadvantage of poor heat dissipation, the conventional technology 2 A disadvantage is a Cavity Down type BGA substrate 30 is proposed. The structure of the BGA substrate 30 in the conventional technique 2 includes a heat sink 3, a resin layer 32, and a circuit layer 33. The heat-dissipating plate 3.1 is a copper plate, and has a square receiving groove 312 in the middle for the wafer 40 to be accommodated therein. The resin layer 32 is laminated on the copper plate forest 31, and the resin layer 32 has a shape. An opening 322 matching the accommodating groove 312 of the copper plate 31; the circuit layer 33 is formed on the surface of the resin layer 32, wherein the circuit layer 32 further has a plurality of wire bonding pads 332 and ball ball pads 334 and more on its surface A layer of nickel gold is plated, and the surface of the circuit layer 33 is covered with a layer of green paint 34 to protect the circuit layer, and the wire pad 332 and the ball pad 334 are exposed to the outside. The structure of the BGA substrate 30 of the conventional technique 2 is used for packaging the wafer 40 by bonding the wafer 40 to the receiving groove 312 of the heat sink 31 and using a plurality of gold wires 41 to couple the circuit layout of the wafer 40 to the circuit layer. 33 of the wire bonding pad 332, at this time, a layer of sealing is used around the surface of the chip 40 and the gold wire 41 (please read the precautions on the back before filling this page) ----- if --- \ binding ___- _u -«I-1 ——II ί nn 1 n —1, this paper size applies Chinese National Standard (CNS) .A4 specification (210 X 297 public. Chu) > 4 ^ 7 7 A7 _____________B7_______ 5. Description of the invention (p The adhesive 42 is protected, and then a plurality of ball balls 43 are soldered to the surface of the ball pad 334 and then combined with the circuit of a circuit board (not shown). The BGA substrate 30 structure of the conventional technology 2 has a higher heat dissipation efficiency than the conventional technology. First, the heat dissipation efficiency is good, but it still has the following disadvantages:... A. The substrate 30 of the conventional technology 2 is a Cavity Down type, which is characterized in that the chip 40 and the ball 43 are arranged on the same side. Different from the traditional: I a

Die up之封裝設計，造成下游封裝廠必須針對Cavity Down 型式之基板作製程上的變更。 b. 習知技術二之基板30由於係將晶片40與鍚球43設於同一 側面，該側面不但要安排晶片40且要提供焊接鍚球43之 面積，因此使得習知技術二之基板30可供鍚球43安排之 數量變少，影響基板30的功能。 c. 習知技術二之基板30其生產成本較高製程複雜，且在進行 封膠42時必須採用頂上注膠(Glob Top)方式或灌膠方式一 顆一顆個別封膠無法整批式製造，產量低可靠度也相對較 . . . . . . . 至Λ. 差。 發明目的： 本發明之主要目的在於提供一種具有高散熱效率之 BGA基板直接散熱型結構，該基板係利用散熱板取代導熱栓 對晶片直接進行散熱，因此不僅可以提高晶片之工作效能與 ·· - . ./!— .............. - - · .. · · . · __ .： ... -- · 靈定性，且不會有Popcorn之問題產生。 本發明之次要目的在於提供一種Die up型式之BGA基 板直接散熱型結構，該基板可供焊接鍚球之數目較習知技術 二之Cavity Down型式多，不僅可以提高基板之功能且下游 . . . · ·... . --— ___ Λ _____ 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) i I!·-'裝Die up's packaging design has caused downstream packaging factories to make process changes to Cavity Down substrates. b. The substrate 30 of the conventional technique 2 is provided with the wafer 40 and the ball 43 on the same side. The side not only arranges the wafer 40 but also provides an area for soldering the ball 43. Therefore, the substrate 30 of the conventional technique 2 can be used. The number of supply balls 43 is reduced, which affects the function of the substrate 30. c. The substrate 30 of the conventional technology 2 has a higher production cost and a complicated process, and the sealing 42 must be performed by the Glob Top method or the pouring method. Individual sealants cannot be manufactured in batches. , And the low reliability of the production is relatively poor. Purpose of the invention: The main object of the present invention is to provide a direct heat dissipation structure of a BGA substrate with high heat dissipation efficiency. The substrate uses a heat sink instead of a thermally conductive pin to directly dissipate the wafer, so it can not only improve the working efficiency of the chip and ... . ./!— ..............--· .. · · · · __.: ...-· Spirituality, and there will be no problems with Popcorn. The secondary objective of the present invention is to provide a Die up type BGA substrate direct heat dissipation type structure. The number of solder balls available for the substrate is larger than the Cavity Down type of the conventional technology 2. It can not only improve the function of the substrate but also downstream. · · .... --- ___ Λ _____ This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page) i I! ·- 'Load

-n It n H 訂· 經濟部智慧財產局員工消費合作社印製 --棒Jvv·----- B7 五、發明說明（/ ) 封裝廠不須對製程做變更。 本發明之BGA基板直接散熱型結構包括一散熱板、一 樹脂層、一上電路層、一下電路層以及複數個導電栓。 該散熱板係爲一金屬散熱板材，具有一本體部、一承載 韶和一結合部，其中該承載部係設於本體部之上方，又該結 .... ... . . 合部係設於本體部之下方且其周圍係向外延伸而形成一凸 緣；該樹脂層係環繞於上述散熱板之本體部外圍’即該散熱 板係埋入於樹脂層之中央，該上電路層係設於該樹脂層之上 側表面，其中在上電路層表面具有複數個打線墊，S在上電 . . ...... ... .. 路層表面係覆蓋一層保護層並使該打線墊曝露於外界。 該下電路層係設於該樹脂層之下側表面，其中在下電路 層表面具有複數個錫球墊，且在上電路層表面係覆蓋上一層 保護層並並使鍚球塾暴露於外界，上述複個導電栓係貫穿該 .. . . ... 樹脂層並連接上、下電路層使其成導通狀態。-n It n H · Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs-Rod Jvv · ----- B7 V. Description of the Invention (/) The packaging plant does not need to make changes to the manufacturing process. The BGA substrate direct heat radiation type structure of the present invention includes a heat radiation plate, a resin layer, an upper circuit layer, a lower circuit layer, and a plurality of conductive pins. The heat radiating plate is a metal heat radiating plate, which has a main body part, a bearing part and a joint part, wherein the bearing part is arranged above the main body part and should be knotted ... The resin layer is arranged below the main body part and its periphery extends outward to form a flange; the resin layer surrounds the periphery of the main body part of the heat sink plate, that is, the heat sink plate is buried in the center of the resin layer, and the upper circuit layer It is located on the upper side surface of the resin layer, where there are a plurality of wire bonding pads on the surface of the upper circuit layer, and S is powered on......... The wire pad is exposed to the outside world. The lower circuit layer is provided on the lower surface of the resin layer, wherein the surface of the lower circuit layer has a plurality of solder ball pads, and the surface of the upper circuit layer is covered with a protective layer and the ball is exposed to the outside. A plurality of conductive bolts pass through the ..... Resin layer and connect the upper and lower circuit layers to make it conductive.

經濟部智慧財產局員工消費合作社印M 該BGA toS在進行封裝時，係將晶片置於散熱板之承 載部，並藉由複數條金線耦合於上電路層之打線墊上，又該 下電路層之鍚球墊表面係焊上鍚球，並藉由該鍚球結合於電 路板之上，同時該散熱板之結合部係利用鍚膏直接焊於電路 板之電路上，該基板在晶片表面與金線附新係覆蓋一層封膠 加以保護，以避免晶片受到外界的影響。 本發明之BGA基板直接散熱型結構係利用散熱板將晶 片所產生之熱量直接傳遞至外界，由於散熱板之截面積較導 熱熱栓之截面積大，因此本發明之散熱效果較習知技術一 佳，不僅可以提高晶片之工作效能與穩定性，且不會有 一___6 _ 一 +、'氏張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 五、發明說明（z) (請先閱讀背面之注音？事項再填寫本頁)Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperatives, this BGA toS is used to place the chip on the heat sink's load-bearing section and couple multiple gold wires to the bonding pads on the upper circuit layer and the lower circuit layer. The surface of the ball pad is soldered with a ball, and is bonded to the circuit board by the ball. At the same time, the joint of the heat sink is directly soldered to the circuit of the circuit board using a paste, and the substrate is on the surface of the wafer and The gold wire with a new system is covered with a layer of sealant to protect the chip from external influences. The direct heat dissipation structure of the BGA substrate of the present invention uses a heat sink to directly transfer the heat generated by the chip to the outside world. Since the cross-sectional area of the heat sink is larger than the cross-sectional area of the thermally conductive plug, the heat dissipation effect of the present invention is better than the conventional technology Not only can improve the working efficiency and stability of the chip, but also will not have a _6 _ a +, '' Zhang scale applicable to the Chinese National Standard (CNS) A4 specifications (210 X 297 mm) V. Description of the invention (z) (Please read the Zhuyin on the back? Matters before filling out this page)

Popcorn之問題產生。此外，本發明之基板係爲Die up型式， 基板可供焊接錫球的面積較習知技術二大，不僅可以提高基 板之功能且下游封裝廠不須進行製程變更，生產速度較快。 爲了使貴審查委員對本發明之目的、特徵及功效，有 更進一步的瞭解與認同，茲配合圖式詳加說明如后： 圖式之簡單說明： 圖一係習知技術一之BGA基板結構示意圖。 圖二係習知技術二之BGA基皮結構示意圖。 圖三係本發明BGA基板直接散熱型結構之第一實施例 圖。 圖四係本發明BGA基板直接散熱型結構之第二實施例 圖。 圖五係本發明BGA基板直接散熱型結構之第三實施例 圖。 圖六係本發明BGA基板直接散熱型結構之第四實施例 圖。 圖七係本發明BGA基板直接散熱型結構之第五實施例 圖。 經濟部智慧財產局員工消費合作社印製 圖式中之圖號說明： 10-基板 11-銅板材 112-導通孔 12-上樹脂層 13- 上電路層 132-打線墊 14- 下樹脂層 15-下電路層 152-鍚球墊 16-導電栓 _；__________2_ 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明) Π-導墊栓 19-綠漆 21-金線 30-基板 312-容置槽 322-開口 332-打線墊 34-綠漆 40-晶片 42-封膠 50- 基板 51- 散熱板 512-承載部 52- 樹脂層 532-打線墊 542-鍚球墊 56-綠漆 60-晶片 62-鍚球 70-二層電路 72-第二電路層 722-導熱電路 73、74-樹脂層 76-導熱栓 18-綠漆 20-晶片· 22-封膠 31- 散熱板 32- 樹脂層 33- 電路層 334-鍚球墊 35-電路層 41-金線 43-鍚球 50a、50b、50c、50d-基板 511-本體部 513-結合部 53- 上電路層 54- 下電路層 55- 導電栓 57-綠漆 61-金線 63-封膠 71-第一電路層 721-導電電路 723-金屬凸塊 75-容置槽 77-導電栓 I ! --------------. ^ i ! I ----- i --------- ί »^,/( (請先閱#背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）Popcorn's problems arise. In addition, the substrate of the present invention is a Die up type, and the area of the substrate for solder balls is larger than that of the conventional technology. Not only can the function of the substrate be improved, but downstream packaging plants do not need to make process changes, and the production speed is fast. In order to allow your reviewers to further understand and agree with the purpose, features and effects of the present invention, we will explain in detail with the drawings as follows: Brief description of the drawings: Figure 1 is a schematic diagram of the BGA substrate structure of the conventional technology 1. . FIG. 2 is a schematic diagram of a BGA base skin structure of the conventional technique 2. FIG. Fig. 3 is a diagram of a first embodiment of a direct heat radiation type structure of a BGA substrate of the present invention. Fig. 4 is a diagram of a second embodiment of a direct heat radiation type structure of a BGA substrate of the present invention. Fig. 5 is a diagram of a third embodiment of a direct heat radiation type structure of a BGA substrate of the present invention. Fig. 6 is a diagram of a fourth embodiment of a direct heat radiation type structure of a BGA substrate of the present invention. Fig. 7 is a diagram of a fifth embodiment of a direct heat radiation type structure of a BGA substrate of the present invention. Description of the drawing numbers in the printed drawings of the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs: 10-substrate 11-copper plate 112-vias 12-upper resin layer 13-upper circuit layer 132-wire pad 14- downer resin layer 15- Lower circuit layer 152-ball ball pad 16-conductive bolt _; __________2_ This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ) Π-guide pad bolt 19-green paint 21-gold wire 30-substrate 312-receiving slot 322-opening 332-wire pad 34-green lacquer 40-chip 42-sealing 50- substrate 51- heat sink 512-bearing Section 52- Resin layer 532- Wire bonding pad 542- Ball ball pad 56- Green paint 60- Wafer 62- Ball 70- Second layer circuit 72- Second circuit layer 722- Thermal circuit 73, 74- Resin layer 76- Thermal plug 18-green lacquer 20-wafer 22-sealing 31- heat sink 32- resin layer 33- circuit layer 334- ball pad 35- circuit layer 41- gold wire 43- ball 50a, 50b, 50c, 50d-substrate 511-body part 513-bonding part 53- upper circuit layer 54- lower circuit layer 55- conductive plug 57- green lacquer 61- gold wire 63- sealant 71- first circuit layer 721- conductive circuit 723- gold It belongs to the bump 75-receiving slot 77-conducting bolt I! --------------. ^ I! I ----- i --------- ί » ^, / ((Please read the notes on the back of # before filling out this page) This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)

五、發明說明（/ ) .: . .. · . ...... . . . .. ..... . .... _ ' ' 經濟部智慧財產局員工消費合作社印製 詳細說明： 本發明係針對習知技術之缺點而改善之基板結構，由於 習知技術一之基板因爲散熱效果不穩定，影響晶片之工作效 能與穩定性，以及習知技術二之基板可供焊接鎮球之數目較 少，影響基板之功能和生產效率，因而提出一種具有高散熱 效率之晶片之基板結構’以改善習知技術之基板所衍生之缺 點、 請參閱圖三所示，其係本發明BGA基板50直接散熱型 ... . ... . . . 結構之第一實施例圖，該BGA基板50包括一散熱板51、一 . . . .... . ..... .. 樹脂層52、一上電路層53、一下電路層54以及複數個導電 ::栓:55。 . ... . .- . .. 該散熱板51係爲一導電導熱板材，包括一本體部511、 . . ........ . . . · . . —承載部512和一結合部513，其中該承載部512係設於本 體部511之上方，又該結合部513係設於本體511之下方且 其周圍係向外延伸而形成一凸緣； . ... . . ： .... .. 該樹脂層52係環繞於上述散熱板51之本體部511外 圍，即該散熱板51係埋入該樹脂層52之中，該上電路層53 係設於該樹脂層52之上側表面，其中上電路層53表面具有 複數個打線墊532，且在上電路層53表面係覆蓋一層綠漆56 並使打線墊532曝露於外界。 該下電路層54係設於該樹脂層52之下側表面，其中在 下電路層54表面具有複數個鍚球墊542，且在下電路層54 . . . -. . . - - 表面係覆蓋上一層綠漆57並使鍚球墊542暴露於外界，上述 複數個導電栓55係貫穿該樹脂層52並連接上、下電路層 (請先閱讀背面之注意事項再填寫本頁) ----—----------.k :訂— .線' 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公楚) A7 B7 454^11 1/ 五、發明說明（/ ) 53、54使其成導通狀態。 c請先閲讀背面之注意事項再填寫本頁) 第一實施例之BGA基板50在進行封裝時，係將晶片60 置於散熱板51之承載部512，並藉由複數條金線61耦合於 上電路層53之打線墊532上，又該下電路層54之鍚球墊542 表面係焊上鍚球62，並藉由該鍚球62結合於電路板之上， 同時該散熱板51之結合部513係利用鍚膏（圖中未示)直接 焊於電路板之上，此外，該基板50在晶片60表面與金線61 附近係覆蓋一層封膠63加以保護，以避免晶片60受到外界 前影響。： ； ..... .·. ... .... ..... 請參閱圖三所示，本實施例在散熱板51之結合部513 表面亦可以是藉由褸數個鍚球62結合於電路板之上，其作法 係在散熱板51之結合部513設置複數個鍚球墊（本圖中未 ..... .. .... ... .. . . 示），其表面並鍍有鎳金，將一層綠漆57覆蓋於散熱板51 之結合部513並使該鍚球墊暴露於外界，將鍚球62焊於鍚球 . ： .... .... . ...... . . ... 塾之上並藉由該鍚球62結合於電路板之上。 .. ........ ...,. . . ... ' .經濟部智慧財產局員工消費合作社印製 請參閱圖四所示，其係本發明BGA基板50a.直接散熱型 結構之第二實施例圖，本實施例在整體之基板50a結構上大 致與第一實施例相同，因此對於元件之圖示部分均給予相同 之編號且不加以贅述，其最大之不同係在於散熱板51之承載 部512在其周圍係向外延伸而形成一凸緣，使該散熱板51 之側視圖係類似一『工』字形，其主要目的係用以強化該基 板5〇a之整體結構，以避免該基板50a因爲受到外力的作用 而發生彎曲，本實施例在對於晶片60之封裝方式與將該基板 50a結合於電路板的方式均與第一實施例相同。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X. 297公楚） 4 Φ飞 κι Β7 五、發明說明（ V17) . . . ...... ..... · 請參閱圖五所示，其係本發明BGA基板50b直接散熱 型結構之第三實施例圖，本實施例在整體之基板50b結構上 大致均與第一實施例相同，因此對於相同之元件在圖示部分 均給予相同之編號且不加以贅述，其最大之不同係在於散熱 .....：.· ： -· V - - -·· ·---'·-— .i ·. r·. ·-Γ~ν.-V-^ ···... ----... -.·· , . ........... -- .... - .......i 板51之承載部512與結合部513均未向外延伸，但是其本體 部5 i i之周菌係向外延伸而形成一凸緣，該樹脂層52係環繞 於上述散熱板51之本體部511外圍，即該散熱板51係埋入 . . ... - ........ . . . 樹脂層52之中，該上電路層53係設於樹脂層52之上側表: . _ _ . . .. .... - 面，該下電路層54係設於樹脂層52之下側表面，其餘部分 之基板50b結構以及對於晶片60之封裝和將該基板50b結合 於電路板之方式均與第一實施例相同。 請參閲圖六所示，其係本發明BGA基板50c直接散熱型 結構之第四實施例圖，本發明BGA基板50c係應用於多晶片 60模組之基板50c結構(Multi-Chip Modulus)，本實施例在整 體之基板50c結構上大致均與第一實施例相同，因此對於相 同之元件在圖示部分均給予相同之編號且不加以贅述，其最 大之不同係在於本實施例係將複數個晶片60封裝於同一片 基板50c之上，由於晶片60的數目多相對地基板50c之功能 也會提高，此外，本實施例對於晶片60的封裝與將基板50c 結合於電路板之方式均與第一實施例相同。 ......... · . 請參閱圓七所示，其係本發明BGA基板50d直接散熱 型結構之第五實施例圖，本實施例在整體之基板50d結構上 大致均與第一實施例相同，因此對於相同之元件在圖示部分 均予相同之編號且不加以贅述，其最大之不同係在於本實施 (請先閲讀贵面之注意事項再填寫本頁) lk:·---- I E--訂！ -線 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）V. Description of Invention (/).:...................... : The present invention is a substrate structure improved for the disadvantages of the conventional technology. Due to the unstable heat dissipation effect of the substrate of the conventional technology 1, the working efficiency and stability of the chip are affected, and the substrate of the conventional technology 2 can be used for solder ball bonding. The number is small, which affects the function and production efficiency of the substrate. Therefore, a substrate structure of a wafer with high heat dissipation efficiency is proposed to improve the disadvantages derived from the substrate of the conventional technology. Please refer to FIG. 3, which is the BGA of the present invention. The substrate 50 is directly heat-dissipating..... The first embodiment of the structure, the BGA substrate 50 includes a heat-dissipating plate 51, a......... Layer 52, an upper circuit layer 53, a lower circuit layer 54, and a plurality of conductive :: pins: 55. ...... The heat sink 51 is a conductive and heat conductive plate, and includes a body portion 511,........ Part 513, wherein the bearing part 512 is disposed above the main body part 511, and the joint part 513 is disposed below the main body 511 and its surroundings extend outward to form a flange;...:. ..... The resin layer 52 surrounds the periphery of the body portion 511 of the heat dissipation plate 51, that is, the heat dissipation plate 51 is embedded in the resin layer 52, and the upper circuit layer 53 is provided in the resin layer 52. The upper surface, wherein the surface of the upper circuit layer 53 has a plurality of bonding pads 532, and the surface of the upper circuit layer 53 is covered with a layer of green paint 56 and the bonding pads 532 are exposed to the outside. The lower circuit layer 54 is provided on the lower side surface of the resin layer 52, and there are a plurality of ball pads 542 on the surface of the lower circuit layer 54. The lower circuit layer 54 is covered with a layer on the surface. The green paint 57 exposes the ball pad 542 to the outside. The above-mentioned multiple conductive plugs 55 penetrate the resin layer 52 and connect the upper and lower circuit layers (please read the precautions on the back before filling this page) ----- ----------. k: order — .line 'This paper size applies to China National Standard (CNS) A4 (210 X 297 Gongchu) A7 B7 454 ^ 11 1 / V. Description of the invention (/ 53, 54 make it into a conducting state. c Please read the precautions on the back before filling this page.) When the BGA substrate 50 of the first embodiment is packaged, the chip 60 is placed on the carrying portion 512 of the heat sink 51, and is coupled to the plurality of gold wires 61 by The ball pad 532 of the upper circuit layer 53 and the ball pad 542 of the lower circuit layer 54 are soldered with the ball 62, and the ball ball 62 is bonded to the circuit board, and the heat sink 51 is bonded together. The portion 513 is directly soldered to the circuit board by using a paste (not shown). In addition, the substrate 50 is covered with a layer of sealant 63 on the surface of the wafer 60 and near the gold wire 61 to prevent the wafer 60 from being exposed to the outside. influences. ：; ............. Please refer to FIG. 3. In this embodiment, the surface of the joint portion 513 of the heat sink 51 may also be formed by several 钖The ball 62 is coupled to the circuit board, and the method is to set a plurality of ball pads on the joint portion 513 of the heat dissipation plate 51 (not shown in this figure ...........) ), Its surface is plated with nickel gold, a layer of green paint 57 is covered on the joint portion 513 of the heat dissipation plate 51 and the ball pad is exposed to the outside, and the ball 62 is welded to the ball.: ... ..... 塾 and 结合 are connected to the circuit board by the 62 ball 62. .. .............,.... '. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, please refer to Figure 4, which is the BGA substrate 50a of the present invention. Direct heat dissipation type Structure of the second embodiment. This embodiment is substantially the same as the first embodiment in the overall structure of the substrate 50a. Therefore, the components of the diagram are given the same number and will not be described in detail. The biggest difference is in heat dissipation. The bearing portion 512 of the plate 51 extends outward to form a flange, so that the side view of the heat sink plate 51 resembles an "I" shape. Its main purpose is to strengthen the overall structure of the substrate 50a. In order to avoid the substrate 50a from being bent due to an external force, the packaging method of the wafer 60 and the method of combining the substrate 50a with a circuit board in this embodiment are the same as those of the first embodiment. This paper size applies to China National Standard (CNS) A4 specification (210 X. 297 Gongchu) 4 Φ κι Β7 V. Description of the invention (V17)........... As shown in FIG. 5, it is a diagram of the third embodiment of the direct heat radiation type structure of the BGA substrate 50 b of the present invention. In this embodiment, the overall structure of the substrate 50 b is substantially the same as that of the first embodiment. All are given the same number and will not be described in detail. The biggest difference is in heat dissipation .....: ..:-· V---·· ---''--- .i ·. R ·. · -Γ ~ ν.-V- ^ ··· ... ----...-. ··,. ...........-....-.... ... i the bearing portion 512 and the joint portion 513 of the plate 51 do not extend outward, but the pericarial system of the body portion 5 ii extends outward to form a flange, and the resin layer 52 surrounds the heat dissipation plate 51 The periphery of the main body portion 511, that is, the heat radiating plate 51 is embedded in the resin layer 52, and the upper circuit layer 53 is provided on the upper side of the resin layer 52. Table:. _ _.. .. ....-surface, the lower circuit layer 54 is provided on the lower surface of the resin layer 52, and the rest of the substrate 50b is connected And are the same as for the first embodiment of the package wafer 60 and the substrate 50b bonded to the circuit board of the embodiment. Please refer to FIG. 6, which is a diagram of a fourth embodiment of the direct heat dissipation structure of the BGA substrate 50c of the present invention. The BGA substrate 50c of the present invention is a substrate 50c structure (Multi-Chip Modulus) for a multi-chip 60 module. In this embodiment, the overall structure of the substrate 50c is substantially the same as that of the first embodiment. Therefore, the same components are given the same number in the illustration and will not be described in detail. The biggest difference is that this embodiment is a plural Each chip 60 is packaged on the same substrate 50c. As the number of wafers 60 is larger, the function of the substrate 50c will also be improved. In addition, in this embodiment, the method of packaging the wafer 60 and combining the substrate 50c with a circuit board are the same. The first embodiment is the same. ......... Please refer to the seventh circle, which is a diagram of the fifth embodiment of the direct heat dissipation structure of the BGA substrate 50d of the present invention. The overall structure of the substrate 50d is substantially the same as that of the first embodiment. An embodiment is the same, so the same components are given the same number in the illustration and will not be described in detail. The biggest difference is in this implementation (please read the precautions of your face before filling out this page) lk: ·- --- I E--Order! -Line Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)

五： rl.1.111111111:11:11: ,1:1. 發明說明（/Λ例係將二層電路70(Two-Layer Circuit)壓合於上電路層53表 面，其中在上層電路53與二層電路7〇之間具有一層樹脂層 74，而該二層電路70係類似一三明治(Sandwich)結構，包括一第一電路層71和一第二電路層72，在上述二電路層71、 ... .... ... ： 72之間夾具有二層樹脂層73-Γ該二·層電路70具有‘二容置槽- . .. ..... . .. ... .. 75，該容置槽75之深度係到達第二電路層72，該第二電路 層72在容置槽75中包括一導電電路721與一導熱電路722, . .... . . 在上述二電路721、722表面各分別形成有複數個金屬凸塊 ... ... , ... . ... .... 723，該導熱電路722係藉由複數個導熱栓76連結於散熱板 .. ......... ........ ....... ... ... 51之承載部511，該導電電路721係藉由複數個導電栓77 連接於第二電路層71.以及上電路層53。... . .. ' . . ............ . '本實施例之基板5〇d在對晶片60進行封裝時，係將晶片 ........ ....... ... 60結合於基板5〇(1之容置槽75中，其中該晶片60之電路佈 局係藉由金屬凸塊723耦合於二層電路70之第二電路層 72，而晶片60所產生之熱量係藉由金屬凸塊723經過導熱栓 ....... . . . . .... 76、散熱板51傳遞至外界，其餘部分之基板50d結樺以及對 於晶片60之封裝和將該基板60結合於電路板之方式均與第 一實施例相同。 以上所述，係爲本發明BGA基板直接散熱型結構50不 同實施例之詳細說明，本發明與習知技術相較其所增加之優 點包括: 本發明之BGA基板50係利用散熱板51對晶片60進行散 熱’與習知技術一利用導熱栓17對晶片20進行散熱，相 較之下，本發明之散熱板51可提供晶片60散熱之截面積 1 閲 讀 背 意 訂 線 本紙張尺度適用中國國家標準（pNS)A4規格（210 X 297公釐）Five: rl.1.111111111: 11: 11:, 1: 1. Description of the invention (/ Λ example is a two-layer circuit 70 (Two-Layer Circuit) laminated to the surface of the upper circuit layer 53, wherein the upper circuit 53 and the second layer There is a resin layer 74 between the circuits 70, and the two-layer circuit 70 is similar to a sandwich structure, and includes a first circuit layer 71 and a second circuit layer 72. The two circuit layers 71,... ...:: Two resin layers 73-Γ sandwiched between 72. The two-layer circuit 70 has a 'two-receiving slot-.............. 75. The depth of the receiving groove 75 reaches the second circuit layer 72. The second circuit layer 72 includes a conductive circuit 721 and a thermally conductive circuit 722 in the receiving groove 75.... A plurality of metal bumps are formed on the surfaces of the circuits 721 and 722, respectively, ..., ... ... 723, and the heat-conducting circuit 722 is connected to the heat sink by a plurality of heat-conducting bolts 76. .. ......... .............. 51 of the bearing portion 511, the conductive circuit 721 is provided by a plurality of conductive bolts 77 Connected to the second circuit layer 71. and the upper circuit layer 53.... '...... When the substrate 50d is used to package the wafer 60, the wafer 60 is combined with the wafer 60 in the accommodation groove 75 of the substrate 50 (1, where the The circuit layout of the chip 60 is coupled to the second circuit layer 72 of the two-layer circuit 70 through the metal bump 723, and the heat generated by the chip 60 passes through the metal bump 723 through the thermal conductive plug ... ... 76. The heat sink 51 is passed to the outside, and the remaining parts of the substrate 50d and the way of packaging the chip 60 and combining the substrate 60 with the circuit board are the same as the first embodiment. This is a detailed description of different embodiments of the direct heat dissipation structure 50 of the BGA substrate of the present invention. The advantages of the present invention compared with the conventional technology include: The BGA substrate 50 of the present invention uses the heat sink 51 to carry out the wafer 60 Heat dissipation 'and the conventional technology 1 uses a thermally conductive pin 17 to dissipate heat from the chip 20. In contrast, the heat sink 51 of the present invention can provide the cross-sectional area of the chip 60 for heat dissipation. pNS) A4 size (210 X 297 mm)

454S7T 7· A7 B7 經濟部智慧財.產局員工.消費合作社印製 五、發明說明（/J ) . ..... ..... .... . . 較大，散熱效果較佳。 b. 本發明之BGA基板50其散熱板51可以大量製造之後再埋 ...... .... . .. . . 入樹脂層52之中，而習知技術一之導熱栓17必須經過鑽 孔、鍍銅和塞孔等製程，相較之下，本發明之製造成本較 低且可以避免習知技術一之導熱栓17發生Popcorn的現 象。::V: . . .. . . . ... ' '' '' .. .. c. 本發明之BGA基板50係採用〇^叩型式之封裝，而習知 技術二係採用Cavity Down型式，所以下游封裝廠商在對 本衰明明之基板50進行封裝時，不必對基板50之製程步 驟進行變更，此外，本發明之BGA基板5〇係耐晶片6〇與 鍚球62設於不同之側面，因此可以解決習知技術二之基板 . . . .. . 30在安排鍚球23時所遭到的困擾。 .· .............. . . . . 當然，以上所述僅爲本發明BGA基板直接散熱型結構 之較佳實施例’並非用以限制本發明之實施範圍，任何熟習 該項技藝者在不違背本發明之精神所做之修改，均應屬於本 發明之範圍，例如本發明之BGA基板直接散熱型結構對於 上電路層與下電路層之設計上可以是單層電路，或是多層電 路但各電路層之間係利用導電栓相連接，使該基板可以適用 於各種型式之封裝，因此本發明之保護範圍當以下列所述之 申請專利範圍做爲依據。 (請先閱讀背面之注意事項再填寫本頁) 丨裝 •縿 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）454S7T 7 · A7 B7 Printed by the Ministry of Economic Affairs, Smart Assets, Employees of the Production Bureau, and Consumer Cooperatives. 5. Description of Invention (/ J)....... . b. The heat sink 51 of the BGA substrate 50 of the present invention can be buried after being mass-produced......... After processes such as drilling, copper plating, and plugging, in comparison, the present invention has a lower manufacturing cost and can avoid the popcorn phenomenon of the thermally conductive plug 17 of the conventional technology 1. :: V:........ '' '' '' .. .. c. The BGA substrate 50 of the present invention is packaged in the type of ^^, while the conventional technology 2 uses the Cavity Down type. Therefore, the downstream packaging manufacturer does not need to change the process steps of the substrate 50 when packaging the obsolete substrate 50. In addition, the BGA substrate 50 of the present invention is a resistant wafer 60 and the ball 62 is located on different sides. Therefore, it is possible to solve the problem of the second substrate of the conventional technology 2... 30 when the shuttlecock 23 is arranged. ....... Of course, the above is only a preferred embodiment of the direct heat dissipation structure of the BGA substrate of the present invention, and is not intended to limit the scope of implementation of the present invention. Any modification made by those skilled in the art without departing from the spirit of the present invention shall fall within the scope of the present invention. For example, the direct heat dissipation structure of the BGA substrate of the present invention may be designed for the upper circuit layer and the lower circuit layer. A single-layer circuit or a multilayer circuit, but the circuit layers are connected by conductive plugs, so that the substrate can be applied to various types of packaging. Therefore, the scope of protection of the present invention should be based on the scope of patent application described below. . (Please read the precautions on the back before filling out this page) 丨 Loading • 纸张 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)

Claims (1)

經濟部智慧財產局員工消費合作社印製 申請專利範圍 · - · . . - . . - - - . . ': 1. 一種BGA基板直接散熱型結構，包括： 一散熱板，具有一本體部、一承載部和一結合部，其中該 承載部係設於本體部之上方，又該結合部係設於本體部 :之下方且其周圍係向外延伸而形成一凸緣； 一樹脂層，係設於散熱板之本體部外圍； 一上電路層，係設於該樹脂層之上側表面，其中該上電路 層具有複數個打線墊，又該上電路層表面係覆蓋一層綠 漆，並使打ϋ墊暴露於外界; .. ...... ... - 一下電路層，係設於該樹脂層之下側表面，其中該下電路 層具有複數個鍚球墊，又該下電路層表面係覆蓋一層綠 漆，並使鍚球墊暴露於外界；以及 .......... .... ..... .... _____ ： _ 複數個導電拴^貫穿該樹脂層並使上電路層和下電路層 成導通狀態。P 2. 如申請專利範議第]；項所述之BGA基板直接散熱型結 構，當該BGA基板在進行封裝時，該散熱板之承載部係可 裝置晶片，並可藉由複數條金線耦合於該上電路層之打線 墊上。 3. 如申請專利範圍第1項所述之BGA基板直寶雙熱型結 構，當該BGA基板在進行封裝時，該下電路層之鍚球墊表 面係焊上鍚球，並藉由該鍚球結合於電路板之上，可供該 散熱板之結合部直接焊於電路板之上。 4. 如申請專利範圍第2項所述之BGA基板直接散熱型結 .. .. 構’其中所述當該BGA基板在進行封裝時，該基板在晶片 和金線表面係藉由一層封膠加以保護。 本紙張尺度適用中國國家標準(CNS)A4規格（210 X 297^¾楚） I------------裝---------訂··--------線 C C請先閱讀背面之注意事項再填寫本頁) ^4^77 —g8s : S 六、申請專利範圍 \如申請專利範圍第1項所述之BGA基板直接散熱型結 構，其中該基板之散熱板其材質係爲高散熱性、低膨脹係 數之金屬。 6.如申請專利範圍第1項所述之BGA基板直接散熱型結 構’其中該金屬係爲金、鋁、鎳或其合金。 7·如申請專利範圍第；[項所_之BGA基板直接散熱型結 構，其中該基板之散熱材板其材質係爲高散熱性、低膨脹 係數之碳纖杖料。 . . · . 国 8. 如申請專利範圍第1項所述之BGA基板直接散熱型結 • - .... ： 構’其中上述導電栓係以鑽孔、鍍銅以及塞孔等方式製造 而成。 ...... .... ..... ... .... .......... ... ..... 9. 如申請專利範圍第1項所述之Β〇Α基板直接散熱型結 構，其中該散熱板之結合部表面係設有複數個鍚球墊，上 · ...... ... . . 述鍚球墊係可當該BGA基板在進行封裝時焊上鍚球，並藉 由所述鍚球結合於電路板之上。 . .... .......... . .... . . . .... 10. 如申請專利範圍第9墳所述之BGA基板直接散熱型結 構，其中該散熱板之結合部表面係利用一層綠漆加以保護 並使鍚球墊暴露於外界。 U.如申請專利範圍第9項所述之BGA基板直接散熱型結 .. ... 構’其中該散熱板之結合部之鍚球墊表面係鍍上一層鎳金。 12.如申請專利範圍第X項所述之BGA基板直接散熱型結 構’其中上電路層之打線墊與下電路層之鍚球墊表面係鍍 上鎳金。 13·如申請專利範圍第1項所述之BGA基板直接散熱型結 (請先閱讀背面之注音？事項再填寫本頁) 丨叙 -si 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 x —公愛） ' --Intellectual Property Bureau of the Ministry of Economic Affairs printed the scope of patent applications for consumer cooperatives ·-·..--.---.. ': 1. A BGA substrate direct heat dissipation structure, including: a heat sink with a body, a A load-bearing portion and a joint portion, wherein the load-bearing portion is provided above the body portion, and the joint portion is provided below the body portion: and the periphery thereof extends outward to form a flange; a resin layer, provided On the periphery of the main body of the heat sink; an upper circuit layer is provided on the upper side surface of the resin layer, wherein the upper circuit layer has a plurality of wire bonding pads, and the surface of the upper circuit layer is covered with a layer of green paint and snoring The pad is exposed to the outside; .. ...--The lower circuit layer is provided on the lower surface of the resin layer, wherein the lower circuit layer has a plurality of ball pads, and the surface of the lower circuit layer It is covered with a layer of green paint, and the ball pad is exposed to the outside world; and ............... ..... .... _____: _ a plurality of conductive bolts ^ penetrate the resin Layer and put the upper circuit layer and the lower circuit layer into a conducting state. P 2. The direct heat dissipation structure of the BGA substrate as described in item [] of the patent application. When the BGA substrate is being packaged, the bearing portion of the heat dissipation plate can be a chip and a plurality of gold wires can be used. The wiring pad is coupled to the upper circuit layer. 3. As described in item 1 of the scope of the patent application, the BGA substrate is a dual heat structure. When the BGA substrate is being packaged, the surface of the ball pad of the lower circuit layer is soldered with a ball, and the ball The ball is bonded on the circuit board, and the joint of the heat sink can be directly soldered on the circuit board. 4. The direct heat dissipation junction of the BGA substrate as described in item 2 of the scope of the patent application.... The structure is described in the above. When the BGA substrate is being packaged, the substrate is sealed by a layer of sealant on the surface of the wafer and the gold wire. Be protected. This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 ^ ¾chu) I ------------ Installation --------- Order ·· ---- ---- Please read the precautions on the back of the line CC before filling in this page) ^ 4 ^ 77 —g8s: S VI. Patent application scope \ The direct heat dissipation structure of the BGA substrate as described in item 1 of the patent application scope, where The material of the heat dissipation plate of the substrate is a metal with high heat dissipation and low coefficient of expansion. 6. The direct heat dissipation structure of the BGA substrate according to item 1 of the scope of the patent application, wherein the metal is gold, aluminum, nickel, or an alloy thereof. 7. If the scope of the application for patent is No. [], the BGA substrate direct heat dissipation structure, where the material of the heat sink material plate of the substrate is a carbon fiber rod material with high heat dissipation and low expansion coefficient. ... Country 8. The direct heat dissipation junction of the BGA substrate as described in item 1 of the scope of patent application •-....: Structure 'where the above-mentioned conductive bolts are manufactured by drilling, copper plating, plugging, etc. to make. ...... ................. ...................... ... The structure of the BOA substrate direct-dissipating type described above, wherein the surface of the joint of the heat-dissipating plate is provided with a plurality of ball pads, and the above-mentioned ball pads can be used as the BGA. When the substrate is packaged, a ball is soldered, and the ball is bonded to the circuit board by the ball. .. ........... 10. The direct heat dissipation structure of the BGA substrate as described in the ninth grave of the scope of patent application, wherein the heat dissipation plate The surface of the joint is protected by a layer of green paint and the ball pad is exposed to the outside world. U. The direct heat-dissipating junction structure of the BGA substrate as described in item 9 of the scope of the patent application, wherein the surface of the ball pad of the joint of the heat-dissipating plate is plated with nickel-gold. 12. The direct heat dissipation structure of the BGA substrate according to item X in the scope of the patent application, wherein the surface of the wire pad of the upper circuit layer and the ball pad of the lower circuit layer are plated with nickel gold. 13 · The direct heat dissipation junction of the BGA substrate as described in item 1 of the scope of patent application (please read the note on the back? Matters before filling out this page) China National Standard (CNS) A4 specification (21〇x-public love) '- 六、申請專利範圍 r：4bA^l 1 構’其中該散熱板之承載部在其周圍係向外延伸而形成一 :凸緣。 14. 如申請專利範圍第^項所述之BGA基板直接散熱型結 構，其中該上電路層係爲一單層電路。 ·-... . ... .... - - . 15. 如申請專利範圍第1項所述之BGA基板直接散熱型結 構’其中該上電路層係爲一多層電路，且各電路層之間係 . . .......... · . . .. ... 藉由複數個導電栓互相導通。 • ....... ...... ..... . .. .... . . .- . 16. 如申請專利範圍第1項所述之boa基板直接散熱型結 構，其中該下電路層係爲一單層電路。 17. 如申請專利範圍第1項所述之BGA基板直接散熱型結 構’其中該下電路層係爲一多層電路，且各電路層之間係 藉由複數個導電栓互相導通。 ....... . ...... ...... ... 18. 如申請專利範圍第丄項所述之BGA基板直接散熱型結 .... ..... .... .... . 搆，其中該散熱板係鍍上一層鎳金，並直接結合於電路板 之上。: ----------11 Γ/ν^---------^ · I------1 ί ^ ί. (請先閱讀背面之注咅？事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 準 標 家 國 (21 格 規 *" ,)公 :7 9Sixth, the scope of the patent application r: 4bA ^ l 1 structure, wherein the bearing portion of the heat sink plate extends outward to form a flange. 14. The direct heat dissipation structure of the BGA substrate as described in item ^ of the patent application scope, wherein the upper circuit layer is a single-layer circuit. · -.... ... ...--. 15. The direct heat dissipation structure of the BGA substrate as described in item 1 of the scope of patent application, wherein the upper circuit layer is a multilayer circuit, and each circuit The layers are connected to each other via a plurality of conductive bolts. • ....... .............. 16. As a direct heat dissipation structure of the boa substrate as described in item 1 of the scope of patent application, The lower circuit layer is a single-layer circuit. 17. The direct heat dissipation structure of the BGA substrate according to item 1 of the scope of the patent application, wherein the lower circuit layer is a multi-layer circuit, and the circuit layers are electrically connected to each other by a plurality of conductive bolts. ....... ............. 18. Direct heat dissipation junction of BGA substrate as described in item 丄 of the patent application scope .................. .... ..... The heat sink is plated with nickel-gold and directly bonded to the circuit board. : ---------- 11 Γ / ν ^ --------- ^ · I ------ 1 ί ^ ί. (Please read the note on the back? Matters before (Fill in this page) The Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs printed the standard home country (21 standards * "), public: 7 9
TW088108336A 1999-05-21 1999-05-21 Direct heat dissipating type structure of BGA substrate TW454277B (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9756721B2 (en) 2015-12-23 2017-09-05 Global Unichip Corporation Multilayer laminated substrate structure
US10998258B2 (en) 2019-08-12 2021-05-04 Unimicron Technology Corp. Circuit carrier and manufacturing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9756721B2 (en) 2015-12-23 2017-09-05 Global Unichip Corporation Multilayer laminated substrate structure
US10998258B2 (en) 2019-08-12 2021-05-04 Unimicron Technology Corp. Circuit carrier and manufacturing method thereof

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