TW452971B

TW452971B - Manufacturing method of bottle-shaped deep trench

Info

Publication number: TW452971B
Application number: TW88123112A
Authority: TW
Inventors: Ming-Hung Lin; Jin-Ruei Li; Nian-Yu Tsai
Original assignee: Promos Technologies Inc; Mosel Vitelic Inc; Siemens Ag
Priority date: 1999-12-28
Filing date: 1999-12-28
Publication date: 2001-09-01

Abstract

This invention provides the manufacture method for bottle-shaped deep trench in a semiconductor substrate, which consists of: proceeding a first etch step using hydrogen bromide, nitrogen trifluoride as plasma gas composition to remove native oxide on the semiconductor substrate; proceeding a second etch step using hydrogen bromide, nitrogen trifluoride and pre-mixed helium/oxygen as plasma gas composition to form a neck profile in the semiconductor substrate, in which the flow rate of hydrogen bromide and nitrogen trifluoride used in the second etch step is greater than that of the first etch step; proceeding a third etch step using hydrogen bromide, nitrogen trifluoride pre-mixed helium/oxygen and chlorine as plasma gas composition to etch the semiconductor substrate underneath the neck profile to form a bottom profile and thus complete the bottle-shaped deep trench structure, in which the flow rate of hydrogen bromide, nitrogen trifluoride and pre-mixed helium/oxygen used in the third etch step is greater than that of the second etch step. The inventive method can increase depth and width of the bottle-shaped deep trench and thus the surface area of the bottle-shaped deep trench increases.

Description

452971 五、發明說明（i) 本發明係有關於一種深溝槽之製造方法，特别有關於一種瓶型深溝槽之製造方法。近年來，隨著積體電路集積度的增加，半導體製程設計亦朝向縮小半導體元件尺寸以提高密度之方向發展，以目前廣泛使用之動態隨機存取記憶體（DRAM : dynamic random access memory)為例，64M DRAM製程已從0.35um 轉換至0.3um以下，而128M DRAM或256M DRAM則更朝向 0,2um以下發展。由於電容器基本上是由隔著一絕緣物質之兩導電層表面（即電極板）構成，而電容器儲存電荷之能力係由三種物理特徵決定，即（1)絕緣物質之厚度；（2 )電極板之表面積；及（3)絕緣物質之電氣性質。其中為了使記憶體電路能包含大量之記憶胞，記憶胞之基底面積必須不斷減少以提高密度，同時，記憶胞電容之電極板部份則仍必須有足夠之表面積以儲存充分之電荷。 —般而言，高密度記憶體係具有兩種不同的電容器形成技術’其中一種為三維（three-dimension)之堆叠式電谷（STC : stacked capacitor cell)，另一種為溝槽式電容。例如皇冠狀（crown)堆疊電容結構，其利用矽晶；存取裝置之上方空間來形成電容電極板，而溝槽式電谷則利用基底主動區（active region)中之深溝槽來形成 $ $ @ #區。本發明之技術則是溝槽式電容技術的延伸。然而’隨著DRAM製程的持續縮小化，深溝槽之孔徑大452971 V. Description of the invention (i) The present invention relates to a method for manufacturing a deep groove, and more particularly to a method for manufacturing a bottle-shaped deep groove. In recent years, with the increase of the integration degree of integrated circuits, the design of semiconductor processes has also developed toward reducing the size of semiconductor elements to increase the density. Take the currently used dynamic random access memory (DRAM) as an example. The 64M DRAM process has been switched from 0.35um to less than 0.3um, while 128M DRAM or 256M DRAM is moving towards 0,2um. The capacitor is basically composed of two conductive layer surfaces (ie, electrode plates) separated by an insulating material, and the ability of the capacitor to store charge is determined by three physical characteristics, namely (1) the thickness of the insulating material; (2) the electrode plate Surface area; and (3) the electrical properties of the insulating substance. In order for the memory circuit to contain a large number of memory cells, the base area of the memory cells must be continuously reduced to increase the density. At the same time, the electrode plate portion of the memory cell capacitor must still have sufficient surface area to store sufficient charge. In general, high-density memory systems have two different capacitor formation technologies. One is a three-dimension stacked capacitor valley (STC), and the other is a trench capacitor. For example, a crown-shaped stacked capacitor structure uses silicon crystals; the space above the access device forms a capacitor electrode plate, and the trench-type valley uses deep trenches in the active region of the substrate to form a $$ @ #Area. The technology of the present invention is an extension of the trench capacitor technology. However, as the DRAM process continues to shrink, the diameter of deep trenches is large.

^52971 五、發明說明（2) '- J亦隨之限縮’當溝槽之縱寬比（aspect rat io)已超過 • 1時’作為電容儲存區之深溝槽將因而受限，此外，合里係與電容電極板之表面積成正比，而溝槽電容 5板表面積為溝槽之深度與溝槽圓周面積之乘積，溝 :。周面積則又與溝槽之孔徑有Μ，換言之，當製程技術 =‘ 2um縮小至〇, 18um時，溝槽之孔徑隨之變小，連帶使 '槽電谷難以得到足夠之電容表面積以使電容量維持於 4 〇 pF左右。再者’欲形成具有較小臨界尺寸之深溝槽，便必須選擇高縱寬比之方式進行蝕刻，同時當溝槽臨界尺寸愈小，即愈難使溝槽保持垂直輪廓，一般溝槽之孔徑係愈趨於基底底部愈加窄化，此亦為目前蝕刻技術所面臨之挑戰。以傳統製程為例，如第1圖所示，首先係提供一由矽或其他材料組成之半導體基底1〇以製造所欲之半導體裝置，例如動態隨機存取記憶體等，其次，於半導體基底上形成一墊堆疊層（pad stack layer)l5，例如以化學氣相沈積製程依序沈積氮化矽層12於半導體基底1〇表面、及沈積一絕緣層如硼矽玻璃層1 4於氮化矽層1 2表面，塾堆叠層 1 5在此係作為一用於深溝槽蝕刻步驟之硬罩幕。另外，可在半導體基底10與氮化硬層12之間形成一墊氧化層I〗以減 >、應力及促進附著效果。接著’於塾堆叠層15内形成一罩幕開口 20以暴露出部分半導體基底表面，例如可先利用光阻材料之塗佈及曝光顯影等微影製程形成一光阻圖案丨6於墊堆疊層1 5表面，然後再利甩反應性離子蝕刻製程或電漿 4 52 9 71 五、發明說明（3) 姓刻製程等蝕刻墊堆疊層丨5以形成一罩幕開口 2 〇。其次’連續進行數階段以不同蝕刻參數控制的溝槽蝕刻步驟如採用非等向性蝕刻製程，在此則以反應性離子姓刻製程為例。其中，由於罩幕開口 20可能會使部分半導體矽基底因暴路於外在環境下而形成原生氧化層（native oxide 1 ay er) ’故有必要先進行一道原生氧化層之蝕刻階段，例如利用溴化氫（ΗΒιτ)、三氟化氮UF3)為主要電漿氣體來源 (plasma gas composition)以钱刻去除（breakthrough)可能出現的原生氧化層。其钱刻參數則如下列所示：2 〇至 50mtorr的壓力，較佳為25mtorr ;500至900w的RF功率，較佳為60 0w ; 10至40高斯之磁場，較佳為15高斯；溴化氫 (HBr)與三氟化氮（NF3)之流量（sccm)比約為2〇 : 5 ;蝕刻時間約為20至40秒，較佳者為25秒。其次’進行瓶型溝槽之頸部輪廓（neck profiie)之蝕刻階段’例如，利用溴化氫（HBr)、三氟化氮（NF3)以及預混合之氦/氧（He/02)為主要電漿氣體來源以蝕刻去除露出之部分半導體矽基底，形成一具有傾斜頂部（tapered t〇p por t i on )且深度約為1 · 2 um之頸部輪廓2 2。其蝕刻參數則如下列所示：80至llOmtorr的壓力，較佳為i〇〇mtorr ; 丨 700至900w的RF功率，較佳為800w ;80至110高斯（Gauss) 之磁場’較佳為100高斯；溴化氫（HBr )、三氟化氮（NF3) 與氦/氧（He/02)之流量（seem)比約為87 : 13 : 35 ;氦/氧 (He/02 )之混合比約為7 0 % : 3 0 % ;蝕刻時間約為9 0至11 0^ 52971 V. Description of the invention (2) '-J will also be reduced accordingly.' When the aspect ratio of the trench (aspect rat io) has exceeded • 1 ', the deep trench as a capacitor storage area will be limited. In addition, The closure is proportional to the surface area of the capacitor electrode plate, and the surface area of the trench capacitor 5 plate is the product of the depth of the trench and the circumferential area of the trench. The peripheral area is again M with the hole diameter of the trench. In other words, when the process technology = '2um is reduced to 0, 18um, the hole diameter of the trench will become smaller, which will make it difficult for the' groove valley 'to obtain a sufficient capacitor surface area so that The capacitance is maintained at about 40 pF. Furthermore, to form deep trenches with a smaller critical dimension, it is necessary to choose a method of etching with a high aspect ratio. At the same time, the smaller the critical dimension of the trench, the more difficult it is to maintain the vertical profile of the trench. The more the system tends to narrow the bottom of the substrate, this is also a challenge facing the current etching technology. Taking the traditional process as an example, as shown in Fig. 1, a semiconductor substrate 10 composed of silicon or other materials is first provided to manufacture a desired semiconductor device, such as a dynamic random access memory, etc., and secondly, a semiconductor substrate A pad stack layer 15 is formed thereon, for example, a silicon nitride layer 12 is sequentially deposited on the surface of the semiconductor substrate 10 by a chemical vapor deposition process, and an insulating layer such as a borosilicate glass layer 14 is deposited on the nitride. The surface of the silicon layer 12 and the plutonium stack layer 15 are used here as a hard mask for the deep trench etching step. In addition, a pad oxide layer I can be formed between the semiconductor substrate 10 and the nitrided hard layer 12 to reduce > stress and promote adhesion. Next, a mask opening 20 is formed in the stack layer 15 to expose part of the semiconductor substrate surface. For example, a photoresist pattern can be formed by using a photolithography process such as coating and exposure development of the photoresist material. 6 On the pad stack layer 1 5 surface, and then flip the reactive ion etching process or plasma 4 52 9 71 V. Description of the invention (3) Etching pad stack layers such as last name engraving process 5 to form a curtain opening 2 0. Secondly, the trench etching step controlled by different etching parameters in several stages is performed continuously, such as using an anisotropic etching process. Here, the reactive ion surname etching process is used as an example. Among them, since the mask opening 20 may cause a part of the semiconductor silicon substrate to form a native oxide layer (native oxide 1 ay er) due to being exposed to the external environment, it is necessary to first perform an etching step of the native oxide layer, such as using Hydrogen bromide (ΗΒιτ), nitrogen trifluoride (UF3) is the main plasma gas composition, and the primary oxide layer that may appear is broken through. The money engraving parameters are as follows: pressure of 20 to 50mtorr, preferably 25mtorr; RF power of 500 to 900w, preferably 60 0w; magnetic field of 10 to 40 Gauss, preferably 15 Gauss; bromination The flow (sccm) ratio of hydrogen (HBr) to nitrogen trifluoride (NF3) is about 20: 5; the etching time is about 20 to 40 seconds, and preferably 25 seconds. Secondly, the “etching stage of the neck profiie of the bottle groove” is performed, for example, using hydrogen bromide (HBr), nitrogen trifluoride (NF3), and pre-mixed helium / oxygen (He / 02) as the main components. The plasma gas source is used to etch and remove a part of the exposed semiconductor silicon substrate to form a neck profile 22 having a tapered top (tapered top por ti on) and a depth of about 1.2 μm. The etching parameters are as follows: a pressure of 80 to 110 mtorr, preferably 100 mtorr; an RF power of 700 to 900 w, preferably 800 w; a magnetic field of 80 to 110 Gauss (preferably 100) Gauss; the flow (seem) ratio of hydrogen bromide (HBr), nitrogen trifluoride (NF3) and helium / oxygen (He / 02) is about 87:13:35; the mixing ratio of helium / oxygen (He / 02) About 70%: 30%; Etching time is about 90 to 110

第7頁 452971 五、發明說明（4) 秒，較佳者為9 5秒广後’ 1參閱第2圖，進行瓶型溝槽之底 ⑽㈣flIe)之轴刻階段’例如’繼續利廓 (ΗΒι·)、三氟化氮（NF3)以及預混合之氦/ H匕虱 I: i ϊ來源以自頸部輪廓22繼續蝕刻去除露出之部^ ΐ 右丨会^ 土底，形成一深度約為6· 3 Um之底部輪廓26。其蝕刻參數則如下列所示：11〇的壓力，較佳、 =51^〇1^;6 00至100(^的叮功率，較佳為1〇〇(^;4〇至6〇鬲，（Gauss)之磁場，較佳為5〇高斯；溴化氫（HBr)、三氟化氮（NF3)與氦/氧（He/〇2)之流量（sccm)比約為87 :13 : 3 5 ’钱刻時間約為4 5 〇至5 〇〇秒’較佳者為4 8 5秒。前述傳統技術之問題在於進行瓶型溝槽之底部輪廓 (bottom profile)之蝕刻階段時’由於此蝕刻製程受溝槽表面孔徑大小和溝槽深度之限制，因此僅能形成錐形深溝槽’而無法形成可以擴大電容儲存區表面積之深溝槽。此外’一種傳統瓶形電容製程，係由T. Ozaki等人所 & 出’參見（0 · 2 2 8 u m T r e n c h C e 1 1 T e c h η ο 1 〇 g i e s w i t h bottle Shaped Capacitor for 1Gbit DRAMs,by T.Ozaki， et al， IEDM， 95， pp66卜664， 1995 )，其中’瓶形電容之製造方法如下所述，首先在溝槽上部形成 —厚度約80nm之環形氧化層（collar oxide layer )，然後執行氧化罩幕和原生氧化層之去除等電容製程，此時，環形氧化層厚度亦因此減少至約5 0 nm左右，接著沈積一複晶矽層’並於同環境下摻雜磷離子，隨之藉由爐管之熱退Page 7 452971 V. Description of the invention (4) seconds, preferably 9 5 seconds. After 1 ', refer to Figure 2 and perform the axis engraving phase of the bottom of the bottle-shaped groove (flIe). For example, continue to profile (ΗΒι ·), Nitrogen trifluoride (NF3) and pre-mixed helium / H dagger I: i ϊ source to continue to etch from the neck contour 22 to remove the exposed part ^ 右 right 丨 will ^ soil bottom, forming a depth of about 6.3 Um bottom contour 26. The etching parameters are as follows: a pressure of 11 °, preferably, = 51 ^ 〇1 ^; a biting power of 600 to 100 °, preferably 100 ° (40; 60 °, (Gauss) magnetic field is preferably 50 Gauss; hydrogen bromide (HBr), nitrogen trifluoride (NF3) and helium / oxygen (He / 〇2) flow (sccm) ratio is about 87: 13: 3 5 'Money engraving time is about 450 to 5000 seconds', preferably 485 seconds. The problem with the aforementioned conventional technique is that the bottom profile of the bottle-shaped groove is etched during the etching phase. The etching process is limited by the surface diameter of the trench and the depth of the trench, so it can only form a tapered deep trench, but not a deep trench that can increase the surface area of the capacitor storage area. In addition, a traditional bottle-shaped capacitor process is made by T. Ozaki et al. &Amp; Out 'see (0 · 2 2 8 um Trench C e 1 1 T ech η ο 1 〇gies with bottle Shaped Capacitor for 1Gbit DRAMs, by T. Ozaki, et al, IEDM, 95, pp66 664, 1995), where the manufacturing method of the bottle capacitor is described as follows, firstly, a ring-shaped oxygen with a thickness of about 80 nm is formed in the upper part of the trench. And then perform a capacitive process such as removing the oxide mask and the native oxide layer. At this time, the thickness of the annular oxide layer is reduced to about 50 nm, and then a polycrystalline silicon layer is deposited and then Doped with phosphorus ions in the same environment, followed by the heat dissipation of the furnace tube

第8頁 4 52 9 7 1 五、發明說明（5) ------- 火製程將磷離子摻雜入溝槽之電容部側壁，環狀氧化層則可阻止磷離子摻雜入溝槽上部，然後利周化學性乾蝕刻去除複晶矽層二同時在環狀氧化層下方之溝槽直徑也因此而擴大。然而前述傳統技術之問題在於，矽基底與摻雜離子之複晶矽層的蝕刻選擇比並未較其他材質例如氧化層等為佳，因此，在半導體裝置尺寸曰益縮小的情形下，度並不符需求。、有鑑於此，本發明之目的即為了解決上述問題，而提出一種瓶型深溝槽之製造方法，適用於一半導體基底，其包括：進行一第一蝕刻階段’其以溴化氫、三氟化氮為；漿氣體組成物，蝕刻去除在半導體基底上之原生氧化物；進=一〃第二蝕刻階段，其以溴化氫、三氟化氮、及預混合之氦/氧為電漿氣體組成物，蝕刻半導體基底以形成一部輪廓’其中，第二蝕刻階段之溴化氫、2氟化氮流量古於第一蝕刻階段之溴化氫、三氟化氮流量；進行一第三: 刻階段，其以溴化氫、三氟化氮、預混合之氦/氧、及氣為電漿·氣體組成物’蝕刻頸部輪廓下之半導體基底以形、成一底部輪廓，完成瓶型深溝槽之製造，其中，溴化氫、一氟化氮和預混合之氦/氧流量高於第二钱刻階段之溴化氮、二氟化氮和預混合之氦/氧流量。如此，可增加瓶深溝槽之深度及寬度’並使瓶型深溝槽之表面積隨之增加。曰為讓本發明之上述和其他目的、特徵、和優點能更顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳Page 8 4 52 9 7 1 V. Explanation of the invention (5) ------- Phosphorous ions are doped into the sidewall of the capacitor portion of the trench during the fire process, and the ring-shaped oxide layer can prevent phosphorus ions from being doped into the trench. In the upper part of the trench, a chemical dry etching is performed to remove the polycrystalline silicon layer. At the same time, the diameter of the trench under the annular oxide layer is also enlarged. However, the problem with the aforementioned conventional technology is that the etching selection ratio between the silicon substrate and the ion-doped polycrystalline silicon layer is not better than that of other materials such as oxide layers. Therefore, when the size of semiconductor devices is shrinking, Does not meet demand. In view of this, the purpose of the present invention is to solve the above-mentioned problems, and propose a method for manufacturing a bottle-shaped deep trench, which is suitable for a semiconductor substrate, which includes: performing a first etching stage, which uses hydrogen bromide, trifluoro Nitrogen is: a plasma gas composition that is etched to remove the native oxide on the semiconductor substrate; in a second etching stage, it uses hydrogen bromide, nitrogen trifluoride, and pre-mixed helium / oxygen as the plasma A gas composition that etches a semiconductor substrate to form a contour. Among them, the flow of hydrogen bromide and nitrogen fluoride in the second etching stage is greater than the flow of hydrogen bromide and nitrogen trifluoride in the first etching stage; : In the engraving stage, it uses hydrogen bromide, nitrogen trifluoride, pre-mixed helium / oxygen, and gas as the plasma and gas composition to etch the semiconductor substrate under the neck contour to form a bottom contour to complete the bottle shape. In the manufacture of deep trenches, the flow of hydrogen bromide, nitrogen monofluoride, and pre-mixed helium / oxygen is higher than the flow of nitrogen bromide, nitrogen difluoride, and pre-mixed helium / oxygen at the second stage. In this way, the depth and width of the deep groove of the bottle can be increased and the surface area of the deep groove of the bottle shape can be increased accordingly. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for details.

第9頁 452971 五、發明說明（6) 細說明如下：圖式簡單說明其顯示傳統之一種其顯示本發明之一第1至2圖為一半導體結構剖面圖瓶塑深溝槽之製造方法實施例。第3至6圖為一半導體結構剖面圖種瓶型深溝槽之製造方法實施例。第7圖為一半導體結構判量下之瓶龍溝槽之外觀輪廊面圖，其顯示在不同氯氣流 [符號說明] 化物2 iln底备11、11〇〜墊氧化物層；12、12°〜墊氮化物層，14、14〇〜氧化物層；15、15〇〜墊堆叠層；16、 160〜光阻層，20、200〜罩幕開口； 22、22〇〜頸部輪廓； 240、260〜底部輪廓；241、26卜底部輪廓側實施例首先凊參閱第3至7圖’其顯示本發明之一實施例之製造流程。 ' 依據第3圖，其係顯示本發明之起始步驟。其中，基底1〇〇為一半導體材質，例如由矽材質（siliC0n )組成，為方便說明起見’在此以一矽基底為例。首先’起始步驟為如第3圖所示’於提供一由矽或其他材料組成之半導體基底100後，接著於半導體基底1〇〇上形成塾堆疊層（pad s tack 1 ayer ) 1 5 0，例如以化學氣相沈積製程依序沈積氮化矽層12〇於半導體基底1〇〇表面、及沈積一絕緣層如硼矽破璃層1 4 0於氮化矽層1 2 0表面，墊堆Page 9 452971 V. Description of the invention (6) A detailed description is as follows: The drawing briefly illustrates a traditional one which shows one of the present invention. FIGS. 1 to 2 are cross-sectional views of a semiconductor structure. . 3 to 6 are cross-sectional views of a semiconductor structure. An embodiment of a manufacturing method of a bottle-shaped deep trench. FIG. 7 is an appearance contour view of a bottle dragon trench measured by a semiconductor structure. It is shown in different chlorine gas streams. [Symbol description] Compound 2 iln with a base layer 11, 11, 10 ~ pad oxide layer; 12, 12 ° ~ pad nitride layer, 14, 14 ~~ oxide layer; 15, 15 ~~ pad stack layer; 16, 160 ~ photoresist layer, 20, 200 ~ mask opening; 22, 22 ~ neck contour; 240, 260 ~ bottom outline; 241, 26. Embodiments of the bottom profile side. First, refer to Figs. 3 to 7 ', which shows a manufacturing process of an embodiment of the present invention. 'According to Figure 3, it shows the initial steps of the invention. The substrate 100 is made of a semiconductor material, for example, it is made of silicon material (silicon). For convenience of description, a silicon substrate is used as an example here. First, the initial step is as shown in FIG. 3. After a semiconductor substrate 100 composed of silicon or other materials is provided, a pad stack layer (pad sack 1 ayer) 1 50 is formed on the semiconductor substrate 100. For example, in a chemical vapor deposition process, a silicon nitride layer 12 is sequentially deposited on the surface of the semiconductor substrate 100, and an insulating layer such as a borosilicate glass break layer 14 is deposited on the surface of the silicon nitride layer 120, and a pad is formed. stack

第10頁 452971 五、發明說明（7) ~— 疊層1 50在此係作為一用於深溝槽蝕刻步驟之硬罩幕。另外，可在半導體基底1 〇〇與氮化矽層丨2〇之間形成一墊氧化層1 1 0以減少應力及促進附著效果。接著，請參閱第4圖，於墊堆疊層150内形成一罩幕開口 2。。以暴露出部分半導體基底表面，例如可先成利用罩光幕：材料之塗佈及曝光顯影等微影製程形成一光阻圖案16〇於墊堆疊層1 5 0表面’然後再利用反應性離子蝕刻製程或電漿蝕刻製程等蝕刻墊堆疊層1 5 〇以形成一罩幕開口 2 〇〇。其次，於去除剩餘之光阻圖案1 6 〇後，連續進行數階段以不同蝕刻參數控制的溝槽蝕刻步驟如採用非等向性蝕刻製程’在此則以反應性離子钱刻製程為例。請參閱第5圖’首先由於罩幕開口 2〇〇可能會使部分半導體矽基底因暴露於外在環境下而形成原生物質，如原生氧化層（native oxide layer)，故可先進行一道原生氧化層之蝕刻階段，例如利用溴化氫（HBr)、三氟化氮（NF3)為主要電漿氣體來源（plasma gas composition)以#刻去除 (breakthrough)可能出現的原生氧化層。其蝕刻參數則如下列所示：20至SOmtorr的壓力，較佳為25mtorr ;500至 90 0w的RF功率，較佳為60 0w ; 10至40高斯之磁場，較佳為 15高斯；溴化氫（HBr)與三氟化氮（NF3)之流量（seem)比約' 為20 : 5 ;蝕刻時間約為20至40秒，較佳者為25秒。其次，進行瓶型溝槽之頸部輪廓（neck profile)之钱刻階段，例如，利用溴化氫（HBr)、三氟化氮（NTF 3 )以及預混合之氦/氧（He/02)為主要電漿氣體來源以蝕刻去除露出Page 10 452971 V. Description of the invention (7) ~-The stack 1 50 is used here as a hard mask for the deep trench etching step. In addition, a pad oxide layer 110 can be formed between the semiconductor substrate 100 and the silicon nitride layer 20 to reduce stress and promote adhesion. Next, referring to FIG. 4, a mask opening 2 is formed in the pad stacking layer 150. . In order to expose part of the surface of the semiconductor substrate, for example, a light-shielding curtain can be used first: a photolithographic process such as coating of materials and exposure and development to form a photoresist pattern 160 on the surface of the pad stack layer 150 and then use reactive ions. An etching pad or a plasma etching process is used to stack 150 layers to form a mask opening 2000. Secondly, after removing the remaining photoresist pattern 160, several steps of trench etching steps controlled by different etching parameters are successively performed. For example, an anisotropic etching process is used. Here, the reactive ion money process is used as an example. Please refer to FIG. 5 'First, since the opening of the mask 200 may cause some semiconductor silicon substrates to form native materials due to exposure to the external environment, such as a native oxide layer, a primary oxidation may be performed first. In the etching stage of the layer, for example, hydrogen bromide (HBr) and nitrogen trifluoride (NF3) are used as the main plasma gas composition (plasma gas composition) in order to break through the possible primary oxide layer. The etching parameters are as follows: a pressure of 20 to SOmtorr, preferably 25 mtorr; an RF power of 500 to 900 0w, preferably 60 0w; a magnetic field of 10 to 40 Gauss, preferably 15 Gauss; hydrogen bromide The ratio (seem) of the flow rate (HBr) to nitrogen trifluoride (NF3) is about 20: 5; the etching time is about 20 to 40 seconds, preferably 25 seconds. Second, the neck profile of the bottle groove is performed, for example, using hydrogen bromide (HBr), nitrogen trifluoride (NTF 3), and pre-mixed helium / oxygen (He / 02) As the main plasma gas source to remove the exposure by etching

第11頁 452971 五、發明說明（8) 之部分半導體石夕基底，形成一具有傾斜頂部（tapered top portion)且深度約為丨· 2 um之頸部輪廓220 〇其蝕刻參數則如下列所示：80至11〇1111;〇1'1'的壓力，較佳為1〇〇1111:〇1'1·; 700至900w的RF功率，較佳為8〇〇w ; 80至110高斯（Gauss) 之磁場，較佳為1〇〇高斯；溴化氫（HBr)、三氟化氮（NF3) 與氦/氧（He/02)之流量（sccm)比約為87 : 1 3 : 35 ;氦/氧 (He/02)之混合比約為70% : 30% ;蝕刻時間約為90至110 秒，較佳者為9 5秒。然後，請參閱第6圖，進行瓶型溝槽之底部輪廓 (bottom prof i le)之蝕刻階段，例如，以溴化氫（HBr)、三氟化氮（NF3)、預混合之氦/氧（He/02)及氯（C12)為主要電漿氣體來源以自頸部輪廓2 2 0繼續蝕刻去除露出之部分半導體矽基底’形成一底部輪廓26 0。其中，為了擴大底部輪廓260 ’必須增加此蝕刻階段的橫向蝕刻（lateral etch)能力’因此其蝕刻參數主要調整為將溴化氫（HBr)、三氟化氮（NF3)、與氦/氧（He/02)之流量比變更為約113 土 12 :17±2 :46±5 ’如此可產生下列效果： (a )增加氣氣，以增加等向蝕刻能力，擴大底部輪廢 260 〇 (b) 增加三氟化氮（NF3)之流量以減少底部輪廓260側壁261之聚合物（Polymer)的生成，增加橫向蝕刻的能力。 (c) 增加溴化氫（HBr)之流量，增加橫向蝕刻的能力。 (d) 增加預混合之氦/氧（H e / 0 2 )之流量，避免過度增加橫向蝕刻的能力。Page 11 452971 V. Description of the invention (8) Part of the semiconductor stone substrate, forming a neck profile 220 with a tapered top portion and a depth of about 丨 · 2 um. The etching parameters are as follows : 80 to 11〇1111; 〇1'1 'pressure, preferably 1001111: 〇1'1 ·; RF power of 700 to 900w, preferably 800w; 80 to 110 Gauss (Gauss ) Magnetic field, preferably 100 Gauss; hydrogen bromide (HBr), nitrogen trifluoride (NF3) and helium / oxygen (He / 02) flow (sccm) ratio of about 87: 1 3: 35; The mixing ratio of helium / oxygen (He / 02) is about 70%: 30%; the etching time is about 90 to 110 seconds, preferably 95 seconds. Then, please refer to Fig. 6 to perform the bottom profiling of the bottle groove, for example, using hydrogen bromide (HBr), nitrogen trifluoride (NF3), and pre-mixed helium / oxygen. (He / 02) and chlorine (C12) are the main plasma gas sources, and the exposed portion of the semiconductor silicon substrate is removed by etching from the neck contour 2 2 0 to form a bottom contour 26 0. Among them, in order to expand the bottom profile 260 'the lateral etch capability of this etching stage must be increased', so its etching parameters are mainly adjusted to hydrogen bromide (HBr), nitrogen trifluoride (NF3), and helium / oxygen ( He / 02) flow rate ratio is changed to about 113 soil 12: 17 ± 2: 46 ± 5 'This can produce the following effects: (a) increase the gas to increase the isotropic etching ability, expand the bottom wheel waste 260 〇 (b ) Increasing the flow of nitrogen trifluoride (NF3) to reduce the generation of polymer (Polymer) on the side wall 261 of the bottom profile 260 and increase the ability of lateral etching. (c) Increase the flow of hydrogen bromide (HBr) and increase the ability to etch laterally. (d) Increase the flow of pre-mixed helium / oxygen (H e / 0 2) to avoid excessively increasing the ability to etch laterally.

第12頁 4297 1 五、發明說明¢9) 至於在本實施例中，調整後之較佳蝕刻參數如下列所示：110至130nitorr的壓力，較佳為125mt〇rr ; 6 0 0至 1 00 0w的RF功率’較佳為looow ;40至55高斯（Gauss)之磁場’較佳為50高斯；溴化氫（HBr)、三氟化氮（NF3)、與氦 / 氧（He/02)之流董分別約為i7sccm : ii3sccm : 46sccm，餘刻時間約為4 0 0至5 0秒，較佳者為4 4 0秒。其中，請參閱第7圖’其顯示在以溴化氫（HBr)、三氟化氮（NF3)、預混合之氦/氧（He/〇2)為主要電漿氣體來源中加入氣氣的效果’如第7圖所示，其顯示在主要電漿氣體來源中未加入氣氣（〇 sccm)及分別加入不同流量之氣氣 (lOsccm、25sccm、40sccm)時之溝槽輪廓（profiie)，以比較不同氣氣流量所產生之不同溝槽寬度。其中，此寬度被定義在溝槽底部之上方1.5um處，亦即溝槽之最寬處，因此’在亂氣流量分別為Osccm、10sccm、25sccm、 40sccm時，其寬度值分別約為160um、213um、296um、及 333um ’亦即’隨著氣氣流量的增加，此溝槽側壁亦隨之橫向擴大。其中，前述氣氣流量控制係依據各瓶型深溝槽之間距容許度而定，在不致使各瓶型深溝槽接觸的情況下，提高氯氣流量可橫向擴大瓶型深溝槽之側壁。同時，由於加入氣氣來進行深溝槽姓刻可減少聚合物（ρ ο 1 y m e r)的殘留，故相對可減少乾式清潔所需時間，並縮短乾式清潔週期和預防保養週期。此外，於完成前述實施例之瓶型深溝槽之後，尚可接Page 12 4297 1 V. Description of the invention ¢ 9) As for the preferred etching parameters after adjustment in this embodiment are as follows: a pressure of 110 to 130nitorr, preferably 125mt0rr; 6 0 to 1 00 RF power of 0w is preferably looow; magnetic field of 40 to 55 Gauss is preferably 50 Gauss; hydrogen bromide (HBr), nitrogen trifluoride (NF3), and helium / oxygen (He / 02) The current directors are about i7sccm: ii3sccm: 46sccm, and the remaining time is about 400 to 50 seconds, and the preferred time is about 440 seconds. Among them, please refer to FIG. 7 ', which shows that the gas is added to the main plasma gas source using hydrogen bromide (HBr), nitrogen trifluoride (NF3), and pre-mixed helium / oxygen (He / 〇2). The effect 'is shown in FIG. 7, which shows the groove profile (profiie) when no gas gas (0sccm) is added to the main plasma gas source and gas gases (lsccm, 25sccm, 40sccm) with different flow rates are respectively added, To compare the different groove widths produced by different gas flow rates. Among them, this width is defined at 1.5um above the bottom of the trench, which is the widest point of the trench. Therefore, when the turbulent gas flow is Osccm, 10sccm, 25sccm, and 40sccm, the width values are about 160um, 213um, 296um, and 333um 'that is,' as the air flow increases, the side walls of this trench also expand laterally. Among them, the aforementioned gas flow control is based on the tolerance between the deep grooves of each bottle type. Without causing the deep grooves of each bottle to contact each other, increasing the chlorine gas flow can laterally enlarge the sidewall of the deep grooves of the bottle type. At the same time, because the addition of air to carry out deep groove engraving can reduce the polymer (ρ ο 1 y m e r) residue, it can relatively reduce the time required for dry cleaning, and shorten the dry cleaning cycle and preventive maintenance cycle. In addition, after completing the bottle-shaped deep groove of the foregoing embodiment,

第13頁 452971 五、發明說明（10) 續之後的傳統例而言，可藉存區。而由於槽之基底侧壁電各儲存區面由於本發而以此形成之需求’甚至是本發明之電容其在有限之記同時’本發明述者’其能由且本發明之結雖然本發以限定本發明神和範圍内，護範圍當視後半導體製程此瓶型深溝本實施例之表面積增加積亦隨之增明之瓶型溝溝槽電容結到達 0. 13uin 結構可應用憶胞面積下中所應用之各種具恰當構空間亦不明已以一較，任何熟習當可做些許附之申請專槽舉舶刑、《甘以电令結構之電容健 ^rn(V ^ ^張’使圍繞溝，·々5 0 %，因此，、、盖祕⑤ ,，霉槽電容結構之加約5 0 %以上。 :製造方法可有效利用空間，因 ’亦可符合下-世代之記憶體之兩個世代製程以上。因此，藉於動態隨機存取記憶體⑼以们， ’可大幅增加相當之電容容量。物質材料’並不限於實施例所引特性之物質和形成方法所置換，限於實施例引用之尺寸大小。佳實施例揭露如下，然其並非用此技藝者，在不脫離本發明之精之更動與潤御，因此本發明之保利範圍所界定者為準。Page 13 452971 V. Description of the invention (10) For the traditional example following the continuation, the deposit area can be borrowed. And because of the requirements of the base wall of the groove and the storage areas of the groove due to this issue, even the capacitors of the present invention have a limited record, and the present invention can also be described by the present invention. 13uin Structure can be used to memorize the cell area. The surface area of the bottle-shaped deep trench in this embodiment is increased to increase the surface area and the capacitance of the bottle-shaped trench is increased. The proper structure of the space used in the following is also unknown. Any familiarity can be used to apply for a special slot sentence, "The capacitance of the structure of the electric power order ^ rn (V ^ ^ 张 '使Surrounding the trench, · 々50%, so ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, and thes More than two generations of processes. Therefore, by using dynamic random access memory, we can 'significantly increase the equivalent capacitance. Material material' is not limited to the material and method of formation of the characteristics cited in the embodiment, but only The dimensions quoted in the examples are disclosed below. The preferred embodiments are disclosed below, but they are not used by the artist, without departing from the essence of the present invention, and therefore the definition of the scope of the present invention shall prevail.

Claims

452971 六、申請專利範圍 1. 一種瓶型深溝槽之製造方法，適用於—半導體基底，其包括下列步驟： (a) 進行一第一蝕刻階段，其以溴化氫、三氟化氮、及預混合之氦/氧為電漿氣體組成物，蝕刻該半導體基底以形成一頸部輪廓；及 (b) 進行一第二蝕刻階段’其以該溴化氫、三氟化氮及預混合之氦/氧、及氣為電漿氣體組成物，蝕刻該頸部輪廓下之半導體基底以形成一底部輪廓。 2 ‘如申請專利範圍第1項所述之方法，其中於步驟（b) 之第二#刻階段’該溴化氫、三氟化氮和預混合之氦/氧流量高於該第一蝕刻階段之溴化氫、三氟化氮和預混合之氦/氧流量。 3. 如申請專利範圍第1項所述之方法，其中於步驟之第一蝕刻階段’該溴化氫、三氟化氮、及預混合之氦/ 氧既定流量之比值為約87 :13 :35。 4. 如申請專利範圍第1項所述之方法，其中於步驟（b) 之第二蝕刻階段，該溴化氫、三氟化氮、及預混合之氦/ 氧既定流量之比值為約11 3 ± 1 2 : 1 7 ± 2 : 46 土 5。 5. 如申請專利範圍第1項所述之方法’其中於步驟（b) 之第二蝕刻階段’該氯氣之流量約在1 〇seem以上。 6. —種瓶型深溝槽之製造方法’適用於一表面具有原生物之半導體基底，其包括： (a)進行一第一蝕刻階段，其以溴化氫、三氟化氮為電聚氣體組成物，姓刻去除在該半導體基底上之原生物；452971 VI. Application for patent scope 1. A method for manufacturing a bottle-shaped deep trench, suitable for a semiconductor substrate, comprising the following steps: (a) performing a first etching stage using hydrogen bromide, nitrogen trifluoride, and The pre-mixed helium / oxygen is a plasma gas composition, and the semiconductor substrate is etched to form a neck profile; and (b) a second etching stage is performed, which uses the hydrogen bromide, nitrogen trifluoride, and the pre-mixed Helium / oxygen and gas are plasma gas compositions, and the semiconductor substrate under the contour of the neck is etched to form a bottom contour. 2 'The method as described in item 1 of the scope of the patent application, wherein the hydrogen bromide, nitrogen trifluoride, and pre-mixed helium / oxygen flow rate is higher than the first etch in the second #etching stage of step (b) Phases of hydrogen bromide, nitrogen trifluoride, and pre-mixed helium / oxygen flow. 3. The method according to item 1 of the scope of the patent application, wherein in the first etching step of the step, the predetermined ratio of the hydrogen bromide, nitrogen trifluoride, and pre-mixed helium / oxygen is about 87:13: 35. 4. The method as described in item 1 of the scope of patent application, wherein in the second etching step of step (b), the predetermined flow rate ratio of the hydrogen bromide, nitrogen trifluoride, and pre-mixed helium / oxygen is about 11 3 ± 1 2: 1 7 ± 2: 46 dirt 5. 5. The method according to item 1 of the scope of the patent application, wherein the flow rate of the chlorine gas in the second etching step of step (b) is about 10 seconds or more. 6. —Manufacturing method of bottle-type deep grooves' is applicable to a semiconductor substrate with a protozoa on the surface, which includes: (a) performing a first etching stage, which uses hydrogen bromide and nitrogen trifluoride as the electropolymerization gas; A composition with a surname carved from the protozoa on the semiconductor substrate;

第15貰 4 52 S'： 1 六、申請專利範圍 (b) 進行一第二餘刻階段，其以该邊化致、二氟化氮、及一預混合之氦/氧為電槳氟體組成物’蝕刻該半導體基底以形成一頸部輪廓；及 (c) 進行一第三蝕刻階段，其以該溴化氫、三氟化氮、及預混合之氦/氧、及氣為電漿氣體組成物’蝕刻該頸部輪廓下之半導體基底以形成一底部輪廓。 7.如申請專利範圍第6項所述之方法’其中於步驟（b) 之第二钱刻階段，該漠化氫和三氣化氪*流直鬲於該第一钱刻階段之溴化氫和三氟化氮流耋 8·如申請專利範圍第6項所述之方法’其中於步驟（c) 之第三蝕刻階段，該溴化氫、彡氟化氮和預混合之氦/氧流量高於該第二蝕刻階段之溴化氫、三氟化氮和預混合之氦/氧流量。 9.如申請專利範圍第6項所述之方法，其中於步驟（a) 之第一餘刻階段，該演化氫、三氣化亂既疋流里之比值為約20 : 5 。 10. 如申請專利範圍第6項所述之方法’其中於步驟 (b) 之第二敍刻階段，該漠化氣，> 氟化鼠、及預混合之氦/氧既定流量之比值為約8 7 : 1 3 3 5 ° 11. 如申請專利範圍第6項所述之方法’其中於步驟 (c) 之第三餘刻階段，該溴化氬，> 氟化氮、及預混合之氦/氧既定流量之比值為約i i 3 土 0 : 1 7 ± 2 : 46 ± 5。 12. 如申請專利範圍第6項所述之方法’其中於步驟 (c)之第三蝕刻階段，該氯氣之流景約在1 0sccm以上No. 15 贳 4 52 S ': 1 6. Scope of patent application (b) A second remaining stage is performed, which uses the side effect, nitrogen difluoride, and a pre-mixed helium / oxygen as the electric paddle fluoride. The composition 'etches the semiconductor substrate to form a neck profile; and (c) performs a third etching stage using the hydrogen bromide, nitrogen trifluoride, and pre-mixed helium / oxygen, and gas as a plasma The gas composition 'etches the semiconductor substrate under the contour of the neck to form a bottom contour. 7. The method as described in item 6 of the scope of the patent application, wherein in the second stage of step (b), the hydrogenated hydrogen and three gasification streams are directed to the bromination of the first stage Hydrogen and nitrogen trifluoride stream 8. The method as described in item 6 of the scope of patent application 'wherein in the third etching step of step (c), the hydrogen bromide, nitrogen fluoride and pre-mixed helium / oxygen The flow rate is higher than the hydrogen bromide, nitrogen trifluoride, and pre-mixed helium / oxygen flow rates in the second etch stage. 9. The method according to item 6 of the scope of patent application, wherein in the first remaining stage of step (a), the ratio of the evolved hydrogen and the three gasification chaos in the current stream is about 20: 5. 10. The method according to item 6 of the scope of the patent application, wherein in the second stage of step (b), the desertified gas, > the fluorinated rat, and the pre-mixed helium / oxygen predetermined flow ratio are Approx. 8 7: 1 3 3 5 ° 11. The method described in item 6 of the scope of patent application 'wherein in the third remaining stage of step (c), the argon bromide, > nitrogen fluoride, and premix The predetermined helium / oxygen flow ratio is approximately ii 3 soil 0: 1 7 ± 2: 46 ± 5. 12. The method according to item 6 of the scope of patent application, wherein in the third etching stage of step (c), the flow rate of the chlorine gas is about 10 sccm or more.

第16寅16th Yin