4528 7 五、發明說明（1) ------- 本發明係有關一種控制遮蔽氧化層（screen 0)(1(^)厚 度的方法，特別有關於一種藉由控制遮蔽氧化 升半導體元件之電性表現的方法。 碎度來k 士曰在半導體製程中，離子佈植製程是將特定離子摻雜至 結晶矽材質中，以形成各種η型、P型半導體區_，而為； 有效抑制離子植入的通道現象’一般會將結晶矽表面氧化 長成非結晶矽材質的二氧化矽層，用來作為犧牲氧化層 (sac^inciaI oxide)或通稱為遮蔽氧化層（screen )’以增加摻質與矽原子撞擊所產生的散射 (scattering) 〇 請參考第1圖，第1圖係顯示習知遮蔽氧化層的剖面示 心圖。習知在製作一場效電晶體（field effect transistor，以下簡稱”丁）1〇時，會先在一矽基底i2上成 長—厚度約為數十埃的第一氧化層14，然後在一預定區域 上定義出閘極圖案丨5，其包含有一多晶矽層〗6、一矽化鎢 層17以及一氮化矽罩幕18。接著，為了降低後續氮化矽側 壁子之應力以增加附著力，會先以熱氧化法於第一氧化層 =表面以及晶矽層16、矽化鎢層17侧壁上成長一厚度約為 〇 〇埃的第二氧化層2 0，後續便可以利用基底1 2表面 上的第一、第二氧化矽層14、2〇做為一遮蔽氧化層23，以 增加摻入離子的散射5隨後，於閘極圖案1 5側壁上形成一 由氮化矽所構成之側壁子22之後’進行高濃度且深度較深 之離子植入’以於閘極圖案丨5兩側之基底丨2上各形成一源 極/汲極區2 4。4528 7 V. Description of the invention (1) ------- The present invention relates to a method for controlling the thickness of a masking oxide layer (screen 0) (1 (^), and more particularly to a method for controlling a semiconductor device by masking the oxide layer. The method of electrical performance. In the semiconductor process, the ion implantation process is doped with specific ions into the crystalline silicon material to form various η-type and P-type semiconductor regions. Inhibit ion implantation channel phenomenon 'Generally, the surface of crystalline silicon is oxidized and grown into a layer of amorphous silicon dioxide, which is used as a sacrificial oxide (sac ^ inciaI oxide) or commonly known as a screen oxide' (screen). Increase the scattering produced by the impact of dopants and silicon atoms. ○ Please refer to Figure 1, which shows a cross-sectional cardiogram of a conventional masking oxide layer. The conventional method is to produce a field effect transistor (field effect transistor, Hereinafter referred to as "Ding", at 10, it will first grow on a silicon substrate i2-a first oxide layer 14 with a thickness of about several tens of angstroms, and then define a gate pattern 5 on a predetermined area, which contains a polycrystalline silicon Layer〗 6, a silicidation Tungsten layer 17 and a silicon nitride mask 18. Next, in order to reduce the stress of the subsequent silicon nitride sidewalls to increase adhesion, the first oxide layer = the surface and the crystalline silicon layer 16 and tungsten silicide will be thermally oxidized first. A second oxide layer 20 having a thickness of about 00 angstroms is grown on the side wall of the layer 17. Subsequently, the first and second silicon oxide layers 14 and 20 on the surface of the substrate 12 can be used as a shielding oxide layer 23. In order to increase the scattering of doped ions 5, after the formation of a sidewall 22 made of silicon nitride on the side wall of the gate pattern 15 'high-concentration and deeper ion implantation' for the gate pattern A source / drain region 24 is formed on each of the substrates 5 on both sides.
4 528 五、發明說明（2) 但是在製作側壁子2 2的過程中，以非等向性乾钱刻方 式來去除基底12表面上的氮化矽，電漿之離子轟擊（丨〇n bombardment)會損傷遮蔽氧化層23的表面23，而使其表面 23’材質鬆散’而且整個遮蔽氧化層23的厚度過厚、不均 勻，不但會影響後續離子佈植製程所形成之源極/汲極區 24深度’還會影響到FET 10的起始電壓（thresh〇ld voltage)與驅動電流（drive current)的穩定性。要解決 上述的問題，一種方式是配合遮蔽氧化層23的厚度使用較 高能量的離子佈植製程，但是摻質的分佈輪廓（pr〇file) 會有擴張（spreading)之虞；另一種方式是延長氮化矽的蝕 刻時間以減少遮蔽氧化層23的厚度，但是如此一來會使侧 壁子22的厚度變得過薄，容易導致閘極與源極/汲極接觸 f(C〇ntact)之間的短路現象。為了避免額外的補救措施 何生出更多的電性問題，目前亟需在不延長氮化矽的蝕刻 時間、離子佈植能量的考量下，發展出一套控制遮蔽氧化 層23厚度的方法，以解決遮蔽氧化層23之厚度過厚且不均 勻的問題。 有鐘於此’本發明之目的係在於提供一種控制遮蔽氧 化層厚度的方法，來解決上述之問題，以提升半導體元件 之電性表現。 本發明提出一種控制遮蔽氧化層厚度的方法，包含有 下列步驟：首先提供一基底，該基底包含有一閘極設於該 基底表面之一預定區域上，一遮蔽氧化層設於該基底表面 上且環繞該閘極，以及一絕緣層覆蓋該閘極以及該遮蔽氧4 528 V. Description of the invention (2) However, in the process of making the side wall 2 2, the silicon nitride on the surface of the substrate 12 is removed by an anisotropic dry etching method, and plasma ion bombardment (丨 〇n bombardment) ) Will damage the surface 23 of the shielding oxide layer 23, and make its surface 23 'loose' and the thickness of the entire shielding oxide layer 23 is too thick and uneven, which will not only affect the source / drain formed by the subsequent ion implantation process The depth of the region 24 also affects the stability of the threshold voltage and the drive current of the FET 10. To solve the above problem, one way is to use a higher energy ion implantation process in accordance with the thickness of the shielding oxide layer 23, but the distribution profile of the dopant may spread. The other way is Prolong the etching time of silicon nitride to reduce the thickness of the shielding oxide layer 23, but this will make the thickness of the side wall 22 too thin, which may easily cause the gate to contact the source / drain f (Cntact) Between short circuits. In order to avoid additional remedial measures that cause more electrical problems, it is urgent to develop a set of methods to control the thickness of the masking oxide layer 23 without prolonging the etching time of silicon nitride and the energy of ion implantation. The problem that the thickness of the shielding oxide layer 23 is too thick and uneven is solved. Here is where the object of the present invention is to provide a method for controlling the thickness of the masking oxide layer to solve the above-mentioned problems and improve the electrical performance of the semiconductor device. The present invention provides a method for controlling the thickness of a masking oxide layer, which includes the following steps: First, a substrate is provided. The substrate includes a gate electrode disposed on a predetermined area of the substrate surface, and a masking oxide layer is disposed on the surface of the substrate. Surrounding the gate, and an insulating layer covering the gate and the shielding oxygen
第5頁 4528 72 五、發明說明（3) 化層》然後進行一非等向性乾餘刻製程以去除位於該閘極 表面以及該基底表面上的絕緣層’而殘留於該閘極側辟之 絕緣層則形成一閘極側壁子。接著，進行一濕姓刻製程， 利用一稀釋氫氣酸（dilute hydr〇fluoric acid)將未被該 侧壁子覆蓋住之遮蔽氧化層餘刻至一預定厚产。 圖式簡單說明 又 為讓本發明之上述目的、特徵、和優點能更明顯易 懂，下文特舉一較佳實施例，並配合所附圖式，作詳細說 明如下： ' 第1圖係顯示習知遮蔽氧化層的剖面示竟圖。 第2圖至第5圖係顯示本發明控制遮蔽氧化層厚度之方 法的不意圖。 第1表係顯示本發明方法之實驗結果比較。 [符號說明] 矽基底〜30 ;閘極氧化層〜32 ;多晶矽層〜34 ;矽化鎢 層〜36 ;氮化矽罩幕〜38 ;閘極圖案〜39 ;快速加熱氧化層 〜40 ;氮化矽層〜42 ;閘極側壁子〜43 ;遮蔽氧化層〜44 ;曰受 損氧化層〜45 ;源極/汲極區〜46 較佳實施例說明： 請參考第2圖至第5圖，第2圖至第5圖係顯示本發明控 制遮蔽氧化層厚度之方法的示意圖。本發明控制遮蔽氧化 層厚度之方法主要應用在FET的製作上。如第2圖所示，一 石夕基底30表面上包含有一厚度約為的閘極氧化層， 閘極圖案3 9包含有一多晶石夕層3 4、一石夕化鎢層3 6以及一Page 5 4528 72 V. Description of the invention (3) Chemical layer "Then an anisotropic dry-etching process is performed to remove the insulating layer located on the gate surface and the substrate surface and remain on the side of the gate. The insulating layer forms a gate sidewall. Then, a wet lasting process is performed, and a masking oxide layer not covered by the sidewall is etched to a predetermined thickness using a dilute hydrofluoric acid. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, the following is a detailed description of a preferred embodiment and the accompanying drawings for detailed description as follows: A cross-sectional view of a conventional masking oxide layer is shown. Figures 2 to 5 show the intent of the method of controlling the thickness of the masking oxide layer of the present invention. Table 1 shows a comparison of the experimental results of the method of the present invention. [Symbol description] Silicon substrate ~ 30; Gate oxide layer ~ 32; Polycrystalline silicon layer ~ 34; Tungsten silicide layer ~ 36; Silicon nitride mask ~ 38; Gate pattern ~ 39; Rapid heating oxide layer ~ 40; Nitriding Silicon layer ~ 42; Gate sidewalls ~ 43; Masking oxide layer ~ 44; Damaged oxide layer ~ 45; Source / drain region ~ 46 Description of preferred embodiments: Please refer to Figure 2 to Figure 5, Figures 2 to 5 are schematic diagrams showing the method for controlling the thickness of the shielding oxide layer according to the present invention. The method for controlling the thickness of the shielding oxide layer of the present invention is mainly applied to the fabrication of FETs. As shown in FIG. 2, the surface of a Shixi substrate 30 includes a gate oxide layer having a thickness of about 30 Å, and the gate pattern 39 includes a polycrystalline silicon layer 3 4, a tungsten tungsten layer 36, and
4 528 五、發明說明（4) 氮化碎罩幕38 ’係设於閉極氧化層32之一預定區域上， 厚度約為〗4 A的快速加熱氧化層（rapid thermal ox ide )40係成長於閘極氧化層32表面以及晶珍層34、£夕化 鎢層36侧壁上，以及一氮化矽層42係覆蓋住基底3〇之表 面。 如第3圖所示，本發明方法是先進行一非等向性乾蝕 刻製程，將閘極圖案39頂部以及基底30表面上的氮化矽屏 42去除，而殘留於閘極圖案39側壁上之氮化矽層“則成^ 一問極側壁子43，係用來作為後續離子佈植製程之幕罩: 而基底30表面上的閘極氧化層32以及快速加熱氧化層4〇， 則是用來作為-遮蔽氧化層44。由於以乾㈣方式來去除 基底30表面上的氮切層42時，電漿會損傷遮蔽氧化層〇 的表面，因此遮蔽氧化層44的表面成為一厚度不 為120〜160 Α)的受損氧化層（damaged⑽丨心）45。 接著對基底30表面進行一清洗製程成之後，如第4圖 所Γ缺進行一濕钱刻製程’利用稀釋比例為1 的稀釋 = :(duute hydrofluoric acid，以下簡稱婦)作為钱 =行時間約為15〜55秒’可以將受損氧化屠杯完 全去除，使遮蔽氧化層44之厚度較為均勻並 度為35〜45 A。如此一夾，梯讦w鈕4 Λ^ ^ 译π /1 a τ ^ ^ 來，便可以解決遮蔽氧化層44之厚 度過厚且不均勻的問題。最後，&第5圖所示，進行一高 濃度且深度較深之離子佈植贺程， .. Λί ^雕卞师植製程以於閘極圖案39兩侧之 基底30上各形成一源極/汲極區。 本發明方法並沒有增加乾钱刻製程的時間，而是於進4 528 V. Description of the invention (4) The nitrided shroud 38 'is located on a predetermined region of the closed-electrode oxide layer 32 and has a rapid thermal ox ide 40 thickness of about 4 A. The growth of the series 40 A silicon nitride layer 42 covers the surface of the substrate 30 on the surface of the gate oxide layer 32 and the side walls of the crystal layer 34 and the tungsten tungsten layer 36. As shown in FIG. 3, the method of the present invention first performs an anisotropic dry etching process to remove the silicon nitride screen 42 on the top of the gate pattern 39 and the surface of the substrate 30, and remain on the sidewall of the gate pattern 39 The silicon nitride layer is formed as a question about the sidewall 43, which is used as a curtain for the subsequent ion implantation process: while the gate oxide layer 32 and the rapid heating oxide layer 40 on the surface of the substrate 30 are It is used as a masking oxide layer 44. Since the nitrogen cutting layer 42 on the surface of the substrate 30 is removed in a dry manner, the plasma will damage the surface of the masking oxide layer 0, so the surface of the masking oxide layer 44 has a thickness different from 120 ~ 160 Α) damaged oxide layer (damaged center) 45. Then, after a cleaning process is performed on the surface of the substrate 30, a wet money engraving process is performed as shown in FIG. 4 'using a dilution ratio of 1 =: (duute hydrofluoric acid, hereinafter referred to as women) as money = Travel time is about 15 ~ 55 seconds' can completely remove the damaged oxidized butcher cup, so that the thickness of the shielding oxide layer 44 is more uniform and the degree is 35 ~ 45 A. Such a clip, the ladder 讦 w button 4 Λ ^ ^ Translated π / 1 a τ ^ ^ Then, the thickness of the shielding oxide layer 44 is too thick and uneven. Finally, as shown in Figure 5, a high-concentration and deeper ion implantation process is performed.. Λί ^ The engraving planter creates a source / drain region on each of the substrates 30 on both sides of the gate pattern 39. The method of the present invention does not increase the time of the dry money engraving process.
第7頁 452872 ------- :¾ ij 五、發明說明（5) ----- 行離子佈植製程之前額外進行一道濕蝕刻製程’將受損氧 化層45完全去除，以解決遮蔽氧化層44之厚度過厚且不均 勻的問題。因此在刻意控制遮蔽氡化層44厚度的情況下， 不需要增強離子佈植製程的能量，就可以控制所形成之源 極/汲極區46的深度，並穩定起始電壓與驅動電流以確' 保FET的電性表現。 請參考第1表，第1表係顯示本發明方法之實驗結果比 較。由實驗結果可知，以相同條件製作之五組p型FET半導 體疋件’經過不同時間的SiN蝕刻處理、DHF蝕刻處理，會 製作出不同厚度之遮蔽氧化層。相較於第三至第五組試 片’在第一、第二組試片中無論是否延長SiN蝕刻處理時 間’均無法大幅減少遮蔽氧化層的厚度，而第三至第五組 試片經過DHF蝕刻處理後，只要將蝕刻時間控制在丨5〜5 5秒 的範圍内’便能將遮蔽氧化層的厚度控制在4〇 A左右。這 不僅能解決遮蔽氧化層之厚度過厚且不均勻的問題，而且 DHF處理時間上具有很大的容忍幅度’可以確保遮蔽氧化 層的品質。除此之外’在其他的電性測試上發現，在經過 DHF處理過的試片上製作的p型FET半導體元件具有較佳且 較穩定之起始電壓、驅動電流、接觸電阻（c〇ntact resistance) ’確實能有效提升p型FET的電性表現aPage 7 452872 -------: ¾ ij V. Description of the invention (5) ----- Before the ion implantation process, an additional wet etching process is performed to completely remove the damaged oxide layer 45 to solve the problem. The shielding oxide layer 44 is too thick and uneven. Therefore, when the thickness of the masking layer 44 is deliberately controlled, the depth of the source / drain region 46 formed can be controlled without increasing the energy of the ion implantation process, and the starting voltage and driving current can be stabilized to determine 'Guarantee the electrical performance of the FET. Please refer to Table 1. Table 1 shows the comparison of the experimental results of the method of the present invention. From the experimental results, it can be seen that five groups of p-type FET semiconductor components' fabricated under the same conditions after different time SiN etching treatment and DHF etching treatment, will produce shielding oxide layers with different thicknesses. Compared with the third to fifth group of test pieces, "whether or not the SiN etching process is prolonged in the first and second groups of test pieces," the thickness of the shielding oxide layer cannot be greatly reduced. After the DHF etching process, as long as the etching time is controlled within the range of 5 to 55 seconds, the thickness of the shielding oxide layer can be controlled to about 40A. This not only solves the problem that the thickness of the masking oxide layer is too thick and uneven, but also has a large tolerance range in DHF processing time ', which can ensure the quality of the masking oxide layer. In addition to this, in other electrical tests, it was found that p-type FET semiconductor devices fabricated on DHF-treated test strips have better and more stable starting voltages, driving currents, and contact resistance ) 'It can effectively improve the electrical performance of p-type FETs a
4528 7 r： 五、發明說明（6) 【第1表] 蝕刻SiN時 間（秒） DHF處理峙免__ Screen oxide 厚度（Μ4528 7 r: V. Description of the invention (6) [Table 1] SiN etching time (seconds) DHF treatment __ Screen oxide thickness (M
雖然本發明已以較佳實施 限定本發明，任何熟習此項技 神和範圍内，當可作更動與潤 當視後附之申請專利範圍所界 例揭露如上，然其並非用以 藝者’在不脫離本發明之精 飾’因此本發明之保護範圍 定者為準。Although the present invention has been limited to the present invention by a preferred implementation, anyone familiar with this skill and scope, when it can be altered and modified, the examples of the scope of the patent application attached below are disclosed above, but it is not intended for artists' Without departing from the spirit of the invention, the scope of protection of the invention shall prevail.