TW449897B - Semiconductor package - Google Patents

Semiconductor package Download PDF

Info

Publication number
TW449897B
TW449897B TW088120744A TW88120744A TW449897B TW 449897 B TW449897 B TW 449897B TW 088120744 A TW088120744 A TW 088120744A TW 88120744 A TW88120744 A TW 88120744A TW 449897 B TW449897 B TW 449897B
Authority
TW
Taiwan
Prior art keywords
patent application
ball
scope
area
metal
Prior art date
Application number
TW088120744A
Other languages
Chinese (zh)
Inventor
Shing-Sheng Wang
Jiang-Han Dai
Original Assignee
Ind Tech Res Inst
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ind Tech Res Inst filed Critical Ind Tech Res Inst
Priority to TW088120744A priority Critical patent/TW449897B/en
Application granted granted Critical
Publication of TW449897B publication Critical patent/TW449897B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors

Landscapes

  • Wire Bonding (AREA)

Abstract

A semiconductor package is disclosed, which has a semiconductor chip. A soft plate is pasted on the surface of the chip through a bonding layer. A center area of the chip or the peripheral I/O bond pad area is exposed to the bonding layer. There is an attached metal circuit on the soft plate whose surface has a plurality of protruded spots connected to said bond pad individually aligned as the bridge of electrical conduction. Said protruded spots are formed by sing mold to apply pressure on the metal plate with mechanical force or by other metal ball adherence method. There is a shadow mask of conductive ball located on top of the metal circuit. The exposed area is the ball-mounting area. The conductive ball is located above said ball-mounting area. The protruded spots are formed by applying pressure of external force on the exposed metal grid structure of the metal circuit, or formed by metal ball adherence. The metal grid structure can be located on the center area, area of both sides, or the area surrounding the conductive solder ball. A plurality of soldered solder balls are electrically connected to the printed circuit board. The solder ball is formed by BGA technology.

Description

經濟部智慧財產局貝工消f合作社印製 ill·89 7_____： 五、發明說明（） 發明領殖： 本發明為一種半導體構裝。 發明訾* : 半導體晶片通常個別地構裝於塑膠或陶瓷材料之構裝 趙之内’構裝體之結構必；ί頁可以保護晶片以及將晶片操作 過程中所產生之熱散出。隨著半導體技術之快速演進，電 子產品在輕薄短小、多功能速度快之趨勢的推動下，1(:半 導體的I/O數目不但越來越多密度亦越來越高，使得構裝 元件的引腳數亦隨之越來越多而高數量I/O之封裝也伴隨 球矩陣排列封裝技術（ball grid array;以下簡稱BGA封裝） 技術之發展而有所突破，因此，1C半導體承載的封裝趨向 於利用球矩陣排列封裝技術（BGA)。BGA構裝的特點是， 負責I/O的引腳為球狀較導線架構裝元件之細長引腳距離 短且不易受損變形，其封裝元件之電性的傳輪距離較短。 一般構裝體包含封膠、晶元（die)、接合焊線與電子連 接元件《由於晶®製程技術的快速進步’積體電路設計者 總是想要以更快的步法增加晶片的集積度。近來’為滿足 晶元構裝最小化的需求。一種稱為晶方尺寸構裝（CSP; chip scale package)的構裝技術已被發展’此構裝由名稱所知具 有相近於晶片尺寸的構裝體β第一圖為 AMKOR TECHNOLOGY所發展的一種晶方尺寸構裝°上述之構裝 2 本紙張尺度適用中a 3家標準（CNS)A4規格（210 X 297公藿） t ---：----：---------1.---------------訂------Γ---線〆 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 4 49 3 9 * A7 _B7___ 五、發明說明（） 體包含一晶片（C h i ρ) 2，一高分子材料（例如 P 0丨y丨m i d e)軟 板6藉由一黏合材料4貼附於晶片2之表面之上。上述黏 合材料之厚度約為1 0 0微米，一穿孔8形成於上述之高分 子材料4以及黏合材料4之中，以曝露出晶片2約莫中央 之區域。上述之高分子材料6之表面則佈有導電性之導線 (trace)圖案ί夫圖示），之上則具有複數個焊墊 10形成於 其上作為電性傳導之機構。部份之焊墊1 0則具有導體球 12形成於其上，作為電性傳遞之橋樑，一般利用球矩陣 排列封裝技術（B GA)完成製作。上述被曝露之晶片2表面 則具有導電塾（conductive pad)14形成於其上，接合焊 線（bond wire}16貝1J由導電塾14引出連接於部份之焊墊 1 0之上以利於晶片2與外界電性聯繫。液態封膠1 8則 填充於穿孔8之中，以覆蓋導電墊14以及接合焊線16 之上，用以避免上述兩元件受外力或水氣之影響。上述之 構裝係利用軟板將I / 0接點重新分配，而軟板與晶圓 (wafer)之晶片（chip)，則利用接合焊線做信號之傳輸， 其缺點為 I / Ο之間距（p itc h)需配合接合焊線組裝之極 限。 發明目的及振述： 本發明之主要目的為利用模具或其他金屬球附著方式 形成I/O凸點以取代傳統之凸塊，以簡化製程，本發明也 利用黏膠當作接合面，以吸收應力。 本紙張尺度適用t國國家標準（CNS)A4規格（210 X 297公» ) 丨— Ί-ϊ ι 訂-----！！鍊) (諳先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消f合作社印製 44989 7 A7 ____B7__ 五、發明說明（） 晶方尺寸構裝（CSP)包含半導體晶片，一軟板藉由—黏 合層貼合在晶片的表面之上-軟板之組成材質具有可塑性 或可曲性，可以選用 高分子例如P〇lyimide之材質。 上述之黏合層將晶片部份曝露，晶片中央或週邊1/〇焊墊 區域可以被黏合層所曝露。其數量以及配置之方式可以依 照不同之需求而改變β軟板之上具有金厲線路，材質最佳 為銅，附著於其上，其表面具有複數個凸點，連接於且個 別對準上述之焊墊，作為電性傳導之橋樑。上述之凸點係 利用模具以機械力量施壓於裸露金屬線路而成。位於金屑 線路上方的則為導電球之遮罩。被曝露之區域則為植球之 區域。導電球則位於上述之植球之區域之上，一般為利用 錫球（solder bal丨）作為上述之導電球。凸點之形成乃利用金 屬線路上之金屬柵狀之結構以外力施壓而形成凸點，金屬 概狀結構可以位於中央之區域、週邊之區域或是環繞導電 錫球之區域。經過成形之金屬柵狀凸點结構，其截面可以 為V型、U型、尖錐型或其他任意形狀之結構。複數個焊 接之錄球以電性連接到印刷電路板（PCB),錫球以球矩形陣 列（BGA)技術形成。為防凸點與晶片1/〇烊墊接觸處氡化， 可在接合處周圍包覆封膠材質β 本發明先行備置一具有金屬線路所附著之軟板，利用 錫球遮罩定義出錫球之區域。形成凸點之區域則裸露出 來。利用模具施壓於裸露金屬上以形成凸點，也可以利用 金屬附著方式形成凸點。完成之後，為防止凸點之氧化可 以在<4點上實施防氡化之處理。接著，利用黏膠或黏合層 4 本紙張尺度適用中®國家標準（CNS)A4规格（2I0 * 297公釐） ----.--Μ 1--Γ — — "·^-----ί^- — —--* 線 (請先閱讀背面之注意事項再填寫本頁) 449897 A 7 B7 五、發明説明（） 將上述之軟板黏合於晶片之上。再利用雷射或熱壓頭將凸 點銲接於焊墊之上。 明式簡蕈說明： 本發明的較佳實施例將於往後之說明文字中輔以下列 圖形做更詳細的闡述： 第一圖為傳統之晶方尺寸構裝之截面圖。 第二、三圖為本發明之積體電路構裝之載面圖以及俯 視圖。 第四A圖至第四C圖為本發明具有柵狀或格狀結構之 金屬線路。 第五圖為將本發明之構裝連接到印刷電路板（PCB)之 示意圖。 第六圖為將本發明之構裝連接到印刷電路板（PCB)之 另一示意囷。 第七圖為第五圖之製作步驟。 第八圖為第六圖之製作步驟。 无#棋猇毋照表 --------1 1裝-------訂-----旅 '線 (请先閲讀背1&之.ii意事項再填寫本I )Printed by the Cooperative of Intellectual Property of the Ministry of Economic Affairs, Ig · 89 7_____: V. Description of the invention () Invention invention: This invention is a semiconductor device. Invention 訾 *: Semiconductor wafers are usually individually mounted on plastic or ceramic materials. The structure of the structure is necessary; the sheet can protect the wafer and dissipate heat generated during the operation of the wafer. With the rapid evolution of semiconductor technology, electronic products are driven by the trend of light, thin, short, and versatile. 1 (: The number of semiconductor I / Os is not only increasing, but also increasing in density. The number of pins has also increased, and high-volume I / O packaging has also broken through with the development of ball grid array packaging technology (hereinafter referred to as BGA packaging). Therefore, 1C semiconductor-borne packaging It tends to use the ball matrix array packaging technology (BGA). The characteristics of the BGA structure are that the pins responsible for I / O are spherical and have a shorter distance than the lead pins of the lead frame component, and are not easily damaged and deformed. The electrical transmission distance is short. The general structure includes sealant, die, bonding wire and electronic connection components. "Because of the rapid advancement of wafer process technology," integrated circuit designers always want to Faster steps increase the degree of integration of wafers. Recently 'to meet the needs of wafer structure minimization. A packaging technology called CSP (chip scale package) has been developed' This structure Known by name There is a structure with a size close to the wafer size. Β The first picture is a crystal size structure developed by AMKOR TECHNOLOGY ° The above structure 2 The paper size is applicable a 3 standards (CNS) A4 (210 X 297)藿) t ---: ----: --------- 1 .--------------- Subscribe ------ Γ --- line 〆 (Please read the notes on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 49 3 9 * A7 _B7___ V. Description of the invention () The body contains a chip (C hi ρ) 2, a high A molecular material (such as P 0 丨 y 丨 mide) soft board 6 is attached to the surface of the wafer 2 by an adhesive material 4. The thickness of the above adhesive material is about 100 microns, and a perforation 8 is formed at the above-mentioned height. The molecular material 4 and the adhesive material 4 are exposed to expose the central area of the wafer 2. The surface of the above-mentioned polymer material 6 is provided with a conductive trace pattern (a graphic illustration of a conductive pattern), and there is a plurality of Each pad 10 is formed thereon as a mechanism for electrical conduction. Some of the pads 10 have conductor balls 12 formed thereon as bridges for electrical transmission, and are generally manufactured using ball matrix array packaging technology (B GA). The surface of the exposed wafer 2 has a conductive pad 14 formed thereon, and a bonding wire (16) 1J is drawn out from the conductive pad 14 and connected to a part of the pad 10 to facilitate the wafer. 2 is in electrical contact with the outside world. The liquid sealant 18 is filled in the perforations 8 to cover the conductive pad 14 and the bonding wire 16 to prevent the two components from being affected by external forces or moisture. The assembly uses a flexible board to redistribute I / 0 contacts, while the flexible board and the wafer of the wafer use chip bonding wires for signal transmission. The disadvantage is the distance between I / 0 (p itc h) Need to match the limits of the bonding wire assembly. Purpose of the invention and description: The main purpose of the present invention is to use a mold or other metal ball attachment to form I / O bumps to replace the traditional bumps to simplify the manufacturing process. The present invention Adhesive is also used as the bonding surface to absorb stress. The paper size is applicable to the national standard (CNS) A4 specification (210 X 297 male ») 丨 — Ί-ϊ ϊ order -----! Chain) ( (阅读 Please read the notes on the back before filling out this page.) Printed by the Consumer Cooperative 44989 7 A7 ____B7__ 5. Explanation of the invention () The crystal size structure (CSP) contains a semiconductor wafer, a flexible board is attached to the surface of the wafer by an adhesive layer-the composition of the flexible board is For plasticity or flexibility, a polymer such as Pollyide can be selected. The above-mentioned adhesive layer partially exposes the wafer, and the center or peripheral 1/0 pad area can be exposed by the adhesive layer. The quantity and configuration method can be changed according to different needs. There are golden lines on the beta soft board. The material is preferably copper and attached to it. The surface has a plurality of bumps connected to and individually aligned with the above. Pads, as a bridge of electrical conduction. The above-mentioned bumps are formed by using a mold to apply mechanical force to bare metal lines. Above the gold filings is a shield of conductive balls. The exposed area is the area where the ball is planted. The conductive ball is located above the area where the ball is planted. Generally, a solder ball is used as the above-mentioned conductive ball. The bumps are formed by using external force on the metal grid-like structure on the metal line to form the bumps. The metal outline structure can be located in the central area, the peripheral area, or the area surrounding the conductive solder ball. The formed metal grid-like bump structure can have a V-shaped, U-shaped, tapered or other arbitrary shape in cross section. The plurality of soldered recording balls are electrically connected to a printed circuit board (PCB), and the solder balls are formed by a ball rectangular array (BGA) technology. In order to prevent the bump from coming into contact with the wafer 1 / 〇 烊 pad, the sealing material can be covered around the joint β. The present invention first prepares a soft board with a metal circuit attached, and uses a solder ball mask to define a solder ball Area. The areas where the bumps are formed are exposed. Using a mold to press the bare metal to form bumps, you can also use metal attachment to form bumps. After the completion, in order to prevent the oxidation of the bumps, anti-sag treatment can be performed at < 4 points. Next, use the adhesive or adhesive layer 4 paper size applicable in the National Standard (CNS) A4 specification (2I0 * 297 mm) ----.-- M 1--Γ — — " · ^ --- --ί ^-— —-- * line (please read the precautions on the back before filling this page) 449897 A 7 B7 V. Description of the invention () Adhere the above soft board to the chip. The laser or thermal head is then used to solder the bumps to the pads. Explanation of the simple formula: The preferred embodiment of the present invention will be described in more detail in the following explanatory text with the following figures: The first figure is a cross-sectional view of a traditional crystal-size structure. The second and third figures are a plan view and a top view of the integrated circuit structure of the present invention. Figures 4A to 4C are metal lines having a grid-like or grid-like structure according to the present invention. The fifth figure is a schematic diagram of connecting the structure of the present invention to a printed circuit board (PCB). The sixth diagram is another schematic diagram for connecting the structure of the present invention to a printed circuit board (PCB). The seventh figure is the manufacturing steps of the fifth figure. The eighth figure is the manufacturing steps of the sixth figure. No # Chess, no need to follow the table -------- 1 1 installed --------- order ----- brigade 'line )

經濟部中夫橾準局負工消費合作杜印5L 半導體晶片22 黏合層24 & 點 3 0a 導電球32 軟板26 金屬線路30 焊墊28 遮罩34 本纸》尺度逋用中國國家梯準（CNS }八4規<格（210X 297公釐） A7 44989 7 B7_____ 五、發明說明（） 金屬栅狀結構30b 印刷電路板40 填膠材質42 封膠材質46 發明掸麵說明： 傳統之晶方尺寸構裝先將I/O分配之後，再長凸洗 (bump)，其製造成本過高。本發明主要利用償廉之故板將 I/O重新取成全陣列（full array)之排列方式，然後形成 BGA型式之構裝。此外，本發明.利用摸具即可長出1/〇 & 點或利用金屬球附著方式以取代傳統之凸城，製程簡單 。 本發明也利用:黏脬當作接^佥面，以吸收應力，因此本發明 具有製造簡單、利用償廉之軟板優勢，以降低製作成本並 且其製程設備簡單。本發明之實施例，將利用參考圖式作 進一步之詳盡的描述。如第二ffl與第三圈所示，其分別為 本發明 @象實 施例之截面®與俯視困，本半導趙封裝包含 一半導體晶片22，一軟板26藉由一黏合層24貼合在晶片 22的表面之上》此處之軟板（flex board)26指的是此軟扳之 組成材質-具-支可』1可曲性，上述之軟板在熟知此項技 藝者可以輕易得知，一般可以選用 高分子（例如 polyimide)之材質》其他物質如黏勝或膠帶能被使用來作為 上述之黏合層24以達到相似的目的。一般基板所使用的材 質如 triazine，phenolic resin 或 bismaleimidetriazine(BT) 也可能用來作為軟板之材料。值得注意的是’上述之黏合 層24並非完全覆蓋於晶片22之上，如第二®所示，晶片 本紙張尺度適用中因國家標準<CNS)A4規格（210 * 297公* ) —ίιΊί 11— --------訂 i*—τ—線"y (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消费合作社印製 經濟部智慧財產局員工消費合作杜印製 4 4989 7The Ministry of Economic Affairs, China ’s Fuquan Bureau of Work and Consumer Cooperation Du Yin 5L semiconductor wafer 22 Adhesive layer 24 & point 3 0a conductive ball 32 soft board 26 metal circuit 30 pad 28 mask 34 paper "size" uses the Chinese national standard (CNS} Regulation 8 < Grid (210X 297 mm) A7 44989 7 B7_____ 5. Description of the invention () Metal grid structure 30b Printed circuit board 40 Filling material 42 Sealing material 46 Description of the invention: Traditional crystal The square-size structure first allocates I / O, and then bumps (bumps), the manufacturing cost is too high. The present invention mainly uses the reason to repay the I / O to get a full array arrangement Then, a BGA-type structure is formed. In addition, the present invention can use the mold to grow 1 / 〇 & points or use the metal ball attachment method to replace the traditional convex city, the process is simple. The present invention also uses: Used as a connection surface to absorb stress, the present invention has the advantages of simple manufacturing and the use of low-cost flexible boards to reduce manufacturing costs and simple process equipment. Embodiments of the present invention will use the reference drawings for further details. Detailed description. Such as the second ffl As shown in the third circle, which are the cross-section of the present invention and the top view, the semiconductor package includes a semiconductor wafer 22, and a flexible board 26 is attached to the surface of the wafer 22 by an adhesive layer 24. Above "Here, the flexible board (flex board) 26 refers to the composition material of this flexible board-with-support" 1 flexibility, the above-mentioned flexible board can be easily known to those skilled in the art, generally can Use polymer (such as polyimide) material> other materials such as adhesive or tape can be used as the above-mentioned adhesive layer 24 to achieve similar purposes. The materials used for general substrates such as triazine, phenolic resin or bismaleimidetriazine (BT) are also It may be used as a material for flexible boards. It is worth noting that 'the above-mentioned adhesive layer 24 is not completely covered on the wafer 22, as shown in the second ®, the size of the paper of the wafer is applicable due to the national standard < CNS) A4 specification (210 * 297 public *) —ίιΊί 11— -------- Order i * —τ—line " y (Please read the precautions on the back before filling out this page) Employees ’Cooperatives, Intellectual Property Bureau, Ministry of Economic Affairs Bureau of Intellectual Property, Ministry of Printing Economy Consumer cooperatives work printed 449,897

板26_之上'具有兔線_.络30，材質最佳為銅，附著於 其上，其表面具有複數個凸點3〇a，連接於且個別對準上 之谭塾28 ’作為電性傳導之橋標。i述之凸點了係利^ 模具以機械力量施壓於裸露金屬線路3〇而成也可以利用 第八圖之金属球附著方式而形成。位於金属線路30上方的 則為導電球32之遮罩34。被曝露之區域則為植球之區域。’ 導電球32貝|!位於上述之植球之區域之上，一般為利用竭球 (solder ball)作為上述之導電球32。上述之導電錫球32之 佈局實施例以及凸點之位置配置示之第二圖以及第三圓。 凸點之形成可以直接利用模具施壓形成，也可以利用具有 金屬柵狀結構之裸露金屬線路3〇，以不同模具施壓而曲折 形成v型a點。更可以利用金屬附著方式形成凸點，其實 施例請參閱第四a圖至第四c圖以及第八圖，金屬線路上 屬，n.n?·之結構3〇b，其金屬栅狀結構3〇b可 以利用外力施壓而曲折形成凸點，如圓所示。金屬柵狀結 構30b可以位於中央之區域 '兩邊之區域或是環繞導電錫 7 本紙張尺度適用t困國家標準（CNS>A4规格（210x297公;* ) -------Ί —---------------^------7--^ f請先間讀背面之注急事項再填寫衣頁ί 4 4989 7 A7 B7 經濟部智慧財產局員工消費合作社印枭 五、發明說明（ 球之週邊區域。經過曲祈之金屬柵狀結構或利用金屬附著 方式形成Λ點’其截面可以為V型、U型、尖錐型或其他 形狀之結構。栅狀結構之間距可以依照需求或Ϊ/0之配置 而有所變化。 第五與第六圖為實施例圖，複數個焊接之錫球3 2以電 性連接到印刷電路板（PCB)40上（顯示於第五圖），錫球32 連接一印刷電路板，如第七圖所示，以便形成熱與電性的 連接。凸點3〇a連接到晶片22，另一端經由導線（圖示32d) 連接到錫球32 »錫球32能以球矩陣排列（bga)技術形成》 為加強與PCB之接合能力及防止接點氧化也可以利用填膠 材質42包覆在晶片22下之周圍區域。 本發明之製程示之於第七圖’首先先行備置一具有金 屬線路30所附著之軟板26，在金屬線路30上利用錫球遮 罩34定義出錫球之區域。形成凸點3〇a之區域則被裸露。 接著如第七圖所示’利用模具44施壓於金屬板30之上以 形成凸點3 0a。經由不同設計之模具44可以形成不同之I/O 凸點30a。完成之後接著利用黏膠或黏合層24將上述之軟 板26黏合於晶片22之上。再利用雷射或熱壓頭將凸點30a 銲接於焊墊28之上。如要散熱或保護，可在晶片22之底 面以黏膠材質48貼附 一散熱裝置50或鍍上金屬層 5 1 (第五圖）。錫球則是利用傳統之植球方式製作於其上。 為防止凸點30a與晶片焊塾接合處氧化，也可以實施防氧 化之處理，例如.利用點膠方式將黏封物質46填充於接合 mlll!!m— 裝 i — ！ ί 1 訂---！1·線 <請先閱讀背面之注*孝項再填寫本頁) 4 4989 7 A7 _B7五、發明說明（） 區 圍 周 字 處 於法 同方 類之 均著 容附 内屬 域第形 其金 圖是 八乃 第成 於形 之之 示0C 程3 製點 一 凸 另 ο 之I/ 明唯 發， 本示 。所 覆圖 包七 點 凸 之 心 實 成 限之 以示 用揭 bi 斤 TTJN 戶 並明 ’發 已本 而離 例脫 施未 實它 佳其 較凡 之’ 明圍 發範 本利 為專 僅請 述申 所之 上明 以發 本 定 請 申 之 述 下 在 含 包 應 均 飾 修 或 變 改 效 等 之 成。 完内 所圍 下範 神利 精專 (請先閱讀背面之注意事項再填寫本頁>Above the board 26_ has a rabbit wire_.net 30, the material is preferably copper, attached to it, and its surface has a plurality of bumps 30a, which are connected to and individually aligned on Tan 28 as electrical The bridge of sexual transmission. The bumps described in the previous paragraph are made by using a mold to apply mechanical force to the exposed metal circuit 30. The mold can also be formed using the metal ball attachment method shown in Figure 8. Above the metal line 30 is a shield 34 of the conductive ball 32. The exposed area is the area where the ball is planted. ′ The conductive ball 32 is located on the above-mentioned area where the ball is planted. Generally, a solder ball is used as the above-mentioned conductive ball 32. The above-mentioned layout example of the conductive solder balls 32 and the positional arrangement of the bumps are shown in the second figure and the third circle. The formation of the bumps can be directly formed by the pressure of a mold, or the bare metal circuit 30 with a metal grid structure can be pressed and twisted to form a v-shaped a point by different molds. It is also possible to form bumps by using a metal attachment method. For examples, please refer to FIGS. 4a to 4c and FIG. b. The bump can be formed by zigzag using external force, as shown by a circle. The metal grid structure 30b can be located in the central area 'on either side' or around the conductive tin 7 This paper size is applicable to the national standard (CNS > A4 specification (210x297 male; *) ------- Ί ----- ------------- ^ ------ 7-^ f Please read the urgent notes on the back first and then fill in the clothing page. 4 4989 7 A7 B7 Staff of Intellectual Property Bureau, Ministry of Economic Affairs Consumption Cooperative Seal 5. Description of the invention (peripheral area of the ball. The Λ point is formed by the metal grid structure of Qu Qi or the use of metal attachment. Its cross section can be V-shaped, U-shaped, tapered or other shapes. The distance between the grid structures can be changed according to the requirements or the configuration of Ϊ / 0. The fifth and sixth figures are examples of the embodiment, and a plurality of solder balls 3 2 are electrically connected to the printed circuit board (PCB) 40 (Shown in the fifth picture), the solder ball 32 is connected to a printed circuit board, as shown in the seventh picture, so as to form a thermal and electrical connection. The bump 30a is connected to the wafer 22, and the other end is connected by a wire (picture Figure 32d) Connecting to solder ball 32 »Ball ball 32 can be formed by ball matrix array (bga) technology" To strengthen the bonding ability with PCB and prevent contact oxygen It is also possible to cover the surrounding area under the wafer 22 with a filler material 42. The process of the present invention is shown in the seventh figure 'First, a soft board 26 having a metal circuit 30 attached is first prepared and used on the metal circuit 30. The solder ball mask 34 defines the area of the solder ball. The area where the bumps 30a are formed is exposed. Then, as shown in the seventh figure, the mold 44 is used to press the metal plate 30 to form the bumps 30a. Different I / O bumps 30a can be formed through the molds 44 of different designs. After completion, the above-mentioned soft board 26 is bonded to the wafer 22 by using an adhesive or an adhesive layer 24. Then, the laser or the thermal head is used to push the projections. The point 30a is soldered on the pad 28. For heat dissipation or protection, a heat sink 50 or a metal layer 5 1 can be attached to the bottom surface of the chip 22 with an adhesive material 48 (fifth picture). The solder ball is It is made on the traditional ball-planting method. In order to prevent the joint of the bump 30a and the solder joint of the wafer from oxidizing, anti-oxidation treatment can also be implemented. For example, the adhesive substance 46 is filled in the joint mlll !! m using a dispensing method. — 装 i —! Ί 1 order ---! 1 · line < Please read the back first (Note * Please fill in this page again.) 4 4989 7 A7 _B7 V. Description of the invention () The word “Zhouwei Zhou” is in the same category as the law, and its inner figure is attached. Its golden figure is the eighth form. Show 0C Cheng 3 I / Ming Weifa, one of the other points of the production system, this display. The overlay of the seven-point convexity is limited to showing the use of the TTJN households, and it's clear that the hair has been issued but the case is out of the rule. Disappearance is not good, it is better than the ordinary ones. The Ming Weifa Fanbenli is only for the application of the application, and the statement of the application for the application shall be repaired or modified. Ended around the next fan Shenli Jingzhu (please read the precautions on the back before filling this page >

哀--111 — — I 訂-- ------I 經濟部智慧財產局員工消費合作杜印製 本紙張尺度適用中國國家標準（CNS)A4規格（210x297公釐）Ai --111 — — I Order------- I Printed by the consumer cooperation of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper size applies to China National Standard (CNS) A4 (210x297 mm)

Claims (1)

449897 申請專利範圍 ABCD .-種半導趙構楚，該半導體構裝包含： 一半導體晶片； 軟板’藉由—點合材質貼合在該晶片的表面之上，該孝 合物質將曝露出該晶片之I/O焊塾區域： H線路’形成於該軟板之上，其表面具有複數個&點， 連接於該谭塾，作為電性傳導之橋樑：及 導電錫球’位於該金屬線路之植球區域上 性傳遞之裝置。 Μ對外部1 2·:π:::;第1項之半導想構裝，其中上述之軟 3.如申請專利範圍第1項之半導體構裝，其中 線路材質包含銅。 上述之金屬 4,如申請專利範圍第1項之半導體構裝， 料將該I/O接合處覆蓋，作為防氧化處理。 5.如申請專利範圍第！項之半導體構裝， & ·已含黏封物質 填充於形成該I/O接合處之區域。 ----^-I;------^------'W-----▲ (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局貝工消貧合作社印製 6.如申請專利範圍第1項之半導體構裝，其中 其截面為V型。 上述之凸點 本紙烺尺度適用中國國家標準（CNS ) Λ4规格（2丨0X297公釐） s J AB,CD 經濟部中央標準局員工消費合作社印袈 々、申請專利範圍 7. 如申請專利範圍第1項之半導體構裝，其中上述之凸點 其裁面為U型。 8. 如申請專利範圍第1項之半導體構裝，其中上述之凸點 其截面為尖錐型a 9. 如申請專利範圍第1項之半導體構裝，其中上述之Λ點 其截面為實心之金屬球。 10. 如申請專利範圍第1項之半導體構裝，更包含貼附或鍍 上一散熱裝置於該晶月之上。 11. 如申請專利範圍第1項之半導體構裝’其中上述之金屬 線路具有柵狀結構或格狀結構以利於形成凸點。 12. 如申請專利範圍第Π項之半導體構裝，其中上述之焊 墊位於該晶片之中央區域。 13. 如申請專利範圍第12項之半導體構裝’其中上述之柵 狀結構或格狀結構對應於該晶片之中央區域.。 14. 如申請專利範圍第U項之半導體構裝，其中上述之焊 墊位於該晶片之週邊區域。 本紙張尺度適用肀囷國家標準（CNS ) A4規格（210X297公釐） J ^^11T-----"線 (請先閲讀背面之注意事項再填寫本頁) 4^989 7 A8 as Cs D8 申請專利範圍 申請專利範圍第14項之半導體構裝，其中 結構或格狀結構對應於該晶片之週邊區域。上崠 2·—種製作半導㉟構裝之方*，該方法包 -Γ». lag 罝一具有金屬線路所附著之敕板並定義出植 赴用棋具施壓於該金屬線路之上以形 < 远 點； W為 利用點合材質將該軟板與一晶片黏合， 上之焊墊接合；及 將與垓 植導電錫球於該植球區域之上。 蜱； 晶片 17,如申請專利範圍第16項之方法，其令上 用金屬附著之方式形成一實心凸點^ 之凸點可利 ί靖先間靖背tg之注意事項再填寫本頁J 复------ 之 19.如申請專利範圍第18項之方法， 穴T上述之防氧化 理包含利用點膠方式將黏封物質填充於府士、_ 、疋於办成該I/O接合處 之區域。 訂· -線. 經濟部中央標準局負工消費合作社印製 20. 如申請專利範圍第17項之方法，其中上述之焊墊與凸 點之接合係包含利用雷射將該凸點銲接於該焊整之上。 21. 如申請專利範圍第17項之方法，其中上述之焊墊與凸 II 本紙浪尺度適用中國國家標準（CNS ) Λ4規格（2Ι〇Χ 297公釐） 449897 A8 B8 C8 D8 、申請專利範圍 點之接合係包含利用熱壓頭將該凸點銲接於該焊塾之上 裝 訂-----—線 (請先閱讀背面之注意事項再填寫本頁) 經濟部十央梯準局員工消費合作社印策 / 本紙張尺度適用中國國家標毕（CNS ) Λ4現格（210X297公釐）449897 Patent application scope ABCD .- A kind of semi-conductor Zhao Gouchu, the semiconductor structure includes: a semiconductor wafer; a flexible board is bonded to the surface of the wafer by a point-fitting material, and the filial substance will be exposed The I / O solder pad area of the chip: The H-line 'is formed on the flexible board, and its surface has a plurality of & points connected to the Tan pad, as a bridge for electrical conduction: and a conductive solder ball is located at the Device for sexual transmission on the ball-planted area of metal lines. Μ for the external 1 2 ·: π :::; The semiconducting structure of the first item, of which the above is soft 3. The semiconductor structure of the first item of the scope of patent application, wherein the circuit material contains copper. The above-mentioned metal 4, such as the semiconductor structure of the first patent application scope, is expected to cover this I / O junction as an oxidation prevention treatment. 5. If the scope of patent application is the first! The semiconductor structure of the item, & • already contains a sealing substance filled in the area forming the I / O junction. ---- ^-I; ------ ^ ------ 'W ----- ▲ (Please read the notes on the back before filling this page) Central Bureau of Standards, Ministry of Economic Affairs Printed by poor cooperatives 6. If the semiconductor device of the first patent application scope, the cross section is V-shaped. The above-mentioned paper scales of the bump are applicable to the Chinese National Standard (CNS) Λ4 specification (2 丨 0X297 mm) s J AB, CD, printed by the Consumer Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs, and the scope of patent application. The semiconductor device of 1 item, wherein the above-mentioned bumps have a U-shaped cut surface. 8. For the semiconductor device in the scope of patent application item 1, the cross section of the above mentioned bumps is a tapered a. 9. In the semiconductor device for the scope of patent application, the cross section of the above Λ point is solid Metal ball. 10. If the semiconductor structure of the first patent application scope includes attaching or plating a heat sink on the crystal moon. 11. The semiconductor device according to item 1 of the scope of the patent application, wherein the above-mentioned metal circuit has a grid structure or a grid structure to facilitate the formation of bumps. 12. For a semiconductor package in accordance with item Π of the application, wherein the above-mentioned pads are located in the central area of the wafer. 13. For the semiconductor structure of item 12 of the application scope, wherein the above-mentioned grid structure or lattice structure corresponds to the central region of the wafer. 14. For a semiconductor package in the U application, the pads are located in the peripheral area of the wafer. This paper size is applicable to the national standard (CNS) A4 specification (210X297 mm) J ^^ 11T ----- " line (Please read the precautions on the back before filling this page) 4 ^ 989 7 A8 as Cs D8 Patent Application Scope The semiconductor structure of the 14th patent application scope, wherein the structure or lattice structure corresponds to the peripheral area of the wafer.崠 2 · —A kind of method for making semi-conducting cymbals. This method includes -Γ ». Lag 罝 has a cymbal board attached to a metal circuit and defines a go-to-use chess set to put pressure on the metal circuit to Shape < far point; W is to bond the soft board to a wafer using a point bonding material, and the pads are bonded; and a conductive tin ball is planted on the planted area. Tick; Wafer 17, if the method in the scope of patent application No. 16 is applied, it will form a solid bump with a metal attachment method ^ The bump can benefit the attention of Jing Xianjian Jing back tg. ------ No. 19. If the method in the scope of patent application No. 18, the above-mentioned oxidation prevention method of the hole T includes the use of a dispensing method to fill the sealing material in the official, _, and I to do the I / O The area of the joint. Order ·-. Printed by the Consumers' Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 20. If the method of applying for the scope of patent No. 17 is adopted, wherein the bonding between the pad and the bump includes welding the bump to the Welded on top. 21. For the method of claim 17 in the scope of patent application, in which the above-mentioned pads and convex II paper waves are applicable to the Chinese National Standard (CNS) Λ4 specification (2Ι〇 × 297 mm) 449897 A8 B8 C8 D8 The joining system consists of welding the bumps to the welding pad with a thermal head and binding them. (-Please read the precautions on the back before filling this page.) Shiyang Elevator Bureau, Ministry of Economic Affairs, Consumer Consumption Cooperative Indian policy / This paper size is applicable to Chinese National Standards (CNS) Λ4 now (210X297 mm)
TW088120744A 1999-11-24 1999-11-24 Semiconductor package TW449897B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW088120744A TW449897B (en) 1999-11-24 1999-11-24 Semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW088120744A TW449897B (en) 1999-11-24 1999-11-24 Semiconductor package

Publications (1)

Publication Number Publication Date
TW449897B true TW449897B (en) 2001-08-11

Family

ID=21643174

Family Applications (1)

Application Number Title Priority Date Filing Date
TW088120744A TW449897B (en) 1999-11-24 1999-11-24 Semiconductor package

Country Status (1)

Country Link
TW (1) TW449897B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7576992B2 (en) 2005-12-23 2009-08-18 Au Optronics Corp. Flexible printed circuit and display device utilizing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7576992B2 (en) 2005-12-23 2009-08-18 Au Optronics Corp. Flexible printed circuit and display device utilizing the same

Similar Documents

Publication Publication Date Title
US6326700B1 (en) Low profile semiconductor package and process for making the same
TWI272705B (en) Heat spreader and package structure utilizing the same
US6819003B2 (en) Recessed encapsulated microelectronic devices and methods for formation
US6426875B1 (en) Heat sink chip package
TW312844B (en)
TW495943B (en) Semiconductor package article with heat sink structure and its manufacture method
TW410446B (en) BGA semiconductor package
TWI353047B (en) Heat-dissipating-type semiconductor package
JP2001520460A (en) Method and structure for improving heat dissipation characteristics of package for microelectronic device
TW200415766A (en) Thermally enhanced semiconductor package with EMI shielding
TW432558B (en) Dual-chip packaging process and method for forming the package
TW461064B (en) Thin-type semiconductor device having heat sink structure
WO2023098545A1 (en) Packaging structure for large-current power semiconductor device and packaging method therefor
TW200534454A (en) Exposed pad module integrated a passive device therein
TW449897B (en) Semiconductor package
JP2000232186A (en) Semiconductor device and its manufacture
KR100251868B1 (en) Chip scale semiconductor package using flexible circuit board and manufacturing method thereof
KR100230189B1 (en) Ball grid array semiconductor package
TW200915458A (en) Test socket and test board for wafer level semiconductor testing
TW200522298A (en) Chip assembly package
JP3529507B2 (en) Semiconductor device
TW200845354A (en) Multi-chip semiconductor device having leads and method for fabricating the same
TW409327B (en) Array metal plug package
TW432644B (en) Ball grid array package with printed trace line and metal plug
TWI324029B (en) Circuit board structure having embedded semiconductor chip

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees