4 485 五、發明說明（i) 【發明領域】 本發明係有關於-種多晶片封袭構造（㈣⑴―chip module, MCM)，特別有關热 ^ n ,, ^ 銲整位於側邊中多晶片封裝構造用以封裝 先前技術】 二越來越輕薄短小，使得用以保護半導體晶 1菌於σ卩電路連接的封裝構造也同樣需要輕薄短小 ίοίϋ 構造（thin 嶋11 〇utline package, 蘭)即為一具代表性之薄形化封裝構造。 #❸郭封扁構造之主要訴求即為較薄之封裝厚度 1CklleSS)，薄小輪廟封裝構造之厚度約為1毫 未’而傳統之薄小輪廊封裝構造（smau。⑴⑽^毫 S = i或薄小輪廓卜腳封裝構造(Smai 1 outl —4 485 V. Description of the invention (i) [Field of the invention] The present invention relates to a multi-chip sealing structure (㈣⑴-chip module, MCM), and particularly relates to a thermal chip ^ n ,, ^ multi-chip welding on the side The packaging structure is used to encapsulate the previous technology.] Two are becoming lighter and thinner, so that the packaging structure used to protect the semiconductor crystal 1 in the σ 卩 circuit connection also requires a thin and thin structure (thin 嶋 11 〇utline package, blue). A representative thinned package structure. # ❸Guo Fengbian's main demand is a thinner package thickness (1CklleSS), the thickness of the thin small round temple package structure is about 1 milli ', and the traditional thin small corridor package structure (smau. i or thin outline bu pin package structure (Smai 1 outl —
J i e a d， S 0 J )封奘姐、± * 庙 * 1C 薄小輪廓封裝構造已：：則約為2· 5至3, 5毫米。由於 配合措施也已發展；^成為主流技術之—’且相關週邊 市場接受。*展成熟，所以其極具成本優勢，且也#為J i e a d, S 0 J) Feng Yijie, ± * Temple * 1C thin small outline package structure has :: about 2.5 to 3, 5 mm. As cooperating measures have also been developed; ^ has become the mainstream technology — 'and relevant peripheral markets have accepted. * Exhibition is mature, so it has a cost advantage, and also # 为
此外，隨荖斜t η 'J 封裝構造在化以及高運作速度需求的增加’多晶片 可藉 泎夕電子裝置越來越吸引人◊多晶片封裝構、± J错由將兩個以u η〜衣稱造 統運作速度之限制，曰曰片組合在單一封裝構造巾’來使系 晶片間連接線^ :小化。此外，多晶片封裝構造可減少 碁參s ’塔之長度而降低訊號延遲以及存取時間。In addition, with the increasing slant t η 'J packaging structure and increasing demand for high operating speeds' multi-chips can be more and more attractive by electronic devices. Multi-chip packaging structures, ± J by the two reasons u η ~ Limited by the limitation of the speed of the system operation, it is said that the chips are combined in a single package structure to make the connecting lines between the system chips ^: small. In addition, the multi-chip package structure can reduce the length of the sage tower and reduce the signal delay and access time.
取'霄見的客曰 U J 片封裝構'土 ’ = /封裝構造為並排式（Slde_by~side)多晶 共同i板Ϊ丄亚係將兩個以上之晶片彼此並排地安裝於二 __面。晶片與共同基板上導電^路間之 4485 1 b .修正 月 曰 案號 89100691 五、發明說明（2) 係藉由線輝法(Wlre b〇nding)。然而該並排式多 册片ί裝構造之缺點為封裝效率太低，因為可用之晶片安 裝區域只限於該共同基板之一面。 因此半導體業界發展出將晶片分別安裝於—共同基板兩 ，的多晶片封裝構造100 (請參照第―圖）。然而該兩面 式（tv/onded)多晶片封裝構造1〇〇之缺點為封裝厚度1法 降低’因為該封膠體HO必須騰出空間以容納連接線 (b⑽ding wire)120、13〇。若晶片與共同基板上導電線路 間之連接採用覆晶（f丨ip chip)的方式，其雖可降低封裝 厚度，然而由於覆晶尚未成為主流技術之一，且其相關週 邊配合措施也未發展成熟，因此將增加製造成本。 【發明概要】 本發明之主要目的係提供一種多晶片封裝構造，其厚度 可降低而利用習用薄小輪廓封裝構造之製程技術製造，因 而降低製造成本。 根據本發明較佳實施例之多晶片封裝構造，其主_赛含 兩第一晶片以及兩第二晶片分別安裝於一基板之上 及下表面，其係藉由一導線架與外界連接。該基板具有一 槽縫位於其中央。該基板之上表面設有複數個第一晶片連 接墊（chip bonding pad)位於其左右兩側邊，該基板之上 表面設有複數個第二晶片連接墊位於該基板槽縫之兩側， 該基板設有複數個基板銲墊（contac t pad)電性連接至相 對應的複數個第一晶片連接墊以及複數個第二晶片連接 塾。該導線架係固設於該基板並且電性連接至相對應的基 板銲墊。該每一晶月皆具有複數個晶片銲墊位於其正面之 " --------------------------------------------Λ Ρ99-0丨8.ptc 第6頁 ---89100691 _年月 曰 佟_ 五、發明說明（3) --— 側邊:，兩第一晶片之背面係固設於該基板之上表面。該 ，第一=片之正面係固設於該基板之下表面使得該兩第二 =片之，數個晶片銲墊係裸露於該基板之槽縫。該兩第— 曰曰片之複數個晶片銲墊係分別電性連接至該基板之複數個 第一晶片連接墊。該兩第二晶片之複數個晶片銲墊係分別 電性連接至該基板之複數個第二晶片連接墊。該基板、導 ，架、兩第一晶片、兩第二晶片係為一封膠體包覆使得該 導線架有部分自該封膠體向外延伸用以與外界電性溝通。 根，本發明較佳實施例之多晶片封裝構造，由於其封裝 效率冋，因此該多晶片封裝構造之厚度可降低而利用習用 薄小輪廓封裝構造之製程技術製造’因而降低製造成本。 為了讓本發明之上述和其他目的、特徵、和優點能更明 顯特徵’下文特舉本發明較佳實施例，並配合所附圖示， 作詳細說明如下。 【發明說明】 請參照第二圖、第三圖以及第四圖，其揭示根據本 較佳實施例之多晶片封裝構造3〇〇，其主要包含一基板g 310、一導線架320、兩第一晶片33〇、兩第二晶片34〇以及 一封膠體35 0。該基板310具有一槽缝（sl〇t)312位於其中 央。違基板3 1 0之上表面設有複數個第一晶片連接塾3 14位 於其左右兩側邊。該基板3 1 0之上表面設有複數個第二晶 片連接墊3 1 6位於該基板3 1 0之槽縫3 1 2之兩側。該基板3 1 〇 之上表面設有複數個基板銲墊3 1 8電性連接至相對應的複 數個第一晶片連接墊3 1 4以及複數個第二晶片連接塾3 i 6。 可以理解的是有複數條導電線路（未示於圖中）設於基板Take 'Xiao Jian's guest's UJ chip package structure' 土 '= / package structure is side-by-side (Slde_by ~ side) polycrystalline common i-board sub-system, two or more wafers are installed side by side on two __ side . 4485 1 between the conductive path on the wafer and the common substrate. B. Amendment No. 89100691 V. Description of the invention (2) is made by Wlre bonding. However, a disadvantage of this side-by-side multi-blade mounting structure is that the packaging efficiency is too low, because the available wafer mounting area is limited to only one side of the common substrate. Therefore, the semiconductor industry has developed a multi-chip package structure 100 in which chips are mounted on two common substrates (see FIG. 1). However, the disadvantage of the two-sided (tv / onded) multi-chip package structure 100 is that the package thickness is reduced by 1 method because the sealing colloid HO must make room to accommodate the bonding wires 120 and 13. If the connection between the chip and the conductive lines on the common substrate is fip chip, although it can reduce the package thickness, as the flip chip has not become one of the mainstream technologies, and its related peripheral coordination measures have not been developed. Maturity will therefore increase manufacturing costs. [Summary of the Invention] The main object of the present invention is to provide a multi-chip package structure whose thickness can be reduced and manufactured using a conventional thin-profile package structure manufacturing technology, thereby reducing manufacturing costs. According to the multi-chip package structure of the preferred embodiment of the present invention, the main package includes two first chips and two second chips, which are respectively mounted on the upper and lower surfaces of a substrate, and are connected to the outside through a lead frame. The substrate has a slot in its center. The upper surface of the substrate is provided with a plurality of first chip bonding pads on its left and right sides, and the upper surface of the substrate is provided with a plurality of second chip bonding pads on both sides of the substrate slot. The substrate is provided with a plurality of substrate pads (contac t pads) electrically connected to the corresponding plurality of first chip connection pads and the plurality of second chip connection pads. The lead frame is fixed on the substrate and is electrically connected to a corresponding substrate pad. Each crystal moon has a plurality of wafer pads located on the front side of it ----------------------------------- ------------ Λ Ρ99-0 丨 8.ptc Page 6 --- 89100691 _ 年月 月 佟 _ V. Description of the invention (3) --- Side: two first The back surface of the wafer is fixed on the upper surface of the substrate. The front face of the first sheet is fixed on the lower surface of the substrate such that the two second pads, and several wafer pads are exposed in the slots of the substrate. The plurality of wafer bonding pads of the first and second wafers are electrically connected to the plurality of first wafer connection pads of the substrate, respectively. The plurality of wafer bonding pads of the two second wafers are respectively electrically connected to the plurality of second wafer connection pads of the substrate. The substrate, the guide, the frame, the two first wafers, and the two second wafers are covered with a colloid, so that the lead frame partially extends outward from the encapsulation for electrical communication with the outside world. As a result, the multi-chip package structure of the preferred embodiment of the present invention can reduce the thickness of the multi-chip package structure due to its low packaging efficiency. The multi-chip package structure can be manufactured using the conventional thin- and small-profile package manufacturing process technology, thereby reducing manufacturing costs. In order to make the above and other objects, features, and advantages of the present invention more apparent, the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings. [Explanation of the Invention] Please refer to the second, third, and fourth figures, which show a multi-chip package structure 300 according to the preferred embodiment, which mainly includes a substrate g 310, a lead frame 320, two first One wafer 330, two second wafers 3440, and one colloid 350. The substrate 310 has a slot 312 in the center. A plurality of first chip connections 塾 3 and 14 are located on the upper surface of the base board 3 1 0 on the left and right sides thereof. A plurality of second wafer connection pads 3 1 6 are provided on the upper surface of the substrate 3 1 0 on both sides of the slot 3 1 2 of the substrate 3 1 0. A plurality of substrate pads 3 1 8 are electrically connected to a corresponding plurality of first wafer connection pads 3 1 4 and a plurality of second wafer connection pads 3 i 6 on the upper surface of the substrate 3 1 〇. It can be understood that there are a plurality of conductive lines (not shown) provided on the substrate.
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d 485 , 修正 Θ 五、發明說明（5) 置。該封膠體3 5 0之材質係為絕緣材料，較佳5塑料 ’molding compound)為 Hitachi Chemical Company 提供之 CEL-9200XU 塑料。 ' 可以理解的是該兩半導體晶片可以將一般常見之銲墊位 在中央之晶片（centra 1-pad design Chip)，經由鮮塾重 佈（pad-rerouting)之加工步驟而得到晶片銲墊位於正 側邊之半導體晶片。 ' 請再參照第一圖及第四圖，就該習用之多晶片封装構造 100而言，由於在該晶片102、104與封膠體11〇邊緣之 須騰出空間來容納連接線12〇、130，因此其封 = 有效降低。就本發明之多晶片封裝構造3〇〇而古又無^法 2 =40之背面與封膠體35{)邊緣之間不 、在 納金線342，因此其封裝厚度可以降低。 門來各 根據本發明較佳實施例之多晶片 會增加該多晶片封裝構造…，因ΠΪΪ 製粒技術製造，因而降低製造成本。 之 雖然本發明已以前述較佳施 =明’任何熟習此技藝者’在不脫離；限 晶片封裝槿/ ί 動與修改。例如根據本發明之多 晶片封含兩個或四個半導體晶片之多 根據本發明之=佳實施例，然而可以理解的是 體晶片。因此本四：以上之半導 所界定者為準。護範圍虽視後附之申請專利範圍d 485, correction Θ V. Description of the invention (5). The material of the sealing compound 3 50 is an insulating material, preferably 5 plastic (molding compound) is a CEL-9200XU plastic provided by Hitachi Chemical Company. '' It can be understood that the two semiconductor wafers can place the common pads in the center (centra 1-pad design Chip), and obtain the wafer pads in the positive position through the pad-rerouting process. A semiconductor wafer on the side. '' Please refer to the first figure and the fourth figure again. As far as the conventional multi-chip package structure 100 is concerned, space must be made on the edges of the wafers 102 and 104 and the sealing compound 11 to accommodate the connecting wires 12 and 130. , So its seal = effective reduction. According to the multi-chip package structure 300 of the present invention, there is no ancient method 2 = 40. The backside and the edge of the sealing compound 35 {) are not within the nanowire 342, so the package thickness can be reduced. The multi-chips according to the preferred embodiment of the present invention will increase the multi-chip package structure ..., which is manufactured by the ΠΪΪ granulation technology, thereby reducing the manufacturing cost. Although the present invention has been described in the foregoing preferred embodiment, 'anyone skilled in the art' will not depart from it; it is limited to chip packaging and modification and modification. For example, as many wafers according to the present invention contain as many as two or four semiconductor wafers. According to the present invention, the preferred embodiment is a bulk wafer, but it can be understood. Therefore, the definition of the fourth: the semi-conductor above shall prevail. Although the scope of protection depends on the scope of patent application attached
Η P99-018.ptc 第9頁 4485 i 8 _案猇 89100691_年月曰_修正 圓式簡單說明 【圖示說明】 第1 圖 習 用 多 晶 片 封裝 構造之剖 面圖 r 第2 圖 * 根 據 本 發 明 較佳 實施例之 多晶 片封 裝 構造移除 封膠體 後 之 上 視 圖 > 第3 圖 ; 根 據 本 發 明 較佳 實施例之 多晶 片封 裝 構造移除 封膠體 後 之 下 視 圖 > 及 第4 圖 根 據 本 發 明 較佳 實施例'之 多晶 片封 裝 構造之剖 面示圖 〇 【圖號 說 明 ] 100 多 晶 片 封 裝 構 造 102 晶片 104 晶 片 110 封膠體 120 連 接線 130 連 接 線 300 多 晶 片 封 裝 構 造 310 基板 312 槽 缝 314 晶片連接塾 316 晶 片連接墊 318 基 板 銲 墊 320 導線架 322 導 線 厂'、 324 金 線 330 晶片 3 3 0a 晶片銲參 332 金 線 340 晶片 340a 晶片銲墊 342 金 線 350 封膠體Η P99-018.ptc Page 9 4485 i 8 _ Case 猇 89100691_ Year Month _ Corrected Circular Simple Description [Illustration] Figure 1 Cross-sectional view of a conventional multi-chip package structure r Figure 2 * According to the present invention Top view of the multi-chip package structure of the preferred embodiment after removing the sealant > FIG. 3; bottom view of the multi-chip package structure of the preferred embodiment after removing the sealant > and FIG. 4 according to A cross-sectional view of a multi-chip package structure according to a preferred embodiment of the present invention. [Explanation of the drawing number] 100 multi-chip package structure 102 chip 104 chip 110 sealing compound 120 connection line 130 connection line 300 multi-chip package structure 310 substrate 312 slot 314 Wafer connection 塾 316 Wafer connection pad 318 Substrate pad 320 Lead frame 322 Wire factory ', 324 Gold wire 330 Wafer 3 3 0a Wafer welding parameter 332 Gold wire 340 Wafer 340a Wafer pad 342 Gold wire 350 Sealant
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