經濟部智慧財產局員工消費合作社印製 447 12 1 A7 6060twf. doc/ 008 B7 五、發明說明（丨） 本發明是有關一種半導體元件的製造方法，且特別是 有關一種堆疊式電容器（Stacked Capacitor)下電極的製造方 法。 .電容器是動態隨機存取記憶體（Dynamic Random Access Memory ; DRAM)中的重要元件。由於現行DRAM 的集積度日漸提高，爲盡可能增大電容器的表面積，常見 的作法是將DRAM中的電容器與位元線配置於不同的晶 圓層中，謂之堆疊式電容器結構。一般來說，DRAM中的 電容器與位元線之配置型式有「位元線位於電容器之上」 (Bit line on Capacitor; BOC)與「電容器位於位元線之上」 (Capacitor on Bit line ; COB)兩種，其中以 COB 型式之 DRAM較爲常見。 在習知技藝中，COB型式之DRAM中的堆疊式電容 器下電極的製造過程簡述如下。請參照第1A圖，首先提 供基底100，此基底100中已形成有節點接觸窗（Node Contact)110，再於基底100上沈積氧化矽層120。接著於 氧化砂層120上形成位元線130，再於基底100上沈積氧 化砂層140。 請參照第1Β圖，接著進行一微影蝕刻製程，以於氧 化矽層120與140中形成電容器接觸窗（Capacitor Contact Opening)l5〇，再於基底100上沈積多晶矽層160，此多晶 矽層160將電容器接觸窗開口 150塡滿而形成電容器接觸 窗 160a。 請參照第1C圖，接下來再進行一次微影蝕刻製程以 3 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (靖先閲璜背面之注$項再填寫本頁) 裝 -- - - ---訂--- 447121 6060t;vf.doc/008 A7 B7 經濟部智慧財產局員工消費合作杜印製 五、發明說明（j) 圖案化多晶砂層160 ’而形成電容器下靈極1纟01)。 , 然而，上述習知之堆疊式電容器的製造方法卻有下列 缺點。其一是定義電容器接觸窗開□ 150與電容器下電極 160b時各須一次微影蝕刻步驟，所以其製程較爲複雜。 其二請參照第圖，由於電容器接觸窗〗60a與位元 線130緊臨，故容易因爲電容器接觸窗開口 150之定位誤 差，而導致電容器接觸窗160a與位元線130短路，此即 表示製作電容器接觸窗開口 150之微影蝕刻製程的裕度 (Margin)甚小。 其三，在習知技藝中，爲了提高製作電容器接觸窗開 口 150之微影飩刻製程的裕度，常見的作法是形成較窄的 位元線Π0，以使位元線130與電容器接觸窗開口 150之 距離增大。然而，較窄的位元線130具有較大的電阻，如 此會使元件的運作效率降低。 本發明提出一種堆疊式電容器下電極的製造方法，其 可用來解決習知技藝之製程較複雜、微影蝕刻製程裕度較 低與位元線寬度受限的問題。此方法適用於已形成有一節 點接觸窗之一基底上，其步驟如下。首先於基底上依序形 成一絕綠層、第一導體層與一 離層，再依序圖案化隔離 層與第一導體層，以使保留之第一導體層與隔離層成爲一 位元線與一帽蓋層。 接下來的作法可分爲兩種，其一是繼續圖案化此絕緣 層，以暴露出節點接觸窗，然後於帽蓋層、位元線與圖案 化之絕緣層的側壁形成一間隙壁。其二是先形成間隙壁於 4 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐〉 (請先閱讀背面之注意事項再填寫本頁) b Λιν 447 彳 2 1 A7 6060twf. doc/ 008 β7 五、發明說明（） 帽蓋層與位元線之側壁，再以此間隙壁與帽蓋層爲罩幕， 蝕去暴露出之絕緣層，並將節點接觸窗暴露出來。此處間 隙壁、位元線與帽蓋層合稱爲位元線結構。 上述兩種作法的後續步驟是相同的，即形成第二導體 層於基底上，再圖案化此第二導體層以形成一電容器下電 極，此電容器下電極係覆蓋於部分的位元線結構上，且與 節點接觸窗電性連接。 另外，上述本發明之自行對準之堆疊式電容器的製造 方法中，更可加上在形成電容器下電極之後，再圖案化此 電容器下電極，以形成具有更大表面積的冠狀電容器下電 極。再者，在形成冠狀電容器下電極之後，更可加上形成 半球形矽晶粒於冠狀電容器下電極之上的步驟，以進一步 增加電容器的面積。 如上所述，本發明之堆疊式電容器下電極的製造方法 具有下列好處。 其一，在本發明之堆疊式電容器下電極的製造方法 中，係以帽蓋層與間隙壁將位元線隔離，然後再於基底上 沈積並定義第二導體層，以形成電容器下電極。因此，本 發明不需習知技藝中定義電容器接觸窗開口 150(請參照第 1B圖）的微影蝕製程，而得以節省整體製程所需時間 其二，在本發明之堆疊式電容器下電極的製造方法 中，係先在位元線之上方與側邊形成帽蓋層與間隙壁，再 沈積並蝕刻第二導體層以形成電容器下電極。因此，使用 本發明時沒有習知技藝中電容器接觸窗與位元線短路的問 5 (請先閲讀背面之注意事項再填窝本頁) -i ! !I 訂·-------- Λ)/ 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 447121 A7 B7 6060twf ,ci〇c/〇〇8 五、發明說明（4 ) 題’而能使電容器下電極的製程裕度大爲增加。 其三，由於在本發明之堆疊式電容器下電極的製造方 法中’位元線上方與側邊以帽蓋層與間隙壁隔離，所以位 元線的寬度與此製程裕度之相關性很小，而可以形成較寬 的位元線以減少電阻，並增加元件的運作效率。 爲讓本發明之上述目的、特徵、和優點能更明顯易懂， 下文特舉一較佳實施例，並配合所附圖式，作詳細說明如 下： 圖式之簡單說明： 第1A-1C圖所繪示爲習知之堆疊式電容器下電極的製 造方法流程剖面圖。 第2A-2E圖所繪示爲本發明第一實施例之堆疊式電容 器下電極的製造方法流程剖面圖。 第3A-3E圖所繪示爲本發明第二實施例之堆叠式電容 器下電極的製造方法流程剖面圖。 圖式之標號說明： 100、200、300 :基底 110、210、310 :節點接觸窗 120、140 :氧化矽層 130、230a、330a :位元線 150 :電容器接觸窗開口 160 :多晶矽層 160a :電容器接觸窗 160b ' 270a、370a :電容器下電極 6 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） <請先間讀背面之注意事項再填寫本頁) -a— K n a— ϋ ϋ - 經濟部智慧財產局員Η消費合作社印製 A7 447 12 1 6060twf*doc/008 五、發明說明（匕） (清先間讀背面t生意事項再填寫本頁) 220、320 :絕緣層 230、270、330、370 :導體層 240、340 :隔離層 240a、340a :帽蓋層 250、350 :間隙壁 260、360 :位元線結構 270b、370b :冠狀電容器下電極 280、380 :半球形矽晶粒 第一實施例 請參照第2A圖，首先提供基底200，其中形成有節 點接觸窗210。接著於基底上依序形成絕緣層220、導體 層230與隔離層240。其中絕緣層220之材質例如爲氧化 矽，導體層230之材質例如爲多晶矽，而隔離層240之材 質例如爲氮化矽（SiN)或氮氧化矽（SiON)。 請參照第2B圖，接著使用非等向性蝕刻法依序圖案 化隔離層240、導體層230與絕緣層220，以使保留之導 體層23〇與隔離層240成爲位元線230a與帽蓋層240a， 並將節點接觸窗210暴露出來。 經濟部智慧財產局員工消費合作社印製 請參照第2C圖，接著於帽蓋層240a '位元線230a與 圖案化之絕緣層220的側壁形成間隙壁250，此間隙壁250 之材質例如爲氮化矽或氧化矽，而其形成方法爲沈積加非 等向性触刻。此處間隙壁25〇 '位元線230a與帽蓋層240a 合稱爲位元線結構260。接下來於基底200上形成導體層 21〇，其材質例如爲多晶矽。 1 本紙張尺度適用令國國家標f(CNS)A4規格（210x297公釐) --- 447121 6060twf.doc/008 A7 B7 經濟部智慧財產局員工消費合作社印製Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 447 12 1 A7 6060twf.doc / 008 B7 V. Description of the Invention (丨) The present invention relates to a method for manufacturing a semiconductor element, and particularly to a stacked capacitor (Stacked Capacitor) Manufacturing method of lower electrode. Capacitors are important components in Dynamic Random Access Memory (DRAM). Due to the increasing accumulation of the current DRAM, in order to maximize the surface area of the capacitor, a common method is to arrange the capacitor and the bit line in the DRAM in different wafer layers, which is called a stacked capacitor structure. In general, the configuration types of capacitors and bit lines in DRAM include "Bit line on Capacitor (BOC)" and "Capacitor on Bit line; COB ) Two types, of which COB type DRAM is more common. In the conventional art, the manufacturing process of the lower electrode of a stacked capacitor in a COB type DRAM is briefly described as follows. Referring to FIG. 1A, a substrate 100 is first provided. A node contact 110 has been formed in the substrate 100, and then a silicon oxide layer 120 is deposited on the substrate 100. Next, bit lines 130 are formed on the oxidized sand layer 120, and then an oxidized sand layer 140 is deposited on the substrate 100. Please refer to FIG. 1B, and then perform a lithography etching process to form a capacitor contact opening 150 in the silicon oxide layers 120 and 140, and then deposit a polycrystalline silicon layer 160 on the substrate 100. The polycrystalline silicon layer 160 will The capacitor contact window opening 150 is full to form a capacitor contact window 160a. Please refer to Figure 1C, and then perform the lithography etching process again to apply the Chinese National Standard (CNS) A4 specification (210 X 297 mm) to 3 paper sizes. (Jing first read the note on the back and fill in this page. ) Packing-----Order --- 447 121 6060t; vf.doc / 008 A7 B7 Consumption cooperation between employees of the Intellectual Property Bureau of the Ministry of Economic Affairs Du printed 5. Description of the invention (j) Patterned polycrystalline sand layer 160 ' Capacitor bottom pole 1 纟 01). However, the conventional method for manufacturing a stacked capacitor has the following disadvantages. One is to define a lithographic etching step for each of the capacitor contact window opening 150 and the capacitor lower electrode 160b, so the process is more complicated. Secondly, please refer to the figure, because the capacitor contact window 60a is close to the bit line 130, it is easy to short the capacitor contact window 160a and the bit line 130 due to the positioning error of the capacitor contact window opening 150. This means the production The margin of the lithography process of the capacitor contact window opening 150 is very small. Third, in the conventional art, in order to increase the margin of the lithography process for making the capacitor contact window opening 150, a common method is to form a narrow bit line Π0, so that the bit line 130 and the capacitor contact window The distance of the opening 150 is increased. However, the narrower bit line 130 has a larger resistance, which will reduce the operating efficiency of the device. The invention proposes a method for manufacturing a lower electrode of a stacked capacitor, which can be used to solve the problems of complicated manufacturing process, low lithography etching process margin and limited bit line width. This method is suitable for one of the substrates where a point contact window has been formed. The steps are as follows. First, a green layer, a first conductor layer, and a separation layer are sequentially formed on the substrate, and then the isolation layer and the first conductor layer are sequentially patterned, so that the retained first conductor layer and the isolation layer become a bit line. Layer with a cap. The next method can be divided into two types. One is to continue patterning the insulating layer to expose the node contact window, and then forming a gap wall on the cap layer, the bit lines, and the sidewall of the patterned insulating layer. The second is to form a gap wall at 4 paper sizes to apply Chinese National Standard (CNS) A4 specifications (210 X 297 mm) (please read the precautions on the back before filling this page) b Λιν 447 彳 2 1 A7 6060twf. doc / 008 β7 V. Description of the invention () The side wall of the cap layer and the bit line, and then the gap wall and the cap layer are used as the screen, and the exposed insulation layer is etched away, and the node contact window is exposed. This The gap wall, the bit line and the cap layer are called a bit line structure. The subsequent steps of the above two methods are the same, that is, forming a second conductor layer on the substrate, and then patterning the second conductor layer to form A capacitor lower electrode, which covers part of the bit line structure and is electrically connected to the node contact window. In addition, in the above-mentioned manufacturing method of the self-aligned stacked capacitor of the present invention, it can further add After the capacitor lower electrode is formed, the capacitor lower electrode is patterned to form a crown-shaped capacitor lower electrode with a larger surface area. Furthermore, after the crown-shaped capacitor lower electrode is formed, a hemisphere can be further formed. The step of silicon crystals on the lower electrode of the crown capacitor to further increase the area of the capacitor. As described above, the method for manufacturing the lower electrode of the stacked capacitor of the present invention has the following advantages. First, under the stacked capacitor of the present invention In the manufacturing method of the electrode, the bit line is separated by a capping layer and a barrier wall, and then a second conductor layer is deposited and defined on the substrate to form a capacitor lower electrode. Therefore, the present invention does not need to know the definition in the art The lithography process of the capacitor contact window opening 150 (refer to FIG. 1B) can save the time required for the overall process. Second, in the method for manufacturing the lower electrode of the stacked capacitor of the present invention, it is first in the bit line. A cap layer and a gap wall are formed on the upper side and the side, and then a second conductor layer is deposited and etched to form the lower electrode of the capacitor. Therefore, when using the present invention, there is no question 5 in which the capacitor contact window is shorted to the bit line in the conventional art Read the precautions on the back before filling in this page) -i!! I Order · -------- Λ) National Standards (CNS) A4 size (210 X 297 mm) 447121 A7 B7 6060twf, ci〇c / 〇〇8 V. invention is described in (4) of the title 'margin and the process can lower capacitor electrode is greatly increased. Third, in the method for manufacturing the lower electrode of the stacked capacitor of the present invention, the bit line is separated from the gap wall by a cap layer above and from the side, so the width of the bit line has little correlation with the process margin. A wider bit line can be formed to reduce resistance and increase the operating efficiency of the device. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Brief description of the drawings: Figures 1A-1C The drawing is a cross-sectional view of a conventional method for manufacturing a lower electrode of a stacked capacitor. Figures 2A-2E are cross-sectional views illustrating a method for manufacturing a lower electrode of a stacked capacitor according to a first embodiment of the present invention. Figures 3A-3E are cross-sectional views of a method for manufacturing a lower electrode of a stacked capacitor according to a second embodiment of the present invention. Description of the symbols of the drawings: 100, 200, 300: substrates 110, 210, 310: node contact windows 120, 140: silicon oxide layers 130, 230a, 330a: bit lines 150: capacitor contact window openings 160: polycrystalline silicon layer 160a: Capacitor contact windows 160b '270a, 370a: Capacitor lower electrode 6 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) < Please read the precautions on the back before filling this page) -a— K na— ϋ ϋ-Printed by A7 447 12 1 6060twf * doc / 008, a member of the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperatives V. Description of the Invention (Dagger) (Read the business matters on the back before Qing and then fill out this page) 220, 320: Insulation layers 230, 270, 330, 370: Conductor layers 240, 340: Isolation layers 240a, 340a: Cap layers 250, 350: Spacers 260, 360: Bit line structures 270b, 370b: Crown capacitor lower electrodes 280, 380 : First Embodiment of Hemispherical Silicon Die Please refer to FIG. 2A. First, a substrate 200 is provided, and a node contact window 210 is formed therein. Then, an insulating layer 220, a conductor layer 230, and an isolation layer 240 are sequentially formed on the substrate. The material of the insulating layer 220 is, for example, silicon oxide, the material of the conductive layer 230 is, for example, polycrystalline silicon, and the material of the isolation layer 240 is, for example, silicon nitride (SiN) or silicon oxynitride (SiON). Referring to FIG. 2B, the isolating layer 240, the conductor layer 230, and the insulating layer 220 are sequentially patterned using an anisotropic etching method, so that the retained conductor layer 23 and the isolating layer 240 become bit lines 230a and caps. Layer 240a, and expose the node contact window 210. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, please refer to Figure 2C, and then form a gap 250 on the cap layer 240a 'bit line 230a and the sidewall of the patterned insulating layer 220. The material of this gap 250 is, for example, nitrogen Silicon or silicon oxide, and its formation method is deposition plus anisotropic etching. Here, the spacer line 250 ′ bit line 230a and the cap layer 240a are collectively referred to as a bit line structure 260. Next, a conductive layer 21 is formed on the substrate 200, and the material is, for example, polycrystalline silicon. 1 This paper size applies to the national standard f (CNS) A4 specification (210x297 mm) --- 447121 6060twf.doc / 008 A7 B7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs
五、發明說明（G) 請參照第2D圖，接下來圖案化導體層270以形成電 容器下電極270a，此電容器下電極270a係覆蓋於部分之 位元線結構260上，且與節點接觸窗210電性連接。 請參照第2E圖，接著再圖案化此電容器下電極270a ^ 以形成具有更大表面積的冠狀電容器下電極270b，然後再 形成半球形矽晶粒280於冠狀電容器下電極270b，以進一 步增加電容器的面積。 筮二實施例 請參照第3A圖，首先提供基底300，其中形成有節 點接觸窗310。接著於基底上依序形成絕緣層320、導體 層330與隔離層340。其中絕緣層320之材質例如爲氧化 矽，導體層3250之材質例如爲多晶矽，而隔離層340之材 質例如爲氮化矽（SiN)或氮氧化矽（SiON)。 請參照第3B圖，接著使用非等向性蝕刻法依序圖案 化隔離層340、導體層330，以使保留之導體層330與隔 離層340成爲位元線330a與帽蓋層340a，再於帽蓋層340a 與位元線330a之側壁形成間隙壁350。此間隙壁350之材 質例如爲氮化矽（SiN)，而其形成方法爲沈積加非等向性蝕 刻。此處間隙壁350、位元線330a與帽蓋層340a合稱爲 位元線結構360。 請參照第3C圖，接著以位元線結構360爲罩幕，使 用非等向蝕刻法除去暴露出的絕緣層320，以使節點接觸 窗310暴露出來。接下來於基底300上形成導體層370， 其材質例如爲多晶矽。 S 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閲讀背面之注意事項再填寫本頁) 0裝V. Description of the Invention (G) Please refer to FIG. 2D. Next, the conductor layer 270 is patterned to form a capacitor lower electrode 270a. The capacitor lower electrode 270a covers part of the bit line structure 260 and contacts the node window 210. Electrical connection. Please refer to FIG. 2E, and then pattern the capacitor lower electrode 270a ^ to form a crown capacitor lower electrode 270b with a larger surface area, and then form a hemispherical silicon grain 280 on the crown capacitor lower electrode 270b to further increase the capacitor's area. Second Embodiment Referring to FIG. 3A, a substrate 300 is first provided, and a node contact window 310 is formed therein. An insulating layer 320, a conductor layer 330, and an isolation layer 340 are sequentially formed on the substrate. The material of the insulating layer 320 is, for example, silicon oxide, the material of the conductive layer 3250 is, for example, polycrystalline silicon, and the material of the isolation layer 340 is, for example, silicon nitride (SiN) or silicon oxynitride (SiON). Referring to FIG. 3B, the isolating layer 340 and the conductive layer 330 are sequentially patterned using an anisotropic etching method, so that the remaining conductive layer 330 and the isolating layer 340 become the bit line 330a and the capping layer 340a, and then The cap layer 340 a and the sidewall of the bit line 330 a form a gap 350. The material of the spacer 350 is, for example, silicon nitride (SiN), and the formation method is deposition plus anisotropic etching. Here, the spacer 350, the bit line 330a, and the cap layer 340a are collectively referred to as a bit line structure 360. Referring to FIG. 3C, the bit line structure 360 is used as a mask, and the exposed insulating layer 320 is removed by anisotropic etching so that the node contact window 310 is exposed. Next, a conductive layer 370 is formed on the substrate 300, and the material is, for example, polycrystalline silicon. S This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page) 0 Pack
· I I I I 線C· ^ 447121 A7 6060twf.doc/008 B7 五、發明說明（7) 請參照第3D圖，接下來圖案化導體層370以形成電 容器下電極370a，此電容器下電極370a係覆蓋於部分之 位元線結構360上，且與節點接觸窗310電性連接。 請參照第3E圖，接著再圖案化此電容器下電極370a， 以形成具有更大表面積的冠狀電容器下電極370b，然後再 形成半球形矽晶粒380於冠狀電容器下電極370b，以進一 步增加電容器的面積。 如上所述，本發明較佳實施例之堆疊式電容器的製造 方法具有數種好處，分別敘述如下。 其一，由於在本發明之較佳實施例中，係以帽蓋層240a (340a)與間隙壁250 (350)將位元線230a (330a)隔離，然後 再沈積導體層270 (370)，並加以定義而形成電容器下電極 27〇a (370a)，因此本發明不需習知技藝中定義電容器接觸 窗開口 150 (請見第1B圖)的微影蝕刻製程，而得以節省 整體製程所需時間 其二，在本發明之較佳實施例中，係在位元線230a (330a)上方與側邊形成帽蓋層240a (340a)與間隙壁250 (350)，再沈積並蝕刻導體層270 (370)以形成電容器下電 極270a (370a)。因此，使用本發明時不會發生習知技藝中 電容器接觸窗160a與位元線U0 (第1B圖）短路的問題， 而能使電容器下電極的製程裕度大爲增加。 其三，由於位元線230a (330a)上方與側邊以帽蓋層 240a (340a)與間隙壁250 (350)隔離，所以位元線230a (330a) 的寬度與此製程裕度之相關性很小，而可以形成較寬的位 9 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公楚） (請先閱讀背面之注意事項再填寫本頁) i — ί— I 訂·！丨 I!-線-C3 經濟部智慧財產局員工消費合作杜印製 447 12 1 A7 __6060tw£ doc/ 008_B7_ 五、發明說明（$ ) 元線230a (330a)以減少電阻，並增加元件的運作速率。 雖然本發明已以一較佳實施例掲露如上，然其並非用 以限定本發明，任何熟習此技藝者’在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 <請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）IIII line C ^ 447121 A7 6060twf.doc / 008 B7 V. Description of the invention (7) Please refer to FIG. 3D, and then pattern the conductor layer 370 to form the capacitor lower electrode 370a. The capacitor lower electrode 370a is partially covered. The bit line structure 360 is electrically connected to the node contact window 310. Please refer to FIG. 3E, and then pattern the capacitor lower electrode 370a to form a crown capacitor lower electrode 370b with a larger surface area, and then form a hemispherical silicon grain 380 on the crown capacitor lower electrode 370b to further increase the capacitor's area. As described above, the method for manufacturing the stacked capacitor according to the preferred embodiment of the present invention has several advantages, which are respectively described below. First, in the preferred embodiment of the present invention, the bit line 230a (330a) is isolated by the cap layer 240a (340a) and the spacer 250 (350), and then the conductor layer 270 (370) is deposited, The capacitor lower electrode 27oa (370a) is defined to form the capacitor. Therefore, the present invention does not require the lithographic etching process for defining the capacitor contact window opening 150 (see FIG. 1B) in the conventional technique, thereby saving the overall process requirements. Secondly, in a preferred embodiment of the present invention, a cap layer 240a (340a) and a spacer 250 (350) are formed above and to the side of the bit line 230a (330a), and then the conductor layer 270 is deposited and etched (370) to form a capacitor lower electrode 270a (370a). Therefore, when the present invention is used, the problem that the capacitor contact window 160a and the bit line U0 (FIG. 1B) are short-circuited in the conventional art does not occur, and the process margin of the capacitor lower electrode can be greatly increased. Third, because the bit line 230a (330a) is separated from the spacer 250 (350) above and to the side by a cap layer 240a (340a), the width of the bit line 230a (330a) is related to the process margin. It is small and can form a wide bit 9 This paper size is applicable to China National Standard (CNS) A4 (210 X 297 Gongchu) (Please read the precautions on the back before filling this page) i — ί — I Order · !!丨 I! -Line-C3 Consumer Cooperation of Intellectual Property Bureau of the Ministry of Economic Affairs Du printed 447 12 1 A7 __6060tw £ doc / 008_B7_ V. Description of the Invention ($) Meta wire 230a (330a) to reduce resistance and increase the operating speed of components . Although the present invention has been disclosed above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application. < Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)