TW445654B

TW445654B - EEPROM manufacture method and its device

Info

Publication number: TW445654B
Application number: TW88112149A
Authority: TW
Inventors: Guo-Yu Jou
Original assignee: Winbond Electronics Corp
Priority date: 1999-07-17
Filing date: 1999-07-17
Publication date: 2001-07-11

Abstract

The present invention discloses an EEPROM manufacture method and its device. A local oxidation and etching process is used to form an U-type groove on the semiconductor substrate. Then, tips are formed between the U-type groove and substrate, so as to make the injection of electrons easy and further reduce the operation voltage of device. Besides, the formation method is a self-aligned process, which is highly compatible with standard semiconductor process.

Description

4 4 5 6 5 4 五、發明說明（1) 本發明係有關於一種半導體記憶元件，特別是有關於一種利用局部氧化製程（LOCOS)以形成尖點，使電子移除更為便捷的一種電氣抹除式可編程唯讀記憶體單元之製造方法及其裝置。電氣抹除式可編程唯讀s己憶體（Electrical Erasable4 4 5 6 5 4 V. Description of the invention (1) The present invention relates to a semiconductor memory element, and more particularly to an electrical device that uses a local oxidation process (LOCOS) to form sharp points and make electron removal more convenient. Manufacturing method and device of erasable programmable read-only memory unit. 1. electrical erasable programmable read-only memory

Programmable Read Only Memory，其後以EEPR0M 簡稱之）為現今資訊電子產品所廣泛採用的記憶元件，—般係以浮動閘極（floating gate)電晶體結構所構成；為清楚起見’在此，請參考第1圖所示習知之EEPR〇M單元，係設置於一矽基板10上’且於其内形成有一源極π，—汲極15，以及通道（channel)13。在ί及極15上方之碎基板1〇表面上方則依序為一薄氧化層（thin oxide)12，一浮動閘極14，一介電層18 ’以及一控制閘極（contr〇i gate)16，在控制閘極1 6舆矽基板1 〇之表面則形成有一氧化矽層丨9與場氧化層FOX，以作絕緣之用。如第1圖所示’此習知之EEPRO Μ單元係靠通過該薄氧化層12 ’其厚度約8〜l〇nm之Fowler-Nordheim穿隧效應 (F-N tunneling effect)而進行寫入程式與抹除數據之動作°當進行程式化（program)以抹除數據時，係施加一高電壓於此元件之控制閘極1 6與沒極1 5間；此時加至控制閘極16之兩電壓係因電容耗合至浮動閘極μ，因而在薄氧化層12處產生尚電場，使得電子因穿随效應而由汲極丨5穿過該薄氧化層12注入該浮動閘極14。反之，要寫入數據時，則施加一高電壓於汲極區1 5，且此控制閘極丨6與矽基板丄〇 445 65 4 五、發明說明（2) 接地，同樣的，由於電容耦合作用，因注生高電場’使得電子因穿隧效應而由浮重氧化層1 2注入該汲極1 5。然而，這種EEPROM單元在進行程式a 作時’往往必須要提供高的電壓；並且，程並非自我校準製程（sei f_al igned),因集度。同時，將電子注入浮動閘所需之電浮動閘所需之電壓高，這主要是因為浮動度不同所造成。故若希望降低元件之操作改善（降低）電子注入浮動閘時所需電壓。有鑑於此，本發明的一個目的在於提式可編程唯讀記憶體單元之製造方法，其準’且與現今半導體製程之相容性高。本發明之另一目的在於提供一種電氣讀记憶體單元之裝置’其能夠具有低電壓為了達到本發明之一個目的，係提供可編程唯讀記憶體單元之製造方法，包括一半導體基板，並於該半導體基板上形成絕緣物具有烏嘴狀之一尖端。接下來要進導體基板使之形成一 u型凹槽，且該u型凹物之該尖端。然後於該半導體基板中形成源/汲極區，並且，該等源/汲極區中之一物之該尖端與該U型凹槽。之後於該等源/ 體基板上方依序形成一閘極介電層、一浮 L薄氧化層1 2處產 >閘極1 4穿過該薄 *而寫入數據之操很顯然的，其製而降低元件之積壓比將電子移出閘與基板之平坦電壓’首先必須供一種電氣抹除製程係為自我校抹除式可編程唯操作的特性。一種電氣抹除式下列步驟：提供 ~絕緣物，且該行的是蝕刻該半槽係緊鄰該絕緣互為相隔之一對者係包圍該絕緣没極間之該半導動閘極、一閘間 445 65 4 五、發明說明（3) --- 介電層、與一控制閘極。在此需注意的是，本發明之尖點與u型凹憎之產生係藉由形成一具有鳥嘴形狀之絕緣物，並以其為畢幕，触'刻該具有半導體基板而形成’整體元件之製程係為自我校^ 準。為了達到本發明之另一目的，係提供一種電氣抹除式可編程唯讀記憶體單元之裝置，包括：一半導體基板=^ 具有一 U型凹槽；一對源/没極，互為相隔設置於該半導體基板中’且該等源/汲極中之一者係包圍該D型凹槽。並且包括一閘極介電層、一浮動閘極、一閘間介電層、與一控制閘極’係依序設置於該等源/汲極間之半導體基板之上方。此外’在該半導體基板與U型凹槽之間尚包括尖點，係使用局部氧化法’經蝕刻而形成於該浮動閘極與該半導體基板間之該半導體基板上。其中’當欲進行程式化或是抹除資料時，由於上述構造中之大點附近之電場強度高於平均電場強度許多，因此能夠降低操作電壓，並且使電子之注入或抹除更為便利。為讓本發明之上述目的、特徵、和優點能更明顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳細說明如下： ° 圖式之簡單說明：第1圖為習知之EEPROM之構造剖面圖；以及第2A〜2H圖顯示依據本發明之EEpR⑽之製造流程剖面圖。Programmable Read Only Memory (hereinafter referred to as EEPR0M for short) is a memory element widely used in today's information electronics products, which generally consists of a floating gate transistor structure; for the sake of clarity, 'here, please Referring to the conventional EEPROM cell shown in FIG. 1, it is disposed on a silicon substrate 10 ′, and a source π, a drain 15, and a channel 13 are formed therein. Above the surface of the broken substrate 10 above the electrode 15 is a thin oxide layer 12, a floating gate 14, a dielectric layer 18 ', and a controi gate in order. 16. On the surface of the control gate 16 and the silicon substrate 10, a silicon oxide layer 9 and a field oxide layer FOX are formed for insulation. As shown in Figure 1, 'the conventional EEPRO M unit is programmed and erased by passing the thin oxide layer 12' with a Fowler-Nordheim tunneling effect (FN tunneling effect) of about 8 to 10 nm in thickness. The action of data ° When the program is erased, a high voltage is applied between the control gate 16 and the immortal 15 of this component; at this time, the two voltage systems added to the control gate 16 Because the capacitor is dissipated to the floating gate μ, a high electric field is generated at the thin oxide layer 12, so that electrons are injected through the thin oxide layer 12 through the thin oxide layer 12 into the floating gate 14 due to the penetrating effect. On the other hand, when writing data, a high voltage is applied to the drain region 15 and the control gate 6 and the silicon substrate 445 445 65 4 5. Description of the invention (2) Grounding, too, due to capacitive coupling Due to the injection of a high electric field, electrons are injected into the drain electrode 15 from the floating heavy oxide layer 12 due to the tunneling effect. However, such an EEPROM cell must often provide a high voltage when performing a program; and, the process is not a self-calibration process (sei f_al igned) because of the degree of concentration. At the same time, the voltage required to inject electrons into the floating gate is high, which is mainly due to the different floating degrees. Therefore, if it is desired to reduce the operation of the component, improve (reduce) the voltage required for electron injection into the floating gate. In view of this, an object of the present invention is to provide a method for manufacturing a programmable read-only memory cell, which is highly compatible with current semiconductor processes. Another object of the present invention is to provide a device for electrically reading a memory cell, which can have a low voltage. In order to achieve one object of the present invention, a method for manufacturing a programmable read-only memory cell is provided. The method includes a semiconductor substrate, and An insulator is formed on the semiconductor substrate and has a pointed tip. Next, the conductor substrate is formed to form a u-shaped groove, and the tip of the u-shaped concave is formed. A source / drain region is then formed in the semiconductor substrate, and the tip and the U-shaped groove of one of the source / drain regions. After that, a gate dielectric layer and a floating L thin oxide layer 12 are sequentially formed over the source / body substrates. The gate 14 passes through the thin layer and writes data. Its system reduces the component's backlog ratio and moves the electrons out of the gate to the flat voltage of the substrate. First, an electrical erasing process must be self-calibrating and programmable. The following steps of an electrical erasing method: provide ~ insulators, and the line is to etch the half-slot system next to the insulation, and a pair of opposite sides is to surround the semi-conductive gate and a gate between the insulation poles. Time 445 65 4 V. Description of the invention (3) --- Dielectric layer and a control gate. It should be noted here that the sharp point of the present invention and the generation of the U-shaped recess are formed by forming an insulator with a bird's beak shape and using it as the curtain. The component manufacturing process is self-calibrating. In order to achieve another object of the present invention, an apparatus for electrically erasing programmable read-only memory cells is provided, which includes: a semiconductor substrate = ^ having a U-shaped groove; a pair of source / non-polarity, separated from each other It is disposed in the semiconductor substrate, and one of the source / drain electrodes surrounds the D-shaped groove. In addition, a gate dielectric layer, a floating gate, an inter-gate dielectric layer, and a control gate are sequentially disposed on a semiconductor substrate between the source / drain electrodes. In addition, a sharp point is included between the semiconductor substrate and the U-shaped groove, and is formed on the semiconductor substrate between the floating gate and the semiconductor substrate by etching using a local oxidation method. Among them, when programming or erasing data, since the electric field strength near the large point in the above structure is much higher than the average electric field strength, the operating voltage can be reduced, and electron injection or erasure is more convenient. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is described below in detail with the accompanying drawings, as follows: ° Brief description of the drawings: Figure 1 is A cross-sectional view of the structure of a conventional EEPROM; and FIGS. 2A to 2H show cross-sectional views of a manufacturing process of EEPR (R) according to the present invention.

445 65 4 五、發明說明符號說明 (4) 10 矽基板 11 源極 12 薄氧化層 13 通道 14 浮動閘極 15 汲極 16 控制閘極 18 閘間介電層 19 氧化矽層 FOX 場氧化層 20 矽基板 21 氮化石夕層 22 凹陷部 23 二氧化矽物 231 ' 232 尖端 24 ' 25 U型凹槽 241 P1、 ' 2 51 源/》及極 P2 尖點 FOX 場氧化層 26 閘極介電層 27 浮動閘極 28 實施例閘間介電層 29 控制閘極接下來’請參考第2 A至第2 G圖所示之流程剖面圖，以更具體地瞭解依據本發明之電氣抹除式可編程啫單元製造方法之較佳實施例。唯㈣體請參看第2A圖，係提供一半導體基板，例如是p型石夕基板20 ’且於其上形成有具有隔離物，如場氧化層[οχ用以界定出元件區，其厚度約在40 0 0〜800 0埃之間；以及絕緣物，其形成之方法請先參照第2B圖，係為在該石夕基板2〇之表面先形成一層經蝕刻定義其圖案之氮化矽層21，其具有一凹陷部22 ;接著，請參看第2C圖，係以局部氧化製程 (LOCOS) ’在該凹陷部22處形成二氧化矽物23，其厚度約445 65 4 V. Symbols of invention description (4) 10 Silicon substrate 11 Source 12 Thin oxide layer 13 Channel 14 Floating gate 15 Drain 16 Control gate 18 Intergate dielectric layer 19 Silicon oxide layer FOX field oxide layer 20 Silicon substrate 21 Nitride layer 22 Recessed portion 23 Silicon dioxide 231 '232 Tip 24' 25 U-shaped groove 241 P1, '2 51 Source / "and P2 sharp point FOX field oxide layer 26 Gate dielectric layer 27 Floating gate 28 Example of inter-gate dielectric layer 29 Control gate Next, please refer to the flow cross-sections shown in Figures 2A to 2G for a more specific understanding of the electrical erasing formula according to the present invention. A preferred embodiment of a method for programming a cell. Please refer to FIG. 2A for the corpuscle. A semiconductor substrate is provided, for example, a p-type stone substrate 20 ′, and a spacer is formed on the substrate, such as a field oxide layer. Between 400 and 800 angstroms; and the method of forming insulators, please refer to FIG. 2B, which is to form a silicon nitride layer on the surface of the Shixi substrate 20 to define its pattern by etching. 21, which has a recessed portion 22; then, referring to FIG. 2C, a local oxidation process (LOCOS) is used to form a silicon dioxide 23 at the recessed portion 22, with a thickness of about

445 65 4 五、發明說明（5) ' _ 在800 〜2000 埃之 pq n 士 + 夕e ί 在軋化矽物23與該氮化矽層21 之交界處形成有具烏嘴形狀（Bird，s Beak) 232;在此需注意的是，該二氧化砂物23可作以1與成的#刻u型凹槽所雪，#衣丨诚t . 、’要开/ 抑夕㈣需遮蔽層’且其所具有鳥嘴形狀之大鈿231與232係為用以形成本發明之尖點的條件之 -—- 〇接下來，要進行的步驟係為蝕刻該半導體基板使之形成一 U型凹槽，且該u型凹槽係緊鄰該絕緣物之該尖端；首先，如第2D圖所示，先要移除該氮化矽層21，例如，以非等向性蝕刻法（anisotr〇pic etching)，蝕刻位於該矽基板20表面之該氮化矽層21 ;接下來，請參看第2E圖，係以該具有鳥嘴形狀之二氧化矽物23及該場氧化層F0X為蝕刻罩幕’利用活性離子姓刻法（ReactiVe i〇n Etching， RIE)，向下蝕刻該矽基板2〇 ’以在該矽基板2〇中形成一u 型凹槽24與25 ’其深度約為2000埃；若由剖面圖觀之係呈一 U形之輪廓（p r 〇 f i 1 e)。緊接著，要進行的步驟係為於該半導體基板中形成互為相隔之一對源/汲極區，且該等源/汲極區中之一者係包圍該絕緣物之該尖端與該U型凹槽；例如，依據第2F圖所示之狀況，以該場氧化層FOX與該二氧化矽物23為離子植入罩幕，利用離子植入法，由U型凹槽24與25植入N型的離子，例如是砷離子，至該矽基板20内，以形成源極241與汲極2 5 1。最後，於該等源/汲極間之該半導體基板上方依序形445 65 4 V. Description of the invention (5) '_ At 800 ~ 2000 Angstroms pq n + + ee ί A spiral shape is formed at the junction of the rolled silicon 23 and the silicon nitride layer 21 (Bird, s Beak) 232; It should be noted here that the sand dioxide 23 can be made with 1 and ## u-shaped groove snow, # 衣丨诚 t., 'To open / suppress the evening need to be shielded The layers 231 and 232 which have a bird's beak shape are the conditions for forming the sharp points of the present invention. Next, the step to be performed is to etch the semiconductor substrate to form a U Groove, and the u-shaped groove is close to the tip of the insulator; first, as shown in FIG. 2D, the silicon nitride layer 21 is first removed, for example, by anisotropic etching (anisotr 〇pic etching), the silicon nitride layer 21 on the surface of the silicon substrate 20 is etched; next, referring to FIG. 2E, the silicon dioxide 23 having a bird's beak shape and the field oxide layer F0X are used for etching. The mask 'reactiVe inn Etching (RIE) is used to etch the silicon substrate 20 ′ downward to form a u-shaped recess in the silicon substrate 20 ′. 24 and 25 'to a depth of about 2000 Angstroms; If the form of a U-shaped profile (p r square f i 1 e) by a line cross-sectional View of FIG. Next, the steps to be performed are forming a pair of source / drain regions in the semiconductor substrate that are separated from each other, and one of the source / drain regions surrounds the tip of the insulator and the U For example, according to the situation shown in FIG. 2F, the field oxide layer FOX and the silicon dioxide 23 are used as ion implantation masks, and the U-shaped grooves 24 and 25 are implanted by the ion implantation method. N-type ions, such as arsenic ions, are introduced into the silicon substrate 20 to form a source electrode 241 and a drain electrode 2 51. Finally, the semiconductor substrates are sequentially formed on the semiconductor substrate between the source / drain electrodes.

445654 _ 五、發明說明（6) 成一閘極介電層、一浮動閘極、一閘間介電層、與一控制閘極，而完成一電氣抹除式可編程唯讀記憶體單元之製造；例如，仍請參考第2 F圖’由於所沈積之二氧化石夕物2 3 具有鳥嘴形狀之尖端231與232，因此，在移除該二氧化石夕物23之後，遂於該矽基板20之表面形成了兩個尖點P1與 P2，如第2G圖所示；接著，請參考第2H圖，以熱氧化法 (thermal oxidation) 於該具有U型凹槽24、25之石夕基板 2 0表面依序形成一閘極介電層2 6，例如是二氧化$夕層，且其厚度約在2 0 0〜6 0 0埃之間；在此需注意一般用以形成閘極氧化層（亦即随穿氧化層，tunneling oxide)之方法，基於其厚度要求薄’且品質高，因此必須以熱氧化法所形成。之後並以化學氣相沈積法（CVD)，依序於該閘極介電層26之表面形成一浮動閘極27，其材質係為複晶碎，且其厚度約在8 0 0〜2 0 0 0埃之間，一閉間介電層2 8，例如是氧化層/氮化層/氧化層（0/N/0)之結構，且其厚度約為2〇〇埃；以及一控制閘極29，其材質係為複晶矽，且其厚度約在 800〜2000埃之間；至此’而完成一電氣抹除式可編程唯讀記憶體單元之製造。 ° 如第2H圖所示’本發明之電氣抹除式可編程唯讀記憶體單元之構造，係設置於一矽基板2 〇上，包括：一對源/ >及極241與251 ’互為相隔設置於該碎基板2〇内；一由複g 矽所形成之浮動閘極27 ’係位於該對源/汲極241與251之上方’且在該浮動閘極27與該矽基板20間更包括一閘極介電層26 ’係由二氧化矽所形成；尖點P1、P2，係形成於該445654 _ V. Description of the invention (6) A gate dielectric layer, a floating gate, an inter-gate dielectric layer, and a control gate are completed to complete the manufacture of an electrically erasable programmable read-only memory unit ; For example, please refer to FIG. 2F again. “Since the deposited silica dioxide 2 3 has bird's beak-shaped tips 231 and 232, after removing the dioxide dioxide 23, the Two sharp points P1 and P2 are formed on the surface of the substrate 20, as shown in FIG. 2G. Next, please refer to FIG. 2H, and thermally oxidize the stone having the U-shaped grooves 24 and 25. A gate dielectric layer 26 is sequentially formed on the surface of the substrate 20, for example, an oxide layer, and its thickness is between about 200 and 600 angstroms. It should be noted that it is generally used to form a gate electrode. The oxide layer (that is, a tunneling oxide) method must be formed by thermal oxidation because of its thin thickness and high quality. Then, a chemical vapor deposition (CVD) method is used to sequentially form a floating gate 27 on the surface of the gate dielectric layer 26. The floating gate 27 is made of multiple crystals and has a thickness of about 80 to 20. Between 0 0 angstroms, a closed dielectric layer 28 is, for example, an oxide layer / nitride layer / oxide layer (0 / N / 0) structure, and its thickness is about 2000 angstroms; and a control gate The pole 29 is made of polycrystalline silicon and has a thickness of about 800 to 2000 angstroms. At this point, the manufacture of an electrically erasable programmable read-only memory cell is completed. ° As shown in FIG. 2H, 'The structure of the electrically erasable programmable read-only memory cell of the present invention is provided on a silicon substrate 20, and includes: a pair of sources /> and poles 241 and 251'. Are arranged in the broken substrate 20 separately; a floating gate 27 formed of complex silicon is 'located above the pair of source / drain electrodes 241 and 251' and between the floating gate 27 and the silicon substrate 20 In addition, a gate dielectric layer 26 ′ is formed by silicon dioxide; the sharp points P1 and P2 are formed at

ΙΙΗΙ IH 第9頁 445654 五、發明說明（7) 閘極介電層2 6與該矽基板2 〇之間；以及一控制閘極2 9，係位於該浮動閘極2 7之上方，且該控制閘極2 9與該浮動閘極 2 7之間更包括一閘間介電層28，係由氧化層/氮化層/氧化層所構成。本發明之電氣抹除式可編程唯讀記憶體之構造特徵主要係在於其製程間所製造之尖點，能讓電子之注入更為便捷，因而降低其操作電壓。然尖點形成之原因為：（丨）在局部氧化過程（LOCOS)中所形成之鳥嘴型氧化物，以及（2) 其所選用之RIE蝕刻製程具有非等向性蝕刻（anis〇tr〇pic etching)之特點’因此於該矽基板上形成尖點。此外，由於在尖端附近之電場強度係為平均場強之數倍以上，因而能夠達到降低操作電壓之目的，而使電子的注入更為便利。一般而言’要產生F-N tunneling其電場必須大於 10MV/cm，假設閘極介電層2〇〇〜600埃，而尖點之場強為平均場強之ίο倍，則浮動閘極與汲極之電壓差僅需2V 6V即可。相較於傳統元件之閘極介電層1〇〇〜200埃所需之電壓差10V〜20V ’本發明所需之操作電壓顯然大為降低。因此’本發明所提出之電氣抹除式可編程唯讀記憶體之新結構，不但具有低電壓操作之優點；很顯然地，由其製程步驟中’亦可發現其整個結構的形成係為自我校準〃 (sel f-al igned)過程，因而能夠達到高積集化之目的且與現今標準之半導體製程之相容性高，適合於量產。且由於本發明之閘極介電層之厚度較傳統元件之閘極介電層ΙΙΗΙ IH Page 9 445654 V. Description of the invention (7) Between the gate dielectric layer 26 and the silicon substrate 20; and a control gate 29, which is located above the floating gate 27, and An inter-gate dielectric layer 28 is further included between the control gate 29 and the floating gate 27, which is composed of an oxide layer / nitride layer / oxide layer. The structure characteristic of the electrically erasable programmable read-only memory of the present invention is mainly due to the sharp points manufactured during the manufacturing process, which can make the injection of electrons more convenient and thus reduce its operating voltage. However, the reason for the formation of sharp points is: (丨) a bird's beak oxide formed in the local oxidation process (LOCOS), and (2) the RIE etching process selected has anisotropic etching (anis〇tr〇). The feature of pic etching) is that sharp points are formed on the silicon substrate. In addition, since the electric field strength near the tip is several times the average field strength, the purpose of reducing the operating voltage can be achieved, and the electron injection is more convenient. Generally speaking, to generate FN tunneling, the electric field must be greater than 10MV / cm. Assuming that the gate dielectric layer is 200 ~ 600 Angstroms, and the field strength at the cusp point is ο times the average field strength, the floating gate and drain The voltage difference only needs 2V 6V. Compared with the voltage difference of 100 ~ 200 angstroms required for the gate dielectric layer of the conventional device, the voltage difference is 10V ~ 20V. The operating voltage required by the present invention is significantly reduced. Therefore, the new structure of the electrically erasable programmable read-only memory proposed by the present invention not only has the advantage of low-voltage operation; it is obvious that from the process steps, the formation of the entire structure is self. The calibration 〃 (sel f-al igned) process can achieve the purpose of high accumulation and has high compatibility with today's standard semiconductor processes, which is suitable for mass production. And because the gate dielectric layer of the present invention is thicker than the gate dielectric layer of a conventional device,

第10頁Page 10

445654 五、發明說明¢8) 厚，亦可提高元件之可靠度（reliability)，並降低缺陷 (defect)之產生。雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此項技藝者，在不脫離本發明之精神和範圍内，當可作更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。445654 V. Description of the invention ¢ 8) It can also increase the reliability of the component and reduce the occurrence of defects. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make changes and retouching without departing from the spirit and scope of the present invention. The scope of protection shall be determined by the scope of the attached patent application.

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Claims

445654 六、申請專利範圍 1‘ —種電氣抹除式可編程唯讀記憶體單元之製造方包括下列各項步驟：提供一半導體基板，並於該半導體基板上形成一絕緣而該絕緣物具有鳥嘴狀之一尖端；餘刻該半導體基板使之形成一 U型凹槽，且該u型凹槽係緊鄰該絕緣物之該尖端；於β亥半導體基板中形成互為相隔之一對源/汲極區，且該4源/没極區中之一者係包圍該絕緣物之該尖端與該U 型凹槽：以及於該等源/汲極間之該半導體基板上方依序形成一閘極介電層、一浮動閘極、一閘間介電層、與一控制閘極。 2. 如申請專利範圍第丨項所述之製造方法，尚包括蝕刻該半導體基板使成另一U型凹槽’其緊鄰該絕緣物之另一尖端，且該等源/汲極區中之另一者係包圍該絕緣物之該另一尖端與該另一 U型凹槽。 3. 如申請專利範圍第1項所述之製造方法等源/汲極區之後’更包括移除該絕緣物。 4_如申請專利範圍第1項所述之製造方法電層之材質係為氧化矽物。 5. 如申請專利範圍第1項所述之製造方法電層之材質係為氧化層/氛化層/氣化層。 6. 如申請專利範圍第1項所述之製造方法半導體基板係為（1 ο 〇)之矽基板。 / 7. 如申請專利範圍第1項所述之製造方法法物在形成該該閘極介該閘間介其中，該其中該絕 Η 第12頁 ^ 445 65 4 六、申請專利範圍緣物係為以^部氧化法所形成之烏嘴型氧化矽物。一 8.如申請專利範圍第1項所述之製造方法其令，該浮動閘極與該控制閘極係由複晶矽所構成。 9· 一種電氣抹除式可編程唯讀記憶體fUi包括： -半導體基板’其具有一㈣凹槽； ^ 一對源/没極，互為相隔設置於該半導體基板令，且邊等源/沒極中之一者係包圍該u型凹槽；以及一閑極介電層、一浮動閘極、一閘間介電層、與一控制閉極’係依序設置於該等源/汲極間之該半導體基板之上方。 10. 如申請專利範圍第9項所述之裝置，其中，該半導體基板尚包括另一U型凹槽，且該等源/汲極區中之另一者係包圍該另一U型凹槽。 11. 如申請專利範圍第9項所述之裝置’其中，在該半導體基板上更包括一鳥嘴狀之尖端，分別緊鄰該等U型凹槽。 1 2.如申請專利範圍第9項所述之裝置’其中，該閘間介電層之材質係為氧化層/氮化層/氧化層。 13. 如申請專利範圍第9項所述之裝置，其中，該半導體基板係為（100)之矽基板。 14, 如申請專利範圍第1〇項所述之裝置’其中，該半導體基板係為（100)之矽基板。 15‘如申請專利範圍第9項所述之裝置’其中，該浮動閘極與该控制閘極係由複晶石夕所構成。445654 VI. Application for patent scope 1'—The manufacturer of an electrically erasable programmable read-only memory unit includes the following steps: Provide a semiconductor substrate, and form an insulation on the semiconductor substrate, and the insulation has a bird A mouth-shaped tip; the semiconductor substrate is engraved to form a U-shaped groove, and the u-shaped groove is close to the tip of the insulator; a pair of sources / spacers are formed in the β-hai semiconductor substrate A drain region, and one of the 4 source / non-electrode regions surrounds the tip of the insulator and the U-shaped groove: and a gate is sequentially formed over the semiconductor substrate between the source / drain electrodes A gate dielectric layer, a floating gate, an inter-gate dielectric layer, and a control gate. 2. The manufacturing method as described in item 丨 of the patent application scope, further comprising etching the semiconductor substrate to form another U-shaped groove 'which is close to the other tip of the insulator, and The other is to surround the other tip of the insulator and the other U-shaped groove. 3. The manufacturing method described in item 1 of the patent application scope, etc. after the source / drain region 'further includes removing the insulator. 4_ The manufacturing method described in item 1 of the scope of patent application The material of the electrical layer is silicon oxide. 5. The manufacturing method described in item 1 of the scope of the patent application The material of the electrical layer is an oxide layer / atmosphere layer / gasification layer. 6. Manufacturing method as described in item 1 of the scope of patent application The semiconductor substrate is a silicon substrate (1 ο 〇). / 7. The manufacturing method as described in item 1 of the scope of patent application is forming the gate electrode and the gate electrode among them, and the gate electrode is the same. Page 12 ^ 445 65 4 It is a silica-shaped silicon oxide formed by the oxidation method. 8. According to the manufacturing method described in item 1 of the scope of patent application, the floating gate and the control gate are composed of polycrystalline silicon. 9. · An electrically erasable programmable read-only memory fUi includes:-a semiconductor substrate 'which has a groove; ^ a pair of sources / inverters, which are arranged on the semiconductor substrate at a distance from each other, One of the poles surrounds the u-shaped groove; and an idler dielectric layer, a floating gate, an inter-gate dielectric layer, and a control closed electrode are sequentially disposed on the sources / sinks. Above the semiconductor substrate between the electrodes. 10. The device according to item 9 of the scope of patent application, wherein the semiconductor substrate further includes another U-shaped groove, and the other one of the source / drain regions surrounds the other U-shaped groove . 11. The device according to item 9 of the scope of the patent application, wherein the semiconductor substrate further includes a bird's beak-shaped tip, which is adjacent to the U-shaped grooves, respectively. 1 2. The device according to item 9 of the scope of the patent application, wherein the material of the inter-gate dielectric layer is an oxide layer / nitride layer / oxide layer. 13. The device according to item 9 of the scope of patent application, wherein the semiconductor substrate is a (100) silicon substrate. 14. The device according to item 10 of the scope of the patent application, wherein the semiconductor substrate is a silicon substrate of (100). 15 'The device according to item 9 of the scope of patent application', wherein the floating gate and the control gate are composed of polycrystalline stone.

第13頁 445654 六、申請專利範圍 1 6.如申請專利範圍第9項所述之裝置，其中，該閘極介電層之材質係為氣化石夕物。第14頁Page 13 445654 6. Scope of patent application 1 6. The device described in item 9 of the scope of patent application, wherein the material of the gate dielectric layer is a gasified stone. Page 14