TW445597B - Manufacturing of semiconductor devices - Google Patents

Manufacturing of semiconductor devices Download PDF

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Publication number
TW445597B
TW445597B TW089100291A TW89100291A TW445597B TW 445597 B TW445597 B TW 445597B TW 089100291 A TW089100291 A TW 089100291A TW 89100291 A TW89100291 A TW 89100291A TW 445597 B TW445597 B TW 445597B
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Taiwan
Prior art keywords
substrate
wafer
layer
semiconductor
resin
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TW089100291A
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Chinese (zh)
Inventor
Takeshi Nakamigawa
Akisato Sato
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Nippon Electric Co
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Publication of TW445597B publication Critical patent/TW445597B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

A semiconductor chip has chip electrodes. An interconnection layer is connected to the chip electrodes. Contact terminals each in the form of a solder bump are connected to the interconnection layer.A substrate is formed on the semiconductor chip. A layer of resin is formed on the substrate. The provision of the layer of resin suppresses any warp and/or deformation of the substrate due to application of heat during processing step. This prevents occurrence of cracks at connection of the bump electrodes to a printed board.

Description

445597 五、發明說明（1) 【發明之背景】 發明之領域 本發明係關於一種半導體裝置及用以製造此半導體裝 置之製程。 、 習知枯術之描述 各種不同型式之半導體封裝技術已蓬勃發展，以符合 增加功能、縮小尺寸和重量、及增加電子設備之速度的需 求。舉例而言’在減少尺寸與重量的需求方面，可藉由在 一半導體晶片上增加元件之數目而滿足。 隨著積體電路半導體晶片技術之發展，個別的主動與 被動元件的尺寸已經變成很小，導致晶片中之元件數目急 劇增加。現代化晶片的尺寸亦有減少之傾向0允種傾向將 繼續維持，並重視用以作輸入/輸出連接之接觸端子的密 度與其整體數目逐漸提高的需求。常被稱為M疊合焊接"的 無引線焊接，係為一種廣泛使用的技術，用以在將晶片電 極、引線、與輸出端子疊合之後’將這些部分焊接在一 起。帶式自動焊接（TAB)屬於無引線焊接。 依據TAB技術，一疊層帶狀基板（於其中’每個金屬層 係呈配線引線之型式）被疊置在對應於半導體晶片之晶月 電極之金屬平板，並焊接至其上以形成複數之配線。美國 專利第5, 844, 304公報（日本特開平8-102466號公報）揭露 一種採用内凸塊焊接技術之半導體裝置製程。依據内凸塊 焊接’複數之晶片電極係被疊置於銅配線引線上之複數預445597 V. Description of the invention (1) [Background of the invention] Field of the invention The present invention relates to a semiconductor device and a process for manufacturing the semiconductor device. 2. Description of the conventional dry technique Various types of semiconductor packaging technologies have been developed vigorously to meet the needs of increasing functionality, reducing size and weight, and increasing the speed of electronic equipment. For example, 'the need to reduce size and weight can be met by increasing the number of components on a semiconductor wafer. With the development of integrated circuit semiconductor wafer technology, the size of individual active and passive components has become very small, resulting in a sharp increase in the number of components in the wafer. The size of modern chips also tends to decrease. The allowable tendency will continue to be maintained, and the demand for the density of the contact terminals used for input / output connections and the overall number of them to increase gradually is emphasized. Leadless soldering, often referred to as M-stacked soldering, is a widely used technique for welding these parts together after laminating wafer electrodes, leads, and output terminals. Tape automatic soldering (TAB) is a leadless soldering. According to TAB technology, a laminated ribbon substrate (wherein each metal layer is in the form of a wiring lead) is stacked on a metal flat plate corresponding to a crystal moon electrode of a semiconductor wafer and soldered thereon to form a plurality of Wiring. U.S. Patent No. 5,844,304 (Japanese Patent Application Laid-Open No. 8-102466) discloses a semiconductor device manufacturing process using an internal bump welding technique. A plurality of wafer electrodes based on internal bump bonding are stacked in advance on a plurality of copper wiring leads.

Λ455 9 五、發明說明（2) 定點，而疊置部分係藉由施加熱能或藉由施加熱能與超音 波而焊接。 參見圖9A-9G與10A-10D，將說明製造一種半導體裝置 之習知製程。如圖9 Α所示，係採用藉由包含有機絕緣材料 之聚醯亞胺而形成薄膜之基板2。於基板2之一主表面上， 形成包含複數銅配線引線之一互連層5。黏接劑4係塗佈於 互連層5之表面上。基板2形成複數開口部，而於圖9A僅顯 示一個開口部6。 參見圖9B與9C，圖9C係為圖9B之縱剖面。如圖9C所 示’基板2係以其塗佈之黏接劑4側向上的方式，被置於一 金屬框7中。 參見圖9D與9E，圖9E係為圖9D之縱剖面。複數半導體 晶片1係以預定圖案之配置，精確地安置於基板2上。然 後’藉由持續數秒施加熱能與壓力’可將複數半導體晶片 1予以焊接至基板2上。每個晶片1皆具有複數之晶片電極 10 = 參見圖9F與9G，圖9G係為圖9F之部份縱剖面之放大 圖。藉由施加熱能與超音波，可實施一種使用焊接工具8 之内凸塊焊接，以將複數之晶片電極1 0予以焊接至互連層 5之複數引線。 s 參見圖10A，於基板2上之複數晶片丨，係藉由***於 其T鄰兩者間的樹脂9而分離。一保護離子層3係形成於每 個晶片1之表面上，如圖9G所示。半導體晶圓係沿著切割 線切割，並在將複數之焊墊13予以沉積於互連層5之複數 4 45 5 9 7 五、發明說明（3) 引線上’與將複數之焊接凸塊12予以沉積於相對應的複數 焊墊1 3上之後，分割成複數之晶粒。 在分離之後，玻璃環氧纖維之一印刷版1 4，係於每個 晶粒上’藉由黏接劑9 1 3而焊接至晶片1之複數焊接凸塊1 2 上’如圖10B所示。 最後，如圖1 0C所示，將補強樹脂91 1塗佈至在每個焊 接凸塊1 2與基板2間之接點，以補強此接點。又，如圖1 〇 d 所示，樹脂9 12係被注入至在印刷版14與基板2間之間隔 中。注入的樹脂9 1 2係於施加熱能與壓力之後硬化。 已經由上述的方法製造之習知半導體裝置，係受到各 種各式之加熱與冷卻。舉例而言，於圖1〇B之處理步驟 中，印刷板1 4係於大約2 4 0 °C之溫度，被焊接至複數之焊 接凸塊1 2。偏壓溫度（BT)測試係於此半導體裝置上實施β 於此測試中，半導體裝置係以於大約125χ：持續24小時之 一預定電壓維持偏壓。又，為了確認在印刷版1 4與各焊接 凸塊1 2之間之焊接可靠度，吾人實施一種溫度循環測試。 於此溫度循環測試中，半導體裝置係被保持於變化的溫度 。環境内。於一個循環中，環境溫度係從—5〇。〇提升至 C，然後，從15 (TC下降至-50 t。此種循環一直重複。於 變化溫度環境中，循環重複之數目共計數百次。當未發現 任何裂痕時，即通過此種測試。 .- _半導體裝置之複數元件部分的熱膨脹係數係彼此不 =。舉例而言’當半導體晶片1係由矽（Si)所組成時，其 …膨脹係數係為3 ppm/t。當基板2係由包含有機絕緣材Λ455 9 V. Description of the invention (2) Fixed point, and the overlapped part is welded by applying heat energy or by applying heat energy and ultrasound. 9A-9G and 10A-10D, a conventional process for manufacturing a semiconductor device will be described. As shown in FIG. 9A, the substrate 2 is formed by using polyimide containing an organic insulating material to form a thin film. An interconnect layer 5 including a plurality of copper wiring leads is formed on a main surface of the substrate 2. The adhesive 4 is applied on the surface of the interconnection layer 5. The substrate 2 has a plurality of openings, and only one opening 6 is shown in FIG. 9A. 9B and 9C, FIG. 9C is a longitudinal section of FIG. 9B. As shown in FIG. 9C, the substrate 2 is placed in a metal frame 7 with the adhesive 4 applied thereon facing upward. 9D and 9E, FIG. 9E is a longitudinal section of FIG. 9D. The plurality of semiconductor wafers 1 are accurately arranged on the substrate 2 in a predetermined pattern configuration. Then, a plurality of semiconductor wafers 1 can be soldered to the substrate 2 by applying thermal energy and pressure for several seconds. Each wafer 1 has a plurality of wafer electrodes 10 = see Figs. 9F and 9G. Fig. 9G is an enlarged view of a part of the longitudinal section of Fig. 9F. By applying thermal energy and ultrasonic waves, a bump welding using a soldering tool 8 can be performed to solder a plurality of wafer electrodes 10 to a plurality of leads of the interconnection layer 5. Referring to FIG. 10A, the plurality of wafers on the substrate 2 are separated by a resin 9 interposed therebetween. A protective ion layer 3 is formed on the surface of each wafer 1, as shown in Fig. 9G. The semiconductor wafer is cut along a cutting line, and a plurality of solder pads 13 are deposited on the interconnection layer 5 in a plurality of 4 45 5 9 7 V. Description of the invention (3) On the leads' and a plurality of solder bumps 12 After being deposited on the corresponding plurality of pads 13, it is divided into a plurality of grains. After separation, one of the glass epoxy fiber printing plates 14 is tied to each die 'welded to the plurality of solder bumps 1 2 of the wafer 1 by the adhesive 9 1 3' as shown in FIG. 10B . Finally, as shown in FIG. 10C, a reinforcing resin 91 1 is applied to a contact between each solder bump 12 and the substrate 2 to reinforce the contact. As shown in FIG. 10 d, the resin 9 12 is injected into the space between the printing plate 14 and the substrate 2. The injected resin 9 1 2 is hardened after applying thermal energy and pressure. The conventional semiconductor device which has been manufactured by the above-mentioned method is subjected to various kinds of heating and cooling. For example, in the processing step of FIG. 10B, the printed board 14 is soldered to a plurality of solder bumps 12 at a temperature of about 240 ° C. A bias temperature (BT) test is performed on the semiconductor device. In this test, the semiconductor device is maintained at a predetermined voltage of about 125x: a predetermined voltage for 24 hours. In addition, in order to confirm the reliability of the welding between the printing plate 14 and each of the welding bumps 12, we performed a temperature cycle test. During this temperature cycling test, the semiconductor device is kept at a varying temperature. Within the environment. In one cycle, the ambient temperature is from -50. 〇Raise to C, and then decrease from 15 (TC to -50 t. This cycle is repeated all the time. The number of cycle repeats totals hundreds of times in a changing temperature environment. When no cracks are found, this test is passed .- _ The thermal expansion coefficients of the multiple element parts of the semiconductor device are not equal to each other. For example, when the semiconductor wafer 1 is composed of silicon (Si), its expansion coefficient is 3 ppm / t. When the substrate 2 Contains organic insulating materials

445 5 9 五、發明說明（4) 料之聚醯亞胺膜形成時’其熱膨脹係數係落在16_2〇ρρπι/ eC的範圍内。當印刷版1 4係由玻璃環氧樹脂所組成時，其 熱膨脹係數係落在16-50ppm/ °C的範圍内。基板2係介設於 具有比基板2的熱膨脹係數小的晶片1，與具有比基板2的 熱膨脹係數大的印刷版1 4之間。因此，在暴露於溫度之升 高與降低之後’基板2會有彎曲之傾向。基板2之變曲將應 力施加至互連層5上之母一個晶片電極與其中一個接觸 焊墊1 3間之接面，與每一個凸塊1 2與印刷版1 4間之接面， 導致於接面上產生裂痕。每一個焊接凸塊12係與其中一個 接觸焊墊13和具有不同熱膨脹係數之印刷版14直接接觸。 複數之焊接凸塊1 2亦與補強樹脂9 1 1或空間填滿樹脂9丨2接 觸’各自具有與各焊接凸塊12不同之熱膨脹係數。因此， 被施加至每一個焊接凸塊12與印刷版14間之焊^點的應力 相當大，導致發生於那邊之裂痕的可能性增加。裂痕發生 導致在半導體裝置内之接面的可靠度減少，並減少製造半 導體裝置之良率。 依據顯示於圖10C之構造’樹脂911可補強基板2與每 一個焊接凸塊1 2間之焊接點。但是，其無法將每一個焊接 凸塊12與印刷版14間之焊接點的強度增加至足夠之高位 準。依據顯示於圖10D之構造，樹脂912將印刷版14與基板 2之間的空間填滿。此空間係以樹脂91 2填滿，俾能使印刷 版1 4與基板2間的部分不再可能被利用，即使這些部分需 要修補亦是如此。 因此’本發明之一個目的係提供一種能避免裂痕之半445 5 9 V. Description of the invention (4) When the polyimide film of the material is formed, its thermal expansion coefficient falls within the range of 16_2 0ρρπι / eC. When the printing plate 14 is composed of glass epoxy resin, its thermal expansion coefficient falls in the range of 16-50 ppm / ° C. The substrate 2 is interposed between a wafer 1 having a smaller thermal expansion coefficient than that of the substrate 2 and a printing plate 14 having a larger thermal expansion coefficient than that of the substrate 2. Therefore, the substrate 2 tends to bend after being exposed to the increase and decrease in temperature. The deformation of the substrate 2 applies stress to the interface between a wafer electrode on the interconnect layer 5 and one of the contact pads 13 and the interface between each bump 12 and the printing plate 14, resulting in Cracks on the joints. Each solder bump 12 is in direct contact with one of the contact pads 13 and a printing plate 14 having a different thermal expansion coefficient. The plurality of solder bumps 1 2 are also in contact with the reinforcing resin 9 1 1 or the space-filling resin 9 丨 2 and each have a thermal expansion coefficient different from that of each of the solder bumps 12. Therefore, the stress applied to the solder joint between each of the solder bumps 12 and the printing plate 14 is relatively large, resulting in an increased possibility of cracks occurring there. The occurrence of cracks reduces the reliability of the interface in the semiconductor device and reduces the yield of manufacturing semiconductor devices. Resin 911 can reinforce the solder joint between the substrate 2 and each solder bump 12 according to the configuration shown in Fig. 10C. However, it cannot increase the strength of the solder joint between each solder bump 12 and the printing plate 14 to a sufficiently high level. According to the structure shown in Fig. 10D, the resin 912 fills the space between the printing plate 14 and the substrate 2. This space is filled with resin 91 2 so that the part between the printing plate 14 and the substrate 2 can no longer be used, even if these parts need to be repaired. Therefore, it is an object of the present invention to provide a half

445 5 9 / 五、發明說明（5) 導體裝置，與製造此種半導 適合於製造高良率之半導體裝置。之方法’此製造方法係 本發明之另一目沾及' 裝置，與製造此種半導體一種易於修補之半導體 τ子體裝置之方法。 【發明概要】 依據本發 置’包含：一 晶片具有複數 電極；複數之 至複數之接觸 熱膨脹係數與 曲與/或形變。 依據本發 置’包含：一 晶片具有複數 上’並連接至 明之一個 基板；一 之晶片電 接觸端子 端子；與 印刷版之 實施樣態，係提供了一 半導體“，位於基板上 極/互連層，連接至複數之晶片 ，連接至互連層；一印刷版，連接 一矯正機構，用以抑制由於基板之 熱膨脹係數所導致之基板的任何彎 明之另一 基板，一 之晶片電 複數之晶 刷版，連 上，用以 膨脹係數 互連層；一印 構，位於基板 與印刷版之熱 形變。. 依據本發 導體裝置，包 半導體晶片具有複數之 實施樣態，提供了 一種半導魏裝 半導體“，位於基板ΐ導匕 極；一互連層，形成於半導體晶片 片電極’·複數之接觸端子，連接至 接至複數之接觸端子；與一矯正機 抑制基板由於在基板之熱膨脹係數 間之差異所導致的任何彎曲與/或 明之一個 含：一基 具體的實施樣態，係提供了 一種半 板；一半導體晶片，位於基板上， 晶片電極；一互連層，形成於半導 ^45597 五、發明說明（6) '〜 體晶片上’並連接至複數之晶片電極；複數之接觸端子， 形成於互連層上’並連接到互連層.；及一樹脂層，形成於 基板上a 、 依據本發明之又另一實施樣態，係提供了一種半導體 襄置之製造方法，包含：形成一互連層於一半導體晶片 上’半導體晶片具有複數之晶片電極；形成一基板於半導 體晶片與互連層上；及藉由印刷，形成一樹脂層於基 上。 、双 依據本發明之又另一實施樣態，係提供了一種半導體 裴置之製造方法，包含：形成一互連層於一半導體晶片 上’半導體晶片具有複數之晶片電極；於半導體晶片與互 連層上形成一基板；與藉由黏性接合一樹脂補強薄板^基 板’形成一樹脂層於基板上。 【較佳實施例之說明】 第一較佳實施例： 參見附圖，圖1A至1G與圖2A至2F顯示用以製造依顯示 於圖3之本發明的第一較佳實施例之半導體裝置之步驟。 圖4顯示依第一較佳實施例之半導體裝置另一實施例。圖5 顯示依據第一較佳實施例之半導體裝置之又另一實施例。 依據第一較佳實施例之半導體裝置，可被埋入於球柵 陣列（BGA)或晶片尺寸封裝（CSP)中。從圖3可輕易地看 出’此種半導體裝置具有一種扇入構造，其中，複數之接 觸端子（例如焊接凸塊丨2)係形成於每個半導體晶片1上。 從圖1A至1G可輕易地看出，半導體裝置之製造係採用内凸445 5 9 / V. Description of the invention (5) Conductor devices and the manufacture of such semiconductors are suitable for the manufacture of high-yield semiconductor devices. Method 'This manufacturing method is another method of the present invention involving a device, and a method for manufacturing such a semiconductor τ daughter device which is easy to repair. [Summary of the Invention] According to the present invention ', it includes: a wafer having a plurality of electrodes; contact from a plurality to a plurality of coefficients of thermal expansion coefficient and curvature and / or deformation. According to the present invention, 'contains: a chip has a plurality of' and is connected to one of the substrates; one of the wafer's electrical contact terminals; and a printed version of the implementation mode, a semiconductor "is located on the substrate pole / interconnection Layer, connected to a plurality of wafers, connected to the interconnection layer; a printing plate, connected to a correction mechanism to suppress any bending of the substrate caused by the thermal expansion coefficient of the substrate, another substrate, and a wafer of multiple electrical crystals The printing plate is connected to the interconnection layer for expansion coefficient; a printing structure is located on the substrate and the thermal deformation of the printing plate .. According to the conductor device of the present invention, the packaged semiconductor wafer has a plurality of implementation modes, and a semiconductor device is provided. "Semiconductor" is located on the substrate; an interconnect layer is formed on the semiconductor wafer electrode "· plural contact terminals connected to the plural contact terminals; and a corrector suppresses the substrate due to the coefficient of thermal expansion of the substrate Any bending and / or mingling caused by the difference between them includes: a specific implementation aspect, which provides a half plate; A semiconductor wafer on a substrate, a wafer electrode; an interconnect layer formed on the semiconductor ^ 45597 V. Description of the invention (6) '~ on a bulk wafer' and connected to a plurality of wafer electrodes; a plurality of contact terminals formed on And a resin layer formed on the substrate a, according to another embodiment of the present invention, a method for manufacturing a semiconductor is provided, including: forming a semiconductor layer; The interconnect layer is on a semiconductor wafer. The semiconductor wafer has a plurality of wafer electrodes; a substrate is formed on the semiconductor wafer and the interconnect layer; and a resin layer is formed on the substrate by printing. According to yet another aspect of the present invention, a method for manufacturing a semiconductor device is provided, including: forming an interconnection layer on a semiconductor wafer; the semiconductor wafer has a plurality of wafer electrodes; A substrate is formed on the continuous layer; and a resin layer is formed on the substrate by adhesively bonding a resin-reinforced sheet to the substrate. [Description of the preferred embodiment] First preferred embodiment: Referring to the drawings, FIGS. 1A to 1G and FIGS. 2A to 2F show a semiconductor device for manufacturing a first preferred embodiment of the present invention shown in FIG. 3. The steps. FIG. 4 shows another embodiment of the semiconductor device according to the first preferred embodiment. FIG. 5 shows still another embodiment of the semiconductor device according to the first preferred embodiment. The semiconductor device according to the first preferred embodiment can be buried in a ball grid array (BGA) or a chip size package (CSP). It can be easily seen from FIG. 3 that this type of semiconductor device has a fan-in structure in which a plurality of contact terminals (e.g., solder bumps 2) are formed on each semiconductor wafer 1. It can be easily seen from FIGS. 1A to 1G that the semiconductor device is manufactured by using convex projection.

第10頁 4455 9 7 、 ’ ΐ·、發明說明（7) ~~1-- f烊接（ΙΒΒ)技術。以複數之晶片電極1〇被置於一互連層5 2預定位置’其乃藉由在麼力下之熱料，或在具有超 s〉·放射之壓力下的熱焊接，而被黏性接合於互連層5。 於圖1乂中，參考數字2表示由一種有機樹脂材料（例 聚醯亞胺樹脂材料與環氧樹脂材料）所組成之基板2。基 板2之主表面係以一層黏接劑（未顯示）塗佈。在決定基板2 之厚度時，由於内凸塊焊接所造成的熱膨脹所導致的熱效 應應被納入考量。基板2最好是30至5〇微米（以…厚。一互 連或配線層5係形成於基板2之主表面之反側上，並具有由 例如銅所構成之複數導體。黏接劑4係被塗佈於互連層5之 表面上。基板2形成複數之開口部6，用以藉由内凸塊焊接 技術達成互連。 其次，如圖1Β與1C所示，基板2係以其黏接·劑4侧朝向 上之方式’黏性接合至一金屬框7。 參見圖1D與1Ε ’複數半導體晶片1係配置於基板2上之 陣列中’然後，藉由持續數秒施加熱能與壓力而谭接到那 裡。於其外周緣部，每個半導體晶片1具有複數之晶片電 極1〇(參見圖1G與3)。複數之晶片電極1〇可能位於每個半 導體晶片1之活性區域之内。每一個晶片電極1 〇可能由含 銘合金所組成。 參見圖1F與1G ’基板2係以其複數之半導體晶片1面向 下的方式’被置於一平台〇上。為了將互連層5之引線焊接 至每一個晶片電極1〇 一内凸塊焊接係藉由使用一焊接工 具8，在施加熱能、壓力、與超音波之下而執行。如果僅Page 10 4455 9 7 ’ΐ ·, Description of the invention (7) ~~ 1-- f 烊 接 (ΙΒΒ) technology. A plurality of wafer electrodes 10 are placed on an interconnect layer 5 2 at a predetermined position 'which is adhered by heat welding under a force or heat welding under a pressure exceeding s> · radiation. Bonded to the interconnect layer 5. In FIG. 1 (a), reference numeral 2 denotes a substrate 2 composed of an organic resin material (for example, a polyimide resin material and an epoxy resin material). The main surface of the substrate 2 is coated with a layer of adhesive (not shown). When determining the thickness of substrate 2, thermal effects due to thermal expansion caused by solder bumps should be considered. The substrate 2 is preferably 30 to 50 micrometers (thick ...). An interconnect or wiring layer 5 is formed on the opposite side of the main surface of the substrate 2 and has a plurality of conductors made of, for example, copper. Adhesive 4 The substrate 2 is coated on the surface of the interconnection layer 5. The substrate 2 forms a plurality of openings 6 for interconnecting by an internal bump welding technique. Second, as shown in FIGS. 1B and 1C, the substrate 2 is based on the substrate 2. Adhesive · Agent 4 side facing upwards' adhesively bonded to a metal frame 7. See FIGS. 1D and 1E 'The plurality of semiconductor wafers 1 are arranged in an array on a substrate 2' Then, heat and pressure are applied for several seconds Tan received it there. At its outer periphery, each semiconductor wafer 1 has a plurality of wafer electrodes 10 (see FIGS. 1G and 3). The plurality of wafer electrodes 10 may be located within the active area of each semiconductor wafer 1. Each wafer electrode 10 may be composed of an alloy containing an alloy. See FIGS. 1F and 1G. 'The substrate 2 is placed on a platform 0 with a plurality of semiconductor wafers 1 facing downwards.' To place the interconnection layer 5 Lead wire bonding to each wafer electrode 101 internal bump bonding It is performed by applying a welding tool 8 under the application of heat, pressure, and ultrasound. If only

第’Π頁 445b ^ . 4 4 5 b 9 7______ 五 '發明說明（8) 在施加熱能與壓力之下完成，則需要相當高的溫度以完成 内凸塊焊接。因此，内凸塊焊接應在施加熱能、壓力、與 超音波之下被執行。因此，形成一種銘與銅合金，以補強 在互連層5之複數之引線與複數之晶片電極1〇間之連接。 參見圖2A與2B，基板2係以其複數半導體晶片1面向 下的方式’被置於一印刷平台2 2中。一過濾件2 4係被置於 基板2之表面上。過濾件24包含一網25與一印刷光罩26。 藉由使用一橡皮滾子23 ’在基板2之表面塗佈以樹脂21。 網25允許樹脂21通過其中。因此，樹脂21層係形成於基板 2之上表面。樹脂2 1係為一種熱塑性樹脂，例如聚醯亞胺 樹脂、環氧樹脂、與聚丙烯樹脂。熱塑性樹脂21具有大於 或等於基板2之CTE之熱膨脹係數（CTE)。CTE之此種關係可 防止於其他情況下通常在製造步驟期間會因施加熱能而造 成之基板2之不佳之翹曲與變形。因此，可避免在複數接 觸端子與一印刷版之間的連接部之裂痕的發生。如圖2B所 示’光罩26覆蓋複數之部分，此等部分將變成對正並直接 與複數基板之複數開口部6連通的複數開口部27(參見圖 2 D )»吾人可明白一項優點：除了此種印刷步驟以外，不 需其他處理步驟，以在基板2之整體表面上形成熱塑性樹 脂21，並可望減少製造半導體裝置之成本。 參見圖2C，複數半導體晶片1係#由埋入於兩晶θ 1 間之位置的樹脂9而分離。一般而言，一保護離子膜3係以 例如氧化薄膜（Si〇2)之型式，保護如圖2B所示之複數半導 體晶片1。然而，為簡化圖式之便，此種保護離子膜並非Page ′ Π 445b ^. 4 4 5 b 9 7______ Five 'Explanation of the invention (8) Completed under the application of thermal energy and pressure, a relatively high temperature is required to complete the bump welding. Therefore, the bump welding should be performed under the application of thermal energy, pressure, and ultrasound. Therefore, a copper alloy and a copper alloy are formed to reinforce the connection between the plurality of leads of the interconnection layer 5 and the plurality of wafer electrodes 10. Referring to Figs. 2A and 2B, a substrate 2 is placed in a printing platform 22 in such a manner that a plurality of semiconductor wafers 1 face down. A filter element 2 4 is placed on the surface of the substrate 2. The filter element 24 includes a net 25 and a printing mask 26. The surface of the substrate 2 is coated with a resin 21 by using a rubber roller 23 '. The net 25 allows the resin 21 to pass therethrough. Therefore, the resin 21 layer is formed on the upper surface of the substrate 2. Resin 21 is a thermoplastic resin such as polyimide resin, epoxy resin, and polypropylene resin. The thermoplastic resin 21 has a coefficient of thermal expansion (CTE) of CTE of the substrate 2 or more. This relationship of the CTE prevents poor warping and deformation of the substrate 2 which would otherwise be caused by the application of thermal energy during the manufacturing steps. Therefore, it is possible to avoid occurrence of cracks in the connection portions between the plurality of contact terminals and a printing plate. As shown in FIG. 2B, 'the mask 26 covers a plurality of parts, and these parts will become a plurality of openings 27 (see FIG. 2D) which are aligned and directly communicate with the plurality of openings 6 of the plurality of substrates. »One of the advantages can be understood by me : In addition to this printing step, no other processing steps are required to form the thermoplastic resin 21 on the entire surface of the substrate 2 and the cost of manufacturing a semiconductor device can be expected to be reduced. Referring to FIG. 2C, the plurality of semiconductor wafers 1 are separated by a resin 9 embedded in a position between two crystals θ 1. In general, a protective ion film 3 protects a plurality of semiconductor wafers 1 as shown in FIG. 2B in the form of, for example, an oxide film (SiO2). However, to simplify the illustration, this protective ion membrane is not

第12頁 445597 五、發明說明（9) 顯示於圖1A-1F與圖2A，2C-2G中。嵌入樹脂9之處理步驟 能在如圖1F所示之製程前立即實施。每一個開口部27露出 互連層5之部分表面。藉由每個開口部27所露出之表面部 分’係以銅或銅金化合物電鍍’以形成一焊墊13(參見^ 3)。如圖2F所示，在於互連層5上形成複數之焊墊13於藉 由複數開口部27之複數露出部分之後，每個皆以一谭接凸 塊12之型式存在之複數接觸端子，係被安裝至每一個焊塾 13 ^取代使用銅電鍍或銅金電鍍的是，可能利用使用金 (Au)之非電解質電鍍’以形成複數之焊塾13。 參見圖2F，接著，半導體晶圓係於複數之畫線部分A 切割。一鑽石切割刀具等係用以於複數之晝線部分A，將 半導體晶圓分離成複數之晶粒。參見圖3，最後，由玻璃 環氧樹脂所組成之印刷版1 4係黏性接合至每個^粒之複數 焊接凸塊12，以形成第一實施例之半導體裝置β 從圖3可見，藉由顯示於與圖2A_2F<處理步 驟所製造的第一實施例之半導體裝置，係採用一種扇入構 造，於其中，複數之焊接凸塊12係形成於每個半導體晶片 1.上》其包含位於一基板2上之半導體晶片工。晶片i形成有 複數之晶片電極10。基板2上之一互連層5包含分別與複數 之晶片電極10接觸之複數引線。複數之焊接凸塊12係分別 與互連層5·之複數引線接觸。一印刷版丨4係與複數之焊-接 凸塊12接觸。一樹脂21層係形成於基板2上。樹脂21層係 作為一續正機構’以抑制由於在基板2之CTE與印刷版丨4之 CTE間之差異所導致的基板2之任何彎曲與/或形變。當晶Page 12 445597 V. Description of the invention (9) is shown in Figs. 1A-1F and Figs. 2A, 2C-2G. The processing steps of the embedding resin 9 can be performed immediately before the process shown in FIG. 1F. Each of the openings 27 exposes a part of the surface of the interconnection layer 5. The surface portion 'exposed through each opening portion 27 is electroplated with copper or copper-gold compound' to form a pad 13 (see ^ 3). As shown in FIG. 2F, after the plurality of solder pads 13 are formed on the interconnection layer 5, after the plurality of exposed portions are exposed through the plurality of openings 27, each of the plurality of contact terminals exists in the form of a bump 12, Instead of using copper plating or copper-gold plating, it is possible to use a non-electrolyte plating using gold (Au) to form a plurality of solder joints 13. Referring to FIG. 2F, the semiconductor wafer is cut at a plurality of line portions A. A diamond cutting tool or the like is used to separate a semiconductor wafer into a plurality of grains in a plurality of daylight portions A. Referring to FIG. 3, finally, a printing plate 14 composed of glass epoxy resin is adhesively bonded to each of the plurality of solder bumps 12 to form a semiconductor device β of the first embodiment. As can be seen from FIG. 3, The semiconductor device of the first embodiment shown in FIGS. 2A_2F < processing steps uses a fan-in structure in which a plurality of solder bumps 12 are formed on each semiconductor wafer 1. A semiconductor wafer operator on a substrate 2. The wafer i is formed with a plurality of wafer electrodes 10. One of the interconnection layers 5 on the substrate 2 includes a plurality of leads which are in contact with a plurality of wafer electrodes 10, respectively. The plurality of solder bumps 12 are in contact with the plurality of leads of the interconnection layer 5 ·, respectively. A printing plate 4 is in contact with a plurality of solder-welding bumps 12. A resin 21 layer is formed on the substrate 2. The resin 21 layer serves as a renewal mechanism 'to suppress any bending and / or deformation of the substrate 2 caused by the difference between the CTE of the substrate 2 and the CTE of the printing plate 4. Dangjing

第13頁 445 υ 445 ο . 五、發明說明（10) ~ 由Λ(~所組成時，其CTE係為3_°C。當基板2係 ^ 3有機絕緣材料之聚醯亞胺膜形成時，其CTE的範圍 ^16-2 0ppni/ C。當印刷版14係由玻璃環氧樹脂所組成 ^•，印刷版14之(^£的範圍為16-50?1)〇1/。〇。樹脂21係為環 氧樹脂或壓克力樹脂。樹脂21需要具有大於基板22Cte。 因為樹脂21層之CTE係大於基板2之CTE，故在施加熱能以 黏性接合印刷版14至複數之焊接凸塊12期間，可避免基板 2之任何彎曲與/或形變的發生。由於基板2之彎曲與/或形 f之抑制’故在複數之焊接凸塊丨2至印刷版14之每個連接 之裂痕的發生可最小化。明顯地，此會導致半導體裝置 之製造良率大量增加。 於前述例子中，複數開口部2 7係分別與複數之晶片電 極1 〇予以對準。具體而言’複數開口部2 7係於办別與複數 之晶片電極10重疊之複數部分’將互連層5之複數引線予 以露出。取代將此等開口部予以配置成與複數晶片電極對 準的是’它們可能配置成與以圖4之3 7顯示或以圖5之4 7顯 示的複數晶片電極不對準。除了複數開口部37之位置以 外’ 一種顯示於圖4之半導體裝置係實質上與顯示於圖3之 半導體裝置相同。此種半導體裝置採用一種扇入構造，於 其中複數之開口部3 7係配置比複數之晶片電極1 〇更朝向 一半導體晶片1之内部。複數開口部37分別容衲複數之焊 接凸塊12。除了複數開口部47之位置以外，顯示於圖5之 一種半導體裝置係實質上與顯示於圖3之半導體裝置相 同。此種半導體裝置採用一種扇出構造，於其中，複數開Page 13 445 υ 445 ο. 5. Description of the invention (10) ~ When composed of Λ (~, the CTE is 3_ ° C. When the substrate 2 is a ^ 3 organic polyimide film of organic insulating material, Its CTE range is ^ 16-2 0ppni / C. When printing plate 14 is composed of glass epoxy ^ •, printing plate 14 (^ £ ranges from 16-50? 1) 〇1 / .〇. Resin 21 is an epoxy resin or acrylic resin. Resin 21 needs to be larger than the substrate 22Cte. Because the CTE of the resin 21 layer is larger than the CTE of the substrate 2, the thermal plate is used to adhesively join the printing plate 14 to a plurality of solder bumps. During the 12th period, any bending and / or deformation of the substrate 2 can be avoided. Due to the suppression of the bending and / or the shape of the substrate 2 ', the number of cracks in each of the plurality of solder bumps 2 to the printing plate 14 The occurrence can be minimized. Obviously, this leads to a large increase in the manufacturing yield of the semiconductor device. In the foregoing example, the plurality of openings 27 are aligned with the plurality of wafer electrodes 10 respectively. Specifically, the 'plurality of openings' 2 7 is a plural part which overlaps with a plurality of wafer electrodes 10, which leads to the plural of the interconnection layer 5 Instead of arranging these openings to align with the plurality of wafer electrodes, they may be arranged to be misaligned with the plurality of wafer electrodes shown in FIG. 4-7 or in FIG. 5-7. Except for the position of the opening 37, a semiconductor device shown in Fig. 4 is substantially the same as the semiconductor device shown in Fig. 3. This semiconductor device adopts a fan-in structure in which a plurality of openings 37 and 7 are arranged more than a plurality. The wafer electrode 10 is further directed to the inside of a semiconductor wafer 1. The plurality of openings 37 respectively accommodate a plurality of solder bumps 12. Except for the positions of the plurality of openings 47, a semiconductor device shown in FIG. It is the same as the semiconductor device of Fig. 3. This semiconductor device adopts a fan-out structure in which a plurality of

第14頁 ' 4455b 五、發明説明〇ι) 口部47係配置成比複數之晶片電極1 〇更不朝向半導體晶片 1之内部。複數開口部47分別容納複數之焊接凸塊1 2。 第二較佳實施例： 以下將結合圖6A至6C說明依本發明第二實施例之一種 半導體裝置與其製造方法。 依第二較佳實施例之半導體裝置，實質上係與圖3相 同，因為兩者皆採用一種扇入構造。依第二較佳實施例之 製程，實質上係與圖1A-1G與圖2A-2F之製程相同。依第二、 較佳實施例之製程亦採用如圖1 A至1 G之處理步驟。然而， 在一基板上形成一樹脂層之方式，前者係與後者不同。依 據第一較佳實施例’樹脂2 1層係藉由印刷而形成於基板2 上（參見圖2A)。依據第二較佳實施例，樹脂之一補強薄板 6 1係黏性接合至一基板2，以於基板2上形成一樹脂層，如 圖6A所示。具體言之’在完成圖ία至ig之處理步驟之後， 補強薄板61係黏性接合至基板2，如圖6A與6B所示。補強 薄板61之材料，實質上可能與樹脂21層之材料相同。補強 薄板61之一主表面係以黏接劑塗佈，而補強薄板6丨係以黏 接劑側朝向下的方式’對著基板2加壓。補強薄板6丨之使 用’簡化了將樹脂層形成於基板2之上的處理步驟。參見 圖6A與6B，補強薄板61於露出一互連層5之複數引線之部 分的複數部分，形成有複數開口部62。因此，補強薄板61 並未將安裝複數之焊接凸塊12的複數部分予以覆蓋。然 後，如圖6C所示，每個係以金屬電鍍之型式存在之複數焊 墊13，係形成於互連層5之複數露出部分上，而複數之焊Page 14 '4455b 5. Description of the invention 〇) The mouth 47 is arranged so as not to face the inside of the semiconductor wafer 1 more than the plurality of wafer electrodes 1 〇. The plurality of openings 47 respectively accommodate a plurality of solder bumps 12. Second Preferred Embodiment: A semiconductor device and a manufacturing method thereof according to a second embodiment of the present invention will be described below with reference to FIGS. 6A to 6C. The semiconductor device according to the second preferred embodiment is substantially the same as that in FIG. 3, because both use a fan-in structure. The process according to the second preferred embodiment is substantially the same as the processes of FIGS. 1A-1G and 2A-2F. The process according to the second and preferred embodiment also uses the processing steps shown in Figures 1 A to 1 G. However, the method of forming a resin layer on a substrate is different from the latter. According to the first preferred embodiment, a layer of resin 21 is formed on the substrate 2 by printing (see Fig. 2A). According to the second preferred embodiment, one of the resin-reinforcing sheets 61 is adhesively bonded to a substrate 2 to form a resin layer on the substrate 2, as shown in FIG. 6A. Specifically, after the processing steps of α to ig are completed, the reinforcing sheet 61 is adhesively bonded to the substrate 2, as shown in FIGS. 6A and 6B. The material of the reinforcing sheet 61 may be substantially the same as that of the resin 21 layer. One of the main surfaces of the reinforcing sheet 61 is coated with an adhesive, and the reinforcing sheet 6 is pressed against the substrate 2 with the adhesive side facing downward '. The use of the reinforcing sheet 6 'simplifies the processing steps for forming the resin layer on the substrate 2. 6A and 6B, a plurality of openings 62 are formed in a plurality of portions of a portion of a reinforcing sheet 61 that exposes a plurality of leads of an interconnection layer 5. Therefore, the reinforcing sheet 61 does not cover a plurality of portions where the plurality of welding bumps 12 are mounted. Then, as shown in FIG. 6C, each of the plurality of bonding pads 13 which is a metal plating type is formed on the plurality of exposed portions of the interconnection layer 5, and the plurality of bonding pads 13

第15頁 445597 五、發明說明（12) 接凸塊12係安裝至複數之焊墊13。接著’類似於第一較佳 實施例地’將半導體晶圓予以切割並分割成複數之晶粒。 最後’ 一印刷版係黏性接合至每個晶粒之複數焊接凸塊 12 ° 第三較佳實施例： 以下將結合圖7A至7C與8說明依本發明第三實施例之 —種半導體裝置與其製造方法。 參見圖8 ’第三較佳實施例實質上係與第一較佳實施、 例相同’但於以下方面係為不同β於圖8中，參考數字1 表示具有一保護層3之一半導體晶片。聚醯亞胺之基板 2 ’係藉由黏接劑4而黏性接合至半導體晶片1。一互連層5 係形成於基板2上。依第三較佳實施例，半導體晶片1、基 板2、與互連層5係依此順序堆疊。依據第一較盛實施例， 半導體晶片1、互連層5、與基板2係依此順序堆疊（參見圖 3)。因此，在堆疊複數層之順序上，第三較佳實施例係與 第一較佳實施例不同。又，—保護層7丨係形成於基板2 上’以覆蓋互連層5 ’如圖7Α所示。保護層71形成有複數 之開口部或複數之窗孔73，各自以金屬電鍍之型式形成之 焊墊74，係經由此等窗孔73而分別形成於互連層5之複數 引線上。基板2上形成有複數之貫通孔，用以暴露複數之 a曰片電極10。基板2之每一個貫通孔係以導電材料π填- 滿，以在每一個晶片電極1 〇與互連層5之其中一條引線之 間達成電連接。 β 參見圖7Β ’樹脂2 1層係藉由與第一較佳實施例相同方Page 15 445597 V. Description of the invention (12) The bump 12 is mounted to a plurality of solder pads 13. The semiconductor wafer is then " similar to the first preferred embodiment " diced and divided into a plurality of dies. Finally, a printing plate is a plurality of solder bumps 12 ° adhesively bonded to each die. A third preferred embodiment: A semiconductor device according to a third embodiment of the present invention will be described below with reference to FIGS. 7A to 7C and 8. With its manufacturing method. Referring to FIG. 8 ′, the third preferred embodiment is substantially the same as the first preferred embodiment, but is different in the following aspects. In FIG. 8, reference numeral 1 indicates a semiconductor wafer having a protective layer 3. The polyimide substrate 2 'is adhesively bonded to the semiconductor wafer 1 by an adhesive 4. An interconnection layer 5 is formed on the substrate 2. According to the third preferred embodiment, the semiconductor wafer 1, the substrate 2, and the interconnection layer 5 are stacked in this order. According to the first embodiment, the semiconductor wafer 1, the interconnection layer 5, and the substrate 2 are stacked in this order (see FIG. 3). Therefore, the third preferred embodiment is different from the first preferred embodiment in the order of stacking a plurality of layers. Moreover, a protective layer 7 is formed on the substrate 2 'to cover the interconnection layer 5' as shown in FIG. 7A. The protective layer 71 is formed with a plurality of openings or a plurality of window holes 73, and pads 74 each formed in a metal plating type are formed on the plurality of leads of the interconnection layer 5 through the window holes 73, respectively. A plurality of through-holes are formed in the substrate 2 to expose the plurality of sheet electrodes 10. Each through-hole of the substrate 2 is filled-filled with a conductive material π to achieve an electrical connection between each wafer electrode 10 and one of the leads of the interconnection layer 5. β See FIG. 7B ′ Resin 2 1 layer is the same as the first preferred embodiment

^45597^ 45597

五、發明說明（13) 式之印刷技術（參見圖2A)，形ώ於仅崎麻71 l ^ ^121 ® ^ ^ ^ ^ ^ ^ 烙成於保濩層71上。在形成樹 =2〗層之處理步驟之後，複數之焊接凸塊^係裝設至t ::墊74 ’如圖7C所示。樹脂層之形&，可藉由^數 相同之方式(參見™，使用-補強樹： 依據本發明之第-、第二與第三較佳實施 <列，樹脂Μ 層係以直接接觸關係，或隔著覆蓋一基板2與一互連層5於 其上之-保護層71，而形成於一基板2上。對於抑制由於. 在焊接步驟期間施加熱能而導致基板2之彎曲與/或形變方 面，樹脂21層之設置係為有效的。以複數之焊接凸塊丨^至 一印刷版14之型式，這已使於接觸端子之複數連接部的 痕之發生最小化。這導致半導體裝置之製造良率大量增 加，使吾人可以於低成本下銷售半導體裝置。. a 於斌述例子中，用以抑制一基板2之任何彎曲與/或形 變的矯正機構，係採用具有大於或等於基板2之(：7£的熱塑 性樹脂2 1層。矯正機構亦可使用其他塗佈層或非晶系金 屬，以取代樹脂層，只要可證明它們對於抑制基板2之彆 曲與/或形變方面係為有效即可。 依本發明第一、第二、與第三較佳實施例，在一半導 體晶月1與一印刷版14間之間隔係為未填滿的。此種未填 滿之間隔可允許介設‘於晶片1與印刷版丨4間，或在互連層5 與印刷版1 4間的部分的簡易修補工作。 關於形成樹脂21層之處理步驟，可依據第一較佳實施 例而使用一印刷技術係，或者，可依據第二與第三較佳實V. Description of the invention (13) The printing technology (see Fig. 2A), which is only sold on the oscillating layer 71 l ^ ^ 121 ® ^ ^ ^ ^ ^ ^ Soldering on the retaining layer 71. After the processing step of forming the tree = 2 layer, a plurality of solder bumps ^ are set to t :: pad 74 'as shown in FIG. 7C. The shape of the resin layer & can be used in the same way (see ™, use-reinforcing tree: according to the first, second, and third preferred embodiments of the present invention < column, the resin M layer is in direct contact Relationship, or formed on a substrate 2 via a protective layer 71 covering a substrate 2 and an interconnection layer 5 thereon. For suppressing the warping of the substrate 2 due to the application of thermal energy during the soldering step and / In terms of deformation or deformation, the arrangement of the resin 21 layer is effective. In the form of a plurality of solder bumps ^^ to a printing plate 14, this has minimized the occurrence of marks on the plural connection portions of the contact terminals. This leads to the semiconductor The manufacturing yield of the device has greatly increased, allowing us to sell semiconductor devices at low cost. A In the example of Yu Bin, the correction mechanism used to suppress any bending and / or deformation of a substrate 2 uses a device having a greater than or equal to Substrate 2 (1: Thermoplastic resin 21 1 layer. The correction mechanism may also use other coating layers or amorphous metals to replace the resin layer, as long as it can be proven that they are effective in suppressing the different curvatures and / or deformations of the substrate 2 Can be effective According to the first, second, and third preferred embodiments of the present invention, the space between a semiconductor crystal moon 1 and a printing plate 14 is unfilled. Such unfilled spaces may be allowed to be interposed ' Simple repair work between wafer 1 and printing plate 4 or between interconnect layer 5 and printing plate 1 4. Regarding the processing steps for forming resin 21 layer, a printing can be used according to the first preferred embodiment. Department of Technology, or, based on the second and third best practices

第17頁 9 4 45 5 五、發明說明（14) 施例而使用由一樹脂材料所組成之一 之使用係為有利的，因為其可—次在 區域形成一層，使其可減少半導體裝 此，樹脂之補強薄板的使用係為有利 基板2上形成一層所需要之工作。 雖已參照三個較佳實施例詳細說 於熟習本項技藝者而言，依據上述說 案 '修改、與變化亦可採用。因此， 神及以下申請專利範圍之情況，所做 屬於本發明之範圍。 補強薄板。印刷技術 基板2表面上之寬廣 置之製造成本。因 的’因為其可減輕於 明本發明’然而， 明之多數的替代方 在不超出本發明之 之種種變化實施，比Page 17 9 4 45 5 V. Description of the invention (14) The use of one of the resin materials is advantageous because it can form a layer in the area one at a time, which can reduce the amount of semiconductor devices. The use of a resin-reinforced sheet is necessary to facilitate the formation of a layer on the substrate 2. Although it has been described in detail for those skilled in the art with reference to the three preferred embodiments, according to the above description, 'modifications, and changes can also be used. Therefore, what God and the following patent application scopes do, is within the scope of the present invention. Reinforcing sheet. Printing technology Wide manufacturing cost on the surface of substrate 2. Therefore, 'because it can be mitigated to the present invention', however, the majority of the alternatives of the present invention are implemented in various changes that do not exceed the present invention.

4 4 5 5 q 7 、 --- —**** 1 ----- --- 圖式簡單說明 圖1A至1G顯示製造依本發明之半導體裝置之第一較佳 實施例之製程的步驟，其中，圖1 C係為圖1 B之縱剖面，圖 1 E係為圖1 D之縱剖面，而圖1 G係為圖1 f之局部放大圖。 圖2A至2F顯示製造程序的處理步驟，其中，圖2B係為 圖2A之局部放大圖。 圖3係半導體裝置之一剖面圖。 圖4係為依本發明之第一較佳實施例的半導體裝置之 另一較佳實施例之剖面圖。 圖5係為依本發明之第一較佳實施例的半導體裝置之 又另一較佳實施例之剎面圖。 圖6A至6C顯示製造依本發明之半導體裝置之第二較佳 實施例之製程的步驟。 圖7A至7C顯示製造依本發明之半導體裝置乏第三較佳 實施例之製程的步驟。 圖8係為依本發明第三較佳實施例之半導體裝置的剖 面圖。 圖9A至9G顯示製造一種半導體裝置之習知製程之製程 步驟。 圖10A至10D顯示習知製程之製程步驟。 【符號之說明】 A〜畫線部分 1〜半導體晶片 2〜基板4 4 5 5 q 7, ----**** 1 ----- --- BRIEF DESCRIPTION OF THE DRAWINGS Figures 1A to 1G show the process of manufacturing a first preferred embodiment of a semiconductor device according to the present invention. 1C is a longitudinal section of FIG. 1B, FIG. 1E is a longitudinal section of FIG. 1D, and FIG. 1G is a partially enlarged view of FIG. 1f. Figures 2A to 2F show the processing steps of a manufacturing process, of which Figure 2B is a partially enlarged view of Figure 2A. FIG. 3 is a cross-sectional view of a semiconductor device. Fig. 4 is a sectional view of another preferred embodiment of the semiconductor device according to the first preferred embodiment of the present invention. FIG. 5 is a brake surface view of another preferred embodiment of the semiconductor device according to the first preferred embodiment of the present invention. 6A to 6C show steps of a manufacturing process of a second preferred embodiment of a semiconductor device according to the present invention. 7A to 7C show the steps of a manufacturing process for a semiconductor device according to the present invention without a third preferred embodiment. Fig. 8 is a sectional view of a semiconductor device according to a third preferred embodiment of the present invention. 9A to 9G show process steps of a conventional manufacturing process for manufacturing a semiconductor device. 10A to 10D show process steps of a conventional process. [Description of symbols] A ~ Drawing part 1 ~ Semiconductor wafer 2 ~ Substrate

第19頁 44559γ 圖式簡單說明 3〜保護離子層 4 ~黏接劑 5〜.互連層 6、 27、 37、 47、 62 〜開口部 7〜金屬框 8〜焊接工具 9、21〜樹脂Page 19 44559γ Simple illustration 3 ~ Protective ion layer 4 ~ Adhesive 5 ~. Interconnect layer 6, 27, 37, 47, 62 ~ Opening 7 ~ Metal frame 8 ~ Welding tool 9, 21 ~ Resin

第20頁 10〜 晶 片 電 極 12〜 焊 接 凸 塊 13、 74 焊 墊 14 ~ 印 刷 板 22〜 印 刷 平 台 23 ~ 橡 皮 滾 子 24 ~ 過 濾 件 25 ~ 網 26〜 光 罩 61〜 補 強 薄 板 71 - 保 護 層 73 - 窗 孔 75 ~ 導 電 材 料 911 、912 樹 913 〜黏接劑Page 20 10 ~ Wafer electrode 12 ~ Welding bumps 13, 74 Pad 14 ~ Printing board 22 ~ Printing platform 23 ~ Rubber roller 24 ~ Filter 25 ~ Net 26 ~ Photomask 61 ~ Reinforcing sheet 71-Protective layer 73 -Window hole 75 ~ Conductive material 911, 912 Tree 913 ~ Adhesive

Claims (1)

445597 _案號 89100291 六、申請專利範圍 1. 一種半導體裝置，包含： 一基板；445597 _ Case No. 89100291 6. Scope of Patent Application 1. A semiconductor device including: a substrate; 修正 /補充 Wi件丨 一 ί -半導體晶片’位於該基板上， ^J 數之晶片電極； f #體曰a 一互連層，形成於該半導艚晶κ 之晶片電極； +導體“上，並連接至該複數 複數之接觸端子’連接至該互連層； 一印刷板’連接至該複數之接觸端子；與 —矯正機構，位於該基板上，用以 ；^ 該基板之熱膨m係數與該印刷板之熱膨脹係。之差異^ 導致的任何彎曲與/或形變。 異所 2_如申請專利範圍第丨項之半導體裝置 構包含一樹脂層》 孩矯正機 有複 3,如申請專利範圍第2項之半導體裝置，其 該 具有大於或等於該基板之熱膨脹係數之熱膨脹係數樹 4. 一種半導體裝置，包含： 一基板； 一半導體晶片，位於該基板上 數之晶片電極； 該半導體晶片具有複 一互連層，形成於該半導體晶片上 之晶片電極； 並連接至該複數Amend / Supply Wi-Fi-a semiconductor wafer is located on the substrate, and the number of wafer electrodes is ^ J; an interconnect layer is formed on the wafer electrode of the semiconductor κ; + conductor "on And connected to the plurality of contact terminals 'connected to the interconnection layer; a printed board' is connected to the plurality of contact terminals; and-a correction mechanism is located on the substrate for: ^ the thermal expansion m Coefficient and thermal expansion of the printed board. Differences ^ Any bending and / or deformation caused. Differences 2_ If the semiconductor device structure of the patent application No. 丨 contains a resin layer, there are 3 correction devices, if applied The semiconductor device of the second item of the patent, which has a coefficient of thermal expansion coefficient greater than or equal to the coefficient of thermal expansion of the substrate 4. A semiconductor device comprising: a substrate; a semiconductor wafer, the number of wafer electrodes on the substrate; the semiconductor The wafer has a plurality of interconnection layers, and a wafer electrode formed on the semiconductor wafer; and is connected to the plurality of wafer electrodes. 第21頁 α 4 5 5 9 7 年Γ月Page 21 α 4 5 5 9 7 Γ 並連接到該互 形成於該互連層上 _案號 89100291 六、申請專利範圍 複數之接觸端子 連層；及 一樹脂層，形成於該基板上。 5. 如申請專利範圍第4項之半導體裝置，其中，該樹脂層 具有大於或等於該基板之熱膨脹係數之熱膨脹係數。 6. —種半導體裝..置之製造方法，包含： 形成一互連層於一半導體晶片上，該半導體晶片具有 複數之晶片電極； 形成一基板於該半導體晶片與該互連層上；及 藉由印刷，形成一樹脂層於該基板上。 7. —種半導體裝置之製造方法，包含： 形成一互連層於一半導體晶片上，該半導體晶片具有 複數之晶片電極； 於該半導體晶片與該互連層上形成一基板；與 藉由黏性接合一樹脂補強薄板至該基板，形成一樹脂 廣於該基板上。And connected to the interconnection layer formed on the interconnection layer _ Case No. 89100291 VI. Patent Application Plurality of contact terminal connection layer; and a resin layer formed on the substrate. 5. The semiconductor device according to item 4 of the application, wherein the resin layer has a thermal expansion coefficient greater than or equal to a thermal expansion coefficient of the substrate. 6. A method for manufacturing a semiconductor device, comprising: forming an interconnection layer on a semiconductor wafer, the semiconductor wafer having a plurality of wafer electrodes; forming a substrate on the semiconductor wafer and the interconnection layer; and A resin layer is formed on the substrate by printing. 7. A method for manufacturing a semiconductor device, comprising: forming an interconnection layer on a semiconductor wafer, the semiconductor wafer having a plurality of wafer electrodes; forming a substrate on the semiconductor wafer and the interconnection layer; and A resin-reinforced sheet is sexually bonded to the substrate to form a resin wider than the substrate. 第22頁Page 22
TW089100291A 1999-01-11 2000-01-07 Manufacturing of semiconductor devices TW445597B (en)

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JP3617647B2 (en) 2002-11-08 2005-02-09 沖電気工業株式会社 Semiconductor device and manufacturing method thereof
JP3618331B2 (en) 2002-11-08 2005-02-09 沖電気工業株式会社 Semiconductor device and manufacturing method thereof
JP3618330B2 (en) 2002-11-08 2005-02-09 沖電気工業株式会社 Semiconductor device and manufacturing method thereof
JP4056360B2 (en) 2002-11-08 2008-03-05 沖電気工業株式会社 Semiconductor device and manufacturing method thereof
JP3844467B2 (en) 2003-01-08 2006-11-15 沖電気工業株式会社 Semiconductor device and manufacturing method thereof
WO2005117096A1 (en) * 2004-05-31 2005-12-08 Sharp Takaya Electronics Industry Co., Ltd. Circuit module manufacturing method and circuit module manufactured by the method
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