經濟部智慧財產局貝工消费合作杜印製 “43 7〇 5827twf.d〇c/006 A7 ___ B7 五、發明說明（/ ) 本發明是有關於一種覆晶構裝基板，且特別是有關 於一種可以改善凸塊接合性的覆晶構裝基板。 覆晶技術（Flip Chip)是經常應用於晶片尺寸構裝 的構裝技術，由於其可以採用面積陣列方式（area array) 配置焊塾’且透過凸塊（bump)連接承載器，故可以縮小構 裝面積’並縮短訊號傳輸路徑。目前覆晶技術產品中，依 照焊罩（solder mask)覆蓋接合墊（Mounting Pad)的程度 不同’改變凸塊與接合墊的接觸面積，進而影響凸塊的崩 塌現象（collapse)。傳統的基板接合墊設計可分爲「焊罩 定義 j (Solder Mask Define，SMD)與「非焊罩定義」（Non Solder Mask Define, NSMD)兩種型態。 請參照第1圖，其繪示習知「焊罩定義」的接合墊 結構。對於覆晶構裝而言，大部分採用積層板 100(laminating board)作爲覆晶構裝基板，積層板1〇〇 的型態包括蹈合型及堆疊型（build-up)等。積層板1〇〇主 要由圖案化線路層及絕緣層102交替疊合構成，其中圖案 化線路層比如由銅箔層經過微影蝕刻定義形成，而絕緣層 102材質包括玻璃環氧基樹脂（FR-4、FR-5)、雙順丁烯二 酸醯 55 胺（Bismaleimide-Triazine，BT)或者環氧樹脂 (epoxy)等。積層板100表層的圖案化線路層會形成多個 接合墊104，做爲積層板100對晶片110的接點。在SMD 型的基板中，焊罩層106覆蓋於表層圖案化線路層，僅最 露出接合墊104的部分表面，即覆蓋接合墊104的外緣表 面。晶片110的主動表面112(active surface)會形成有 3 本紙張尺度遶用中困Η家標準（CNS>A4规格ί210 X 297公釐） ---------I I----------訂 ------ - -線1-^ (請先閱讀背面之注意事項再填寫本頁) 4443 7 〇 5827twf,d〇c/006 A7 B7 經濟部智慧財產局貝工滴费合作社印製 五、發明說明（z ) 多個焊墊（bonding pad)，其上形成有球底金屬層 114(Under Bump Metal，UBM)，在球底金屬層114上形成 凸塊116 ’比如是錫錯凸塊（solder bump)。由於球底金屬 層Π4的大小與焊罩層1〇6會限制凸塊116崩塌的範圍， 所以焊罩層106開口 108的尺寸不但決定凸塊116與接合 墊104的接合面積，還會影響凸塊116的崩塌現象，及最 後凸塊116的高度。 請參照第2圖，其繪示習知「非焊罩定義」的接合 墊結構。在NSMD的結構中，焊罩層l〇6a會完全暴露出接 合墊104a的整個表面，凸塊116會與接合墊104a的上表 面120及側面122接合，增加了凸塊116與接合墊104a 間的接觸面積。此時開口 108與凸塊116會保持一段間隙， 所以焊罩層l〇6a的開口 108a已不會影響凸塊116崩塌的 現象，及凸塊116的最後高度。 無論SMD或是NSMD結構，在應用上皆有其優缺點， 而本發明的目的之一就是提出一種同時具有SMD及MSMD 結構的覆晶構裝基板，並加以適當安排，使得覆晶構裝的 製造良率提商。 本發明的另一目的就是在提供一種覆晶構裝基板， 可以容許較大的凸塊共平面度誤差，以及接合墊共平面度 誤差，使得覆晶構裝的製造裕度增加。 爲達成本發明之上述和其他目的，提出一種覆晶構 裝基板，包括：多層圖案化線路層及至少一絕緣層，絕緣 層配置於圖案化線路層之間，用以隔離圖案化線路層，並 4 (請先閱讀背面之注意事項再填寫本頁) — 11 訂---------線. 本紙張尺度適用+ B國家《準（CNS>A4规格<210 * 297公* > A7 B7 4443 70 5827twf . doc/006 五、發明說明（j) 與圖案化線路層疊合。而圖案化線路層彼此電性連接，其 中圖案化線路層之一位於覆晶構裝基板之表面，其至少包 括多個第一接合墊及多個第二接合墊。，焊罩層，覆蓋於覆 晶構裝基板表面之圖案化線路層上，暴露出第一接合墊的 部分表面，並覆蓋第一接合墊外緣的部分表面，且完全暴 露出第二接合墊的表面。 依照本發明的一較佳實施例，其中絕緣層中具有多 個貫孔以電性連接圖案化線路層。而第一接合墊間的間距 小於第二接合墊間的間距；且第一接合墊配置在覆晶構裝 基板之外圍，且第二接合墊位於覆晶構裝基板之內圍。本 發明的覆晶構裝基板應用於覆晶構裝時，凸塊會與第一接 合墊的上表面接合，而凸塊與第二接合墊則接合於上表面 及側面。 爲讓本發明之上述和其他目的、特徵、和優點能更 明顯易懂，下文特舉一較佳實施例，並配合所附圖式，作 詳細說明如下： 圖式之簡單說明： 第1圖繪示習知「焊罩定義」的接合墊結構。 第2圖繪示習知「非焊罩定義」的接合墊結構。 第3圖繪示依照本發明一較佳實施例的一種覆晶構 裝基板剖面圖。 第4圖繪示依照本發明一較佳實施例的一種覆晶構 裝基板俯視圖。 第5圖繪示依照本發明較佳實施例之一種覆晶構裝 5 本紙張疋度適用中困g家標準<CNS)A4規格（210 x 297公釐） --I--1 I ---訂--- - -----線〆 {請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 4 443 7 582 7 twf . doc/Ο 0 6 A7 B7 經濟邾智慧財產局貝工消费合作社印製 五、發明說明（f) 剖面圖。 圖式之標示說明： 100 :積層板 102 :絕緣層 104、104a :接合墊 106、222 :焊罩層 108 ' 108a、224 :開口 110、250 :晶片 112、250a :主動表面 114、252 :球底金屬層 116、254 :凸塊 120、214a、216a :上表面 122 :側面 200 :覆晶構裝基板 202 :絕緣芯層 204、206 ··絕緣層 208、210 :圖案化線路層 212 :貫孔 214 :第一接合墊 216 :第二接合墊 218 :外圍區域 220 :內圍區域 230、232 :間距 256 :塡充材料 本紙張尺度適用中國囲家標準（CNS)A4規格<210 X 297公釐） --- -----Γ 111 ---]—---訂--------- ^^1^ <請先閱讀背面之注意事項再填寫本頁) 4443 7〇 5827twf.doc/006 A7 B7 五、發明說明（<) 實施例 就覆晶構裝基板之設計而言，SMn的設計由於凸塊 與接合墊接合後，凸塊與焊罩層間沒有空隙，所以在後續 塡充製程（underfilling)，較不易產生氣泡，因此可以提 高良率。然而SMD也由於凸塊與接合墊的接觸面積較少， 所以崩塌現象（coll apse)較差，接合效果（joint〉較差， 而且對於覆晶構裝基板的共平面度icoDlanarity)要求較 嚴格，所以製程裕度較低（process window)。相反地，就 NSMD的設計而言，由於凸塊與接合墊的接觸面積較大，包 括接合墊的上表面及側面，所以崩塌珥象較好，接合效罢 亦較優，可以提高覆晶構裝基板對於共平面誤差的忍受 度。然而，爲了避免後續塡充製程中，因爲凸塊與焊罩層 間的間距而造成氣泡，必須將焊罝層開口的尺寸適當地放 大。此種需求，必須增加接合墊間的間距（pitch)，使得 覆晶構裝基板的佈置（layout)難度提高，而且可能會降低 構裝之密度。因此如何兼具SMD與NSMD的優點，並降低SMD 及NSMD對應之缺點是十分重要的。 目前覆晶產品中，凸塊的分佈主要分爲周邊及全矩 陣方式，而對應覆晶構裝基板的佈置，由於製作及設計能 力的關係，會限制接點配置的方式。以堆疊型（build-up) 覆晶構裝基板，且爲六層板（2+2+2)爲例，通常訊號接點 的接合墊只能配置於外圍之六圈，而內圍部分則配置電源 接點（power)、接地接點（ground)及擬接點（dummy)。而在 中間的部分空間較大，所以通常接合墊的間距可以較大。 本紙張尺度適用中國困家棵準<CNS)A4规格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) -¾--------訂---------線一！ 經濟部智慧財產局員工消费合作社印製 4443 7 〇 5 82 7twf. doc/〇 〇 6 A7 B7 五、發明說明（ό ) I 閱 讀 背 面 之 注 意 事 項 再 填 寫 本 頁 請同時參照第3圖及第4圖，其中第3圖繪示依照 本發明一較佳實施例的一種覆晶構裝基板剖面圖；而第4 圖繪示依照本發明一較佳實施例的一種覆晶構裝基板俯視 圖。本發明中覆晶構裝基板200主要由絕緣層202、204、 206及圖案化線路層208、210交替疊合形成。其中絕緣層 202爲絕緣芯層，其材質比如爲玻璃環氧基樹脂（FR-4、FR-5) 或雙順丁嫌二酸醯亞胺（8丨3财16丨11^(16-1'1^32丨116,：81')等； 而絕緣層204、206之材質比如是環氧樹脂（epoxy)。圖案 化線路層208、210比如是由銅箔經過微影蝕刻製程定義 形成，而圖案化線路層208 ' 210間係透過配置於絕緣層 204、206中的貫孔212(via)形成電性連接。覆晶構裝基 板200表層的圖案化線路層除了形成線路外，還會形成第 一接合墊214(mounting pad)及第二接合墊216，以作爲 晶片凸塊的接點。其中，第一培合墊214位於覆晶構裝基 板200的外圍區域218 ;而第二接合墊216仿於內圍區域 2?.0。其中，絕緣層204及206、圖案化線路層210及表層 的圖案化線路層，可以藉由堆疊的方式（build-up)形成。 經濟邾智慧財產局Μ工消费合作杜印製 表層的圖案化線路層表面會覆蓋一焊罩層222,而 焊罩層222之材質爲絕緣材料，包括紫外線型綠漆及熱硬 化型綠漆等，形成焊罩層222之方法則包括滾筒塗佈法 (Roller Coating)、簾幕塗佈法（Curtain Coating)、網 版印刷法（Screen Printing)、浸染法（Dip)以及乾膜（Dry Film)形成方法等。如圖所示焊罩層222對於外圍區域218 的第一接合墊214僅暴露出其部分上表面214a :而對於內 本纸張尺度適用中國國家標準（CNS)A4規格<210 X 297公釐〉 A7 B7 4443 7〇 5827twf-doc/006 五、發明說明（7) 圍區域220則形成開口 224 ’完全暴露出第二接合燊216 的上表面216a及側面216b。所以，在外圍區域2丨8逶屬 於SMD的接合墊結構；而內圍區域220是屬於NSMD的接 合墊結構。然而，由於內圍區域220之空間較大，所以第 二接合墊216之佈置可以較爲寬鬆。其中，第一接合勢 之間的間距230(Ditch)小於第二接合墊216之間的間距 232 ;而間距230、232皆大約爲150〜250微米。 接著請參照第5圖，其繪示依照本發明較佳實施例 之一種覆晶構裝剖面圖。本發明之覆晶構裝基板200應用 於覆晶構裝時，同樣地，在外圍區域218第一接合墊214 係爲SMD結構，而內圍區域220的第二接合墊216則採用 NSMD結構。晶片250的主動表面250a具有多個焊墊，每 一焊墊上配置一球底金屬層252，而球底金屬層252上形 成一凸塊254。凸塊254分別對應第一接合墊214及第二 接合墊216，並與其接合形成電性連接。同時，晶片25〇 與覆晶構裝基板 200之間會塡入一塡充材料 256〈underfill)，以吸收晶片250與覆晶構裝基板2〇〇間 因熱膨脹係數差異而產生之熱應力，提高覆晶構裝中凸塊 254的可靠度》 由於本發明之覆晶構裝基板200在外圍區域218採 用SMD結構，所以對應之凸塊254只與第一接合墊214之 上表面214a接合’而在塡入塡充材料256時不會產生氣 泡（void)，可提高製程良率。而內圍區域220採用msmd 結構’所以對應之凸塊254與第二接合墊216的上表面216a 9 本紙張尺度適財ΒΒ家株年（CNS)A4規格<210x297公釐） I — — —*1—--._1!11 訂-- -------線]-^ t請先Μ讀背面之注意事項再填寫本頁} 經濟邨%慧財產局貝工消t合作社印製 4443 7〇 5827twf,d〇c/006 A7 B7 經濟部智慧財產局貝工消费合作社印製 五、發明說明) 及側面216b接合，而由於內圔區域220的空間較大，如 前所述第二接合墊216間之間距較大’亦即開口 224尺寸 較大，所以在塡入塡充材料256時亦不會產生氣泡。另外， 由於凸塊254與第二接合墊216的上表面216a及側面216b 接合，所以產生較大之崩塌現象，可以提供較佳的接合品 質，而且覆晶構裝時，增加對覆晶構裝基板200及凸塊254 共平面度誤差的容忍度，提高製程良率及製程裕度。 綜上所述，本發明之覆晶構裝基板至少具有下列優 點： 1. 本發明之覆晶構裝基板同時具有SMD及NSMD結 構，並加以適當安排，即SMD的間距較小，NSMD間距較大， 可以同時兼具二者之優點，並免除二者之缺點，使得覆晶 構裝的製造良率提高。 2. 本發明之覆晶構裝基板，可以容許較大的凸塊共 平面度誤差，以及接合墊共平面度誤差，使得覆晶構裝的 製造裕度增加，並避免塡充材料中氣孔的發生。 雖然本發明已以一較佳實施例揭露如上’然其並非 用以限定本發明，任何熟習此技藝者，在不脫離本發明之 精神和範圍內，當可作些許之更動與潤飾，因此本發明之 保護範圍當視後附之申請專利範圍所界定者爲準。 本紙張尺度適用中國踽家標準（CNS>A4规格（210 X 297公藿） (請先閱讀背面之注意事項再填寫本頁) ρ------- —訂-----Produced by Shelley Consumer Cooperation, Intellectual Property Bureau, Ministry of Economic Affairs, "43 7〇5827twf.d〇c / 006 A7 ___ B7 V. Description of the Invention (/) This invention relates to a flip-chip mounting substrate, and in particular to A flip-chip mounting substrate that can improve bump bonding. Flip Chip is a mounting technology that is often applied to wafer-scale mounting. Because it can use area array to configure solder pads, and The carrier is connected through bumps, so the installation area can be reduced and the signal transmission path can be shortened. In the current flip chip technology products, depending on the degree of solder mask covering the mounting pad, changing the bump The contact area between the block and the bonding pad, which in turn affects the collapse of the bump. The traditional substrate bonding pad design can be divided into "Solder Mask Define (SMD)" and "Non Solder Definition" Mask Define, NSMD). Please refer to Figure 1, which shows the pad structure of the conventional "shield definition". For flip-chip mounting, most of them use a laminating board (laminating board) 100 as the flip-chip mounting substrate. The types of the laminating board 100 include a kick-in type and a build-up type. The laminated board 100 is mainly composed of a patterned circuit layer and an insulating layer 102 alternately laminated, wherein the patterned circuit layer is formed by, for example, a copper foil layer and defined by lithographic etching, and the material of the insulating layer 102 includes glass epoxy resin (FR -4, FR-5), bismaleic acid hydrazone 55 amine (Bismaleimide-Triazine (BT) or epoxy). The patterned circuit layer on the surface of the laminated board 100 will form a plurality of bonding pads 104 as the contacts of the laminated board 100 to the wafer 110. In the SMD type substrate, the solder mask layer 106 covers the surface patterned circuit layer, and only a part of the surface of the bonding pad 104 is exposed most, that is, the outer edge surface of the bonding pad 104 is covered. The active surface 112 of the wafer 110 will be formed with 3 paper-size wrapping standard (CNS > A4 specification 210 x 297 mm) --------- I I ---- ------ Order --------Line 1- ^ (Please read the notes on the back before filling this page) 4443 7 〇5827twf, doc / 006 A7 B7 Intellectual Property Bureau, Ministry of Economic Affairs Printed by the Industrial Drop Cooperative Co., Ltd. 5. Description of the Invention (z) Multiple bonding pads (Under Bump Metal, UBM) are formed thereon, and bumps 116 are formed on the ball-bottomed metal layer 114. 'For example, a solder bump. Since the size of the ball bottom metal layer Π4 and the solder mask layer 106 can limit the collapse of the bump 116, the size of the opening 108 of the solder mask layer 106 not only determines the bonding area of the bump 116 and the bonding pad 104, but also affects the bump The collapse phenomenon of the block 116, and the height of the final bump 116. Please refer to Figure 2, which shows the pad structure of the conventional "non-solder shield definition". In the structure of the NSMD, the solder mask layer 106a will completely expose the entire surface of the bonding pad 104a, and the bump 116 will be joined with the upper surface 120 and the side 122 of the bonding pad 104a, increasing the space between the bump 116 and the bonding pad 104a. Contact area. At this time, the opening 108 and the bump 116 will maintain a gap, so the opening 108a of the solder mask layer 106a will not affect the collapse of the bump 116 and the final height of the bump 116. Both the SMD and NSMD structures have their advantages and disadvantages in application. One of the objectives of the present invention is to propose a flip-chip mounting substrate with both SMD and MSMD structures, and arrange them appropriately to make the flip-chip mounting Manufacturing yield promotion. Another object of the present invention is to provide a flip-chip mounting substrate, which can tolerate large coplanarity errors of the bumps and coplanarity errors of the bonding pads, thereby increasing the manufacturing margin of the flip-chip mounting. In order to achieve the above and other objectives of the present invention, a flip-chip mounting substrate is provided, including: a plurality of patterned circuit layers and at least one insulating layer, the insulating layer is disposed between the patterned circuit layers to isolate the patterned circuit layer, And 4 (Please read the notes on the back before filling in this page) — 11 orders --------- line. This paper size is applicable + country B standard (CNS > A4 specifications < 210 * 297 public * > A7 B7 4443 70 5827twf .doc / 006 V. Description of the invention (j) Laminated with patterned circuits. The patterned circuit layers are electrically connected to each other, and one of the patterned circuit layers is located on the surface of the flip-chip mounting substrate. It includes at least a plurality of first bonding pads and a plurality of second bonding pads. A solder mask layer covers the patterned circuit layer on the surface of the flip-chip mounting substrate, exposes a part of the surface of the first bonding pad, and covers A part of the surface of the outer edge of the first bonding pad completely exposes the surface of the second bonding pad. According to a preferred embodiment of the present invention, the insulating layer has a plurality of through holes for electrically connecting the patterned circuit layer. The spacing between the first bonding pads is less than The distance between the bonding pads; and the first bonding pad is arranged on the periphery of the flip-chip mounting substrate, and the second bonding pad is located on the inner periphery of the flip-chip mounting substrate. The flip-chip mounting substrate of the present invention is applied to flip-chip mounting In this case, the bumps are bonded to the upper surface of the first bonding pad, and the bumps and the second bonding pad are bonded to the upper surface and the sides. In order to make the above and other objects, features, and advantages of the present invention more comprehensible The following is a detailed description of a preferred embodiment and the accompanying drawings, which are described in detail as follows: Brief description of the drawings: Figure 1 shows the structure of a conventional bonding pad with the definition of "solder shield." Figure 2 shows The "bonding pad definition" is known. Figure 3 shows a cross-sectional view of a flip-chip mounting substrate according to a preferred embodiment of the present invention. Figure 4 shows a Top view of a flip-chip mounting substrate. Figure 5 shows a flip-chip mounting according to a preferred embodiment of the present invention. The paper size is suitable for the standard of the family < CNS) A4 (210 x 297 mm). --I--1 I --- Order -------------------------------------------------- Please read the precautions on the back first Refill this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 443 7 582 7 twf. Doc / 〇 0 6 A7 B7 Printed by the Shellfish Consumer Cooperatives of the Economic and Intellectual Property Bureau 5. Description of the invention (f) Sectional drawing. Description of the drawing: 100: laminated board 102: insulating layers 104, 104a: bonding pads 106, 222: solder mask layers 108 '108a, 224: openings 110, 250: wafers 112, 250a: active surfaces 114, 252: balls Bottom metal layers 116, 254: bumps 120, 214a, 216a: upper surface 122: side surface 200: flip-chip mounting substrate 202: insulating core layer 204, 206, insulating layer 208, 210: patterned circuit layer 212: Hole 214: First bonding pad 216: Second bonding pad 218: Peripheral area 220: Inner peripheral area 230, 232: Pitch 256: Refill material This paper size is applicable to Chinese Standard (CNS) A4 specifications < 210 X 297 (Mm) --- ----- Γ 111 ---] ---- Order --------- ^^ 1 ^ < Please read the notes on the back before filling in this page) 4443 7〇5827twf.doc / 006 A7 B7 V. Description of the invention (<) Example As far as the design of the flip-chip mounting substrate is concerned, after the bumps are bonded to the bonding pads, there is no gap between the bumps and the solder mask layer. Therefore, in the subsequent underfilling process, bubbles are less likely to be generated, and thus the yield can be improved. However, SMD also has a small contact area between the bump and the bonding pad, so the collapse phenomenon is poor, the joint effect is poor, and the icoDlanarity of the flip-chip mounting substrate is strict, so the manufacturing process Low margin (process window). On the contrary, in terms of the design of NSMD, because the contact area between the bump and the bonding pad is large, including the upper surface and the side of the bonding pad, the collapse phenomenon is better, and the bonding effect is better, which can improve the flip chip structure. The tolerance of the mounting substrate to coplanar errors. However, in order to avoid air bubbles caused by the distance between the bump and the solder mask layer in the subsequent solder filling process, it is necessary to appropriately increase the size of the solder layer opening. Such a requirement must increase the pitch between the bonding pads, which makes the layout of the flip-chip structured substrate difficult, and may reduce the density of the structure. Therefore, how to combine the advantages of SMD and NSMD and reduce the corresponding disadvantages of SMD and NSMD is very important. At present, the distribution of bumps in chip-on-chip products is mainly divided into peripheral and full matrix methods, while the corresponding chip-on-chip substrate layout will restrict the way of contact placement due to the relationship between manufacturing and design capabilities. Take a build-up flip-chip substrate and a six-layer board (2 + 2 + 2) as an example. Generally, the bonding pads of the signal contacts can only be arranged in the outer six circles, while the inner periphery is Configure power contacts, ground contacts, and dummy contacts. The space in the middle is larger, so the pitch of the bonding pads can usually be larger. This paper size is applicable to China's poor family < CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling this page) -¾ -------- Order ---- ----- Line one! Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4443 7 〇5 82 7twf. Doc / 〇〇6 A7 B7 V. Description of the invention (ό) I Read the notes on the back and fill in this page. Please refer to Figure 3 and Figure 4 at the same time 3 is a cross-sectional view of a flip-chip mounting substrate according to a preferred embodiment of the present invention; and FIG. 4 is a plan view of a flip-chip mounting substrate according to a preferred embodiment of the present invention. In the present invention, the flip-chip mounting substrate 200 is mainly formed by alternately stacking the insulating layers 202, 204, 206 and the patterned circuit layers 208, 210. The insulating layer 202 is an insulating core layer, and the material is, for example, glass epoxy resin (FR-4, FR-5) or bismaleic acid diimide (8 丨 3 财 16 丨 11 ^ (16-1 '1 ^ 32 丨 116,: 81'), etc .; and the material of the insulating layers 204 and 206 is, for example, epoxy. The patterned circuit layers 208 and 210 are, for example, formed by copper foil through a lithographic etching process definition, The patterned circuit layers 208 ′ and 210 are electrically connected through vias 212 (vias) disposed in the insulating layers 204 and 206. The patterned circuit layer on the surface layer of the flip-chip mounting substrate 200 will not only form circuits but also form circuits. A first bonding pad 214 (mounting pad) and a second bonding pad 216 are formed to serve as contacts for the bumps of the wafer. The first bonding pad 214 is located in the peripheral region 218 of the flip-chip mounting substrate 200; and the second bonding The pad 216 is similar to the inner area 2? .0. Among them, the insulating layers 204 and 206, the patterned circuit layer 210, and the patterned circuit layer of the surface layer can be formed by a stack-up method. Economy 邾 Smart Property The surface of the patterned circuit layer of the printed surface layer will be covered with a solder mask layer 222, and the material of the solder mask layer 222 Insulating materials, including ultraviolet-type green paint and heat-hardening type green paint, etc., the method of forming the solder mask layer 222 includes a roller coating method, a curtain coating method, and a screen printing method. Printing), dip method and dry film formation method, etc. As shown in the figure, the solder mask layer 222 exposes only a part of the upper surface 214a of the first bonding pad 214 in the peripheral region 218: The paper size applies the Chinese National Standard (CNS) A4 specification < 210 X 297 mm> A7 B7 4443 7〇5827twf-doc / 006 V. Description of the invention (7) The surrounding area 220 is formed with an opening 224 'Full exposure of the second The upper surface 216a and the side surface 216b of the joint 燊 216. Therefore, in the peripheral region 2 丨 8 逶, it belongs to the bonding pad structure of SMD; and the inner region 220 belongs to the NSMD pad structure. However, because the space of the inner region 220 is more Large, so the arrangement of the second bonding pads 216 can be relatively loose. Among them, the pitch 230 (Ditch) between the first bonding potentials is smaller than the pitch 232 between the second bonding pads 216; and the pitches 230 and 232 are both about 150. ~ 250 microns. Then refer to FIG. 5 is a cross-sectional view of a flip-chip mounting according to a preferred embodiment of the present invention. When the flip-chip mounting substrate 200 of the present invention is applied to a flip-chip mounting, similarly, the first bonding is performed in the peripheral region 218 The pad 214 is an SMD structure, and the second bonding pad 216 of the inner periphery region 220 is an NSMD structure. The active surface 250a of the wafer 250 has a plurality of solder pads. Each solder pad is provided with a ball-bottom metal layer 252, and a bump 254 is formed on the ball-bottom metal layer 252. The bumps 254 correspond to the first bonding pad 214 and the second bonding pad 216, respectively, and are bonded to form an electrical connection. At the same time, an underfill material 256 is inserted between the wafer 25 and the flip-chip mounting substrate 200 to absorb the thermal stress caused by the difference in thermal expansion coefficient between the wafer 250 and the flip-chip mounting substrate 200. Improving the reliability of bumps 254 in flip-chip mounting "Since the flip-chip mounting substrate 200 of the present invention uses an SMD structure in the peripheral region 218, the corresponding bumps 254 are only bonded to the upper surface 214a of the first bonding pad 214 ' In addition, voids are not generated when the filling material 256 is poured, which can improve the process yield. The inner area 220 adopts the msmd structure. Therefore, the corresponding surface of the bump 254 and the upper surface 216a of the second bonding pad 216 9 paper size is suitable for this year (CNS) A4 size < 210x297 mm) I — — — * 1 —--._ 1! 11 Order-------- line]-^ t Please read the precautions on the back before filling out this page} Printed by the Economic Village% Hui Property Bureau Shellfisher Cooperative 4443 7〇5827twf, doc / 006 A7 B7 Printed by Shelley Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs, and 5. Description of invention) and side 216b joint, and because the space inside the inner area 220 is larger, as mentioned above, the second The distance between the bonding pads 216 is larger, that is, the size of the opening 224 is larger, so no bubbles are generated when the filling material 256 is inserted. In addition, since the bump 254 is bonded to the upper surface 216a and the side surface 216b of the second bonding pad 216, a large collapse phenomenon occurs, which can provide better bonding quality, and during the flip-chip mounting, the flip-chip mounting is increased. The tolerance of the coplanarity error of the substrate 200 and the bump 254 improves the process yield and the process margin. In summary, the flip-chip mounting substrate of the present invention has at least the following advantages: 1. The flip-chip mounting substrate of the present invention has both SMD and NSMD structures, and is appropriately arranged, that is, the pitch of the SMD is smaller and the pitch of the NSMD is smaller Large, can have the advantages of both, and avoid the disadvantages of both, so that the manufacturing yield of flip-chip packaging is improved. 2. The flip-chip mounting substrate of the present invention can tolerate large coplanarity errors of the bumps and coplanarity errors of the bonding pads, which increases the manufacturing margin of the flip-chip mounting and avoids the pores in the filling material. occur. Although the present invention has been disclosed above in a preferred embodiment, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. This paper size is in accordance with Chinese standards (CNS > A4 size (210 X 297 cm)) (Please read the precautions on the back before filling this page) ρ ------- —Order -----