♦ · ♦ · 經濟部智慧財產局貝工消费合作社印製 4429 6 9 5268iwf,d〇c/006 A7 •----B7 五、發明說明（/) 本發明是有關於一種快閃記憶體之製造方法，且特別 是有關於一種二位元快閃記憶體之製造方法。 習知的快閃記憶體，爲一種可抹除可程式唯讀記憶體 (Erasable Programmable Read-Only Memory ; EPROM)。 快閃記憶體的特色在於可以進行”一塊一塊”（bl ock by block)方式的記憶淸除（erase)工作，且速度非常的快， 約1到2秒之間即可完成記憶淸除工作。較一般epr〇M的 速度快’因爲一般的EPROM進行”一個位元接著一個位 元”（bit by bit)方式的記憶淸除工作，約要數分鐘才能完 成資料的淸除。 一般而言，快閃記憶胞係由具有可電性改變起始電壓 的金氧半導電晶體所組成，而氮化矽氧化矽半導體 (silicon nitride oxide semiconductor，SNOS)則爲快 閃記憶體之一種。 第1圖係爲習知一種二位元SN0S記憶體元件之剖面 簡圖。SM0S記憶體元件包括在基底100中，形成有一源極 /汲極區102，在源極/汲極區102之間的基底100上，形 成有一層薄氧化砍層104，而在薄氧化砂層104上形成有 氮化矽層106,在氮化矽層106上形成有多晶矽閘極108'. 當SN0S之快閃記憶體進行資料儲存時，分別在源極/ 汲極區102以及多晶矽閘極108上施以一高電壓，使熱電 子（Hoi electrons)從源極/汲極區102流出後，在靠近汲 極源極/汲極區102附近垂直穿過薄氧化矽層104,注入並 陷於靠近源極/汲極區102的氮化矽層106中，以在氮化 3 本紙張尺度適用中國圉家標準（CNS>A4規格（210 X 297公釐） -----^----^---,1 --------訂---------線V (請先閱讀背面之注意事項再填寫本頁) A7 B7 —第二源 5268tw f.doc/006 五、發明說明（1) 矽層106之兩端分別儲存一個位元，達到可儲存二位元的 目的。 然而，習知二位元SNOS快閃記憶體，因爲熱電子在 穿透薄氧化矽層104，儲存於氮化矽層106之後，不易停 留在氮化矽層106的兩端，電子會進行再分佈 (redistribute)，並散佈於於整個氮化矽層106中。這種 再分佈的現象使得由汲極區端射入氮化矽層106，以及從 源極區端射入氮化矽層106之熱電子重新混合並散佈於氮 化矽層106中，因而限制了快閃記憶胞的操作模式，並導 致過編程（ove r - progr ammi ng )等問題。/ 因此本發明就是在提供一種快閃記憶體的製造方 法1此方法簡述如下：首先提供一基底，其上依序形成一 層薄氧化砂層、一層氮化砂層與一層材料層。之後，於材 料層與氮化矽層中，形成裸露薄氧化矽層之第一開口與第 二開口。繼之，於第一與第二開口所裸露之薄氧化矽層下 方之該基底中，分別形成一第 極/汲極區。續之，於第一與第二開口中形成塡滿第一與 第二開口之第一介電層。接著移除部分材料層與部分第一 介電層，以在第一介電層之側壁上，形成由剩下材料層與 剩下氮化矽層所組成之間隙壁，並裸露出第一與第二源極 /汲極區之間的基底上的部分薄氧化矽層。之後，移除剩 下之材料層，並以剩下之氮化矽層與第一介電層爲罩幕， 移除部分薄氧化矽層。緊接著，進行一氧化製程，以在薄 氧化矽層所裸露之基底上形成第二介電層。最後，於基底 本紙張尺度適用中國國家標準（CNS)A4规格（2101297公釐〉 -----Γ----------訂---------線V (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印较 A7 B7 4429 6 9 _S268【wf-doc/006 五、發明說明（彡） 上方形成一控制閘° 依照本發明的一較佳實施例，其中材料層對氮化矽層 有較大的蝕刻選擇比，而材料層可以是由化學氣相沉積法 所形成的多晶矽層。於本發明中，將位於兩源極/汲極區 之間的基底上的氮化矽層，以第二介電層分隔成兩個可分 別儲存一位元之氮化矽層。由於兩氮化矽層之間以第二介 電層電性隔離，因此不會有電子再分布造成造成儲存二位 元之問題以及過編程之問題。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 第1圖係爲習知一種二位元SNOS記憶體元件之剖面 簡圖； 第2A圖至第2F圖所示，爲根據本發明一較佳實施例 之一種二位元快閃記憶體之製造流程剖面圖。 其中，各圖標號與構件名稱之關係如下： 100、200 :基底 102、208a、208b :源極/汲極區 104、202、202a :薄氧化矽層 106、204、204a :氮化矽層 108 :多晶砂層 205 :間隙壁 206、206a :材料層 本紙張尺度適用中國國家橾準（CNS)A4規格（210 X 297公* ) ------------,1 -------—訂 -- ----線™^" (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局WC工消费合作杜印製 ν' 442^6 9 Α7 Β7 五、發明說明（f) 209a 、 209b :開□ 210、212 :介電層 2 ] 4 :導電層♦ · ♦ · Printed by Shelley Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 4429 6 9 5268iwf, doc / 006 A7 • ---- B7 V. Description of the Invention (/) The present invention relates to a type of flash memory. The invention relates to a manufacturing method, and more particularly to a manufacturing method of a two-bit flash memory. The conventional flash memory is an Erasable Programmable Read-Only Memory (EPROM). The characteristic of flash memory is that it can perform memory erasure work in a "bl ock by block" manner, and the speed is very fast, and the memory erasure work can be completed in about 1 to 2 seconds. It is faster than the general epr0M. Because the general EPROM performs the "bit by bit" memory erasure, it takes several minutes to complete the erasure of the data. Generally speaking, a flash memory cell line is composed of a gold-oxygen semi-conductive crystal that can electrically change the starting voltage, and silicon nitride oxide semiconductor (SNOS) is a type of flash memory. . Fig. 1 is a schematic cross-sectional view of a conventional two-bit SNOS memory element. The SMOS memory element is included in the substrate 100, and a source / drain region 102 is formed. On the substrate 100 between the source / drain regions 102, a thin oxide chopper layer 104 is formed, and a thin oxide sand layer 104 is formed on the substrate 100. A silicon nitride layer 106 is formed thereon, and a polycrystalline silicon gate 108 'is formed on the silicon nitride layer 106. When the SN0S flash memory is used for data storage, it is in the source / drain region 102 and the polycrystalline silicon gate 108, respectively. A high voltage is applied to cause hot electrons (Hoi electrons) to flow out from the source / drain region 102 and pass through the thin silicon oxide layer 104 vertically near the source / drain region 102, implanted and trapped near In the silicon nitride layer 106 of the source / drain region 102, the Chinese paper standard (CNS > A4 specification (210 X 297 mm)) is applied to the paper size of 3 nitrides ----- ^ ---- ^ ---, 1 -------- Order --------- Line V (Please read the notes on the back before filling this page) A7 B7 —Second source 5268tw f.doc / 006 V. Description of the invention (1) One bit is stored at each end of the silicon layer 106 to achieve the purpose of storing two bits. However, the two-bit SNOS flash memory is known because hot electrons penetrate thin oxygen. After the silicon layer 104 is stored in the silicon nitride layer 106, it is not easy to stay at both ends of the silicon nitride layer 106, and the electrons are redistributed and dispersed throughout the silicon nitride layer 106. This redistribution The phenomenon of hot electrons entering the silicon nitride layer 106 from the end of the drain region and the silicon nitride layer 106 from the end of the source region is remixed and dispersed in the silicon nitride layer 106, thereby limiting flash memory. Operating mode of the cell and cause problems such as over-programming (ove r-progr ammi ng). / Therefore, the present invention is to provide a flash memory manufacturing method 1 This method is briefly described as follows: First, a substrate is provided, which is A thin oxide sand layer, a nitrided sand layer, and a material layer are sequentially formed. Then, in the material layer and the silicon nitride layer, a first opening and a second opening of the exposed thin silicon oxide layer are formed. Then, in the first and A first electrode / drain region is respectively formed in the substrate under the thin silicon oxide layer exposed by the second opening. Further, a first interstitial that is full of the first and second openings is formed in the first and second openings. Electrical layer. Then remove some material layers and parts A first dielectric layer to form a spacer composed of the remaining material layer and the remaining silicon nitride layer on the sidewall of the first dielectric layer, and expose the first and second source / drain regions Part of the thin silicon oxide layer on the substrate in between. Then, remove the remaining material layer, and use the remaining silicon nitride layer and the first dielectric layer as a mask to remove a portion of the thin silicon oxide layer. Tight Next, an oxidation process is performed to form a second dielectric layer on the exposed substrate of the thin silicon oxide layer. Finally, the Chinese paper standard (CNS) A4 specification (2101297 mm>) is applied to the paper size of the substrate ---- -Γ ---------- Order --------- Line V (Please read the notes on the back before filling out this page) Employee Cooperatives of Intellectual Property Bureau of the Ministry of Economic Affairs printed A7 B7 4429 6 9 _S268 [wf-doc / 006 V. Description of the invention (彡) A control gate is formed on the top ° According to a preferred embodiment of the present invention, the material layer has a larger etching selection ratio to the silicon nitride layer, and the material The layer may be a polycrystalline silicon layer formed by a chemical vapor deposition method. In the present invention, a silicon nitride layer on a substrate located between two source / drain regions is separated by a second dielectric layer into two silicon nitride layers that can respectively store one bit. Because the two silicon nitride layers are electrically isolated by a second dielectric layer, there will be no redistribution of electrons that will cause the problem of storing two bits and over-programming. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Brief description of the drawings: FIG. 1 It is a simplified cross-sectional view of a conventional two-bit SNOS memory element; FIG. 2A to FIG. 2F are cross-sectional views of a manufacturing process of a two-bit flash memory according to a preferred embodiment of the present invention . The relationship between each icon number and the component name is as follows: 100, 200: substrates 102, 208a, 208b: source / drain regions 104, 202, 202a: thin silicon oxide layers 106, 204, 204a: silicon nitride layer 108 : Polycrystalline sand layer 205: Spacer walls 206, 206a: Material layer The paper size is applicable to China National Standard (CNS) A4 (210 X 297 male *) ------------, 1- -----— Order----- line ™ ^ " (Please read the notes on the back before filling out this page) Printed by WC Industry Consumer Cooperation, Intellectual Property Bureau, Ministry of Economic Affairs ν '442 ^ 6 9 Α7 Β7 V. Description of the invention (f) 209a, 209b: Open 210, 212: Dielectric layer 2] 4: Conductive layer
經 濟 部 智 慧 財 產 局 員 工 消 费 合 作 杜 印 製 實施例 第2A圖至第2F圖所示，爲根據本發明一較佳實施例 之一種二位元快閃記憶體之製造流程剖面圖。 請參照第2A圖，首先提供一基底200，於基底200上 依序形成一層薄氧化砂層202、一層氮化砂層204與一層 材料層206。其中，薄氧化矽層202之厚度約小於30埃， 且氮化砂層204例如是由化學氣相沉積法（chem 1 ca 1 vapor deposition，CVD)所形成之氮化砂層，而其厚度約 介於100到200埃之間。此外，材料層206對其下層之氮 化矽層 204 有較大的蝕刻選擇比（etching s e 1 e c t i v i t y)，而材料層206可以是由化學氣相沉積法所 形成之多晶矽層。 接著，請參照第2B圖，圖案化材料層206與氮化矽 層204，以在材料層206與介電層208中，形成裸露出部 分薄氧化矽層202之開口 209a與209b。接著，進行一離 子摻雜製程，以分別在開口 209a與209b所裸露之部分薄 氧化矽層202的下方基底200中，分別形成源極/汲極區 208a與208b。其中所植入的離子比如是N型導電型的砷 (As)離子，植入的劑量約爲1015 atoms/cm2。由於在開口 209a與209b中之基底200上，形成有薄氧化矽層202， 本紙張尺度適用中國國家標準（CNSJA4規格（210 X 297公釐） 請 先 閱 讀 背 面 之 注 意 事 項 ΨThe consumption and cooperation of employees of the Intellectual Property Office of the Ministry of Economic Affairs. Du Printed Embodiments Figures 2A to 2F are cross-sectional views showing the manufacturing process of a two-bit flash memory according to a preferred embodiment of the present invention. Referring to FIG. 2A, a substrate 200 is first provided, and a thin oxide sand layer 202, a nitrided sand layer 204, and a material layer 206 are sequentially formed on the substrate 200. The thickness of the thin silicon oxide layer 202 is less than about 30 angstroms, and the nitrided sand layer 204 is, for example, a nitrided sand layer formed by a chemical vapor deposition (chem 1 ca 1 vapor deposition, CVD) method, and the thickness is approximately between Between 100 and 200 Angstroms. In addition, the material layer 206 has a larger etching selectivity (etching s e 1 e c t i v i t y) of the underlying silicon nitride layer 204, and the material layer 206 may be a polycrystalline silicon layer formed by a chemical vapor deposition method. Next, referring to FIG. 2B, the material layer 206 and the silicon nitride layer 204 are patterned to form openings 209a and 209b of the thin silicon oxide layer 202 in the material layer 206 and the dielectric layer 208 with exposed portions. Next, an ion doping process is performed to form source / drain regions 208a and 208b in the underlying substrate 200 of the thin silicon oxide layer 202 exposed in the openings 209a and 209b, respectively. The implanted ions are, for example, N-type conductive arsenic (As) ions, and the implanted dose is about 1015 atoms / cm2. As a thin silicon oxide layer 202 is formed on the substrate 200 in the openings 209a and 209b, this paper size applies to the Chinese national standard (CNSJA4 specification (210 X 297 mm)). Please read the notes on the back side first. Ψ
I 訂 ▲I order ▲
A7 44296 9 ^------- 五、發明說明（夕） 因此可以防止在離子摻雜製程中對基底2〇〇表面造成損 害。 續之，請參照第2C圖’於開口 209a與209b中’形 成一層介電層210，且此介電層210塡滿開口 209a與 209b。其中，此介電層210對材料層206有較大的蝕刻選 擇比，而此形成介電層210之方法例如是於基底200上 方，以化學氣相沉積法形成一層氧化矽層（未繪示），且此 氧化矽層塡滿開口 209a與209b，之後’以回蝕刻法移除 部分氧化矽層’直到裸露出材料層206之表面，以在開口 209a與209b中形成介電層210。 繼之，請參照第2D圖’移除部分材料層206與氮化 矽層204，以在介電層210之側壁上，形成由材料層2〇6a 與氮化矽層204a所組成的間隙壁205，並且裸露出源極/ 汲極區208a與208b之間的部分薄氧化矽層2〇2。其中， 移除部分材料層206與氮化砂層204之方法包括非等項性 蝕刻法。 之後請參照第2E圖’移除材料層2〇6a，直到裸露出 介電層210之部分側壁，以及氮化矽層2〇4a之表面^接 著’以氮化矽層204a與介電層210爲罩幕，移除部分薄 氧化砂層202 ’直到裸露出部分基底2〇〇之表面，並將薄 氧化矽層202轉換成薄氧化矽層202a。 繼之，進行一氧化製程，以在薄氧化層2〇2a所裸露 之部分基底200上，亦即是氮化砂層2〇4a之間，形成一 介電層212，其中，氧化製程例如是熱氧化法。 7 ------I II .--- (請先閱讀背面之注意事項再i升寫本頁) 訂---------線y. 經濟部智慧財產局貝工消f合作社印製 本紙張尺度適用中國困家標準（CNS)A4規格（2Ϊ〇_ 297公釐〉 A7 B7 4429 6 9 5268tw1\doc/006 五、發明說明（6) 由於在薄氧化層202a所裸露之基底200上形成介電 層212,所以可將用於儲存熱電子之氮化矽層204a電性隔 離。很明顯的，可以用來儲存熱電子的氮化矽層204a有 兩個，亦即是一種不會發生電子再分佈的二位元的快閃記 憶體。如此一來，分別從源極/汲極區208流出之熱電子， 會沿源極/汲極區208之邊緣，穿過薄氧化矽層202a ’分 別儲存在氮化矽層204a中，因爲介電層Π2之電性隔離 作用，所以每一氮化矽層204a所儲存的電子，不會進行 再分布，故習知由於電子再分布，造成儲存二位元之問題 以及過編程之問題可以得到解決。 接著請參照第2F圖，於基底200上方形成一層導電 層（未繪示），之後，定義導電層，以形成控制閘214 ’完 成二位元快閃記憶體之製造。 於本發明中，將位於源極/汲極區之間的基底上的氮 化矽層，以一介電層分隔成兩個可分別儲存一位元之氮化 矽層。由於兩氮化矽層之間以介電層電性隔離，因此不會 有電子再分布造成造成儲存二位元之問題以及過編程之 問題。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 8 -----^----Γ--Γ --------訂------|!線^ (諳先Μ讀背面之注意事項，i.寫本頁) 經濟部智慧財產局負工消费合作社印製 本紙張尺度適用中®國家標準（CNS)A4規格（210 X 297公« >A7 44296 9 ^ ------- 5. Description of the Invention (Even) Therefore, it is possible to prevent damage to the surface of the substrate 200 during the ion doping process. Continuing, please refer to FIG. 2C to form a dielectric layer 210 in the openings 209a and 209b, and the dielectric layer 210 fills the openings 209a and 209b. Wherein, the dielectric layer 210 has a larger etching selection ratio to the material layer 206, and the method for forming the dielectric layer 210 is, for example, a silicon oxide layer (not shown) by using a chemical vapor deposition method over the substrate 200 ), And the silicon oxide layer fills the openings 209a and 209b, and then “removes part of the silicon oxide layer by etch-back method” until the surface of the material layer 206 is exposed to form a dielectric layer 210 in the openings 209a and 209b. Next, please refer to FIG. 2D 'removing part of the material layer 206 and the silicon nitride layer 204 to form a partition wall composed of the material layer 206a and the silicon nitride layer 204a on the sidewall of the dielectric layer 210. 205, and a part of the thin silicon oxide layer 202 between the source / drain regions 208a and 208b is exposed. Among them, the method for removing a part of the material layer 206 and the nitrided sand layer 204 includes an isotropic etching method. Afterwards, please refer to FIG. 2E 'remove the material layer 206a until part of the sidewall of the dielectric layer 210 and the surface of the silicon nitride layer 204a are exposed. Then,' the silicon nitride layer 204a and the dielectric layer 210 are exposed. For the mask, a part of the thin oxide sand layer 202 ′ is removed until a part of the surface of the substrate 2000 is exposed, and the thin silicon oxide layer 202 is converted into a thin silicon oxide layer 202 a. Next, an oxidation process is performed to form a dielectric layer 212 on a part of the substrate 200 exposed by the thin oxide layer 202a, that is, between the nitrided sand layer 204a. The oxidation process is, for example, thermal Oxidation method. 7 ------ I II .--- (Please read the precautions on the back before i write this page) Order --------- line y. Intellectual Property Bureau of the Ministry of Economic Affairs The paper size printed by the cooperative is applicable to the Chinese Standard for Household Standards (CNS) A4 (2Ϊ〇_ 297 mm) A7 B7 4429 6 9 5268tw1 \ doc / 006 V. Description of the invention (6) Due to the exposure of the thin oxide layer 202a A dielectric layer 212 is formed on the substrate 200, so the silicon nitride layer 204a for storing thermal electrons can be electrically isolated. Obviously, there are two silicon nitride layers 204a that can be used for storing thermal electrons, that is, A two-bit flash memory that does not redistribute electrons. In this way, the hot electrons flowing from the source / drain region 208, respectively, will pass through the thin edge of the source / drain region 208. The silicon oxide layer 202a 'is stored in the silicon nitride layer 204a, respectively. Because of the electrical isolation of the dielectric layer Π2, the electrons stored in each silicon nitride layer 204a will not be redistributed. The redistribution can solve the problem of storing two bits and over-programming. Next, please refer to FIG. 2F, above the substrate 200. Form a conductive layer (not shown), and then define the conductive layer to form the control gate 214 'to complete the manufacture of the two-bit flash memory. In the present invention, the substrate located between the source / drain regions The silicon nitride layer on the top is separated by a dielectric layer into two silicon nitride layers that can store one bit respectively. Since the two silicon nitride layers are electrically isolated by the dielectric layer, there will be no electrons. The distribution causes the problem of storing two bits and the problem of over-programming. Although the present invention has been disclosed above with a preferred embodiment, it is not intended to limit the present invention. Anyone skilled in this art will not depart from the spirit of the present invention. Within the scope and scope, various modifications and retouching can be made, so the protection scope of the present invention shall be determined by the scope of the attached patent application. 8 ----- ^ ---- Γ--Γ- ------ Order ------ |! Thread ^ (I read the precautions on the back, i. Write this page) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperatives, Paper Size Applicable ® National Standard (CNS) A4 specification (210 X 297 male «>