^ 4 4 0 9 2 2 A7 __5487twf,doc/Q0 8 B7 五、發明説明（i ) 本發明是有關於一種薄膜電晶體液晶顯示器（丁卩丁-LCD，Thin Film Transistor - Liquid Crystal Display)光罩 製程’且特別是有關於一種於第二道光罩製程形成源極與 汲極時使用具有粗細不等圖案之光罩，以形成不同厚薄，程 度的光阻層之薄膜電晶體液晶顯示器光罩製程。 薄膜電晶體液晶顯示器主要由薄膜電晶體元件和液 晶顯示元件構成，其中薄膜電晶體元件是由多個薄膜電晶 體組成，而以矩陣的方式排列，且每個薄膜電晶體都有一 畫素電極(pixel electrode)。上述之薄膜電晶體係由在—絕 緣的基材上形成閘極、通道層、源極與汲極堆疊而成，而 薄膜電晶體係用來作爲液晶顯示單元的開關元件。 請參照第1A圖至第1E圖，其所繪示的是習知薄膜 電晶體液晶顯示器之製程步驟示意圖，每一圖所表示的是 經過每一次微影蝕刻步驟後的實體，即每越過一圖代表使 用一道光罩製程，亦即，一次的光阻塗布、曝光、蝕刻、 以及去除光阻。 首先，請參照第1A圖，於絕緣基材102上依序以濺 鑛法鍍上第一鈦金屬層120、第一鋁金屬層122、以及第 二鈦金屬層124，藉由第一道光罩製程，蝕刻定義出一金 屬閘極104與一驅動電路118。接著，以電漿加強式化學 氣相沉積法（PECVD)沉積一氮化砂層（SiNx)106，覆蓋住金 屬閘極104與驅動電路118，並於介電質層106上，同樣 的以電漿加強式化學氣相沉積痒沉積一非晶矽層（a-Si:H)108，以及沉積摻N型雜質的矽層(n+-Si)110。藉由 ______3 本紙張尺度適财酬緖準（CNS ) A4W ( 210X297公釐) (請先閲讀背面之注意事項再填寫本頁) 訂 經濟部智慧財產局.8工消費合作社印製 440922 A7 5487twf.doc/008 B7 五、發明説明（ 第二道光罩製程，形成一島狀結構於前述金屬閘極區域之 上。 其次，請參照第1C圖，鍍上第三鈦金屬層126、第 二鋁金屬層128、以及第四鈦金屬層130,或第126, 1.28 與130層只用單一金屬鉻（Cr)層，並藉由第三道光罩製程， 蝕刻定義出源極與汲極線路112。接著，請參照第1D圖 沉積一介電質保護層114於整個元件上，藉由第四道光罩 製程與電漿蝕刻法於驅動電路118上蝕刻定義一開口區 132以作爲視訊電路面板之銲墊。 最後，請參照第1E圖，濺鍍一層銦化錫116於介電 質保護層114上，並藉由第五道光罩製程形成畫素電極。 整個製程可以摘要如下： 第1A圖使用第一道光罩製程，形成金屬閘極104與 驅動電路118。 第1B圖使用第二道光罩製程，於金屬閘極104區域 上形成通道非晶矽層108與非晶矽層110,作爲形成源極 與汲極之前置基礎。 第1C圖使用第三道光罩製程，蝕刻源極/汲極金屬層 112、非晶矽層110與通道非晶矽層108而形成一源極與 一汲極。 第1D圖使用第四道光罩製程，蝕刻出視訊電路面板。 第1E圖使用第五道光罩製程，製造出畫素電極116。 由於每一道光罩製程皆須經由去水烘烤、塗底、上 光阻、軟烤、曝光、曝光後烘烤、顯影、硬烤以及蝕刻等 4 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 訂 經濟部智慧財產局員工消費合作社印製 440922 A7 5487twf.doc/008 B7 五、發明説明（乃） 步驟，每增加一光罩製程，即增加許多成本。而且每經由 上述步驟，量產之良率亦會降低。 (請先閱讀背面之注意事項再填寫本頁) 因此本發明的主要目的就是在提供一種四道薄膜電 晶體液晶顯示器之光罩製程，較上述習知技藝改進之處， .是利用在第二道光罩（原來傳統的第三道光罩）上，源極/汲 極線路與通道線路圖案粗細之不同，即，源極/汲極線路 的尺寸大於通道線路的尺寸，而在黃光製程時，經由曝光 能量與顯影時間的控制，使源極/汲極線路能完全顯影出， 而通道線路部份顯影，即，完全去除源極/汲極線路處之 光阻層而於通道線路處留下較薄層之光阻，接著，利用後 續鈾刻製程之控制，蝕刻出所需的源極/汲極線路與通道 線路。 此處所謂粗與細，是如此定義的：請參照第3A圖至 第3D圖所示之通道寬度a與通道長度b，若b對a的比 値b/a大於1.5，則稱此通道夠細，而能在曝光與顯影製程 步驟後留下一薄層光阻層於通道上。 經濟部智慧財產局員工消費合作社印製 本發明使用四道光罩，除了以本製程第2道光罩製 程取代習知製程之第2道與第3道光罩製程之外，其餘製 程皆與習知技藝相同。 爲讓本發明之上述目的、特徵、和優點能更明顯易 懂，下文特舉一較佳實施例，並配合所附圖式，作詳細說 明如下： 圖式之簡單說明： . 第1A圖至第1E圖是習知技藝之製造流程剖面圖 5 本紙張尺度適用中國國家標準（CNS ) A4规格（210 X M7公釐） 經濟部智慧財產局員工消費合作社印製 〃 440 92 2 A7 5487twf,doc/008 B7 五、發明説明（4) 第2A圖至第2F圖是顯示根據本發明較佳實施例四 道薄膜電晶體液晶顯示器光罩製程之第2道製造流程剖面 圖。 第3A圖至第3D圖是顯示根據本發明較佳實施例四 道薄膜電晶體液晶顯示器光罩製程之第2道製造流程上視 圖。 圖式之標記說明： 102、202 :絕緣基材 104、204 :金屬閘極 106、206 :介電質層 108、208、316 :通道非晶矽層 110、210 :非晶矽層 112、212、314 :源極/汲極金屬層 114 :介電質保護層 116 :銦化錫畫素電極 118 :驅動電路 120 :第一欽金屬層 122 :第一錦金屬層 124 :第二鈦金屬層 126 :第三鈦金屬層 128 :第二鋁金屬層 130 :第四鈦金屬層 132 :開口區 214、310 :源極/汲極線路光阻層 _ (請先聞讀背面之注意事項再填寫本頁)^ 4 4 0 9 2 2 A7 __5487twf, doc / Q0 8 B7 V. Description of the invention (i) The present invention relates to a thin film transistor-liquid crystal display photomask Process, and in particular, it relates to a thin-film transistor liquid crystal display mask process using a photomask with a pattern of varying thicknesses to form a source and a drain in a second photomask process to form photoresist layers of different thicknesses and degrees. . The thin film transistor liquid crystal display is mainly composed of a thin film transistor element and a liquid crystal display element. The thin film transistor element is composed of a plurality of thin film transistors and arranged in a matrix manner. Each thin film transistor has a pixel electrode ( pixel electrode). The above-mentioned thin film transistor system is formed by stacking a gate electrode, a channel layer, a source electrode and a drain electrode on an insulating substrate, and the thin film transistor system is used as a switching element of a liquid crystal display unit. Please refer to FIG. 1A to FIG. 1E, which show the process steps of a conventional thin film liquid crystal display. Each figure shows the entity after each lithographic etching step, that is, every time it passes The figure represents the use of a photomask process, that is, one photoresist coating, exposure, etching, and photoresist removal. First, referring to FIG. 1A, a first titanium metal layer 120, a first aluminum metal layer 122, and a second titanium metal layer 124 are sequentially plated on the insulating substrate 102 by a sputtering method. During the mask process, an metal gate 104 and a driving circuit 118 are defined by etching. Next, a plasma-enhanced chemical vapor deposition (PECVD) method is used to deposit a nitrided sand layer (SiNx) 106 to cover the metal gate 104 and the driving circuit 118, and the same is applied to the dielectric layer 106. The enhanced chemical vapor deposition deposits an amorphous silicon layer (a-Si: H) 108 and a silicon layer (n + -Si) 110 doped with N-type impurities. With ______3 this paper standard (CNS) A4W (210X297 mm) (Please read the precautions on the back before filling this page) Order the Intellectual Property Bureau of the Ministry of Economic Affairs. Printed by 8 Industrial Consumer Cooperative 440922 A7 5487twf .doc / 008 B7 V. Description of the invention (The second mask process forms an island structure on the metal gate area. Second, please refer to Figure 1C, plate the third titanium metal layer 126 and the second aluminum The metal layer 128 and the fourth titanium metal layer 130, or the 126, 1.28, and 130 layers only use a single metal chromium (Cr) layer, and the third photomask process is used to etch to define the source and drain lines 112. Next, referring to FIG. 1D, a dielectric protective layer 114 is deposited on the entire device, and an opening area 132 is defined on the driving circuit 118 by the fourth photomask process and the plasma etching method to be used for soldering of the video circuit panel. Finally, referring to FIG. 1E, a layer of indium tin oxide 116 is sputtered on the dielectric protective layer 114, and a pixel electrode is formed by a fifth photomask process. The entire process can be summarized as follows: A mask process to form metal gates 104 and driving circuit 118. Figure 1B uses a second mask process to form a channel amorphous silicon layer 108 and an amorphous silicon layer 110 on the metal gate 104 area, as a pre-foundation basis for forming the source and drain. Figure 1C uses the third mask process, and the source / drain metal layer 112, the amorphous silicon layer 110, and the channel amorphous silicon layer 108 are etched to form a source and a drain. Figure 1D uses the fourth mask process. The video circuit panel is etched. Figure 1E uses the fifth mask process to make the pixel electrode 116. Since each mask process must be de-watered, coated, photoresisted, soft-baked, exposed, Post-exposure baking, development, hard baking, and etching 4 paper sizes are applicable to Chinese National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling out this page) Order the intellectual property of the Ministry of Economic Affairs Printed by the Bureau ’s Consumer Cooperatives 440922 A7 5487twf.doc / 008 B7 5. Description of the invention (Yes) Each additional mask process adds a lot of cost. And every time the above steps are passed, the yield of mass production will also decrease. (Please read the back (Please fill in this page for the matters needing attention) Therefore, the main purpose of the present invention is to provide a mask process for a four-film thin-film transistor liquid crystal display. Compared with the above-mentioned conventional techniques, it is used in a second mask (the original traditional The third mask), the thickness of the source / drain circuit is different from that of the channel circuit, that is, the size of the source / drain circuit is larger than the size of the channel circuit. In the yellow light process, the exposure energy and development time are used. Control, so that the source / drain lines can be fully developed, while the channel lines are partially developed, that is, the photoresist layer at the source / drain lines is completely removed and a thin layer of photoresist is left at the channel lines. Then, the control of the subsequent uranium etching process is used to etch out the required source / drain lines and channel lines. Here the so-called thickness and thinness are so defined: please refer to the channel width a and channel length b shown in Figures 3A to 3D. If the ratio of b to a 値 b / a is greater than 1.5, the channel is said to be sufficient It is thin and can leave a thin layer of photoresist layer on the channel after the exposure and development process steps. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, the present invention uses four masks, except that the second and third mask processes of the conventional process are replaced by the second mask process of this process. the same. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings to make a detailed description as follows: Brief description of the drawings: FIG. 1A to Figure 1E is a cross-sectional view of the manufacturing process of the conventional technique. 5 This paper size applies to the Chinese National Standard (CNS) A4 (210 X M7 mm). Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 〃 440 92 2 A7 5487twf, doc / 008 B7 V. Description of the invention (4) Figures 2A to 2F are cross-sectional views showing the second manufacturing process of the four-film thin-film transistor liquid crystal display mask manufacturing process according to a preferred embodiment of the present invention. 3A to 3D are top views showing a second manufacturing process of a photomask process for a four-film thin-film transistor liquid crystal display according to a preferred embodiment of the present invention. Description of the drawing symbols: 102, 202: insulating substrates 104, 204: metal gates 106, 206: dielectric layers 108, 208, 316: channel amorphous silicon layers 110, 210: amorphous silicon layers 112, 212 , 314: source / drain metal layer 114: dielectric protection layer 116: indium tin pixel electrode 118: driving circuit 120: first metal layer 122: first brocade metal layer 124: second titanium metal layer 126: the third titanium metal layer 128: the second aluminum metal layer 130: the fourth titanium metal layer 132: the opening area 214, 310: the source / drain circuit photoresist layer (This page)
A7 B7 0 92 5487twf.doc/008 五、發明説明（k) 216、312 :通道線路光阻層 實施例 請參照第2A圖至第2F圖，其繪示本發明之較佳實 施例。首先，如第2A圖所示，絕緣基材202上，例如.爲 砂基底，已形成一金屬閘極204，其材料爲第一駄金屬層、 鋁金屬層、以及第二鈦金屬層。接著，如第2B圖所示， 依序沉積一介電質層206、一通道非晶矽層208、一非晶 矽層210、與一源極/汲極金屬層212。然後，經由第二道 光罩製程，藉由源極/汲極線路與通道線路其圖案於光罩 上粗細程度之不同，即，源極/汲極線路的尺寸大於通道 線路的尺寸，而於曝光時控制曝光能量與顯影時間，形成 厚薄不一的源極/汲極線路光阻層214、310與通道線路光 阻層216、312,如第2C圖所示，源極/汲極線路光阻層214、 310的厚度較通道線路光阻層216、312的厚度爲厚。 其次，以乾式蝕刻法或濕式蝕刻法對源極/汲極金屬 層212進行蝕刻，深度約爲1500-3000埃。請參照第2D 圖，請注意，由通道線路光阻層216、312所覆蓋之部份 源極/汲極金屬層212並未被蝕刻。 緊接著，藉由〇2灰化法，去除部分源極/汲極線路光 阻層214、310與所有通道線路光阻層216、312，結果如 桌2E圖所示。 然後，以乾式蝕刻法，或濕式蝕刻法加上乾式蝕刻 法’對源極/汲極金屬層212、非晶砂層210、與通道非晶 矽層208進行蝕刻，直至暴露出介電質層206。注意，之 本’氏張尺度適用中囤囤家標準（CNS ) A4规格< 2!〇Χ 297公產 (請先閱讀背面之注意事項再填寫本頁) 訂 濟 部 智 慧 財 4. 局 員 工 消 費 合 作 社 印 製 4 40 92 2 A7 5487twf4doc/008 B7 五、發明説明（t) 前覆蓋有通道線路光阻層216、312處則會蝕刻至通道非 晶砂層208。最後，去除光阻，結果如第2F圖所示。 請參照第3A圖至第3D圖，第3A圖爲第2C圖之上 視圖，第3B圖爲第2D圖之上視圖，第3C圖爲第2E.圖 .之上視圖，第3D圖爲第2F圖之上視圖，其中定義有一通 道長度b與一通道寬度a，b對a的比値，即，b/a，必須 大於一特定値，較佳的値是1.5，於曝光製程顯影後方能 於欲作爲通道部份的源極/汲極金屬層上方留下一薄層光 阻層，否則即與習知製程一般，所有定義有圖案處皆無光 阻層覆蓋。 雖然本發明已以一較佳實施例揭露如上，然其並非 用以限定本發明，任何熟習此技藝者，在不脫離本發明之 精神和範圍內，當可作各種之更動與潤飾，因此本發明之 保護範圍當視後附之申請專利範圍所界定者爲準。 (請先閱讀背面之注意事項再填寫本頁)A7 B7 0 92 5487twf.doc / 008 V. Description of the invention (k) 216, 312: Channel line photoresist layer Examples Please refer to Figures 2A to 2F, which show the preferred embodiments of the present invention. First, as shown in FIG. 2A, a metal gate 204 has been formed on the insulating substrate 202, for example, as a sand substrate. The material is a first metal layer, an aluminum metal layer, and a second titanium metal layer. Next, as shown in FIG. 2B, a dielectric layer 206, a channel amorphous silicon layer 208, an amorphous silicon layer 210, and a source / drain metal layer 212 are sequentially deposited. Then, through the second mask process, the thickness of the pattern on the mask is different between the source / drain line and the channel line, that is, the size of the source / drain line is larger than the size of the channel line, and the exposure The exposure energy and the development time are controlled at the time to form source / drain line photoresist layers 214, 310 and channel line photoresist layers 216, 312 of different thicknesses. As shown in FIG. 2C, the source / drain line photoresist The thicknesses of the layers 214 and 310 are thicker than the thickness of the channel line photoresist layers 216 and 312. Next, the source / drain metal layer 212 is etched by dry etching or wet etching to a depth of about 1500-3000 Angstroms. Please refer to FIG. 2D. Please note that a portion of the source / drain metal layer 212 covered by the channel line photoresist layers 216, 312 is not etched. Immediately after, a part of the source / drain line photoresist layers 214 and 310 and all the channel line photoresist layers 216 and 312 were removed by the O 2 ashing method. The results are shown in Table 2E. Then, the source / drain metal layer 212, the amorphous sand layer 210, and the channel amorphous silicon layer 208 are etched by a dry etching method, or a wet etching method and a dry etching method, until the dielectric layer is exposed. 206. Note that the booklet's scale is applicable to the China Hoarding Standard (CNS) A4 specification < 2! 〇 × 297 public property (please read the precautions on the back before filling this page). Ministry of Economic Affairs, Smart Wealth 4. Bureau employee consumption Printed by the cooperative 4 40 92 2 A7 5487twf4doc / 008 B7 V. Description of the invention (t) Where the channel line photoresist layers 216 and 312 are covered before, the channel amorphous sand layer 208 will be etched. Finally, the photoresist is removed, and the result is shown in FIG. 2F. Please refer to FIGS. 3A to 3D, FIG. 3A is a top view of FIG. 2C, FIG. 3B is a top view of FIG. 2D, FIG. 3C is a top view of FIG. 2E. The top view of Figure 2F, which defines a channel length b and a channel width a, b to a ratio 値, that is, b / a must be greater than a specific 値, the preferred 1.5 is 1.5, which can be developed after the exposure process. A thin photoresist layer is left over the source / drain metal layer that is to be used as a channel portion, otherwise it is the same as the conventional manufacturing process, and there is no photoresist layer covering all the defined patterns. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. (Please read the notes on the back before filling this page)
經濟部智慧財產局員工消費合作社印製 8 本紙張尺度適用中國國家標準（CNS ) A4規格（2!0Χ297公釐）Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 8 This paper is sized for the Chinese National Standard (CNS) A4 (2! 0 × 297 mm)