經濟部中央標準局员工消贽合作社印製 436798 五、發明説明（丨） 本發明是有關於一種記億體元件的測試電路，且特別 是有關於一種利用內容可定址式記憶體（CAM, Qontent Addressable Memory)來作爲記憶體元件的測試電路，用以 省卻許多的測試時間。 當積體電路的記憶體密度愈來愈大時，測試與修複所 需的時間很長，相對地，亦使得成本加重。在記憶體之製 程中，以往的做法是將每一個位元都寫入數據，然後再讀 出來。測試機本身有一記憶體以記下寫及讀的數據模式， 再將之一一比較，並找出錯誤的位元。而其減少測試時間 的方法，例如是用多位元(Multibit)的測試模式，同時對4〜8 位元進行測試，可將測試時間減少至約1/4或1/8左右。但 是此種多位元測試的方法卻受於面積的限制，而無法使用 於16位元以上之同時測試。另外，在編號爲0018-9200/89/1000-1184 的 IEEE 雜誌中，Kazutami Arimoto 等人 提到一種有關於線模式測試(Line Mode Test)的方法，對於 記憶體的測試已有相當大的改善，可將測試時間減少至約 1/1000左右。然而，此一方法，僅能在有任何一行位址中 有錯誤位元時才可測得，且無法適當地分辨輸入與輸出的 結果，因此修補的效率較低，並非上述之結果，相對使得 測試時間較長；並且必須多出一個銲墊（Pad)，且測試卡 (Probe Card)的製作與測試機台匹配較不易。 因此本發明的主要目的就是在提供一種能夠大量節省 半導體之測試與修複時間的測試電路，當在作讀與比較數 據時，將整個字元線上之錯誤，可在一個時脈週期內找出 並修複；並且不需要額外的銲墊，只需利用晶片上原本所 3 本紙張尺度適用中國國家標準 ( CNS ) A#兄格（2〗0 X 2V7公碰） ---------裝-------，1Τ------〆 '【 (請先閱讀背面之注意事項再4寫本頁) I* I* 經濟部中央標举扃貞工消费合作社印裝 9 Β 1892twf.d〇c/008 五、發明説明（）） 需的銲墊即可，使得測試時間更短、修補效率高，有效地 改善傳統的記憶體測試方法。 根據本發明的目的，提出一種記憶體元件的測試電 路，至少包括：一字元線；複數個行位址；複數個記憶體 晶胞，各用以儲存一數據，並以字元線與一行位址來控制 記憶體晶胞中的數據之儲存，而得到一儲存數據；複數個 數據線與互補數據線，各用以提供數據以儲存於記憶體晶 胞中；複數個記憶體測試電路，各耦接至一記億體晶胞， 用以接收數據線與互補數據線之數據，然後與儲存數據比 較，得到一匹配訊號的輸出；一測試控制訊號輸入端，用 以啓動記憶體測試電路，以對記憶體晶胞作測試；複數個 栓鎖電路，各經由一電晶體的閘極耦接於匹配訊號，同時 在電晶體的汲極產生一反相位準的輸出，並將反相位準栓 鎖住；以及複數個反相器，各與反相位準耦接，然後輸出 至一比較結果輸岀端並記錄測試結果。因此，本發明提供 '一種能夠大量節省半導體之測試方法，可將整個字元線上 之錯誤位元，在一個時脈週期內找出並記錄，有效地增加 處理效率。 根據本發明的另一目的，提供一種記憶體元件的測試 電路，至少包括：複數個記憶體區塊，每一記憶體區塊均 至少包括有複數個字元線，每一字元線均對應有複數個行 位址；複數個數攄線，各有一第一數據；複數個記憶體晶 胞，各對應於一行位址，並有一儲存數據；複數個記憶體 測試電路，各耦接至一記憶體晶胞，用以將記憶體晶胞的 儲存數據與數據線的第一數據比較，然後得到一匹配訊號 4 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X297^1 ) — (請先閱讀背面之注意事項再填-VT本頁) 一裝- -5 經濟部中央標準局員工消费合作社印製 43ST98 Λ7 1892twf * doc/008 l> 五、發明説明（乃） 的輸出；一測試控制訊號輸入端，用以啓動記憶體測試電 路，以同時對記憶體晶胞作測試；以及一測試記錄埠，用 以記錄記憶體晶胞的匹配訊號。此目的可用以將測試結果 得到的記憶體錯誤訊息記錄下來，以省卻原本每次導通字 元線所需之大量時間週期，更增加效率。 爲讓本發明之上述目的、特徵、和優點能更明顯易懂， 下文特舉一較佳實施例，並配合所附圖式，作詳細說明如 下： <；. 圖式之簡單說明： 第1圖繪示依照本發明一較佳實施例的一種記憶體元 件測試電路圖。 第2圖繪示依照本發明上述記憶體元件測試電路方塊 圖。 第3圖繪示依照本發明記憶體元件測試電路時序圖。 實施例 在一般的記憶體中，通常包括有一些記憶體區塊，每 一記憶體區塊中會以一些字元線來控制記憶體晶胞的存 取。以一般的記憶體爲例，至少包括有字元線、行位址、 記憶體晶胞與感測放大器。在本發明記憶體元件測試電路 中，更需以部份測試電路來作爲記憶體的測試。 請參照第1圖，其繪示依照本發明一較佳實施例的一 撞記憶體元件測試電路圖。如第1圖所示，記憶體元件測 試電路中的每一位元例如是一記憶體晶胞10,記憶體晶胞 10以字元線WLj(7=0,1，2...，爲一記憶體區塊中各字元線的 序號）與行位址COLiU=〇,l,2...，爲各記憶體晶胞10的序號) 5 本紙张尺度適用中國國家標準（CNS ) 規格（210X 297公犮） ~ > ^^^^1 ^^^^1 -: 1— ^ϋί f. n^l T- (請先間讀背面之注意事項再填寫本頁) -訂 經濟部中决標準局負工消費合作社印製 4-367 98 Λ7 1892twf,d〇c/008 Η? 五、發明説明（仏） 來控制數據之儲存。行位址COL/‘的動作係由數據線 DU/=o, 1,2…）與互補數據線ΰΓ7上的數據經由電晶體1 〇〇 與電.晶體101來控制。感測放大器12係用以將記憶體晶胞 10中的電壓與感測放大器12中的參考電壓做比較，以決 定記憶體晶胞10中所儲存的數據爲“Γ或“〇”。記憶體測試 電路Η以一測試控制訊號TESTen來控制，並同時根據數 據線DLi、互補數攄線"5L7與行位址COL/來比對測試，然 後產生一匹配訊號^^17(/=0，1，2...)的輸出，若是匹配訊號 1ΪΧΪ7的輸出爲低位準，表示記憶體晶胞10爲正常，若是 匹配訊號MAT/的輸出爲高位準，表示記憶體晶胞10爲錯 誤。 當記憶體晶胞10在作測試時，其步驟如下： 1. 首先將測試控制訊號TESTen致能(位於高位準），並 將預置電位百I由低位準提昇至高位準。原本當預置電位 i在低位準時，電晶體102位於導通狀態，所以在比較 結果輸出端Match/會產生一低位準的輸出。電晶體102爲 一預置電位控制裝置，例如是以一 PMOS所組成。在此， 同時將預置電位i提昇至高位準，電晶體102關閉，便 可使比較結果輸出端Match/的輸出開始由記憶體測試電 路14來控制，而不影響測試結果的記錄。當比較結果輸出 端Match?的輸出維持在低位準時，代表測試結果正常；若 維持在高位準時，代表測試結果不正常。 2. 將每一行位址COL/·置於導通的狀態，敢根據數據 線DLi與互補數據線Τ5Γ7上的數據，經由行位址COLi寫入 每一個位元，例如是寫入記憶體晶胞10中，形成一儲存數 6 -- (#先閱讀背面之注意事項再填寫本頁) ，-° 么·' 本紙张尺度適用中國國家標準（CNS ) Ad规格（210X297公垃) A7 B7Printed by the Staff of the Central Bureau of Standards of the Ministry of Economic Affairs, printed by the cooperative 436798 V. Description of the invention (丨) The present invention relates to a test circuit for recording billion-body components, and in particular, to a content-addressable memory (CAM, Qontent) Addressable Memory) is used as a test circuit for memory components to save a lot of test time. When the memory density of integrated circuits is getting larger, the time required for testing and repairing is very long, and relatively, it also increases the cost. In the memory process, the previous method is to write every bit into the data and then read it out. The test machine has a memory to write down and read the data patterns, then compare them one by one, and find out the wrong bit. The method for reducing the test time, for example, is to use a multi-bit test mode and test 4 to 8 bits at the same time, which can reduce the test time to about 1/4 or 1/8. However, this multi-bit test method is limited by area and cannot be used for simultaneous testing of more than 16 bits. In addition, in the IEEE magazine numbered 0018-9200 / 89 / 1000-1184, Kazutami Arimoto et al. Mentioned a method related to the Line Mode Test, which has improved the memory test considerably. , Can reduce the test time to about 1/1000. However, this method can only be measured when there is an error bit in any row of the address, and the results of input and output cannot be distinguished properly. Therefore, the efficiency of patching is low, which is not the above-mentioned result. The test time is long; and an additional pad must be provided, and the production of the test card and the test machine are not easy to match. Therefore, the main object of the present invention is to provide a test circuit capable of saving a large amount of time for testing and repairing semiconductors. When reading and comparing data, errors on the entire word line can be found and processed in a clock cycle. Repair; and no additional pads are required, just use the original paper on the wafer. 3 paper sizes are applicable to Chinese National Standards (CNS) A # 哥格 （2〗 0 X 2V7 male touch) --------- install -------, 1Τ ------ 〆 '[(Please read the precautions on the back before writing this page 4) I * I * The Ministry of Economic Affairs publishes the print of 扃 Chung Kung Consumer Cooperative 9 9 Β 1892twf.d〇c / 008 V. Description of the invention ()) The required soldering pad can be used, which makes the test time shorter, the repair efficiency is high, and effectively improves the traditional memory test method. According to the purpose of the present invention, a test circuit for a memory element is provided, which includes at least: a word line; a plurality of row addresses; a plurality of memory cells, each for storing a data, and a word line and a line Address to control the storage of data in the memory cell, to obtain a stored data; a plurality of data lines and complementary data lines, each for providing data to be stored in the memory cell; a plurality of memory test circuits, Each is coupled to a billion unit cell for receiving data from the data line and the complementary data line, and then comparing it with the stored data to obtain a matching signal output; a test control signal input terminal for activating the memory test circuit To test the memory cell; multiple latch circuits, each coupled to the matching signal via the gate of a transistor, produce an out-of-phase quasi-output at the drain of the transistor, and invert The level pins are locked; and a plurality of inverters are each quasi-coupled to the inverse phase, and then output to a comparison result input terminal and record the test results. Therefore, the present invention provides a test method capable of saving a large amount of semiconductors, which can find and record error bits on the entire word line within a clock cycle, effectively increasing the processing efficiency. According to another object of the present invention, a test circuit for a memory element is provided, which includes at least a plurality of memory blocks, and each memory block includes at least a plurality of character lines, and each character line corresponds to There are a plurality of row addresses; a plurality of stub lines each having a first data; a plurality of memory cell cells each corresponding to a row address and a stored data; a plurality of memory test circuits each coupled to a The memory cell is used to compare the stored data of the memory cell with the first data of the data line, and then obtain a matching signal. 4 The paper size applies the Chinese National Standard (CNS) Λ4 specification (210X297 ^ 1) — (Please Read the precautions on the back before filling -VT page) One Pack--5 Printed by the STCC Employee Consumer Cooperatives 43ST98 Λ7 1892twf * doc / 008 l > V. Output of the invention description (Y); a test control The signal input terminal is used to start the memory test circuit to test the memory cell at the same time; and a test recording port is used to record the matching signal of the memory cell. This purpose can be used to record the memory error message obtained from the test results, so as to avoid the large time period that is required to turn on the character line each time, and increase the efficiency. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is described below in detail with the accompanying drawings as follows: <;. A brief description of the drawings: FIG. 1 is a circuit diagram of a memory device test according to a preferred embodiment of the present invention. FIG. 2 is a block diagram of a test circuit for a memory device according to the present invention. FIG. 3 is a timing diagram of a memory device test circuit according to the present invention. Example In general memory, there are usually some memory blocks, and each memory block will use some word lines to control the access of the memory cell. Taking a general memory as an example, it includes at least a word line, a row address, a memory cell, and a sense amplifier. In the memory element test circuit of the present invention, it is necessary to use a part of the test circuit as a memory test. Please refer to FIG. 1, which illustrates a test circuit diagram of a crash memory device according to a preferred embodiment of the present invention. As shown in FIG. 1, each bit in the memory element test circuit is, for example, a memory cell 10, and the memory cell 10 is represented by a word line WLj (7 = 0,1,2, ...) as The serial number of each character line in a memory block) and the row address COLiU = 0, 1, 2, ..., which is the serial number of each memory cell 10) 5 This paper size applies the Chinese National Standard (CNS) specifications (210X 297) 犮 > ^^^^ 1 ^^^^ 1-: 1— ^ ϋί f. N ^ l T- (Please read the precautions on the back before filling in this page)-Order the Ministry of Economy Printed by the China Workmanship Standards Bureau ’s Consumer Cooperatives 4-367 98 Λ7 1892twf, doc / 008 Η? 5. Description of the Invention (仏) To control the storage of data. The action of the row address COL / ′ is controlled by the data on the data line DU / = o, 1,2, ...) and the complementary data line ΰΓ7 via the transistor 100 and the transistor 101. The sense amplifier 12 is used to compare the voltage in the memory cell 10 with a reference voltage in the sense amplifier 12 to determine whether the data stored in the memory cell 10 is "Γ" or "0". The memory The test circuit is controlled by a test control signal TESTen, and the test is compared according to the data line DLi, the complementary data line "5L7" and the row address COL /, and then a matching signal is generated ^^ 17 (/ = 0, 1, 2 ...), if the output of the matching signal 1 匹配 × Ϊ7 is low, it means that the memory cell 10 is normal, and if the output of the matching signal MAT / is high, it means that the memory cell 10 is wrong. When the memory cell 10 is being tested, the steps are as follows: 1. First, enable the test control signal TESTen (located at the high level), and raise the preset potential 100 from the low level to the high level. Originally, the preset potential When i is at a low level, the transistor 102 is in a conducting state, so Match / at the comparison result output terminal will produce a low-level output. The transistor 102 is a preset potential control device, for example, it is composed of a PMOS. Here, At the same time raise the preset potential i At the highest level, the transistor 102 is turned off, so that the output of Match / at the comparison result output terminal can be controlled by the memory test circuit 14 without affecting the recording of the test result. When the output of Match? At the comparison result output terminal is maintained at a low level Punctuality means that the test result is normal; if it is maintained at a high level, it means that the test result is abnormal. 2. Put the address COL / · of each row in a conducting state, and dare to pass the data on the data line DLi and the complementary data line T5Γ7 via The row address COLi is written into each bit, for example, it is written into the memory cell 10 to form a storage number 6-(#Read the precautions on the back before filling in this page),-°? · This paper Standards are applicable to Chinese National Standard (CNS) Ad specifications (210X297). A7 B7
436798 18 92twf1.doc/002 第87116702號說明書修正頁 89/10/4 五、發明說明（f) ’ 據。 3. 當數據寫入於記憶體晶胞10之後，將所有的行位址 COU關閉，使得記憶體測試電路14可以比對記憶體晶胞 10的儲存數據與數據線DL/或是互補數據線"5E7上之數據 是否匹配。在此所使用之記憶體測試電路14例如是由圖中 所示的4個NMOS所組成。 4. 依序選取一字元線WLj‘，並將字元線WLy置於高位 準，對整條字元線上的每一記憶體晶胞10作測試。同時並 將原本寫入記憶體晶胞10之數據再輸入至數據線DL/與互 補數據線Έΰ上。 5. 記憶體測試電路Μ比對記憶體晶胞1〇之儲存數據 與數據線DL/或是互補數據線ΰυ上之數據，然後將比對 結果產生一匹配訊號ΜΑΊ7的輸出。其比對方法如下說明： (1)當數據線DL/之數據爲1，亦即互補數據線"5Γ7上 之數據0時，此時因爲記憶體晶胞10之儲存數據爲1，且 測試控制訊號TESTEN位於高位準，使得閘極輸入測試控制 訊號TESTen的測試用電晶體導通，此時，測試用電晶體的 汲極爲低準位，並且在電晶體104的汲極也呈現低準位。 由於，電晶體104的閘極連接至記憶體晶胞10,電晶體106 的閘極連接至數據線D1/，因爲記憶體晶胞10與數據線DL/ 之數據皆爲1(即爲高準位），所以，電晶體104與電晶體106 均位於導通狀態。因此，匹配訊號MAT7的輸出爲低位準 (NMOS位於導通狀態的源極電位）。若是記憶體晶胞10之 儲存數據有誤，則電晶體104無法位於導通狀態，因此匹 7 ----------- -裝-----1!—訂·—-------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準<CNS)A4規格（210 X 297公釐） 4 3 67 9 8 1892twfl.doc/002 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（‘） 配訊號MAT/的輸出爲高位準，表示此一記憶體晶胞10不 正常。 (2)當數據線DL/之數據爲0，亦即互補數據線ΰΓ7上 之數據1時，此時因爲記憶體晶胞10之儲存數據爲〇，且 測試控制訊號TESTw亦位於高位準，使得閘極輸入測試控 制訊號TESTen的測試用電晶體導通，此時，測試用電晶體 的汲極爲低準位，並且在電晶體108的汲極也呈現低準位。 由於，電晶體104的閘極連接至電晶體101的汲極，電晶體 106的閘極連接至數據線"5E7，因爲電晶體101的汲極與數 據線H7之數據皆爲1(即爲高準位），所以，電晶體108與 電晶體110均位於導通狀態。因此，匹配訊號¥Χϊ7的輸出 爲低位準。若是記憶體晶胞10之儲存數據有誤，則電晶體 108無法位於導通狀態，因此使得匹配訊號¥Χΐ7的輸出爲 高位準，表示此一記憶體晶胞10不正常。 6.匹配訊號MAT/輸出至電晶體112的閘極，例如是一 NMOS電晶體的閘極，並在電晶體112的汲極產生一反相位 準的輸出。例如：當匹配訊號MAT7的輸出爲低位準，則電 晶體112關閉，而在電晶體112的汲極產生一高位準，並經 由栓鎖電路16將此位準維持住，所以經由反相器114之 後，在比較結果輸出端Match/的輸出爲低位準；若是匹配 訊號MAT/的輸出爲高位準，則電晶體112導通，而在電晶 體112的汲極產生一低位準，並經由栓鎖電路16將此位準 維持住，所以在比較結果輸出端Match/’的輸出爲高位準。 所以當比較結果輸出端Match/的輸出爲低位準時，代表記 8 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐〉 -----------i---裝----l·! — 訂·！-線 (請先閱讀背面之注意事項再填寫本頁) . 4 3 6 7 9 〇 1892twfl.doc/〇〇2 經濟部智慧財產局員工消費合作社印製 五、發明說明（q) 億體晶胞10爲正常；若爲高位準時，代表記億體晶胞10 有錯誤。匹配訊號1^ΧΪ7經由電晶體112、栓鎖電路16與 反相器114，然後由比較結果輸出端Match/輸出，可避免 影響記憶體經過測試後的記錄結果。 以此種方法，可以一次將整個字元線的比對結果讀出， 便可得知那些位元有錯誤，而不需要對一個個位元作比 較，然後再作修復。並重複上述步驟，直到所有字元線WL/ 上之各位元的錯誤均讀出爲止。因此，若是在一個字元線 上有128個行位址，則測試時間爲原來的1/128 ;若是在一 個字元線上有1024個行位址，則測試時間爲原來的 1/1024 。 實際上 > 在作記憶體元件測試時，包括有許多的記憶體 區塊20。請參照第2圖，其繪示依照本發明上述記憶體元 件測試電路方塊圖。所以在測試開始時，當一記憶體區塊 20的測試控制訊號TESTe^U：=〇，1，2…，爲記憶體區塊的序 號)致能後，產生下列之測試步驟： 1. 在每一記憶體區塊20中選取一個字元線WU/，每一 字元線WL_/均有一對應之輸出/輸入控制訊號10)，此時將 所有之行位址COL/置於導通的狀態，並將數據寫入每一個 記憶體晶胞10中。 2. 當數據寫入於記憶體晶胞10之後，將所有的行位址 COL/關閉，然後開始測試。如上所述，每一記憶體晶胞10 均有一相對之匹配訊號¥^的輸出。直到比較結果輸出端 將此一記憶體區塊20之所有錯誤位元的記錄輸出 9 ------------------ (請先閱讀背面之注意事項再填寫本頁) 言 r 矣 良 ^紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） A7 A7 經濟部智慧財產局員工消費合作社印製 / 0 02 β7 I發明說明（客） 舄止。並將結果經由輸出緩衝器22輸出至測試記錄埠24 趣記錄。 3.繼續對每一記憶體區20選取下一個字元線WU’直 到記憶體的測試都結束爲止，然後再對整個字元線作溶絲 修復(Fuse Repair)的工作。 其中，當記憶體區塊20作正常讀寫時’多工器26選擇 將輸出/輸入控制訊號i〇y的結果輸出至輸出緩衝器22 ;當 記憶體區塊20開始作測試時，多工器26選擇將比較結果 輸出端Match/·的結果輸出至輸出緩衝器22 ° 在傳統的方法中，正常的讀寫，係在某一記憶體區塊中 一次對一字元線作存取，然本發明係同時對所有的記憶體 區塊中之某一字元線作讀寫’因此省卻了分別對個記憶體 區塊之字元線之讀寫時間。例如，傳統方法之讀寫是在η 個記憶體區塊中只選中某一個記憶體區塊之字元線做讀 寫，則需對η個記憶體區塊之字元線逐一讀寫，共需做η 次’而此法則只需做一次即可。 如上所述之測試步驟，在第一個時脈週期中，便可將每 一個字元線的數據均寫入以作比對；並且，在錯誤的訊息 讀出之後，不需要再重新啓動每一個字元線wl_/，只要將 每—記憶體區塊20中的字元線WLy之測試結果輸出至測試 記錄埠24以記錄下來即可。因此，可以省卻原本每次導通 字元線所需之測試時間週期，因爲在更換每個記憶體區塊 20中之字元線的讀取時，只要從比較結果輸出端1^7更 換即可’如同在一般記憶體之頁位址模式中只需更換行位 10 本紙張尺度適用申國國家標準（CNS)A4規格（210 X 297公釐） nil —--------i I — l· I I I 訂----l I — (諳先閱讀背面之注意事項再填窝本頁) A7 4.3 6 7 9 〇 1892twfl.doc/002 五、發明說明（1 ) 址即可一樣。另外，由於每個錯誤之位元都已記錄下來， 所以也不需要再透過一個個行位址去讀取出。 綜上所述，在本發明中，若是一個列位址上可以啓動 1024個位元，那麼便可將測試週期節省至1/1024 ;若是每 一個列位址選通(Row Address Strobe，RAS)的時間週期爲60 奈秒(nS)，一般而言，比較結果輸出端iatch/的讀出大約 是在10nS以下，所以每一個記憶體區塊之比較結果輸出端 Match/的讀出大約可以將讀取時間節省到1/6左右。每個 時間週期可省至1/6，且每個測試週期可省至1/1024，所以 整個測試時間可大約節省至（1/6)χ(1/1024)=1/6144左右。對 於產品的產率有很大的助益。 在上述測試過程中，若是需要用到較爲繁複的測試模式 時’只需將測試控制訊號TESTew接地，即可回復到正常的 記憶體晶片作業。 請參照第3圖，其繪示依照本發明記憶體元件測試電路 時序圖。在測試開始時，將記憶體測試控制訊號 TESTEfu(i：=〇，i,2...，爲記憶體區塊的序號)致能，由低位準上 升至高位準；接著，在列位址Row ADD送出之後，當低致 能列位址選通訊號RAS降至低位準時（例如約60奈秒左 右）’將各記憶體區塊之字元線導通，此時數據線DLy·皆已 將數據載入至記憶體中；當低致能寫入訊號降至低位 準時’開始將數據寫入記憶體晶胞10中；最後，在比較結 果之後，依序將記憶體區塊位址BAvKkO，l，2...，爲記憶體 區塊的序號)輸出之同時(例如均爲1〇奈秒），並將測試結果 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 χ 297公釐） ---!l!J-----I I l·----11---1-----線 (請先閱讀背面之注$項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 1 A3S1BB a7 1892twfl-doc/0〇2 _ Β/ 五、發明說明（/0) OPjt(ir=Of 1,2... *爲記憶體區塊的序號）輸出。 因此’本發明的特徵之一是在於提供一種能夠大量節省 半導體之測試與修複時間的方法，可將整個字元線上之錯 誤位元，在一個時脈週期內找出並修複，有效地增加處理 效率。 本發明的特徵之二是將測試結果得到的記憶體錯誤訊 息記錄下來’以省卻原本每次導通字元線所需之大量時間 週期，更增加效率。 雖然本發明已以一較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍內’當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）436798 18 92twf1.doc / 002 No. 87116702 amendment page 89/10/4 V. Description of the invention (f) ′. 3. After the data is written into the memory cell 10, all row address COUs are closed, so that the memory test circuit 14 can compare the stored data of the memory cell 10 with the data line DL / or the complementary data line. " Whether the data on 5E7 match. The memory test circuit 14 used here is composed of, for example, four NMOS as shown in the figure. 4. Select a character line WLj ′ in sequence, and set the character line WLy to a high level, and test each memory cell 10 on the entire character line. At the same time, the data originally written in the memory cell 10 is input to the data line DL / and the complementary data line Έΰ. 5. The memory test circuit M compares the stored data of the memory cell 10 with the data on the data line DL / or the complementary data line ΰυ, and then compares the result to produce an output that matches the signal ΜAΊ7. The comparison method is described as follows: (1) When the data of the data line DL / is 1, that is, the data of the complementary data line " 5Γ7, the data is 0, because the stored data of the memory cell 10 is 1, and the test The control signal TESTEN is at a high level, so that the test transistor of the gate input test control signal TESTen is turned on. At this time, the drain of the test transistor is extremely low, and the drain of the transistor 104 is also low. Because the gate of the transistor 104 is connected to the memory cell 10 and the gate of the transistor 106 is connected to the data line D1 /, because the data of the memory cell 10 and the data line DL / are both 1 (that is, Micro Motion) Bit), so the transistor 104 and the transistor 106 are both in a conducting state. Therefore, the output of the matching signal MAT7 is at a low level (the source potential of the NMOS in the on state). If the stored data of the memory cell 10 is wrong, the transistor 104 cannot be in the on state, so the 7 is matched. ----- Line (Please read the notes on the back before filling this page) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs Employee Cooperatives This paper is printed in accordance with Chinese National Standards < CNS) A4 (210 X 297 mm) 4 3 67 9 8 1892twfl.doc / 002 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (') The output of the signal MAT / is at a high level, indicating that this memory cell 10 is abnormal. (2) When the data of the data line DL / is 0, that is, the data 1 on the complementary data line ΰΓ7, because the stored data of the memory cell 10 is 0, and the test control signal TESTw is also at a high level, so that The test transistor of the gate input test control signal TESTen is turned on. At this time, the drain of the test transistor is at a very low level, and the drain of the transistor 108 is also at a low level. Because the gate of transistor 104 is connected to the drain of transistor 101 and the gate of transistor 106 is connected to the data line " 5E7, because the data of the drain of transistor 101 and data line H7 are both 1 (that is, High level), so transistor 108 and transistor 110 are both in a conducting state. Therefore, the output of the matching signal ¥ × ϊ7 is at a low level. If the stored data of the memory cell 10 is incorrect, the transistor 108 cannot be in the on state, so that the output of the matching signal ¥ × 7 is high, indicating that the memory cell 10 is abnormal. 6. The matching signal MAT / is output to the gate of transistor 112, such as the gate of an NMOS transistor, and produces an out-of-phase output at the drain of transistor 112. For example, when the output of the matching signal MAT7 is at a low level, the transistor 112 is turned off, and a high level is generated at the drain of the transistor 112, and this level is maintained by the latch circuit 16, so the inverter 114 is used. After that, the output of Match / at the output of the comparison result is at a low level; if the output of the matching signal MAT / is at a high level, the transistor 112 is turned on, and a low level is generated at the drain of the transistor 112 and passed through the latch circuit 16 maintains this level, so the output of Match / 'at the comparison result output is high. Therefore, when the output of Match / at the output of the comparison result is at a low level, it means that the 8 paper sizes are applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ----------- i-- -Install ---- l ·! — Order ·! -Line (please read the precautions on the back before filling in this page). 4 3 6 7 9 〇1892twfl.doc / 〇〇2 Employee Consumer Cooperatives, Intellectual Property Bureau, Ministry of Economic Affairs Printed 5. Description of the invention (q) The billion cell unit 10 is normal; if it is at a high level, it means that the billion cell unit 10 has an error. The matching signal 1 ^ χΪ7 passes through the transistor 112, the latch circuit 16 and the inverter. 114, and then match / output from the comparison result output terminal to avoid affecting the recorded results of the memory after the test. In this way, the comparison result of the entire word line can be read out at one time, and those bits can be known There is an error, and there is no need to compare the individual bits and then repair them. Repeat the above steps until all the errors on the word line WL / are read out. Therefore, if it is on a character line With 128 row addresses, the test time is 1/128 of the original; if it is on a character line There are 1024 row addresses on it, so the test time is 1/1024 of the original. Actually, when testing the memory components, a lot of memory blocks 20 are included. Please refer to FIG. The block diagram of the above-mentioned memory element test circuit of the present invention. Therefore, at the start of the test, when the test control signal TESTe ^ U of a memory block 20: = 0, 1, 2, ... is the serial number of the memory block) After that, the following test steps are generated: 1. Select a character line WU / in each memory block 20, and each character line WL_ / has a corresponding output / input control signal 10). The row address COL / is placed in a conducting state, and data is written into each memory cell 10. 2. After the data is written to the memory cell 10, turn off all the row addresses COL /, and then start the test. As described above, each memory cell 10 has an output corresponding to the matching signal ¥ ^. Until the comparison result output end outputs a record of all error bits of this memory block 20 ------------------ (Please read the precautions on the back before filling (This page) rr 矣 良 ^ Paper size applies to Chinese National Standard (CNS) A4 (210 X 297 mm) A7 A7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs / 0 02 β7 I Invention Description (Guest) . The result is output to the test record port 24 through the output buffer 22 to the interesting record. 3. Continue selecting the next character line WU 'for each memory area 20 until the memory test is completed, and then perform fuse repair on the entire character line. Among them, when the memory block 20 is used for normal reading and writing, the multiplexer 26 chooses to output the result of the output / input control signal i0y to the output buffer 22; when the memory block 20 starts testing, the multiplexing The device 26 chooses to output the result of the comparison result output Match / · to the output buffer 22 ° In the traditional method, normal reading and writing is to access one word line at a time in a certain memory block. However, the present invention reads and writes a certain character line in all the memory blocks at the same time, so the read and write time of the character lines of each memory block is saved. For example, in the traditional method of reading and writing, only the character lines of a certain memory block are selected for reading and writing in the n memory blocks, the character lines of the n memory blocks need to be read and written one by one. It needs to be done a total of η 'and this rule only needs to be done once. As described above, in the first clock cycle, the data of each word line can be written for comparison; and, after the wrong message is read, it is not necessary to restart each For a character line wl_ /, it is only required to output the test result of the character line WLy in each memory block 20 to the test recording port 24 for recording. Therefore, the test time period required to turn on the character line every time can be omitted, because when the reading of the character line in each memory block 20 is replaced, it only needs to be replaced from the comparison result output terminal 1 ^ 7. 'As in the general memory page address mode, only the line position needs to be changed. 10 This paper size applies to the national standard (CNS) A4 (210 X 297 mm) nil —-------- i I — L · III Order ——l I — (Read the precautions on the back before filling in this page) A7 4.3 6 7 9 〇1892twfl.doc / 002 5. The invention description (1) The address can be the same. In addition, since each error bit has been recorded, there is no need to read it out through the row address again. In summary, in the present invention, if 1024 bits can be activated on a column address, the test period can be saved to 1/1024; if it is a row address strobe (RAS) The time period is 60 nanoseconds (nS). Generally speaking, the comparison result output terminal iatch / is read below 10nS, so the comparison result output terminal Match / of each memory block can read about Reading time is saved to about 1/6. Each time period can be saved to 1/6, and each test period can be saved to 1/1024, so the entire test time can be saved to (1/6) χ (1/1024) = 1/6144. It is very helpful for product yield. In the above-mentioned test process, if a more complicated test mode is needed, ‘just ground the test control signal TESTew, and then you can resume normal memory chip operation. Please refer to FIG. 3, which shows a timing diagram of a memory device test circuit according to the present invention. At the beginning of the test, the memory test control signal TESTEfu (i: = 0, i, 2 ..., is the serial number of the memory block) is enabled, and rises from a low level to a high level; then, at the column address After the Row ADD is sent, when the low-enabled column address selection signal RAS drops to a low level (for example, about 60 nanoseconds), the character lines of each memory block are turned on. At this time, the data lines DLy The data is loaded into the memory; when the low-enable writing signal drops to a low level, the data is written into the memory cell 10; finally, after comparing the results, the memory block addresses BAvKkO are sequentially written, l, 2 ..., the serial numbers of the memory blocks) are output simultaneously (for example, both are 10 nanoseconds), and the test results are based on the Chinese National Standard (CNS) A4 specification (21〇χ 297 public) Li) ---! L! J ----- II l · ---- 11 --- 1 ----- line (please read the note on the back before filling this page) Intellectual Property of the Ministry of Economic Affairs Printed by the Bureau's Consumer Cooperative 1 A3S1BB a7 1892twfl-doc / 0〇2 _ B / V. Description of the Invention (/ 0) OPjt (ir = Of 1,2 ... * is the serial number of the memory block) is output. Therefore, one of the features of the present invention is to provide a method that can greatly save the test and repair time of semiconductors. The error bits on the entire word line can be found and repaired in a clock cycle, effectively increasing the processing. effectiveness. The second feature of the present invention is to record the memory error information obtained from the test result 'in order to save a large number of time periods that would otherwise be required to turn on the character line each time, and increase efficiency. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. (Please read the precautions on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper is in accordance with China National Standard (CNS) A4 (210 X 297 mm)