A7 B7 436 7 9 4 3974TWFltwfl . DOC/002 五、發明說明（丨） 本發明是有關於一種非揮發性(n.on-volatile)半導體記憶 裝置，且特別是有關於一種快閃記憶體(flash memory)之感 測技術。 ‘ 在傳統半導體記憶裝置技術中，要將資料寫入到一可 抹除且可編碼唯§買記憶體（erasable programmable ROM，簡 稱EPROM)中時’電荷係經由通道絕緣薄膜(tunnel insulating film)傳到浮置閘（floating gate)，藉此假設該記憶體處於第 一狀態，例如儲存資料“0” ，而其臨限電壓（threshold voltage，VTH)被設成一高準位電壓；相反地，若將電荷移 離浮置閘，其臨限電壓則爲一低準位電壓，代表第二狀態 之資料“Γ 。當要讀取記憶體所儲存的資料時，便藉由 感測該記憶體之臨限電壓VTH係處在第一或第二狀態，而 讀出“0”或“Γ 。藉由施加一高於上述之高準位的臨限 電壓或低於低準位之臨限電壓到記憶體的控制閘上，習知 之EPRpM便可以達到存放兩種狀態的資料，即選擇第一 狀態或第二狀態。然而，此種編碼記憶體的方式一次只能 存一位元的資料，所以有記憶容量太小的缺點。 爲了要將快閃記憶體之編碼成爲多階（multilevel)狀 態，一般習知技藝的做法係將施加於快閃記憶體的控制閘 電壓（字元線電壓）固定，而對汲極電壓（位元線電壓）作調 變，即施加一階梯電壓（step voltage)波形，使得快閃記億 體能夠具有不同的臨限電壓分布，亦即達到多階編碼的目 的。或是，將汲極電壓固定，而調變施加於控制閘極的電 壓。然而，一般之快閃記憶體的汲極電壓有一定的上限’ 3 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -------------裝----l·—訂---------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 ;' 4367 94 3 9 7 4 TWFItwf 1 . DOC/OO. A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（2 ) 爲了確保快閃記憶體能夠正常且無誤地***作，其施加於 汲極的電壓便必須被限制在安全的範圍（safety window)之 內。也就是說施加於汲極的最大電壓不可以超過其崩潰 電壓（breakdown voltage)以避免發生貫穿效應（punch through effect)。因此’爲了避免快閃記憶體發生貫穿效應，記憶 體的汲極電壓的範圍便被窄化，這也侷限了快閃記憶體所 能夠達到多階編碼的記憶範圍。 由上所述可知，爲了避免崩潰現象產生而限制住汲極 電壓的最大値，習知之快閃記憶體的多階編碼操作便有所 侷限，亦即限制了快閃記憶體的多階編碼範圍。’ 因此本發明的目的就是在提供一種快閃記憶體多階編 碼方法，其可以在避免快閃記憶體崩潰之汲極電壓的最大 値之內，達到對快閃記憶體進行多階編碼的目的。 本發明的另一目的就是在提供一種快閃記憶體多階編 碼方法V其對快閃記憶體的編碼階數可以不受汲極電壓的 限制。 爲達上述與其他之目的，本發明提出一種快閃記憶體 多階編碼方法，其簡述如下： 本發明揭露一種多階快閃記憶體的編碼方式。此方法 係在一快閃記憶體的控制閘與汲極同時施加階梯狀電壓波 形。 在對一快閃記憶體陣列中的其中之一記憶胞進行編碼 時，於快閃記憶胞之汲極（位元線）施加第一階梯狀電壓， 其中第一階梯狀電壓具有多個相異定値電壓。同時於第一 4 --------— — — — — — an^ 011 (請先閱讀背面之注意事項再填寫本頁) 言： Γ 良 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 Γ' 4 3 6 7 9 4 3974TWFltwfl.DOC/002 五、發明說明（，） 階梯狀電壓之各個相異定値電壓的作用期間，於快閃記憶 體的控制閘極（字元線）施加一第二階梯狀電壓，其中第二 階梯狀電壓具有多個相異定値電壓。 藉由在控制閘極與汲極同時施加階梯狀電壓來編碼快 閃記憶體，達到多階編碼的目的。而前述之第一階梯狀電 壓之各個相異定値電壓與第二階梯狀電壓之各個相異定値 電壓之差値以大於6V爲佳，使得快閃記憶體得以利用富 勒-諾德亥姆穿隨效應（Fowler-Nordheim tunneling effect，F-N效應)之方式來編碼快閃記憶體。再者，第一階梯狀電壓 之該些相異定値電壓的最大値以4V爲佳，以使汲極電壓 能在正常的工作電壓之下操作，而不致於導致記憶體發生 貫穿效應而崩潰。此外，更能在正常的工作電壓範圍之下 操作。因此，本發明之方法可以避免習知方法因爲受到汲 極工作電壓範圍的影響，而使得快閃記憶體進行多階編碼 的階數蓉到限制。 -爲讓本發明之上述目的、特徵、和優點能更明顯易懂， 下文特舉較佳實施例，並配合所附圖式，作詳細說明如下： 圖式之簡單說明： 第1圖繪示一快閃記憶胞陣列的示意圖； 第2圖繪示控制第1圖之快閃記憶胞陣列讀取與寫入 之電路方塊圖； 第3圖繪示編碼第1圖之快閃記憶胞陣列其中之一記 憶胞時，控制閘極與汲極所施加的電壓波形圖； 第4圖繪示控制閘極與汲極間的壓差以及相對應的臨 5 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -----裝·----^!·訂·1------線 (請先閱頡背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 「436794 3974TWFltwfl,DOC/002 幻 ____B7 五、發明說明（f) 限電壓間的關係圖；以及 . 第5圖繪示臨限電壓與記憶胞所儲存之資料之分佈 圖。 · 圖式之標示說明： 10時序電路 12汲極可變電壓震璗電路 U位元線選擇器 16控制閘之可變電壓震盪電路 18解碼器 20記憶胞陣列 Ml〜M16快閃記憶胞 WL1-WL4字元線 BL1〜BL4位元線 S1〜S4源極線 實施例% 本發明fe出種陕問冗憶體的多階編碼（multilevel programming or writing)方法。本方法係利用富勒-諾德亥姆 穿隧效應（Fowler-Nordheim tunneling effect，F-N 效應）之方 式來編碼快閃記憶體。因爲要利用F-N穿隧效應來編碼快 閃記憶體，所以控制閘極與汲極之間的最小壓差便必須至 少大於6V。 以下的說明將以一記憶胞儲存四階（four level)八位元 的資料爲例子，但非用以限制本發明所提的方法。假設一 指定的資料要寫入到如第1圖所示之記憶胞陣列中的其中 6 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐〉 ------------裝-----..----訂------線 (請先閱讀背面之注意事項再填寫本頁) ^ 436794 397 4TWFltwfl . DOC/002 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（$ ) 之一個記憶胞。第1圖所示的記憶胞陣列係由十六個快閃 記憶胞Ml〜M16所構成的陣列，其中包括四條位元線(bit line) BL1~BL4以及四條字元線（word line) WL1〜WL4。現在 以將指定資料寫入由BL1與WL1所定出之快閃記憶胞Ml 作爲例子。 當要對快閃記憶胞Ml進行寫入操作時，一般係在記 憶胞的控制閘極（字元線WL1)與汲極(位元線BL1)施加電 壓。本發明之操作特徵係在字元線WL1與位元線BL1均 施加階梯狀的電壓脈衝。 請參考第2圖，當準備對記憶胞Ml進行資料寫入操 作時，此時時序電路10便產生一觸發訊號A給汲極可變 電壓震盪電路12，用以產生一第一階梯狀電壓脈衝，此第 一階梯狀電壓脈衝以等時間間距爲佳。此時，位元線選擇 器14便選擇記憶胞陣列20中的其中之一位元線，如位元 線BL1Y，而第一階梯狀電壓脈衝便施加於位元線BL1上。 同诗，時序電路10更產生一觸發訊號B給控制閘極可變 電壓震盪電路16，用以在第一階梯狀電壓脈衝中每一相異 的定値電壓的作用期間，產生一第二階梯狀電壓脈衝’此 第二階梯狀電壓脈衝亦以等時間間距爲佳；並且，X解碼 器14便選擇記憶胞陣列20中的其中一字元線，如字元線 WL1，而第二階梯狀電壓脈衝便施加於字元線WL1上°藉 此，在第一階梯狀電壓脈衝施加於位元線BL1的期間’在 每一相異電壓定値的作用時間之內，字元線WL1所受到 的電壓亦爲階梯狀電壓，即第二階梯狀電壓。 7 ---------裝-----..----訂-------！線 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 436794 3974TWFltwfl.DOC/〇〇2 A7 B7 五、發明說明（厶） 請參考第3圖，其分別繪示出上述之第一與第二階梯 狀電壓脈衝（即分別爲位兀;線電壓與字元線電壓）的波形例 子。藉由第3圖來詳細說明本發明之快閃記憶體多階編碼 的操作方法。圖式中所示之電壓値與作用時間皆作爲說明 例之用，而並非用以限制本發明。 爲了要以F-N穿隧效應來編碼快閃記憶體，避免發生 崩潰現象以及有較高的操作速度，所以本例中之最低的控 制閘極操作電壓設定成10V，同時最高的汲極電壓設定爲 4V。如此便可以達到最低的F-N穿隧效應所需的電壓以及 避免快閃記憶體崩潰。前述之汲極可變電壓震盪電路17 所產生的第一階梯狀電壓如第3圖所示之位元線BL1電 壓，其爲每隔2ms產生一定値電壓，分別爲0V、2V、3V 與4V。總汲極電壓施加期間爲8ms。在汲極電壓，即第一 階梯狀電壓的每一定値電壓的作用期間，同時在快閃記憶 體Ml約控制閘極施加一第二階梯狀電壓如第3圖所示之 字元線WL1電壓。此電壓爲每隔〇.5ms產生一電壓値，分 別爲0V、10V、11V與12V。舉例來說，例如在汲極電壓 2V的作用期間，控制閘極同時所施加的第二階梯狀電壓 分布爲0V、10V、11V與12V。因此，便在快閃記憶體Ml 的控制閘極與汲極之間產生8V、9V與10V的壓差，而這 些壓差滿足產生F-N穿隧效應的最低電壓6V。故，以此 電壓分布施加於快閃記憶體Ml確實能使記憶體以F-N穿 隧效應來將資料寫入記憶胞之中。 同理可知，在汲極電壓，即第一階梯狀電壓中的每一 8 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ---------- (請先閱讀背面之注意事項再填寫本頁) Γ 經濟部智慧財產局貝工消費合作社印製 經濟部智慧財產局員工消費合作社印製 436794 3974TWFltwfl,DOC/002 五、發明說明（q > 個定値電壓(OV、2V、3V與4V)的2ms作用期間，均同時 施加一第二階梯狀電壓於控制閘極上。由上述之說明，在 第一與第二階梯狀電壓同時分別施加於快閃記憶體的汲極 與控制閘極時，便可以產生〇V、6V、7V、8V、9V、10V、 11V與12V八個相異汲極與控制閘極之間的電壓差組合。 _此八個相異的電壓差便對應到八個相異的臨限電壓，此對 應關係如第4圖所示。由第4.圖所示可以看出，當在此例 子中同時以兩組不同電壓分布的階梯狀電壓同時分別施加 於快閃記憶胞的控制閘與汲極時，可以將快閃記憶體編碼 成可以儲存八個相異資料的容量。同時.，臨限電壓與汲極、 控制閘極之間的電壓差的分布呈現一良好的線性關係。第 5圖係繪示臨限電壓與記憶胞所儲存之資料之分佈圖，由 此圖可以看出以第一與第二階梯狀電壓分別施加於汲極與 控制閘上，所產生的臨限電壓分布確實解析出八個相異的 資料。 -再者，位元線BL1所施加的電壓，即第一階梯狀電壓， 其最大値僅有4V並不會超過使快閃記憶體崩潰的最高汲 極電壓，約爲9V，所以可以在安全的電壓範圍之內達到 多階編碼的目的，且不會使快閃記憶體發生貫穿效應而崩 潰。 藉由適當的電壓分布，例如由電壓震盪電路12與16 的控制，便可以將汲極所施加的電壓控制在安全電壓範圍 之內，以產生多階編碼的目的。 因此，本發明的特徵係在快閃記憶體的汲極與控制閘 9 本紙張尺度適用中國國家標準（CNS〉A4規格（210 X 297公釐） I-------I--I i - 1 1 I l· U 1 « - I !111 (請先閱讀背面之注意事項再填寫本頁) 436 7 94 3974TWFltwfl,DOC/002 五、發明說明（Ϊ ) 極同時施加階梯狀的電壓，以達到對記憶體作多階編碼的 目的。 本發明的另一特徵係在汲極的正常工作電壓範圍之內 便可以達到多階編碼的目的，且不受汲極工作電壓範圍的 影響。 '綜上所述，雖然本發明已以較佳實施例揭露如上，然 其並非用以限定本發明，任何熟習此技藝者，在不脫離本 發明之精神和範圍內，當可作各種之更動與潤飾，因此本 發明之保護範圍當視後附之申請專利範圍所界定者爲準。 - --------1111 * I n l· I ! ^--------- (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作杜印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）A7 B7 436 7 9 4 3974TWFltwfl. DOC / 002 5. Description of the Invention (丨) The present invention relates to a non-volatile (n.on-volatile) semiconductor memory device, and more particularly to a flash memory (flash memory) sensing technology. '' In traditional semiconductor memory device technology, when data is to be written into an erasable programmable ROM (EPROM), the charge is transmitted through a tunnel insulating film To the floating gate, thereby assuming that the memory is in the first state, such as storing data "0", and its threshold voltage (VTH) is set to a high level voltage; conversely, If the charge is removed from the floating gate, its threshold voltage is a low level voltage, which represents the second state of data "Γ. When the data stored in the memory is to be read, the memory is sensed by The threshold voltage VTH is in the first or second state, and "0" or "Γ" is read out. By applying a threshold voltage higher than the high level above or a threshold voltage lower than the low level to the control gate of the memory, the conventional EPRpM can store data in two states, that is, choose the first State or second state. However, this method of encoding memory can only store one bit of data at a time, so it has the disadvantage of too small memory capacity. In order to make the flash memory code into a multilevel state, the common practice is to fix the control gate voltage (word line voltage) applied to the flash memory, and the drain voltage (bit The element line voltage is adjusted, that is, a step voltage waveform is applied, so that the flash memory can have different threshold voltage distributions, that is, the purpose of multi-level coding is achieved. Alternatively, the drain voltage is fixed and the voltage applied to the control gate is modulated. However, there is a certain upper limit for the drain voltage of general flash memory. 3 This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) ------------- Packing ---- l · --Order --------- line (Please read the notes on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs; '4367 94 3 9 7 4 TWFItwf 1. DOC / OO. A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the Invention (2) In order to ensure that the flash memory can be operated normally and without errors, the voltage applied to its drain must be Limited to a safety window. That is, the maximum voltage applied to the drain must not exceed its breakdown voltage to avoid a punch through effect. Therefore, in order to prevent the flash memory from penetrating, the range of the drain voltage of the memory is narrowed, which also limits the flash memory's ability to reach the multi-level encoding memory range. It can be known from the above that in order to avoid the collapse phenomenon and limit the maximum voltage of the drain voltage, the conventional multi-level encoding operation of the flash memory is limited, that is, the multi-level encoding range of the flash memory is limited. . '' Therefore, the object of the present invention is to provide a multi-level encoding method for flash memory, which can achieve the purpose of multi-level encoding for flash memory within the maximum threshold of the drain voltage for avoiding flash memory collapse. . Another object of the present invention is to provide a flash memory multi-level encoding method V, in which the encoding order of the flash memory is not limited by the drain voltage. To achieve the above and other objectives, the present invention proposes a flash memory multi-level encoding method, which is briefly described as follows: The present invention discloses a multi-level flash memory encoding method. This method involves applying a stepped voltage waveform to both the control gate and the drain of a flash memory. When encoding one of the memory cells in a flash memory array, a first stepped voltage is applied to the drain (bit line) of the flash memory cell, where the first stepped voltage has multiple differences. Set the voltage. At the same time in the first 4 --------— — — — — — an ^ 011 (Please read the precautions on the back before filling this page) Words: Γ Rare paper size applies Chinese National Standard (CNS) A4 Specifications (210 X 297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Γ '4 3 6 7 9 4 3974TWFltwfl.DOC / 002 V. Description of the invention A second stepped voltage is applied to the control gate (word line) of the flash memory, wherein the second stepped voltage has a plurality of different fixed voltages. By applying a stepped voltage to the gate and drain at the same time to encode the flash memory, the purpose of multi-level encoding is achieved. The difference between the different fixed voltages of the first stepped voltage and the different fixed voltages of the second stepped voltage is preferably greater than 6V, so that the flash memory can use the Fuller-Nordheim wear. The Fowler-Nordheim tunneling effect (FN effect) is used to encode the flash memory. In addition, the maximum of the different fixed voltages of the first stepped voltage is preferably 4V, so that the drain voltage can be operated under normal operating voltage without causing the memory to break through. In addition, it can operate under the normal operating voltage range. Therefore, the method of the present invention can prevent the conventional method from being affected by the working voltage range of the drain, which causes the order of the flash memory to perform multi-level coding to be limited. -In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, the following exemplifies preferred embodiments, and in conjunction with the accompanying drawings, the detailed description is as follows: Brief description of the drawings: Figure 1 shows Schematic diagram of a flash memory cell array; Figure 2 shows a block diagram of the circuit that controls the reading and writing of the Flash Memory Array of Figure 1; Figure 3 shows the Flash Memory Array encoding Figure 1. In the case of one memory cell, the waveform of the voltage applied by the control gate and the drain; Figure 4 shows the voltage difference between the control gate and the drain and the corresponding threshold. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ----- install · ---- ^! · Order · 1 ------ line (please read the precautions on the back before filling this page) Wisdom of the Ministry of Economy Printed by the Consumer Cooperative of the Property Bureau "436794 3974TWFltwfl, DOC / 002 Magic ____B7 V. Description of the invention (f) Diagram of the relationship between limit voltages; and Figure 5 shows the distribution of the threshold voltage and the data stored in the memory cell Fig. · Symbol description of the diagram: 10-sequence circuit, 12-drain variable voltage oscillator circuit, U-bit line selection 16 Variable voltage oscillating circuit of control gate 18 Decoder 20 Memory cell array M1 ~ M16 Flash memory cell WL1-WL4 word line BL1 ~ BL4 bit line S1 ~ S4 source line embodiment% The multilevel programming or writing method of redundant memory. This method uses the Fowler-Nordheim tunneling effect (FN effect) to encode flash memory. Because To use the FN tunneling effect to encode flash memory, the minimum voltage difference between the control gate and the drain must be at least greater than 6V. The following description will store four level eight bits in one memory cell The data is an example, but it is not intended to limit the method proposed in the present invention. Assume that a specified data is to be written into the memory cell array shown in Figure 1 of which 6 paper standards are applicable to the Chinese National Standard (CNS) A4 specifications (210 X 297 mm) ------------ installation -----..---- order ------ line (please read the precautions on the back before (Fill in this page) ^ 436794 397 4TWFltwfl. DOC / 002 A7 B7 Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Description of the invention One memory cell ($). The memory cell array shown in Figure 1 is an array of sixteen flash memory cells M1 to M16, including four bit lines BL1 ~ BL4 and four word lines WL1 to WL4. Now take the writing of the specified data to the flash memory cell M1 defined by BL1 and WL1 as an example. When a write operation is performed on the flash memory cell M1, a voltage is generally applied to a control gate (word line WL1) and a drain (bit line BL1) of the memory cell. The operation characteristic of the present invention is that a step-like voltage pulse is applied to both the word line WL1 and the bit line BL1. Please refer to FIG. 2, when a data write operation is to be performed on the memory cell M1, the timing circuit 10 generates a trigger signal A to the drain variable voltage oscillation circuit 12 to generate a first stepped voltage pulse. This first step-like voltage pulse is preferably at equal time intervals. At this time, the bit line selector 14 selects one of the bit lines in the memory cell array 20, such as the bit line BL1Y, and the first stepped voltage pulse is applied to the bit line BL1. In the same poem, the timing circuit 10 further generates a trigger signal B to the control gate variable voltage oscillation circuit 16 for generating a second stepped shape during the action of each distinct fixed voltage in the first stepped voltage pulse. Voltage pulse 'The second stepped voltage pulse is also preferably at equal time intervals; and, the X decoder 14 selects one of the word lines in the memory cell array 20, such as the word line WL1, and the second stepped voltage The pulse is applied to the word line WL1. Thus, during the period when the first step-like voltage pulse is applied to the bit line BL1, the voltage applied to the word line WL1 is within the action time of each distinct voltage. It is also a stepped voltage, that is, a second stepped voltage. 7 --------- Installation -----..---- Order -------! (Please read the precautions on the back before filling this page) This paper size is applicable to Chinese National Standard (CNS) A4 (210 X 297 mm) 436794 3974TWFltwfl.DOC / 〇〇2 A7 B7 V. Description of the invention (厶) Please refer to FIG. 3, which respectively illustrates waveform examples of the first and second stepped voltage pulses (that is, bit voltage; line voltage and word line voltage) respectively. The operation method of the multi-level encoding of the flash memory of the present invention will be described in detail with reference to FIG. The voltage 値 and the action time shown in the drawings are used for illustrative purposes and are not intended to limit the present invention. In order to encode the flash memory with the FN tunneling effect, to avoid crashes and high operating speeds, the lowest control gate operating voltage in this example is set to 10V, and the highest drain voltage is set to 4V. In this way, the voltage required for the lowest F-N tunneling effect can be achieved and the flash memory can be avoided. The first stepped voltage generated by the aforementioned drain-variable voltage oscillating circuit 17 is the bit line BL1 voltage shown in FIG. 3, which generates a certain voltage every 2ms, which are 0V, 2V, 3V, and 4V. . The total drain voltage application period is 8ms. During the action period of the drain voltage, that is, each fixed voltage of the first stepped voltage, a second stepped voltage is applied to the control gate of the flash memory M1 at the same time as the zigzag line WL1 voltage shown in FIG. 3 . This voltage generates a voltage 値 every 0.5ms, which are 0V, 10V, 11V, and 12V, respectively. For example, during the action period of the drain voltage 2V, the second stepped voltage distributions applied by the control gate at the same time are 0V, 10V, 11V, and 12V. Therefore, a voltage difference of 8V, 9V, and 10V is generated between the control gate and the drain of the flash memory M1, and these voltage differences satisfy the minimum voltage of 6V which causes the F-N tunneling effect. Therefore, applying this voltage distribution to the flash memory M1 can indeed make the memory write data into the memory cell with the F-N tunneling effect. Similarly, it can be known that the Chinese National Standard (CNS) A4 specification (210 X 297 mm) is applicable to every 8 paper sizes in the drain voltage, that is, the first stepped voltage. ---------- ( Please read the notes on the back before filling out this page) Γ Printed by the Shellfish Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 436794 3974TWFltwfl, DOC / 002 V. Description of the Invention During the 2ms period of the voltage (OV, 2V, 3V and 4V), a second stepped voltage is simultaneously applied to the control gate. From the above description, the first and second stepped voltages are simultaneously applied to the flash memory at the same time. When the body's drain and control gate are connected, the voltage difference combination between the eight different drains and control gate can be generated: 0V, 6V, 7V, 8V, 9V, 10V, 11V, and 12V. _The eight The different voltage differences correspond to eight different threshold voltages, and the corresponding relationship is shown in Figure 4. As can be seen from Figure 4. When this example uses two sets of different voltage distributions at the same time When the stepped voltage is applied to the control gate and the drain of the flash memory cell The flash memory can be encoded into a capacity that can store eight different data. At the same time, the threshold voltage and the voltage difference between the drain and the control gate show a good linear relationship. Figure 5 is a drawing The distribution diagram of the threshold voltage and the data stored in the memory cell is shown. From this figure, it can be seen that the first and second stepped voltages are respectively applied to the drain and the control gate, and the generated threshold voltage distribution is indeed resolved. Eight different data.-Furthermore, the voltage applied to the bit line BL1, that is, the first stepped voltage, has a maximum voltage of only 4V and does not exceed the maximum drain voltage that causes the flash memory to collapse. It is 9V, so it can achieve the purpose of multi-level encoding within a safe voltage range, and it will not cause flash memory to break through and break down. With proper voltage distribution, for example, control by voltage oscillation circuits 12 and 16 , The voltage applied by the drain can be controlled within the safe voltage range to generate multi-level coding. Therefore, the feature of the present invention is the drain and control gate of the flash memory. National Standards (CNS> A4 Specification (210 X 297 mm) I ------- I--I i-1 1 I l · U 1 «-I! 111 (Please read the precautions on the back before (Fill in this page) 436 7 94 3974TWFltwfl, DOC / 002 V. Description of the invention (Ϊ) The electrodes are applied with a stepped voltage at the same time to achieve the purpose of multi-level encoding of memory. The purpose of multi-level coding can be achieved within the normal working voltage range, and it is not affected by the working voltage range of the drain electrode. The present invention, anyone skilled in the art can make various modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the appended patent application. --------- 1111 * I nl · I! ^ --------- (Please read the notes on the back before filling out this page) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)