434S0 9.. 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（） 5 -1發明領域： 本發明係有關於一種非揮發性記憶體，特别是一種具 高電容耦合率的高密度非揮發性記憶體。 5-2發明背景： 非揮發性記憶體{nonvolatile memory)包含罩幕式 唯讀記憶體（Mask R01VU、可程式唯讀記憶體丨PR〇M)、可 抹除且可程式唯讀記憶體（EPROM)、可電除且可程式唯讀 記憶體（E E P R〇Μ 〇 r E2 P R 0 Μ }、以及快閃記憶體（f I a s h m e m o r y)等，可以在電源移除後仍保留住所儲存的另料’ 在電子及計算機工業中應用非常廣泛。A. Bergemont等 人在其論文"Low V。丨tage NVGtm: A New High Performance 3 V/5 V Flash Technology for Portable Computing and Telecommunications Application" {in IEEE Trans. Electron Devices Vot. 43, p. 1 5 1 0, 1 996) 之中陳述，近幾年來，由於市場的發展快速’可撰式電腦 與電信工業已成爲半導體積體電路設計技術的主要驅動 力，因此對於低功率、高密度且可重複讀寫的非揮發性記 憶體產生了大量的需求。這些可裎式且可抹除的記憶體如 EPROM ' E 2 P R 0 Μ 、與flash memory等可以儲存上述 系統中的作業系統以及應用軟體，是不可或缺的基本元件 之一。 本紙張尺度適用中國國家標隼（CNS ) A4規格（2!0x297公釐） (請先閱讀背面之注意事項再填寫本頁) -0裝. 訂 4349 〇 9 A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明（） 可抹除且可程式的唯讀記憶體的基本儲存胞包含一 個具有雙重閘極的儲存電晶體，其中懸浮閘極（fl〇ating gate)由介電質所包圍，而與堆疊於其上的控制閘極 (control gate)電容耦合。可電除且可程式唯讀記憶體則 更包含一個存取電晶體，或稱選擇電晶禮，作爲控制元 件。在這些可抹除且可程式的記憶體中，資料的存入{稱 爲程式化）與抹除是以懸浮閘極充放電的方式來達成。例 如’可抹除且可程式唯讀記憶體將選定的記憶胞的汲極熱 電子流注入懸浮閘極來進行資料的寫入，而以紫外光或X 光加速懸浮閘極中的電荷使之脱離來將寫入的資料抹 除。而可電除且可程式唯讀記憶體以及大部分的快閃記憶 體則可以採熱電子流注，或是採稱爲FI 〇 w e r - N 〇 r d h e i rn 穿隧的冷電子穿隧效應，來進行資料的寫入，而主要以 FI 〇 w e r - N 〇 r d h e i m穿隧將電子由懸浮閘極驅入源極來執 行資料抹除的動作。 aim.穿隧效應，或稱冷電子穿隧效應/ . - a. 是一種量子效應，容許具有較低能量的電子穿^位能障較 〜八 —— _ ▲ 為·· — --- --— 高的！與氧化矽界_母。Η S h i r a i等人在其論文 "A 〇·54μηι2 Self-Aligned, HSG Floating Gate Cell (SAHF Cell) for 256 Mbit Flash Memoriesw (in IEDM Tech. Dig. Vol. 95, p. 65 3" 1995)中述及，由於採用 Flower-Nordheim穿隧效應來進行記憶胞之程式化與資 料抹除，具有較低的電流消耗率，因此已成爲製造低功率 ~ _ 之可電除且可程式唯讀記憶體以及快閃記憶體不可或缺 本紙張尺度適用中國國家梯準（.CNS〉规格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) -裝·434S0 9 .. Printed by A7 B7, Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention () 5 -1 Field of the invention: The present invention relates to a non-volatile memory, especially a high-capacitance coupling ratio. Density non-volatile memory. 5-2 Background of the Invention: Nonvolatile memory includes non-volatile memory (Mask R01VU, programmable read-only memory 丨 PROM), erasable and programmable read-only memory ( EPROM), programmable and read-only memory (EEPR〇Μ 〇r E2 PR 0 Μ}, and flash memory (f I ashmemory), etc., can retain the stored additional materials after the power is removed '' It is widely used in the electronics and computer industry. A. Bergemont et al. In their dissertation " Low V. 丨 tage NVGtm: A New High Performance 3 V / 5 V Flash Technology for Portable Computing and Telecommunications Application " {in IEEE Trans Electron Devices Vot. 43, p. 1 5 1 0, 1 996) states that in recent years, due to the rapid development of the market, the “writeable computer and telecommunications industry has become the main driving force for semiconductor integrated circuit design technology. Therefore, there is a great demand for low-power, high-density, non-volatile memory that can be read and written. These removable and erasable memories, such as EPROM 'E 2 P R 0 Μ and flash memory, can store the operating system and application software in the above system, which is one of the essential basic components. This paper size applies to China National Standard (CNS) A4 specification (2! 0x297 mm) (Please read the notes on the back before filling out this page)-0 Pack. Order 4349 〇9 A7 B7 Staff Consumption of Central Standards Bureau, Ministry of Economic Affairs Printed by the cooperative V. Description of the invention () The basic storage cell of the erasable and programmable read-only memory contains a storage transistor with a double gate. The floating gate is made by the dielectrics. Is enclosed, and is capacitively coupled to a control gate stacked thereon. The erasable and programmable ROM only includes an access transistor, or select transistor as a control element. In these erasable and programmable memories, the storage of data (referred to as stylization) and erasure are achieved by charging and discharging the floating gate. For example, 'erasable and programmable read-only memory injects the hot electrons of the drain of the selected memory cell into the suspension gate to write data, and accelerates the charge in the suspension gate with ultraviolet or X-rays to make it Exit to erase the written data. The erasable, programmable read-only memory and most flash memory can use hot electron flow injection, or the cold electron tunneling effect called FI 〇wer-N 〇rdhei rn tunneling, to The data is written, and the data erasing action is mainly driven by the FI Ower-N rdheim tunneling to drive electrons from the floating gate to the source. aim. Tunneling effect, or cold electron tunneling effect /.-a. It is a quantum effect that allows electrons with lower energy to pass through the ^ potential barrier is ~ 8-_ ▲ is ·· — ---- -- High! And silicon oxide world _ mother. Hi Shirai et al. In his paper " A 〇.54μηι2 Self-Aligned, HSG Floating Gate Cell (SAHF Cell) for 256 Mbit Flash Memoriesw (in IEDM Tech. Dig. Vol. 95, p. 65 3 " 1995) It is mentioned that, due to the use of the Flower-Nordheim tunneling effect for programming and data erasing of memory cells, it has a lower current consumption rate, so it has become a programmable and read-only memory with low power ~ _ And flash memory is indispensable. This paper size applies to China National Standard (.CNS) specifications (210X297 mm) (Please read the precautions on the back before filling this page)
VV
ltT 43480 經濟部中央標準局員工消费合作社印製 A7 B7 五、發明説明（） 的設計體系。但是要以Flower-Nordheim穿隧來進行資 料寫入與抹除，需要在基板與懸浮閘極間的介電層提供可 反轉的強電場，因此、必」^施加高隻應_電j於己憶胞的控制 、閉、極。而爲了要降低此控制閘極偏壓，則必須要提高記憶 麁為構的電容耦合率。 Y· S. Η丨samune等人在論文"八1~1丨911。3卩3。丨1:丨\/6-Coupling Ratio (HiCR) Cell for 3 V-Only 64 Mbit and Future Flash Memories"( IEDM Tech. Dig. Vo!. 93, p. Ί 9 , 1 9 9 3 )中提出一個製造快閃記憶體的方珐，採無接點 的記憶胞陣列並具有高電容耦合率。然而爲了要達到高電 容耦合率的目標，此一方法施行了四次的多晶矽沈積，製 程十分複雜。此外，如 C. J. Hegarty 等人在論文 "Enhanced Conductivity and Breakdown of Oxides Grown on Heavily Implanted Substrates" {Solid-State Electronics, Vol. 34, p. 1 207, 1 991}中所提及，要在 低功率非揮發性記憶體中重捧雜的基板上製造薄的穿暖 氧化層以提南電子流注效率及電荷崩潰（charge-to. breakdown) »是極不容易的。因此，以簡單的製程來達 到高電容耦合率、高電子流注效率以及高電荷崩溃，已成 爲今日製造高密度、低功率之非揮發性記憶體的重要課 題0 <· 5-3發明目的及概述： 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 0¾ ‘ τ° -韵 (請先閲讀背面之注意事項再填{'^本10(ltT 43480 Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs A7 B7 V. Design System of Invention Description (). However, in order to write and erase data using the Flower-Nordheim tunneling, a strong reversible electric field needs to be provided in the dielectric layer between the substrate and the floating gate. Therefore, it is necessary to apply high power only. I remember my cell's control, closure, and extremes. In order to reduce this control gate bias, it is necessary to increase the capacitive coupling ratio of the memory structure. Y.S. Η 丨 Samune et al. In the paper " Aug. 1 ~ 1 丨 911. 3 卩 3.丨 1: 丨 \ / 6-Coupling Ratio (HiCR) Cell for 3 V-Only 64 Mbit and Future Flash Memories " (IEDM Tech. Dig. Vo !. 93, p. Ί 9, 1 9 9 3) Square enamel for flash memory is manufactured with a contactless memory cell array and has a high capacitive coupling rate. However, in order to achieve the goal of high capacitance coupling rate, this method performed four times of polycrystalline silicon deposition, and the process was very complicated. In addition, as mentioned by CJ Hegarty et al. In the paper "Enhanced Conductivity and Breakdown of Oxides Grown on Heavily Implanted Substrates" {Solid-State Electronics, Vol. 34, p. 1 207, 1 991}, low power It is extremely difficult to make a thin through-oxide layer on a non-volatile memory in order to improve the efficiency of electron injection and charge-to. Breakdown ». Therefore, the simple process to achieve high capacitive coupling rate, high electron flow efficiency and high charge collapse has become an important issue in today's manufacturing of high-density, low-power non-volatile memory. 0 < · 5-3 Inventive purposes And overview: This paper size is applicable to Chinese National Standard (CNS) A4 specification (210X297mm) 0¾ 'τ ° -Yun (Please read the notes on the back before filling in {' ^ 本 10 (
434§〇g ” A7 ---------- B7 五、發明説明（） 鑒於上述之發明背$中，#統的非揮發性記憶體不 易〇心的製寿呈逵到高—電容合率、$ $子流以皂 31j ;賣的要—來。根據以上的目的，本發明;^ —具有 糙表面穿隨氧化層之非揮發性記憶體。此記憶體結構包含 一非穿隨氡化層形成於半導體基板之上;具有粗糙表面的 穿随乳化滑形成於非穿随氧化層的兩側，雜質捧雜區 於半導體基板中穿隧氧化層的下方作爲源極與汲極 浮閘極形成於非穿遂氧化層與穿隨氧化層之上；一内介電 層形成於懸浮閘極之上；以及一控制閘極形成於内介電 之上。其製程敛述如下。 首先於基板上形成場氧化隔離層並定義主動區域。沈 積氧化矽與氮化矽堆疊層然後定義穿隧氧化區<以高溫氧 化法形成非穿隧氡化層，在去除氮化矽層後植人雜質離子 形成源極與汲極。以熱退火製程修護基板的損害並驅入雜 了離子。去除氧化软層並？成二未墼竺盖立 .二3—/層^加复轉』1_^_成）I球曼竺虽粒)考。以熱 3化法將t摻ϋ的j A石n或半球:形石夕晶上層氧^ 有粗^表面色穿隧氧化層。最後依序形成懸浮閘 經濟部中央樣準局員Η消资合作社印^ 電層與控制閘極。高密度、高運作速度的非揮發性記憶體 於焉形成。 5-4闽式簡單説明： 本發明的較佳實施例將於往後之説明文字中輔以下 4 3 4 ο 7 β 明説明發 Λ五 述 :闡 述的 闡細 的詳 細更 詳做 更形 做圖 形列 圖 歹 基 於 層 化 氮 與 矽 化 氧 成 形； 明圖 發面 本剖 據圓 根晶 爲體 圖導 一半 第的 上 板 半 的 上 板 基 於 區 化 氧 隧 穿 義 定 明 發 本 據 的 上 板 基 於 層 化 氧 熱 後 i 成 形 明 發 本 據 根圖根 爲面爲 圖剖圖 工圓三 第晶第 體 導 的 中 板 基 於 區 極 汲 與 極 源 成 形 明 發 ; 本 圖據 面根 剖爲 圓圖 晶四 體第 導 半 化 氧 墊 除 去 並 火 退 熱 溫 高 施 實 明 發 .， 本 圖據 面根 ，夸 爲 圓圖 晶五 體第 導 半 球 半 或 層 矽 晶 br 寻 ο 之圖 薄面 超剖 1 圓 成晶 形體 丨明導 圖發半 面本的 剖據上 圓根板 晶爲基 體圖於 導六層 半第晶 的 矽 層 形 ίι T^J 之圊 薄晶 超體 將導 法半 化的 氧層 熱化 溫氧 高随 施穿 實的 明面 發表 本糙 據粗 根具 爲成 圖變 七轉 第層 矽 晶 圖 面 懸 義 定 並 層 矽 晶 多 型 N 成 形 明 發 本 據 艮 才 爲 圖 八 第 閘 浮 懸 於 層 電 介 内 之 薄 超 〇 1 圖形 面明 剖發 圓本 晶據 體根 導爲 半圖 的九 極第 閘 浮 ^ί 面 剖 圓 晶 體 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標华局員工消f合作社印製 義 定 並 層 晶 多 型 N 1 另。 成圖 形面 明剖 發圓 本晶 據體 根導 爲半 導圖的 半十極 的第閘 上 制 極 控 明説細詳 明發 5 I 5 本紙張尺度適用中國國家標隼（CNS ) A4規格（210 X 297公釐） 4348 A7 B7 五'發明説明（） 本發明提供一個簡單的方法以製造具高電容耦合率 的高密度非揮發性記憶體。其中應用到許多在傳統抆藝中 已廣爲熟知的技術如微影、蝕刻、以及化學氣相沈積法 (Chemical Vapor D.eposition, CVD)等，在此即不再詳述 其内容。此外，本發明製造具有粗糙表面的穿隧氧化層以 提高電子注流效率與電荷崩潰。 參見第一圖中所顯示，基板2爲結晶面向<100>的 單晶矽。首先在此基板2上形成一氧化矽層4,此氧化矽 層 4可以採用低壓化學氣相沈積法（i_ow Pressure Chemical Vapor Deposition, LPCVD)在攝氏溫度約 400-750度之下形成’也可以在攝氏溫度約8〇0-11〇〇 度之下以熱氧化法形成。此氧化梦層4 .除了可作爲塾氧 化層{ p a d ο X ί d e丨之外’並且可以在後績的離子植入法中 作爲犧牲氧化層（sacrificial oxide)以防止通道效應的產 生。 經濟部中央榡準局員工消費合作社印製 (請先閲讀背面之注意事項再填寫本頁) 接著在墊氧化層4之上形成一氮化矽層6作爲氧化 罩幕’此氮化石户層6同樣可以採用低壓化學氣相沈積法 在攝氏溫度約7 0 0 - 8 0 0度之下形成。然後，以光阻塗佈、 曝光、顯影等標準的微影，製程技術在氮化發層6之上形 成光阻層以疋義出絶緣區的圖形。以此光阻層爲罩幕實施 等向性蝕刻法蝕刻氮化矽層6以定義氧化罩幕，於去光 阻後實施熱氧化法，於絶緣區上形成厚度約爲3〇〇〇至 7 本紙浪尺度適用中國國家標準（CNS ) A4規格（2I0X29?公釐） 348 348 經濟部中央標準局貝工消費合作社印t 五、發明説明（ 80〇〇埃的場氧化層8，作 區S形成後，可選擇將原氮：：離區。在場氧化隔離 氮化矽層10於基板2上^ 6去除，重新形成一 參閲第二圖’以另-微影製程在主動 隧氧化區與非穿隧氧化區。以韭笑二 疋義出穿 非寺向性蝕刻法蝕刻氮化矽 層1 〇，暴露出非穿隧氧化汚 > 、益P 』乳化夕 孔化£上又墊氧化層4;此 性蝕刻製程可採用CFjc^ eF /μ| ^ > 寺勹 " 4 2丨CFVH2, cHF3或是 NF作爲 蝕刻電漿源。蝕刻後，於溫户糾述A 馬 尤恤度約攝氏8〇〇至η 〇〇度之 下實施高溫蒸氣氧化祛，在非穿醏备 好 牙隨氧化區上形成一層厚教 乳化層12。如第三圖中所顯示，此熱氧化層12的厚卢' 約爲300至25。0埃，可以提高記憶胞的電容裸合率广 接下來參見第四圖，以熱磷酸溶液作爲濕蝕刻液去除 餘下的氮化矽層1。。然後實施離子植入nf的雜 質離子經由氧化矽層4植入基板2中以形成源極與汲極 區。摻入的離子可爲磷離子、砷離子或是銻離子，植入的 能量與劑量分别约爲0.5至150KeV以及5xi〇w ·5χ 1〇16 atoms/cm2。在此離子植入製程中，氧化矽層4可 作爲缓衝以防止基板2受到離子轟擊之損壞，並可防止 摻質離子發生通道效應；厚熱氧化層12則使摻質離子難 以穿透’無法進入其正下方之基板區。實施退火製程修補 基板損壞，同時可將掺質活化並驅入以形成最佳分佈，如 第五圖中所顯示。此退火製程以在溫度約攝氏7〇〇至8〇〇 度之下貫 快表熱餐程y (rapid thermal processing, R丁P) 本紙張尺度適用中國國家榇準（CNS > A4規格（210X297公釐） (請先閲讀背面之：;.i意事項再填海本頁)434§〇g ”A7 ---------- B7 V. Description of the invention () In view of the above-mentioned inventions, the non-volatile memory of the system is not easy. Capacitance, sub-flow of soap 31j; what to sell-come. According to the above purpose, the present invention; ^-non-volatile memory with a rough surface through the oxide layer. This memory structure contains a non-through The sacrificial layer is formed on the semiconductor substrate; the penetrating emulsification with a rough surface is formed on both sides of the non-penetrating oxide layer, and the impurity doped region is below the tunneling oxide layer in the semiconductor substrate as a source and a drain. The floating gate is formed on the non-penetrating oxide layer and the trailing oxide layer; an internal dielectric layer is formed on the floating gate; and a control gate is formed on the internal dielectric. The process is described below. A field oxide isolation layer is first formed on the substrate and an active area is defined. A stacked layer of silicon oxide and silicon nitride is deposited and then a tunneling oxide region is defined < a non-tunneling halide layer is formed by a high temperature oxidation method, after removing the silicon nitride layer Implanted impurity ions to form source and drain. Repair substrate with thermal annealing process Damage and drive into the mixed ions. Remove the oxidized soft layer and make it into a two-year-old Zhuge Li. 2 3-/ layer ^ plus reversion "1 _ ^ _ Cheng) I ball Manzhu)) test by thermal method t-doped j A stone n or hemisphere: the upper layer of the shape of the stone Xixi oxygen ^ has a rough ^ surface color tunneling oxide layer. Finally, the Central Bureau of the Ministry of Economics of the Suspension Gate Ministry of Economics and Economic Cooperation Cooperative printed ^ electrical layer and control Gate. Non-volatile memory with high density and high operating speed is formed in tritium. 5-4 Fujian type brief description: The preferred embodiment of the present invention will be supplemented by the following explanatory text 4 3 4 ο 7 β The five descriptions of the explanation: the detailed elaboration is explained in more detail, and the shape is graphically formed. 歹 Based on stratified nitrogen and silicide oxygen formation; the figure is published, and the circular root crystal is the first half of the volume map. The upper plate of the plate half is based on the zoned oxygen tunneling. The upper plate of the paper is based on the layered oxygen heat. The shape of the paper is based on the root of the figure. The plate is based on the area pole drain and pole source forming; the figure is based on the root section The circular figure crystal four-body semi-conductive oxygen pad is removed and the heat is high and the temperature is high. The figure is based on the surface roots, which is exaggerated as the circular figure five-body semi-conductive hemisphere hemisphere or layer of silicon crystal. Section 1 Rounded into a crystalline body 丨 The schematic diagram is shown in half the original. The circular root plate crystal is used as the substrate. The six-layered and semi-crystalline silicon layer is formed. The thin crystal superstructure of T ^ J is a half-oxygen layer. The heating temperature and the high oxygen content were published on the bright side of the paper. The rough roots have a rough surface for the picture. The first layer of the silicon crystal surface is suspended. The layered silicon crystal polytype N is formed. The thin gate floating in the dielectric layer of the gate. The figure 1 clearly shows the rounded crystal. The nine-pole gate floating ^ ί plane crystal (please read the precautions on the back first) (Fill in this page) Employees of the Central Standardization Bureau of the Ministry of Economic Affairs and the FFC Cooperative Co., Ltd. have printed a polymorphic N 1 polymorph. The figure shows that the circular base crystal is based on the semi-decade pole gate control of the semi-ten pole, and the detailed explanation is issued. 5 I 5 This paper size applies to China National Standard (CNS) A4 specifications ( 210 X 297 mm) 4348 A7 B7 Five 'Invention Description () The present invention provides a simple method to manufacture high density non-volatile memory with high capacitive coupling ratio. Among them, it is applied to many technologies that are well known in the traditional arts, such as lithography, etching, and chemical vapor deposition (CVD), etc., which will not be described in detail here. In addition, the present invention manufactures a tunneling oxide layer with a rough surface to improve the electron injection efficiency and charge collapse. As shown in the first figure, the substrate 2 is a single crystal silicon with a crystal orientation < 100 >. First, a silicon oxide layer 4 is formed on the substrate 2. This silicon oxide layer 4 can be formed by using a low pressure chemical vapor deposition method (i_ow Pressure Chemical Vapor Deposition, LPCVD) at a temperature of about 400-750 degrees Celsius. It is formed by a thermal oxidation method at a temperature of about 8000-1100 degrees Celsius. This oxide dream layer 4. In addition to being used as a hafnium oxide layer {p a d ο X ld e 丨 ′ ′, it can also be used as a sacrificial oxide in subsequent ion implantation methods to prevent the generation of channel effects. Printed by the Consumers' Cooperative of the Central Government Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page). Then, a silicon nitride layer 6 is formed on the pad oxide layer 4 as an oxide mask. This nitride layer 6 It can also be formed by low-pressure chemical vapor deposition at a temperature of about 700-800 degrees Celsius. Then, using a standard lithography such as photoresist coating, exposure, and development, a process technique is used to form a photoresist layer on the nitrided layer 6 to define the pattern of the insulating region. Using the photoresist layer as a mask, an isotropic etching method is used to etch the silicon nitride layer 6 to define an oxide mask. After removing the photoresist, a thermal oxidation method is performed to form a thickness of about 3000 to 7 on the insulating region. The scale of this paper applies the Chinese National Standard (CNS) A4 specification (2I0X29? Mm) 348 348 Printed by the Bayer Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (field oxide layer 80000 angstroms, formed as area S After that, the original nitrogen :: off region can be selected. In-situ oxidation isolation silicon nitride layer 10 is removed from the substrate 2 ^ 6, and a second image is formed as shown in the second figure. Non-tunneling oxidation zone. The silicon nitride layer 10 is etched by a non-tunneling etching method using a chimney, and the non-tunneling oxide pollution is exposed, and the P is emulsified and oxidized. Layer 4; This etching process can use CFjc ^ eF / μ | ^ > Tera " 4 2 丨 CFVH2, cHF3 or NF as the etching plasma source. After etching, correct the A Mayo shirt in Wenhu High temperature steam oxidation treatment is carried out at a temperature of about 800 ° C to η ° C, and it is formed on the non-perforated prepared teeth following the oxidation zone. The thickness of the emulsified layer is 12. As shown in the third figure, the thickness of the thermally oxidized layer 12 is about 300 to 25.0 angstroms, which can increase the capacitance nakedness of the memory cell. The hot phosphoric acid solution is used as a wet etching solution to remove the remaining silicon nitride layer 1. Then, the impurity ions of the ion implantation nf are implanted into the substrate 2 through the silicon oxide layer 4 to form the source and drain regions. The doped ions It can be phosphorus ion, arsenic ion, or antimony ion. The implantation energy and dose are about 0.5 to 150KeV and 5xi0w · 5χ 1016 atoms / cm2. In this ion implantation process, the silicon oxide layer 4 can be As a buffer to prevent the substrate 2 from being damaged by ion bombardment, and to prevent the channel effect of the dopant ions; the thick thermal oxide layer 12 makes it difficult for the dopant ions to penetrate 'cannot enter the substrate area directly below it. Repair by annealing process The substrate is damaged, and the dopants can be activated and driven in to form the optimal distribution, as shown in the fifth figure. This annealing process runs through the hot meal process at a temperature of about 700 to 800 degrees Celsius. y (rapid thermal processing, R 丁 P) paper size Applicable to China National Standards (CNS > A4 specification (210X297 mm) (Please read the following:;. I Italian matter before filling in this page)
經濟部中央標準局貝工消費合作社印製 A7 _____87__ 五、發明説明（） 爲適當°然後以.缓衝氧化石夕姓刻液/ ( b u f f e r e d ο X i d e - 一 — ^ ^ ^ ^ ^ ^ - etching solution, BOE solution)或是稀釋的氫氟酸{HF} 溶液去除氧化矽層4。 參見第六圖，沈積一超薄的非晶矽層 1 6於基板2 上。此非晶矽層1 6之厚度約爲2 0至3 0 0埃，由低壓化 學氣相沈積法在攝氏溫度約4 0 〇 - 5 6 0度之下形成。然後 在氮氣的環境中實施熱製程，將溫度由攝氏約25度逐漸 升高至9 5 0度，使非晶矽層1 6轉變成多晶矽層。此外也 可以採用厚度约爲 40至 500埃的半球型矽晶粒 (hemispherical grained silicon H S G - S i)代替多晶矽層 16。接著在第七圖中顯示，於itu袤境中實施溫度約爲 攝氏7巨0至1 1 5 0度的熱氧化法，將多晶矽層16氧化成 氧化矽層 Ί 8'γ根據—吳協霖博士等人在其論文 "Characterization of Thin Textured Tunnel Oxide Prepared by Thermal Oxidation of Thin Polysilicon Film on Silicon" ( IEEE Trans. Electron Devices, Vol. 43, p. 上996丨中發表的研究，在晶_界處氧; ，的立散^度_較快，因此有較铯的！化速气j 化..梦層__ 1 8將會形成一粗糙（textured)的5夕與氧.界> 面。此一粗糙界面會造成局部的，高電場，而使從基板 2 注入氧化層的電子流增大。因此較之於傳統的穿隧氧化層 結構，表面粗糙的穿隧氧化層可以增加電子流注效能，降 低電荷捕獲率並使電荷崩潰增大。 本紙張尺度適用中囷國家榇準（CNS )以規格f 210父297公釐） (請先閱讀背面之注意事項再填寫本頁) ίο裝· 訂 經濟部中央標準局負工消費合作社印製 根據 隧氧化層 體結構包 上；穿隧 質摻雜區 作爲源極 與穿隧氧 20之上； 上述之穿 43490 9 A7 __ _^----i7… 五、發明説明（） ^ ^ ~ 如^八圖中所顯示，沈積—導電層2〇於基板.、 上，此導電層2〇可以採用掺雜或同步捧雜的多 ^ 質，以低壓化學氣相沈積法形忐 馬材 ,^ a 成°接奢以檩準的微影製程 在導電層20之上定義出懸浮閘極的圖案，而採 HBr、SF6或是SiCI4爲蝕刻電裂菩 2、 晶矽層以形成懸浮閘極20於主動 夕 疋、王劫£域及部份的場氧化隔 離區上。 在第九圖中_示出一^.3^# + ♦ „ 。4的内多晶石夕介電層22沈積 於懸浮閘極20的表面上。此由友θ作人 此内多晶矽介電層22可採用 五氧化二钽（Ta2〇s) 、BST、由新仆歆作备仏 田虱化矽與虱化矽組成的複 合薄膜、或是由氧化矽、氮化矽與氧化矽組成的三重薄膜 爲材質。最後，參見第十圖中所示，沈積並姓刻另_導電 層以形成控制閘極，此控制閘極同樣可以採用摻雜或同步 掺雜的多晶矽爲材質，以低壓化學氣相沈積法形成。 以上所提的方法’本發明完成一具有粗糙表面穿 之非揮發性記憶體。如第十圖中所顯示，此記憶 含一非穿隧氧化層12形成於半導體基板2之 氧化層1 8形成於非穿随氧化層Ί 2的兩側，雜 14形成於半導體基板2 _穿隧氧化層的下方， 與没極；一懸浮閘極2 〇形成於非穿隧氧化層1 2 化層1 8之上；一内介電層2 2形成於懸浮閘極 以及一控制閘極24形成於内介電層22之上。 隧氧化層18具有粗糙的上下表面，可產生高區 10 本紙張尺度通用中國國家標準（CNS > A；J規格（2丨〇 χ別公沒 f靖先聞讀背面之注意#v碩再iA'!iir4頁)Printed by A7 _____87__ by the Central Bureau of Standards of the Ministry of Economic Affairs _____87__ V. The description of the invention () is appropriate ° and then the buffer oxide XI Xi engraved solution / (buffered ο X ide-a — ^ ^ ^ ^ ^ ^-etching solution, BOE solution) or diluted hydrofluoric acid {HF} solution to remove the silicon oxide layer 4. Referring to FIG. 6, an ultra-thin amorphous silicon layer 16 is deposited on the substrate 2. The amorphous silicon layer 16 has a thickness of about 20 to 300 angstroms, and is formed by a low-pressure chemical vapor deposition method at a temperature of about 400 to 560 degrees Celsius. Then, a thermal process is performed in a nitrogen environment, and the temperature is gradually increased from about 25 degrees Celsius to 950 degrees Celsius, so that the amorphous silicon layer 16 is transformed into a polycrystalline silicon layer. Alternatively, hemispherical grained silicon H S G-S i having a thickness of about 40 to 500 angstroms may be used instead of the polycrystalline silicon layer 16. Then, in the seventh figure, a thermal oxidation method at a temperature of about 7 ° C to 115 ° C is performed in the itu environment, and the polycrystalline silicon layer 16 is oxidized to a silicon oxide layer. 8'γ According to Dr. Wu Xielin and others The research published in his paper "Characterization of Thin Textured Tunnel Oxide Prepared by Thermal Oxidation of Thin Polysilicon Film on Silicon" (IEEE Trans. Electron Devices, Vol. 43, p. 996 丨, 996 丨The squaring degree of _ is faster, so there are more cesium! The rate of speed and gasification. The dream layer __ 1 8 will form a roughened surface of the 5th and oxygen. Boundary> This. A rough interface will cause a local, high electric field, which will increase the electron flow injected into the oxide layer from the substrate 2. Therefore, compared with the traditional tunneling oxide structure, the rough surface of the tunneling oxide layer can increase the electron flow injection efficiency. Reduce the charge trapping rate and increase the charge breakdown. This paper size is applicable to the Chinese National Standard (CNS) to specification f 210 parent 297 mm) (Please read the precautions on the back before filling this page) Central Laboratories of Ministry of Economic Affairs It is printed on the basis of the structure of the tunnel oxide layer; the tunneling doped region is used as the source and the tunneling oxygen 20; the above-mentioned pass 43490 9 A7 __ _ ^ ---- i7 ... 5. Description of the invention () ^ ^ ~ As shown in the figure ^, a conductive layer 20 is deposited on the substrate. The conductive layer 20 may be doped or simultaneously doped, and formed by low pressure chemical vapor deposition. Ma Cai, ^ a into the following standard lithography process to define the floating gate pattern on the conductive layer 20, and use HBr, SF6 or SiCI4 to etch the electro-split 2, crystal silicon layer to form Suspension gate 20 is located on the active oxidant, Wang Jieyu field and part of the field oxidation isolation zone. In the ninth figure, _ shows a ^ .3 ^ # + ♦. The inner polycrystalline silicon dielectric layer 22 of 4 is deposited on the surface of the floating gate 20. This is made by the friend θ as the polycrystalline silicon dielectric. The layer 22 may be made of tantalum pentoxide (Ta2Os), BST, a composite film composed of silicon oxide and silicon oxide prepared by the new company, or silicon oxide, silicon nitride, and silicon oxide. The triple film is made of material. Finally, as shown in the tenth figure, another conductive layer is deposited and engraved to form a control gate. This control gate can also be doped or synchronously doped polycrystalline silicon. Formed by vapor deposition method. The method mentioned above completes a non-volatile memory with rough surface penetration. As shown in the tenth figure, this memory contains a non-tunneling oxide layer 12 formed on the semiconductor substrate 2 An oxide layer 18 is formed on both sides of the non-pass-through oxide layer Ί 2, and a dopant 14 is formed under the semiconductor substrate 2 _ tunneling oxide layer, and the electrode; a floating gate 20 is formed on the non-tunneling oxide layer 1 2 on the layer 18; an internal dielectric layer 2 2 is formed on the floating gate and a control gate 2 4 is formed on the inner dielectric layer 22. The tunnel oxide layer 18 has rough upper and lower surfaces, which can produce high areas. The paper size is in accordance with China National Standards (CNS >A; J specifications (2 丨 〇 别 别 公 没 f). Jingxian heard the note on the back #v 硕 再 iA '! Iir page 4)
A7 經濟部中央標率局員工消費合作社印製 4 3 4 y B7 五、發明説明（） 域電場，增加電子流注效能，降低電荷捕獲率並使電荷崩 潰增大。採用此具有粗糙表面的穿隧氧化層18，可以在 比傳統穿隧結構面積較小的條件下達到相同的穿隧電 流，因此可以製造高密度、高運作速度的非揮發性記億 體。 以上所述僅爲本發明之較佳實施例而已，並非用以限 定本發明之·申請專利範圍；凡其它未脱離本發明所揭示之 精神下所完成之等效改變或修飾，均應包含在下述之申請 專利範圍内β 本紙張尺度適用中困國家標準（CNS-) Α4規格（2!0Χ297公釐） (請先閣讀背面之·./.£.意事項再填寫本頁)A7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 4 3 4 y B7 V. Description of the invention () Field electric field, increase the efficiency of electron flow injection, reduce the charge capture rate and increase the charge collapse. By adopting the tunneling oxide layer 18 having a rough surface, the same tunneling current can be achieved under a condition that the area of the tunneling structure is smaller than that of a conventional tunneling structure, so that a non-volatile memory with high density and high operating speed can be manufactured. The above description is only the preferred embodiments of the present invention, and is not intended to limit the scope of the invention and patent application; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention shall include Within the scope of the following patent application β This paper size is applicable to the National Standard for Difficulties (CNS-) Α4 specification (2! 0 × 297 mm) (Please read the ../.£. Notice on the back before filling out this page)