TW434775B - Failure mode analysis method of automatic wafer test - Google Patents

Abstract

The present invention relates to an automatic failure mode analysis device and method for performing parametric tests to wafer products in a semiconductor manufacturing process. The failure mode analysis device can receive N test results obtained from sampling and performing N test items to the wafers in one lot. The N test results is expressed by an N-order test result vector, wherein the I-th element of the test result vector represents a failure ratio of the I-th test item. Then the N-order test result vector is multiplied with one NxN-order transform matrix in the failure mode analysis device to obtain a N-order failure mode vector, wherein the I-th element of the failure mode vector represents a ratio of the I-th failure mode. With the device and method, it is able to expand the features of assembling analysis and failure cause to products of all lots, thereby compiling a statistical and comprehensive data, and obtaining the correlation of the functional failure mode, including the cause of the manufacturing machine, the wafer and the lot.

Description

經濟部中央標準局貝工消费合作社印裝 434775 2831twf.doc/006 A 7 i?7 五、發明説明（/ ) 本發明是有關於一種失敗模式辨識裝置與方法，且特 別是有關於一種在半導體製程中，對晶圓產品進行之晶圓 合格測試(Wafer Acceptance Test，簡稱WAT)之自動化失敗 模式辨識裝置與方法。 在半導體製程中，有許多因素影響製造出來的產品是 否可用，因此在設計電路時，必需考慮配合生產完成後的 測試需求，預先加入測試點或測試結構，當晶圓製造完成 後，根據預訂的測試項目進行WAT之數據測試，由測試 的結果可評估在製程中可能發生的問題。但是因爲產品的 數量很多，對每一個成品做完所有的測試項目是不切實際 的1 一個較好的做法是在每一個批次(lot)的產品中做抽樣 測試，即在一個批次的產品中抽選出一定比例的樣品，進 行所有項目的測試，再依據測試結果分析在製程中可能發 生的問題，並且使用統計的方法將結果推展至同一批次的 所有產品上。 切口測試結構(kerf macro)是評估方法的一種，其方式 是在晶圓上的晶粒（dice)間的切口加上數據測試用的結 構，如此可有效利用晶圓面積，而不會佔用生產出來的晶 片面積。收集與評估由使用切口測試結構進行晶圓合格測 試所得的數據測試資料(parametric test data)是診斷生產線 的健全性（health-of-line)及鑑別製程失敗的關鍵性步驟。 WAT資料亦是提供關於功能性測試的失誤分析的必要補充 資料。 切口測試結構的原則是在所有的產品批次中抽樣做數 本紙張尺度適用中囷國家標準（CNS ) Λ4规拮（2丨0X29h>^ ) 、ys T务 (锖先閱讀背面之注意事項再填寫本頁)Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative, 434775 2831twf.doc / 006 A 7 i? 7 V. Description of the Invention (/) The present invention relates to a device and method for identifying failure modes, and in particular, to a device for identifying failure modes. In the manufacturing process, an automatic failure mode identification device and method for wafer acceptance test (Wafer Acceptance Test, WAT for short) performed on wafer products. In the semiconductor process, there are many factors that affect the availability of the manufactured product. Therefore, when designing the circuit, you must consider the test requirements after the production is completed, and add test points or test structures in advance. When the wafer manufacturing is completed, The test items are WAT data tests. The test results can evaluate the problems that may occur during the manufacturing process. However, because of the large number of products, it is impractical to complete all the test items for each finished product. 1 A good practice is to conduct sampling tests in each lot of products, that is, in a batch. A certain percentage of samples are selected from the product, all items are tested, and the problems that may occur during the process are analyzed according to the test results, and the results are pushed to all products in the same batch using statistical methods. Kerf macro is a kind of evaluation method. The method is to add a structure for data testing to the notch between the dice on the wafer, so that the wafer area can be effectively used without occupying production. The area of the wafer coming out. Collecting and evaluating parametric test data obtained from wafer qualification tests using nick test structures is a critical step in diagnosing the health-of-line of the production line and identifying process failures. WAT data is also necessary to provide supplementary information on the analysis of errors in functional tests. The principle of the notch test structure is to sample several papers in all product batches. Paper standards are applicable to the national standard (CNS) Λ4 regulations (2 丨 0X29h > ^), ys T service (锖 read the precautions on the back before reading) (Fill in this page)

經濟部中央榡準局另工消费合作社印製 4347?| 2831twf.doc/006 A7 B7 五、發明説明（2) 據測試，然後將結果延伸至所有的情況。然而因爲在生產 線上所得的資料數量極爲龐大，因此只有少數的資料可由 數據測試工程師做詳細的分析》並且在一般實際的狀況 下，只追蹤每一個別測試項目的趨勢，而沒有評估整個測 試平均中的失敗組合，但是組合的失敗模式(pattern)通常 可以明顯地指出特殊的製程錯誤，甚至，在許多情形中， 測試項目還可以彼此過濾。 綜合上述之討論*可知習知由數據測試工程師分析的 做法，有下列之缺點： 1. 只針對單一測試項目的問題做追蹤，無法充分利用 測試所得的資料。 2. 無法由測試所得的資料和生產的機台、晶圓、及生 產的批次做關聯性的分析。 3. 無法利用數學性的工具，把資料做更充分的應用。 因此本發明的主要目的就是在提供一種自動化晶圓測 試之失敗模式辨識裝置及方法，可以把組合分析及失敗原 因特性擴展到所有的產品批次(lot)，並且可以彙編出統計 的綜觀資料，以及得到功能性失敗模式的相關性，包括對 於生產機台、晶圓、及批次的基礎，因而可以增進得到的 WAT資料的利用性，是一個能加強生產的強大工具。 爲達成本發明之上述和其他目的，本發明提出一種自 動化晶圓測試之失敗模式辨識裝置及方法，該失敗模式辨 識裝置可接受針對一批次晶圓抽樣進行N個測試項目所得 的N個測試結果，經過該失敗模式辨識裝置處理後輸出一 本紙張尺度適用中固國家標準（CNS ) Λ4規格（2IOX297公餘） I — — —-J.——(l· 裝------訂.---(線 (婧先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局負工消费合作社印製 434775 2831twf,d〇c/006 A7 Η 7 五、發明説明（>) 以一失敗模式爲基底的辨識結果。 該失敗模式辨識裝置之處理方法爲在接受該N個測試 結果後’先將該N個測試結果以一N階測試結果向量表示， 其中該測試結果向量的第i個元素表示第i個測試項目的 失敗比例，然後將該N階測試結果向量與該失敗模式辨識 裝置內部之一 ΝχΝ階轉換矩陣相乘，得到N階之失敗模 式向量’其中該失敗模式向量的第i個元素表示第i個失 敗模式的比例，該失敗模式向量即該辨識結果。 依照本發明的一較佳實施例，該失敗模式辨識裝置更 可接受一失敗模式設定之輸入，用以設定該轉換矩陣。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂’下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 第1圖是WAT數據測試所得的失敗頻譜。 第2A圖及第2B圖是第1圖之失敗頻譜的其中兩個次 頻譜。 第3圖是以失敗模式爲基底的頻譜。 第4圖是一個三維空間的向量轉換的例子。 第5圖是5x5的轉換矩陣與5階失敗向量相乘的例子。 第6圖是本發明之失敗模式辨識裝置的方塊示意圖。 第7圖是本發明之失敗模式辨識方法的流程示意圖。 第8圖是DRAM晶圓測試例子的真値表的一部份。 本紙張尺度適用中國國家梯準（CNS ) Λ4规播（2丨OX 297公龄） ---；--l-r---^ 1裝------訂^-------、線 (誚先閲讀背面之注項再填寫本頁) 經濟部中央標準局貞工消费合作社印狀 4347?§ 2831twf .doc/006 A 7 B7 五、發明説明（¥ ) 圖式中標示之簡單說明： 60失敗模式辨識裝置 較佳實施例 對於一批次產品進行N個測試項目的WAT數據測試， 以一固定序列安排由該N個測試項目所得的測試失敗率的 百分比，以該N個測試項目爲橫軸，各測試項目的失敗率 爲縱軸畫出一圖形，可以當作此一批次産品的失敗頻譜(fail spectrum)，此一失敗頻譜請參照第1圖所示，此一失敗頻 譜代表此一批次的整體之測試數據之狀態，分析的目的是 要將頻譜分離出個別製程的問題。 根據切口測試結構的定義，一個特殊的製程問題會導 致一個特定組合的失敗峰値，此可以當成次頻譜（sub-spectnim)。因此針對一個特殊的製程問題，可分離出一個 次頻譜，而此製程問題則當成一個失敗模式(fail pattern)， 若有N個失敗模式，則可分離出N個次頻譜，如第2A圖 及第2B圖所繪示爲其中兩個次頻譜的圖形。因此整體的 失敗頻譜即爲所有加權的次頻譜的疊置，可表示如下： a 1 .pat 1+a2 .pat2+…+aN.patN =整體失敗頻譜 其中patl至patN表示N個失敗模式，al至aN則裹 N個失敗模式對整體失敗頻譜的貢獻，亦即其加係數。 把以測試項目爲基底的失敗頻譜轉換成以失敗模式爲 基底(basis)的頻譜，可更容易的找出製程上的問題，如第 3圖所示爲一個以失敗模式爲基底的頻譜圖形 本紙張尺度適用中國國家標準（CNS U视格（210X297公势） ---^—y---ί 裝------Irl·—.---漆 {請先閱讀背面之注意事項再填寫本頁) 434771 2831twf.doc/006 A7 B7 五、發明説明（ί) 因此自動化晶圓測試之模識辨識方法的目的即是將以 測試項目爲基底的頻譜轉換爲以失敗模式爲基底的頻譜圖 形’可容易地看出每一單位次頻譜對整個失敗頻譜的貢 獻’此過程正如一個頻譜分析儀的工作，一個很好的比喻 是質譜儀可將質譜分離出個別分子物體的分離頻譜。 從數學的角度來看，一個失敗頻譜可視爲N維空間的 一個向量，失敗的百分比即爲其係數，而單獨的一個測試 項目則視爲一卡氏座標的單位向量(unit vector)，失敗特徵 模式(characteristic fail pattern)可以視爲轉換的卡式座標的 基底向量(base vector)，失敗模式辨識裝置即是將失敗頻譜 的向量投影在失敗特徵模式的基底(base)上。當定義出失 敗模式後，轉換的工作即成爲簡單的矩陣運算，可以簡單 地應用在所有的原始資料，測試分析專家或工程師要做的 工作就只剩定義失敗模式的定義，要定義失敗模式，可利 用失敗模式與實際失敗分析結果之相關性來完成。 經濟部中央標準局員工消費合作社印製 (讀先閱讀背面之注意事項再填寫本頁) 如第4圖所示爲一個三維空間的向量轉換的例子，單 位向量[100]、[010]、及[001]爲三度空間的卡式座標的單 位向量，此三個向量對應到三個測試項目，則從三個測試 項目所得的結果可以得到一個組合的向量P。若以23、 及C代表失敗模式的基底向量，則自動化失敗模式辨識裝 置與方法之目的即是要將向量f投影至gi、及^之新的 單位向量上，並分別得到係數a、b、及C，此三個係數表 示每個失敗模式對整體測試結果的貢獻，亦即實際生產線 的某個製程因素對產品良率的影響。因此向量P可表示爲 本紙張尺度通用中固國家標準（CNS ) Αϋ規格（2丨0X297公龄） 經濟部中央標準局另工消费合作社印裝 434??! 2831twf.doc/006 A7 B7 五、發明説明（6)Printed by the Central Bureau of Standards of the Ministry of Economic Affairs and other consumer cooperatives 4347? | 2831twf.doc / 006 A7 B7 V. Description of the invention (2) According to the test, the results are extended to all cases. However, because the amount of data obtained on the production line is extremely large, only a small amount of data can be analyzed in detail by the data testing engineer. In general, only the trend of each individual test item is tracked without evaluating the entire test average Combination of failures, but the combination of failure patterns (patterns) can usually clearly point out special process errors, and even, in many cases, test items can be filtered from each other. Based on the above discussion *, it is known that the practice of data analysis by the data test engineer has the following disadvantages: 1. It only tracks the problems of a single test item, and cannot make full use of the data obtained from the test. 2. It is impossible to analyze the correlation between the data obtained from the test and the machine, wafer, and batch produced. 3. Unable to use mathematical tools to make fuller use of data. Therefore, the main purpose of the present invention is to provide an automatic wafer test failure mode identification device and method, which can expand the combination analysis and failure cause characteristics to all product lots, and can compile statistical comprehensive data, And to get the correlation of functional failure modes, including the basis for production equipment, wafers, and batches, so that the availability of the WAT data obtained can be improved, and it is a powerful tool that can strengthen production. In order to achieve the above and other objectives of the invention, the present invention proposes a failure mode identification device and method for automated wafer testing. The failure mode identification device can accept N tests obtained by performing N test items on a batch of wafer samples. As a result, after processing by the failure mode recognition device, a paper size is output to apply the National Solid State Standard (CNS) Λ4 specification (2IOX297 public) I — — — —J .—— (l · 装 ———— Order .--- (Line (Jing first read the notes on the back and then fill out this page) Printed by the Central Standards Bureau of the Ministry of Economic Affairs and Consumer Cooperatives 434775 2831twf, doc / 006 A7 Η 7 V. Description of the Invention (>) A failure mode is the identification result of the base. The processing method of the failure mode identification device is to 'represent the N test results by an N-th order test result vector after receiving the N test results, where the first The i element represents the failure ratio of the i-th test item, and then the N-th order test result vector is multiplied by an N × N-th order transformation matrix inside the failure mode identification device to obtain an N-th order failure mode vector. The i-th element of the failure mode vector represents the proportion of the i-th failure mode, and the failure mode vector is the recognition result. According to a preferred embodiment of the present invention, the failure mode recognition device can further accept a failure mode setting. The input is used to set the transformation matrix. In order to make the above and other objects, features, and advantages of the present invention more obvious and understandable, a preferred embodiment is given below, and will be described in detail with the accompanying drawings as follows : Brief description of the figure: Figure 1 is the failed spectrum obtained from the WAT data test. Figures 2A and 2B are two sub-spectrums of the failed spectrum of Figure 1. Figure 3 is based on the failure mode. Spectrum. Figure 4 is an example of vector transformation in a three-dimensional space. Figure 5 is an example of a 5x5 transformation matrix multiplied by a fifth-order failure vector. Figure 6 is a block diagram of the failure mode identification device of the present invention. The diagram is a schematic flow chart of the failure mode identification method of the present invention. Fig. 8 is a part of the authenticity table of the DRAM wafer test example. This paper standard is applicable to the Chinese National Standard (CNS) Λ4 regulation. Broadcast (2 丨 OX 297 males) ---; --lr --- ^ 1 pack ------ order ^ -------, line (诮 first read the note on the back before filling in this Page) Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Zhengong Consumer Cooperative, 4347? § 2831twf .doc / 006 A 7 B7 V. Description of the invention (¥) A brief description marked in the drawing: 60. Batch products are tested for WAT data of N test items, and the percentage of test failure rates obtained from the N test items is arranged in a fixed sequence. The N test items are used as the horizontal axis, and the failure rate of each test item is reported as A graph is drawn on the axis, which can be used as the fail spectrum of this batch of products. Please refer to Figure 1 for this failed spectrum. This failed spectrum represents the status of the overall test data of this batch. The purpose of the analysis is to separate the spectrum from the problems of individual processes. According to the definition of the notch test structure, a special process problem will cause a specific combination of failure peaks, which can be regarded as sub-spectnim. Therefore, for a special process problem, a sub-spectrum can be separated, and this process problem can be regarded as a fail pattern. If there are N failure modes, N sub-spectrums can be separated, as shown in Figure 2A and Figure 2B shows two graphs of the sub-spectrum. Therefore, the overall failure spectrum is the superposition of all weighted sub-spectrums, which can be expressed as follows: a 1 .pat 1 + a2 .pat2 + ... + aN.patN = overall failure spectrum where patl to patN represent N failure modes, and al to aN is the contribution of N failure modes to the overall failure spectrum, that is, its addition coefficient. Converting the failed spectrum based on the test item into the spectrum based on the failure mode can more easily identify the process problems. As shown in Figure 3, a spectrum chart based on the failure mode is shown. Paper size applies to Chinese National Standards (CNS U Vision grid (210X297 public power) --- ^ — y --- ί Loading ------ Irl · —.--- Lacquer {Please read the precautions on the back first (Fill in this page) 434771 2831twf.doc / 006 A7 B7 V. Description of Invention (ί) Therefore, the purpose of the method for identifying patterns in automated wafer testing is to convert the spectrum based on the test items into the spectrum based on the failure mode. The graph 'can easily see the contribution of each unit spectrum to the entire failed spectrum' This process is just like the work of a spectrum analyzer. A good analogy is that the mass spectrometer can separate the mass spectrum into the separated spectrum of individual molecular objects. From a mathematical point of view, a failure spectrum can be regarded as a vector in N-dimensional space, and the percentage of failure is its coefficient, and a single test item is regarded as a unit vector of the Karst coordinate. The failure feature The pattern (characteristic fail pattern) can be regarded as the base vector of the transformed card-type coordinates. The failure pattern recognition device projects the vector of the failure spectrum onto the base of the failure characteristic pattern. After the failure mode is defined, the conversion work becomes a simple matrix operation, which can be simply applied to all the original data. The work of the test analysis expert or engineer is only to define the definition of the failure mode. To define the failure mode, This can be done using the correlation between the failure mode and the actual failure analysis results. Printed by the Employees' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (read the precautions on the back before filling this page). Figure 4 shows an example of vector transformation in three-dimensional space. The unit vectors are [100], [010], and [001] is a unit vector of card-shaped coordinates in a three-dimensional space, and the three vectors correspond to three test items, and a combined vector P can be obtained from the results obtained from the three test items. If 23, and C are the basis vectors of the failure mode, the purpose of the automatic failure mode identification device and method is to project the vector f onto the new unit vectors of gi and ^, and obtain the coefficients a, b, and And C, these three coefficients represent the contribution of each failure mode to the overall test result, that is, the impact of a certain process factor of the actual production line on the product yield. Therefore, the vector P can be expressed as the common solid state national standard (CNS) Αϋ size (2 丨 0X297-year-old) of the paper standard. The central standard bureau of the Ministry of Economic Affairs prints 434 ?? 2831twf.doc / 006 A7 B7 V. Invention Description (6)

F ^a A-^b-B+C'C 以技術來實現，在測試過程中，進行N個測試項目， 得到的N個測試結果可以用N階的測試結果向量表示，其 中測試結果向量的第η個係數代表第η個測試項目的失敗 的百分比。 然後根據實際的製程，定義Ν個代表失敗模式的單位 向量’這些失敗模式代表新的基底向量，在定義的失敗模 式中’某些失敗模式可以與測試項目相同》 基本上，分離的過程即是將由以測試項目爲基底的測 試結果向夏轉換成以失敗模式爲基底的失敗模式向量。 在實際轉換的技術上，這只是一個Ν階向量與大小爲 ΝχΝ的矩陣之相乘運算，完全沒有用如類神經網路(neural network)這一類複雜的運算，可以快速地直接由數値運算 得到所需的結果。 因此，N個測試項目的失敗百分比可當成一個向量， 而將代表整體的失敗頻譜轉換成以失敗模式爲基底的向 量’可經由簡單的矩陣相乘運算。例如向量F代表以測試 項目爲基底的測試結果，要轉換爲以失敗模式爲基底的向 量p，可以用下式表示：F ^ a A- ^ b-B + C'C is implemented by technology. During the test process, N test items are performed, and the N test results obtained can be represented by a test result vector of order N. Among the test result vectors, The nth coefficient represents the percentage failure of the nth test item. Then according to the actual process, define N unit vectors representing failure modes. These failure modes represent new base vectors. In the defined failure modes, some failure modes can be the same as the test items. Basically, the separation process is The test result based on the test item is transformed into a failure mode vector based on the failure mode. In terms of actual conversion technology, this is just a multiplication operation of an N-th order vector and a matrix of size χχΝ. It does not use complex operations such as neural networks, and can be directly and directly operated by numbers. Get the desired result. Therefore, the failure percentage of the N test items can be regarded as a vector, and the failure spectrum representing the whole can be converted into a vector based on the failure mode 'through a simple matrix multiplication operation. For example, the vector F represents the test result based on the test item. To convert to the vector p based on the failure mode, it can be expressed by the following formula:

P=T xF 其中矩陣T爲轉換矩陣，代表實際的測試項目與製程 失誤之關係。轉換矩陣Τ爲一由單位向量組成的稀疏矩陣， 即其中的兀素不是〇即是1兩種値，而矩陣中爲1的元素 較少。如第5圖所示爲此轉換的實際例子，此例中以5x5 本紙張尺度適用中國國家樣準（CNS ) Λ4说格（2丨OX297公ι ) ---M· J---.---L 裝------訂--ι.---^球 (諳先閱讀背面之注意事項再填寫本頁) 434775 2831twf *d〇c/006 A7 B7 經濟部中央標隼局貝工消费合作社印製 五、發明説明（7) 的轉換矩陣爲例，即由5個測試項目得到測試的代表失敗 率的失敗向量F爲[0.2,0,0.4,0,0.1]，經矩陣運算與轉換矩 陣T相乘後，可得到以失敗模式爲基底的轉換向量p爲 [0.2,0,0,0,0.3]。 如第6圖所示，爲本發明之自動化晶圓測試之失敗模 式辨識裝置的一較佳實施例的方塊示意圖，失敗模示辨識 裝置60可接受測試結果所得的測試數據’此測試數據是 一組代表所有測試項目的失敗百分比的數據’失敗模示辨 識裝置60中主要的功能即是將輸入之測試數據做處理， 以得到一辨識結果，其處理過程即是前述之矩陣相乘運 算，得到的辨識結果則是以失敗模式爲基底的數據，可供 分析製程上可能的潛在問題。失敗模示辨識裝置60可接 受失敗模式設定，此功能是來設定失敗模示辨識裝置60 的轉換矩陣的內容，例如根據測試項目改變矩陣的維度， 以及針對不同的產品或生產流程’分別設定特定的轉換矩 陣。 如第7圖所示，爲本發明之自動化晶圓測試之失敗模 式辨識方法的一較佳實施例的流程示意圖。 開始之後，在步驟71中，針對一個生產的晶圓進行 既定的測試項目。 在步驟72中，由測試項目中得到各項目的失敗百分 比，將此測試結果以一測試結果向量表示，向量中的係數 分別爲對應之測試項目之測試結果的失敗百分比。 在步驟73中，將代表測試結果的測試結果向量送至 (請先閲讀背面之注意事項再填寫本頁) -裝. 訂 f線 本紙張尺度適用中國困家栋準（CNS ) Λ4说格（210X297公贷） 經濟部中央標率局員工消费合作社印梨 434W§ 2831twf.doc/006 A7 B7 五、發明説明（y ) 失敗模式辨識裝置60，以進行向量之轉換，此轉換方法使 用前述之矩陣相乘方法。在進行轉換之前，已根據實際的 測試項目及失敗模式的關係，由測試專家或工程師完成設 定轉換矩陣的內容。 在步驟74中，爲由失敗模式辨識裝置60得到以失敗 模式爲基底的失敗模式向量，以供分析。 在步驟75中，根據得到的失敗模式向量，由專家或 負責的工程師分析製程中可能的問題，並依照分析的結果 改善製程的問題，以提高成品的良率。 根據以上之討論，當測試分析方面的專家根據預定的 測試項目及製程上的問題，設定好轉換矩陣，供失敗模式 辨識裝置或方法使用，在實際測試時，按照各個測試項目 進行測試所得的結果，將每個測試項目的不良率以向量表 示，將此向量與轉換矩陣相乘，即可轉換成以失敗模式爲 基底的向量，可分析在製造過程中，那一個製程步驟的產 品不良率的影響最大，可據以改善製程。下面即以一例子 解說本發明之實際應用。 這個晶圓測試之失敗模式分析的應用實例是根據一個 動態隨機存取記憶體(Dynamic Random Access Memory，簡 稱DRAM)之測試例子，在此晶圓上使用寬廣切口（wide kerf)，可供加上用來進行廣泛數據測試的測試結構。 在此DRAM晶圓上的寬廣切口上進行數據測試主要是 用來鑑別在第一金屬化層（first metallization layer，或稱 Metal 0，簡稱M0)下方的連線端結構（front-end-of-line 本紙張尺度適用中國國家栋準（CNS ) A4規格{ 2丨) (請先閱讀背而之注^^項再填寫本頁) • ------訂 ---------線 經濟部中央標率局負工消费合作社印裂 434776 2831twf.d〇c/006 A7 B7 五、發明説明（7) structure)間的短路、漏電、及開路。這是由所謂的缺陷陣 歹[Rdefect array)來完成，缺陷陣列是一個不能工作而具有 類似胞陣列（cell array)的結構，在其上可進行簡單的直流 數據測試，用以判斷短路或開路。可設計不同的缺陷陣列， 每個不同的缺陷陣列省略一些不同的結構，用以縮小失敗 主因的範圍。在缺陷陣列上具有呈曲線形及梳狀結構的導 電層，即M0及MOSFET之閘極接觸點(Gate Contact，簡 稱GC)，在這些導電層上，簡單地以直流測量其導通的電 流對電壓特性曲線。當由曲線形導線之一端到另一端的電 流被阻斷時，表示其爲開路(open)，在曲線形導線與梳形 導線間之電流超過一本質漏電流(intrinsic leakage)極限時， 則表示其爲短路(short)，同時由一施偏壓(bias)結構與接地 周圍間的導通情形來測量整合的漏電，並改變偏壓的極性 用來測試二極體(diode)效應。 缺陷陣列可依結構組成的不同分成四種形式，所有的 測試都是在此四種形式的缺陷陣列上重覆進行。此四種形 式之區分如下： 第一種形式是沒有CD(Contact to Diffusion)及 SS(Surface Strap)，其中CD是指接觸至位元線及胞電晶體 汲極擴散之間，SS是指接觸至胞電晶體源極擴散及溝渠儲 存電容器之多晶矽接觸點； 第二種形式是有CD而沒有SS ; 第三種形式是沒有CD而有SS ;以及 第四種形式是兼有CD及SS。 本紙張尺度適用中國國家標準（CNS)A4規你（2丨0X2W公梦） * - i ----I --- n ΙΊ V --- ---—r n —r --- (請先閲讀背面之注項再填寫本頁) 2831twf. doc/006 A7 B7 經濟部中央標準局员工消费合作社印聚 五、發明説明（/0) 以上的測試是在CD或SS存在或不存在的情況下，測 試其與CD與SS間爲開路或短路，同樣的，可將gc層設 定爲高電位或低電位*以進行M0至M0之相關測試;是;^ 導通。 依據測試項目及測試條件的組合，即可建立真値表 (truth table)，亦即將特殊的製程失敗因素對應至某些測試 結果。如第8圖所示，爲此DRAM測試例子的真値表的— 部份。在圖中的真値表中，每一列爲一個測試項目，在測 試項目之後的括弧中爲測試條件，以“+”表示正的偏壓， 表示負的偏壓’ GC設定爲高電位則註記爲“0N”。 每一行對應一個製程失敗因素，行列之交叉處以“x”表示 一個預期的失敗，其意義爲當一個測試項目爲失敗，在該 測試項目那一列的空格中有註記“X”的對應製程失敗因素 皆有可能引起此項測試項目失敗，而相對的，一個製程失 敗因素成立時，在該製程失敗那一行的空格中有註記“X” 的對應測試項目在進行測試時，都應得到失敗的結果。例 如，在真値表中的第8個測試項目爲“GC至全部(·)” ， 按表中“X”的註記可知，會引起這個測試項目失敗的製程 失敗因素有“閘Ox崩潰”、“GC至GC短路(在模式時造 成的)”' 以及“GC至M0直接短路”等，相對的，在表 中的第6個製程失敗因素爲“GC至CD短路(整流性或二 極體性）”，若這個製程失敗因素造成的失敗，將在“GC 至全部(-，SS，CD)”及“GC至全部(-’ CD)”這兩個測試 項目得到失敗的結果，在其他測試項目則爲正常。 (請先閲讀背面之注意事項再填寫本頁) jA|裝_P = T xF where matrix T is the transformation matrix, which represents the relationship between the actual test items and process errors. The transformation matrix T is a sparse matrix composed of unit vectors, that is, the elements in it are either 0 or 1, and there are fewer elements with 1 in the matrix. A practical example of this conversion is shown in Figure 5. In this example, the Chinese National Standard (CNS) Λ4 Grid (2 丨 OX297) is applied to the 5x5 paper size --- M · J ---.- --L Pack ------ Order --ι .--- ^ ball (read the precautions on the back before filling this page) 434775 2831twf * d〇c / 006 A7 B7 Central Bureau of Standards, Ministry of Economic Affairs Printed by the Industrial and Consumer Cooperatives. 5. The transformation matrix of the invention description (7) is taken as an example, that is, the failure vector F representing the failure rate obtained from 5 test items is [0.2,0,0.4,0,0.1], which is calculated by the matrix. After multiplying with the transformation matrix T, the transformation vector p based on the failure mode can be obtained as [0.2,0,0,0,0.3]. As shown in FIG. 6, it is a block diagram of a preferred embodiment of a failure mode identification device for an automated wafer test of the present invention. The failure mode identification device 60 may accept test data obtained from the test results. The test data is a The group of data representing the percentage of failures of all test items. The main function of the failure mode identification device 60 is to process the input test data to obtain an identification result, and the processing process is the aforementioned matrix multiplication operation to obtain The identification results are based on failure mode data, which can be used to analyze potential problems in the process. The failure mode identification device 60 can accept the failure mode setting. This function is used to set the content of the conversion matrix of the failure mode identification device 60, such as changing the dimensions of the matrix according to the test items, and setting specific settings for different products or production processes. Transformation matrix. As shown in FIG. 7, it is a schematic flowchart of a preferred embodiment of a method for identifying a failure mode of an automated wafer test of the present invention. After the start, in step 71, a predetermined test item is performed for a production wafer. In step 72, the failure percentage of each item is obtained from the test items, and the test result is represented by a test result vector, and the coefficients in the vector are the failure percentages of the corresponding test items. In step 73, the test result vector representing the test result is sent to (please read the precautions on the back before filling out this page)-binding. The f-line paper size is applicable to the Chinese Standard for Homelessness (CNS) Λ4 saying grid ( 210X297 public loan) Employees' Cooperatives of the Central Standards Bureau, Ministry of Economic Affairs, Consumer Cooperatives, India 434W§ 2831twf.doc / 006 A7 B7 V. Description of the Invention (y) Failure mode identification device 60 for vector conversion. This conversion method uses the aforementioned matrix Multiplication method. Before the conversion, according to the relationship between the actual test items and the failure mode, the content of the conversion matrix is set by the test expert or engineer. In step 74, a failure mode vector based on the failure mode is obtained by the failure mode identification device 60 for analysis. In step 75, according to the obtained failure mode vector, an expert or a responsible engineer analyzes a possible problem in the manufacturing process, and improves the manufacturing process according to the analysis result, so as to improve the yield of the finished product. According to the discussion above, when the experts in test analysis set up a conversion matrix for the failure mode identification device or method according to the predetermined test items and process problems, in actual testing, the test results are obtained according to each test item. , The defect rate of each test item is represented by a vector, and this vector is multiplied with a transformation matrix to convert it into a vector based on the failure mode. It can analyze the product defect rate of that process step in the manufacturing process. The greatest impact can be used to improve the process. The following illustrates the practical application of the present invention with an example. The application example of the failure mode analysis of the wafer test is based on a test example of Dynamic Random Access Memory (DRAM). A wide kerf is used on this wafer, which can be added. Test structure for extensive data testing. Data testing on a wide cut on this DRAM wafer is mainly used to identify the front-end-of-connection structure under the first metallization layer (or Metal 0, M0 for short). line This paper size is applicable to China National Building Standard (CNS) A4 specification {2 丨) (Please read the back note ^^ before filling this page) • ------ Order -------- -The Central Laboratories of the Ministry of Economic Affairs, Central Labor Bureau, Consumer Cooperative Cooperative, printed 434776 2831twf.doc / 006 A7 B7 V. Description of the invention (7) Short circuit, leakage, and open circuit between structures). This is done by the so-called defect array (Rdefect array). A defect array is a structure that does not work and has a similar cell array. A simple DC data test can be performed on it to determine a short circuit or an open circuit. . Different defect arrays can be designed. Each different defect array omits some different structures to reduce the scope of the main cause of failure. The defect array has a curved and comb-shaped conductive layer, that is, the gate contact point (Gate Contact, GC for short) of M0 and the MOSFET. On these conductive layers, the conducting current versus voltage is simply measured by direct current. Characteristic curve. When the current from one end to the other end of the curved wire is blocked, it means that it is open. When the current between the curved wire and the comb wire exceeds an intrinsic leakage limit, it means It is a short circuit. At the same time, the integrated leakage current is measured by a conducting condition between the bias structure and the surrounding ground, and the polarity of the bias is changed to test the diode effect. The defect array can be divided into four types according to the structure composition. All tests are repeated on these four types of defect arrays. The difference between the four forms is as follows: The first form is without CD (Contact to Diffusion) and SS (Surface Strap), where CD refers to the contact between the bit line and the drain diffusion of the cell crystal, and SS refers to contact Polycrystalline silicon contact point to cell transistor source diffusion and trench storage capacitor; the second form is without CD and SS; the third form is without CD and SS; and the fourth form is both CD and SS. This paper size applies to China National Standard (CNS) A4 regulations (2 丨 0X2W public dream) *-i ---- I --- n ΙΊ V --- ----- rn --r --- (please Read the note on the back and fill in this page) 2831twf. Doc / 006 A7 B7 Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of Invention (/ 0) The above tests are performed in the presence or absence of CD or SS , Test it to be open or short between CD and SS. Similarly, the gc layer can be set to high or low potential * for M0 to M0 related tests; yes; ^ conductive. Based on the combination of test items and test conditions, a truth table can be established, and special process failure factors are mapped to certain test results. As shown in Figure 8, this is part of the truth table of the DRAM test example. In the truth table in the figure, each column is a test item, and the brackets after the test item are the test conditions. "+" Indicates a positive bias voltage, which indicates a negative bias voltage. "0N". Each row corresponds to a process failure factor, and the intersection of the rows with "x" indicates an expected failure, which means that when a test item is a failure, there is a corresponding process failure factor marked "X" in the space of the column of the test item All of them may cause this test item to fail. In contrast, when a process failure factor is established, corresponding test items marked with an “X” in the blank space of the line where the process fails should receive a failure result when tested. . For example, the 8th test item in the Shinji table is "GC to all (·)". According to the note of "X" in the table, it can be known that the process failure factors that cause this test item to fail are "gate Ox crash", "GC to GC short circuit (caused in the mode)" and "GC to M0 direct short circuit" and so on. In contrast, the sixth process failure factor in the table is "GC to CD short circuit (rectifier or diode) "), If the failure caused by this process failure factor, failure results will be obtained in the" GC to all (-, SS, CD) "and" GC to all (-'CD) "test items, in other The test items are normal. (Please read the notes on the back before filling this page) jA | 装 _

/1T/ 1T

A 本紙浪尺度適用中困國家標準（CNS )A4規格（210XN7公处） 經濟部中戎標準局員工消费合作社印製A The paper scale is applicable to the National Standard for Difficulties (CNS) A4 specification (210XN7 public office) Printed by the Consumer Cooperative of Zhongrong Standards Bureau, Ministry of Economic Affairs

S 2 8 3 11 wf * doc / 0 0 6 A7 B7 五、發明説明（/ί ) 根據測試項目及製程失敗因素建立的真値表等於是單 位失敗向量的集合，由此真値表可直接建立轉換矩陣，在 實際測試時，只要將由所有測試項目得到的失敗向量，經 由上述的先敗模式辨識裝置或方法，得到以失敗模式爲基 底的向量，亦即從製程失敗因素的角度來分析所得的測試 結果。以上所述之缺陷陣列的範例只是實際的單位失敗向 量的部份集合而已，要建立整個轉換矩陣還必須考慮完整 的晶圓測試過程。 因此，根據上述的裝置及方法，當一批次半導體之晶 圓完成之後，按照預定的測試項目進行各種測試，得到由 各測試項目的失敗百分比所組成的測試結果向量，經由以 上所述之本發明之自動化晶圓測試之失敗模式辨識裝置及 方法，可將測試結果向量轉換爲以失敗模式爲基底的失敗 模式向量，亦即將每一個製程失敗因素對此一批次晶圓失 敗的影響分離出來，此亦爲整批產品的統計性綜觀資料， 測試專家或工程師可以很容易的得知此一批次產品的特 性，亦可在失敗因素與生產機台、晶圓材料、及批次之間 找出其關聯性，藉以分析何者對產品的品質造成最大的影 響。 從以上之討論，可知本發明之自動化晶圓測試之失敗 模式辨識裝置及方法習知作法比較，具有下列優點： 1. 可以把組合分析及失敗原因特性擴展到所有的產品 批次(lot)。 2. 彙編出統計的綜觀資料》 本紙張尺度逋用中國國家標车（CNS ) Λ4規格（2丨ΟΧ297公系} (請先閱讀背面之注意事項再填寫本頁)S 2 8 3 11 wf * doc / 0 0 6 A7 B7 V. Description of the invention (/ ί) The truth table created according to the test items and process failure factors is equal to the set of unit failure vectors, so the truth table can be created directly The conversion matrix, in actual testing, as long as the failure vectors obtained from all the test items are passed through the pre-failure pattern recognition device or method described above, a vector based on the failure mode is obtained, that is, the obtained result is analyzed from the perspective of the process failure factor Test Results. The example of the defect array described above is only a partial set of the actual unit failure vector. To establish the entire conversion matrix, a complete wafer test process must also be considered. Therefore, according to the above device and method, after a batch of semiconductor wafers is completed, various tests are performed according to predetermined test items to obtain a test result vector composed of the failure percentage of each test item. The invented automatic wafer test failure mode identification device and method can convert the test result vector into a failure mode vector based on the failure mode, that is, isolate the influence of each process failure factor on the failure of this batch of wafers This is also a statistical overview of the entire batch of products. Test experts or engineers can easily know the characteristics of this batch of products. It can also be between the failure factor and the production machine, wafer materials, and batches. Find out their relevance and analyze which has the biggest impact on the quality of the product. From the above discussion, it can be seen that the failed pattern recognition device and method comparison method of the automated wafer test of the present invention has the following advantages: 1. The combination analysis and failure cause characteristics can be extended to all product lots. 2. Compile statistics overview data "This paper uses China National Standard Vehicle (CNS) Λ4 specification (2 丨 〇297297) (Please read the precautions on the back before filling this page)

、1T Λ" 4341"? 5 2831twf *doc/006 Λ7 Η7 五、發明説明（/2) 3.可以得到功能性失敗模式的相關性，包括對於生產 機台、晶圓、.及批次的基礎。 因此可以增進得到的WAT資料的利用性，是一個能 加強生產的強大工具。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作少許之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局只工消费合作社印繁 本紙張尺度適用中國囤家標率（CNS ) Λ4規格（210 X 2们公辁）1T Λ " 4341 "? 5 2831twf * doc / 006 Λ7 Η7 V. Description of the invention (/ 2) 3. The correlation of functional failure modes can be obtained, including the basis for production equipment, wafers, and batches. . Therefore, the availability of the WAT data obtained can be enhanced, and it is a powerful tool to enhance production. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make a few changes and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. (Please read the notes on the back before filling out this page) The Central Standards Bureau of the Ministry of Economic Affairs only prints and prints on the consumer cooperatives. The paper size is applicable to the Chinese household standard rate (CNS) Λ4 specification (210 X 2 men's money)

Claims (1)

1.一種自動化晶圓測試之失敗模式辨識方法，包括下 列步驟： 對一批次晶圓抽樣進行N個測試項目所得的N個測試 結果； 將該N個測試結果以一 N階測試結果向量表示’其中 該失敗向量的第i個元素表示第i個測試項目的失敗比例； 提供一 ΝχΝ階的轉換矩陣； 將該轉換矩陣與該Ν階測試結果向量相乘得到一 Ν階 的失敗模式向量；以及 該失敗模式向量爲以一失敗模式爲基底’其中該輸出 向量的第i個元素表示第i個失敗模式的比例。 > (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）1. A method for identifying a failure pattern of an automated wafer test, comprising the following steps: N test results obtained by performing N test items on a batch of wafer samples; and expressing the N test results as an N-order test result vector 'Where the i-th element of the failure vector represents the failure ratio of the i-th test item; providing a transformation matrix of order N × N; multiplying the transformation matrix by the test result vector of the order N to obtain a failure mode vector of order N; And the failure mode vector is based on a failure mode ', where the i-th element of the output vector represents the proportion of the i-th failure mode. > (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm)