434648 A7 ________ B7 五、發明説明（） 發明背景 本發明係相關於功率金氧半導體閘極裝置，尤其 是與具有減少切換耗損之嶄新低電壓]P通道金氧半導 體。 功率金氧半導體閘極裝置爲熟知之裝置，且包含 如系統金氧半導體場效電晶體，IGBT，閘極控制整流裝 置等有關。在此裝置的低電壓應用中，尤其是應用電池 操作之可攜式電子裝置，如個人電腦，細胞式電話等， 經常被稱爲無線電系統，這些上必需進行極小心的功率 管理以擴散電池壽命且電荷之使用。 一般可將無線系統中功率管理系統的使用分爲兩 類。一爲從一外部DC源對電池充電。對於特定的電池 技術正確地控制充電電流及電壓爲一項相當重要的事 情。此項控制可由在熟知的方式中，調變功率源極及電 池之間電晶體的佔空循環完成。第二類爲動作需要系統 之一部份。在此例子中，電晶體配置在電池及將動作的 負載之間，該負載如RF功率放大器。在某些系統中， 多功率材料電壓需要DC/DC轉換。此可應用熟知的低下 降線性穩壓器或者是增壓切換穩壓器完成。 可使用上述應用中作爲電晶體之N通道及P通道 功率金氧半導體電晶體。一般P通道裝置較易在這些電 路中使用。因此，當P通道金氧半導體場效電晶體置於 功率匯流排上時，可應用在功率軌及接地之間切換的邏 輯輸入控制。此允許對於整個系統達到單一不可中斷之 接地。在功率匯流排中的N通道裝置需要一閘極信號， 增加此信號的電壓使高於該匯流排，其需要額外的電 ---. ____________ 本纸張尺度適用中國國家標準（CNS ) Λ4規格（210X 297公釐） (諳先閲讀背面之注意事項再填寫本頁) -丁 、-=a 經濟部智慧財產局員工消費合作杜印製 43464 8 A 7 __B7_ 五、發明説明（） 路。 在過去，P通道裝置的簡化將付出使耗損增加的代 價。外部P通道裝置依靠電洞導通，而在矽材料中電洞 的載體遷移率比電子低。動作電晶體的導通電阻正比於 載體的遷移率，且其耗損正比率導通電阻 Rdson 0 爲了克服此一限制，可使得電阻路徑的長度最小 化，且在電晶體內的寬度可能最小。在路徑中電洞的限 制爲達到最大。達到此其他之一方式爲儘可能地減少最 大電壓的額定値，其允許可使用更低的電阻率及具較高 摻雜濃度的矽。 因爲大部份的電池在只有幾伏特之下操作，一般對 於無線電應用而言，12V的額定値即足敷使用。先前使 用之裝置其額定値爲20V，且在閘極到源極具有相當合 理之低値電壓RDSON2.5V。這些組件來自多種晶粒帜寸 及封裝型式，其範圍從Micro3(SOT 23)到S08。列下表 中的數値係用於封裝中的單一電晶體，當然Micros及 S08封裝具有兩種'型式。使用這些裝置的功率耗損可高 達9%，其指定轉譯以減少使用。 (請先閱讀背面之注意事項再填寫本頁) 、-α 經漓部智慧財產局員工消費合作社印製 負載電流 元件編號 封裝型式 Rdson @2,5V V下降或Pdiss 5V供給當作％ 5 00mA IRLML6320 Micro3TM 0.9 Ω 9% 1 A IRLMS6702 Micro6TM 0.4 Ω 8% 2A IRF7604 Micro8TM 0.13 Q 5% 4A IRF7416 SO-8 0.035 Ω 3% 已知可應用渠道型式技術製造低電壓功率金氧半 4_ 本紙張尺度適用中國國家標準（CNS ) A4規格（2]0X 297公釐） 434648 A7 B7 展 部 智 財 產 M) ；/) 合 ii 社 印 製 五、發明説明（） 導體場效電晶體以得到減少的RDS ON，閘極到源極電容 以減少Q(閘極電荷）。切換耗損正此於裝置尺⑽⑽及Qg 的乘積，因此也需要在此裝置中減少rdson。本發明中 的P通道渠道型式功率金氧半導體場效電晶體使用具有 P通道磊晶層之P型基體。在P型源極擴散後由來自磊 晶層上表面的深N型擴.散區形成該裝置的通道區域。然 後，大部份的電壓封鎖在P型之磊晶層中，導致一相當 大的電阻下降，且因此增加無線電系統中的耗損。這些 耗損又減少電荷之間的電池壽命。 發明槪述 依據本發明，在一 P通道渠道型式的金氧半導體 閘極裝置中，去除傳統上使用的P型基體磊晶層，且由 磊晶成長的N型通道區取代擴散通道。現在通道區域具 有均勻的濃度，且相當低摻雜之通道區域允許在通道區 域的電壓被封鎖住，且減少用於導通的臨界電壓VT。因 此，應用該嶄新的'結構，可去除導通電阻的主要成份， 且在2.5伏的電壓下，可使得該裝置閘極到源極完全導 通。 當本發明中的嶄新晶粒包封在上述之表中的封裝 內時，RDS〇n及功率耗損可減少四倍，如下表所示者： i^^i- —^n ^^^^1 I - —^—^1 —i^^i 1-1- — ^^^^1 an lOJ (請先閱讀背面之注意事項再填寫本頁) 封裝型式 V下降或Pdiss 負載電流 兀件編號 [email protected] V 5 V供給當作％ 本紙張尺度適用中國國家樣隼（CNS ) A4规格（2丨0'乂297公釐〉 434648 A7 B7 明说明4~~) / V \ i _ 500mA Micro3TM 0.1 8 Ω 1.8% 1 A Micro6TM 0.07 Ω 1.5% 2A Micro8TM 0.025 Ω \% 4A SO-8 0.01 Ω 0.8% 經濟部智慧財產局負工消費合作社印製 因此，整個電路耗·損減少到小於2%。甚至在放電 電池爲2.5伏的情況下仍相同。 圖式之簡單說明 圖1爲習知型式之渠道型P通道金氧半導體場效 電晶體的單晶胞之接點圖樣的截面圖。 圖2爲與圖1類似的截面圖，但是其中顯示本發 明之接點圖樣及型式。 圖3示以圖1及2之兩金氧半導體場效電晶體的 電路圖，連接該金氧半導體場效電晶體以形成雙向導電 裝置。 圖4爲與圖4位在之截面圖，由顯示以修改的接 點圖樣，由此形成一雙向金氧半導體場效電晶體。 圖5爲圖4之雙向場效電晶體的電路圖。 圖6爲用於製造圖2之裝置之矽基體部份的上視 圖。 圖7，8，9及10顯示在進行多個處理步驟之後， 沿圖6之線7-7所視之圖6中矽的截面部份的外觀。 元件圖號說明 ^n. - I —: I I n^i -- hr—I— I _ I— -. s *T (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X297公漦） 434648 五、發明説明（） Α7 Β7 20 基體 21 p+層 22 N +通道擴散區 23，24 渠道 25 - 26 閘極氧化層 28，29 導電多晶係層 3〇 5 31 » 32，33源極區 35，36 氧化絕緣plug 40 鋁源極接點 41 汲極接點 50 缺槽 5 1 N++擴散區 60 N晶晶成長層 70，71 ’ 72，73終端 74 共用閘極端 較佳實施例之詳細說明： n ϋ n .^1 I - It - 士^―^ I I - n τ I-- (請先閱讀背面之注意事項再填寫本頁} 經濟部智慧財產局Μ工消费合作社印製 現在請參考圖1，其中顯示習知技術中P通道渠道 型金氧半導體場效電晶'體。圖中所顯示的單一晶胞可在 一晶片的表面上重複多次複製。 因此，該裝置具有P +摻雜之基體20，其係應用沉 積方式製造而成，並微摻雜P +層21於其上。N+通道擴 散區22擴散入P-層2 1的上表面，因此形成層級式擴 散。如相間隔的渠道23，24蝕刻於晶圓或晶片的上表 面，該晶圓或晶片顯示在圖中，且下通道擴散區22的 7 適用中國國家標準（CNS) Α4規格（2丨0X 297公釐） A7 434648 五、發明説明（） 下方延伸。這些渠道與閘極絕緣層（如在渠道區23，24 中對應的閘極氧化層25 ’ 26)對齊，且分別充塡彼此互 相連接（圖中沒有顯示）的導電多晶矽層28，29。在渠道 23，24的上方分別形成28，29。須注意渠道23，24可 爲延長的條狀結構，且源極區30到33也可以是伸長的 條帶區域。但是’渠道‘2 3 ’ 2 4也可以是多角形的形態， 在該例子中，P +源極包圍對應的渠道。這些渠道也可以 包圍多角形源極。氧化絕緣接頭35，36覆蓋多晶矽帶 條28，29，且產生多晶矽帶條與覆蓋的鋁源極接點40 絕緣。絕緣接點40與源極區30，31，32，33及通道擴 散區22以一般方式連接。汲極接點41連接晶粒的底 部，以達成垂直導電的渠道裝置。 操作時，需要將足夠高的閘極電壓加入多晶矽閘 極28，29中，以使得尾級型態的通道擴散區22沿著從 源極30到33至P-磊晶層21的整個長度方向反轉。因 此，需要相當高的閘極電壓以保證通道擴散區高濃度部 位的反轉。而且|，一將該裝置導通時，在汲極41及源 極40之間流動的導體。流過汲極4 1及源極40之間的 載體將看到源極層21上的高電阻Repi，因此，使得裝 置產生一增加的RDS0N。 本發明中提供一嶄新的結構，其可允許供應低閘 極電壓，且在P通道渠道型式的金氧半導體閘極裝置中 具有一相當低的 Rdson 。圖 2 中顯示此一，其中此裝置 的組件與圖1中的組件相似者，則以相同的編號標示。 需要先注意在圖2中的源極接點以同於共同待審 之美國專利申請案案號08/299,5^3。因此’將一缺槽50 ±表?Ti (請先閲讀背面之注意事項再填寫本頁) 經濟部智祛財產局負工消費合作社印製 、張尺度適ϋ國家標準（CMS ) A4規格(210X297公釐1 " 434648 A7 B7 五、發明説明（） 触刻過P +源極條帶以使得源極電極40接觸P +源極條帶 31-3 3，且下層N型通道區域。N + +擴散區51也可以置 於控制缺槽下，以改進鋁源極40及矽60之間的接點。 I ----1 ---- n I I (祷先閲讀背面之注意事項再填寫本頁) 依據本發明，圖1中層級式通道擴散區22及P-磊晶層21，由N +磊晶成長層60替代，且直接在P +基體 20上成長。N +層60在整個長度方向上具有固定的濃度 (0的垂直梯度），且接收不同的渠道結構23，24。選擇 其架構以提供低臨界電壓VT。P +源極30到33擴散入 N +磊晶層60的上方^ 由於新結構的結果，可減少臨界電壓，以允許約 2.5電壓以完全導通該裝置，此係因爲沿與渠道側壁相 鄰之可逆層之全長上，濃度均相當低且均勻。而且，因 爲圖1中電阻組件Rcpi從圖2的裝置中去除掉，因此該 裝置的導通電阻也跟著減少。 圖1或2的裝置也可以如圖4所示，對於圖2之 裝置製造成一雙向金氧半導體場效電晶體。因此，圖4 的裝置與圖2中的裝置相同，唯源極接點只接觸P+源極 區域30到33，且不與通道區域60相接觸。 經濟部智¾对產局員工>7ί'費合作社印製 圖4的結構單一雙向金氧半導體場效電晶體，其 使用較少的矽區域，且導通電阻比兩串聯金氧半導體場 效電晶體之導通電阻還要小（如圖1及2中所示者），以 產生雙向控制的電路。因此，在過去，兩垂直導通的金 氧半導體場效電晶體吸7 1需要在兩終端70，7 1之間串 聯，且具有共用閘極端74，以容許如圖3所示之終端 72，73之電路的雙向控制。比照上，如圖5所示，裝置 80，其爲圖4之A因此，將在終端72及73之間提供雙 本紙張尺度適州中國國家標隼（CNS ) A4規格（210X 297公楚） 434648 A7 B7 經濟部智慧財產局員工消費合作社印熨 五、發明説明（） 向控制。但是，如圖5所示，裝置80(圖4之裝置）將在 終端72及73之間提供雙向控制。但是，圖4及5的裝 置及電路具有圖3之電路RDS0N之半，且具有矽儲存之 半。 圖6到10說明用於製造圖2之裝置的較佳實施例 程序。圖1及2中與圖‘ 6到10中相同的裝置以相同的 編號表示。 對於一 1 2伏之P通道裝置之啓始晶圓的處理程序 爲將硼滲雜P +基體20，其電阻率少於0.005ohm，且厚 度爲3 75 μπι。在基體20上方成長N+磊晶層60，且摻雜 電阻率爲〇.17ohm且厚度爲2.5//m的磷。 圖6，7中顯示的第一主要步驟爲在磊晶層60的 上方形成渠道，光罩，且蝕刻渠道23，24等到1200A 的深度。然後製備用於閘極氧化物的渠道側壁，且執行 初始犧牲層氧化，而留下如圖7所示的裝置。 此時，如圖8所示，在渠道壁（及上矽表面）的內側 成長閘極氧化層2'5，26。在950°C09/TCA下成長閘極氧 化化3 0分鐘。 其次，且如圖8所示，在晶圓上表面成長多晶矽， 且深入渠道作爲多晶矽閘極28，29。成長厚度約7500 埃的多晶矽。在成長多晶矽後，植入劑量1E14且能量 80KeV的硼而使其導電。植入後，進行在I 050°C的氮中， 進行韌化及驅動。然後將光罩加上以將多晶矽從活化裝 置表面的上方蝕刻掉（終端步驟在此不再說明，這些步驟 係傳統上習用方式），且然後如圖定位所示顯示該晶圓。 此後，在97VC下於02/TCA中進行多層氧化步驟 ------J0____ 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公赘） —^1- ^^^1 ^—^1 I I - ti I ^^^1 ^^^1 ^^^1 11 ......... T^i 、T (請先閲讀背面之注意事項再填寫本頁) 434648 經濟部智毡財產局員工消費合作社印製 A7 五、發明説明（） 4〇分鐘，以在各渠道中，於多晶矽的上方成長氧化物。 然後執行源極植入步驟以如圖9中所示者形成P +植入 物，其將位在圖2.中的P +源極區域30到33。圖9中的 源極植入係在劑量2E15及量50KeV下植入硼。其次， 如圖9中所示者，在晶圓上方沉積TEOS絕緣層35, 36， 到其厚度爲7500埃爲止。 其次，如圖1 〇中所示者，進行源極驅動以在氮氣 中於850度c下驅動30分鐘，而將P +源極區域驅動入 石夕中。 作用在圖10之晶圓的步驟產生圖2中所示之結 構，且包含接觸罩步驟以在形成N+ +層51之後打開接觸 窗口而改進矽及鋁源極金屬之間的接觸。可經由植入 1E15及50KeV的能量而形成區域51。在製備適當的金 屬形成後，經由濺射8 // m的鋁，而作用鋁前金屬40。 此後，由硏磨將晶圓20的厚度爲210//m，背金屬 或汲極41適當地沉積，形成圖2所示的裝置。 在執行上述程丨續時，使用寬0.6 Am的渠道及寬1.8 的平台。也可以選擇其它的尺寸。而且，可使用方 形的晶胞，雖然也可以使用條帶形設計在適當晶圓後， 形成大小爲75密爾X 90密爾且88%活化區的晶粒。也 可以使用102密爾（2.591mm)x 157密爾（3.988mm)且具 有92%活化區之大尺寸晶粒。 雖然文中已應較佳實施例說明本發明，但嫺熟本 技術者需了解可對上述實施例加以更改及變更，而不偏 離本發明的精神及觀點，因此，本發明並不限制於上述 說明的實施例，而是由所附之申請專利範圍加以限定。 ___1 ί ___ 本紙張尺度適用中國囤家標準（CNS ) Α4規格（2]ϋΧ 297公釐） dπ— (請先閲讀背Is.之注意事項再填寫本頁)434648 A7 ________ B7 V. Description of the invention () Background of the invention The present invention relates to power metal-oxide semiconductor gate devices, especially to a new low-voltage] P-channel metal-oxide semiconductor with reduced switching losses. Power metal-oxide-semiconductor gate devices are well-known devices and include, for example, system metal-oxide-semiconductor field-effect transistors, IGBTs, and gate-control rectifiers. In low-voltage applications of this device, especially battery-operated portable electronic devices, such as personal computers, cell phones, etc., are often referred to as radio systems. Extremely careful power management is required to spread battery life. And the use of charge. The use of power management systems in wireless systems can generally be divided into two categories. One charges the battery from an external DC source. It is very important to properly control the charging current and voltage for a specific battery technology. This control can be accomplished in a well-known manner by modulating the duty cycle of the transistor between the power source and the battery. The second category is part of the action requirement system. In this example, the transistor is placed between the battery and a load that will operate, such as an RF power amplifier. In some systems, multi-power material voltages require DC / DC conversion. This can be done using the well-known low-drop linear regulator or boost switching regulator. The N-channel and P-channel power metal-oxide semiconductor transistors used as transistors in the above applications can be used. Generally P-channel devices are easier to use in these circuits. Therefore, when the P-channel metal-oxide-semiconductor field-effect transistor is placed on the power bus, a logic input control that switches between the power rail and ground can be applied. This allows a single, uninterruptible grounding of the entire system. The N-channel device in the power bus requires a gate signal. Increasing the voltage of this signal makes it higher than the bus, which requires additional power ---. ____________ This paper size applies to China National Standard (CNS) Λ4 specifications (210X 297mm) (谙 Please read the notes on the back before filling this page) -Ding,-= a Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Du Du 43464 8 A 7 __B7_ V. Description of the invention () Road. In the past, the simplification of the P-channel device has come at the cost of increased losses. External P-channel devices rely on holes to conduct, while holes in silicon have a lower carrier mobility than electrons. The on-resistance of the action transistor is proportional to the mobility of the carrier, and its loss is proportional to the on-resistance Rdson 0 To overcome this limitation, the length of the resistance path can be minimized, and the width within the transistor may be the smallest. The holes are limited to the maximum in the path. One of the other ways to achieve this is to minimize the maximum voltage 値, which allows the use of lower resistivity and higher silicon doping concentrations. Because most batteries operate at only a few volts, for radio applications, a 12V rating is usually sufficient. Previously used devices were rated at 20V and had a reasonably low RDSON 2.5V from gate to source. These components come from a variety of die sizes and package types, ranging from Micro3 (SOT 23) to S08. The numbers in the table below are for a single transistor in the package. Of course, there are two types of Micros and S08 packages. Power consumption using these devices can be as high as 9%, with a designated translation to reduce usage. (Please read the precautions on the back before filling this page), -α The load current component number printed by the Intellectual Property Bureau employee consumer cooperatives is packaged as Rdson @ 2,5V V drops or Pdiss 5V supply is regarded as% 5 00mA IRLML6320 Micro3TM 0.9 Ω 9% 1 A IRLMS6702 Micro6TM 0.4 Ω 8% 2A IRF7604 Micro8TM 0.13 Q 5% 4A IRF7416 SO-8 0.035 Ω 3% It is known that channel voltage technology can be used to manufacture low-voltage power metal-oxygen half 4_ This paper is applicable to China Standard (CNS) A4 specification (2) 0X 297 mm) 434648 A7 B7 Exhibition Department Intellectual Property M); /) Printed by Heii Corporation 5. Description of invention () Conductor field effect transistor to reduce RDS ON, brake Electrode-to-source capacitance to reduce Q (gate charge). The switching loss is exactly the product of the device size and Qg, so it is also necessary to reduce rdson in this device. The P-channel channel type power metal-oxide semiconductor field effect transistor in the present invention uses a P-type substrate having a P-channel epitaxial layer. The channel region of the device is formed by a deep N-type diffused region from the upper surface of the epitaxial layer after the P-type source is diffused. Then, most of the voltage is blocked in the P-type epitaxial layer, which results in a considerable decrease in resistance and therefore increases losses in the radio system. These losses in turn reduce battery life between charges. SUMMARY OF THE INVENTION According to the present invention, in a P-channel channel type metal-oxide semiconductor gate device, the conventionally used P-type substrate epitaxial layer is removed, and the diffusion channel is replaced by an N-type channel region grown by epitaxial growth. The channel region now has a uniform concentration, and the relatively low-doped channel region allows the voltage in the channel region to be blocked and reduces the threshold voltage VT for conduction. Therefore, the new 'structure' can be used to remove the main component of the on-resistance, and at a voltage of 2.5 volts, the device can be completely turned on from the gate to the source. When the new die in the present invention is encapsulated in the package in the above table, the RDSOn and power consumption can be reduced by four times, as shown in the following table: i ^^ i- — ^ n ^^^^ 1 I-— ^ — ^ 1 —i ^^ i 1-1- — ^^^^ 1 an lOJ (Please read the precautions on the back before filling this page) Package type V drop or Pdiss load current element number Rdson @ 2.5 V 5 V supply as% This paper size applies to China National Sample (CNS) A4 specification (2 丨 0 '乂 297mm> 434648 A7 B7 4 ~~) / V \ i _ 500mA Micro3TM 0.1 8 Ω 1.8% 1 A Micro6TM 0.07 Ω 1.5% 2A Micro8TM 0.025 Ω \% 4A SO-8 0.01 Ω 0.8% Printed by the Consumer Goods Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Therefore, the overall circuit consumption and loss is reduced to less than 2%. It is the same even when the discharged battery is 2.5 volts. Brief Description of the Drawings Fig. 1 is a cross-sectional view of a contact pattern of a single cell of a conventional channel-type P-channel metal-oxide semiconductor field effect transistor. Fig. 2 is a sectional view similar to Fig. 1, but showing a contact pattern and pattern of the present invention. Fig. 3 shows a circuit diagram of the two metal-oxide-semiconductor field-effect transistors of Figs. 1 and 2, which are connected to form a bidirectional conductive device. Fig. 4 is a cross-sectional view taken from Fig. 4, showing a modified contact pattern, thereby forming a bidirectional metal-oxide-semiconductor field-effect transistor. FIG. 5 is a circuit diagram of the bidirectional field effect transistor of FIG. 4. FIG. 6 is a top view of a silicon substrate portion used to manufacture the device of FIG. 2. FIG. FIGS. 7, 8, 9 and 10 show the appearance of the cross-sectional portion of the silicon in FIG. 6 as viewed along line 7-7 of FIG. 6 after a plurality of processing steps. Description of component drawing numbers ^ n.-I —: II n ^ i-hr—I— I _ I—-. S * T (Please read the precautions on the back before filling this page) This paper size applies to Chinese national standards (CNS) Λ4 specification (210X297) 434648 V. Description of the invention (A7 B7 20 Base 21 p + layer 22 N + channel diffusion region 23, 24 channel 25-26 gate oxide layer 28, 29 conductive polycrystalline layer 3 〇5 31 »32, 33 source area 35, 36 oxidation insulation plug 40 aluminum source contact 41 drain contact 50 slot 5 1 N ++ diffusion region 60 N crystal growth layer 70, 71 '72, 73 terminal 74 Detailed description of the extremely preferred embodiment of the shared gate: n ϋ n. ^ 1 I-It-Taxi ^ ^ ^ II-n τ I-- (Please read the precautions on the back before filling this page} Intellectual Property Bureau, Ministry of Economic Affairs Printed by MG Consumer Cooperative, please refer to Fig. 1, which shows the P-channel channel metal-oxide semiconductor field effect transistor in the conventional technology. The single unit cell shown in the figure can be repeated multiple times on the surface of a wafer Therefore, the device has a P + -doped substrate 20, which is fabricated by a deposition method and The hetero P + layer 21 is thereon. The N + channel diffusion region 22 diffuses into the upper surface of the P-layer 21, thus forming a layered diffusion. For example, the spaced channels 23, 24 are etched on the wafer or the upper surface of the wafer, the The wafer or wafer is shown in the figure, and 7 of the lower channel diffusion area 22 is applicable to the Chinese National Standard (CNS) A4 specification (2 丨 0X 297 mm) A7 434648 5. The description of the invention () extends below. These channels and gates The insulating layers (such as the corresponding gate oxide layers 25'26 in the channel regions 23, 24) are aligned and filled with conductive polycrystalline silicon layers 28, 29, which are connected to each other (not shown). In the channels 23, 24, 28 and 29 are formed on the top respectively. It should be noted that the channels 23 and 24 can be elongated strip structures, and the source regions 30 to 33 can also be elongated strip regions. However, the 'channel' 2 3 '2 4 can also be multiple The shape of the angle, in this example, the P + source surrounds the corresponding channel. These channels can also surround the polygon source. The oxidized insulation joints 35, 36 cover the polycrystalline silicon strips 28, 29, and the polycrystalline silicon strips and the covered The aluminum source contact 40 is insulated. The insulation contact 40 is separated from The pole regions 30, 31, 32, 33 and the channel diffusion region 22 are connected in a general manner. The drain contact 41 is connected to the bottom of the die to achieve a vertically conductive channel device. During operation, a sufficiently high gate voltage needs to be added In the polycrystalline silicon gates 28 and 29, the channel diffusion region 22 of the tail stage type is inverted along the entire length direction from the source 30 to 33 to the P-epitaxial layer 21. Therefore, a relatively high gate voltage is required to ensure the inversion of the high-concentration portion of the channel diffusion region. Furthermore, a conductor that flows between the drain 41 and the source 40 when the device is turned on. The carrier flowing between the drain 41 and the source 40 will see the high resistance Repi on the source layer 21, so that the device generates an increased RDSON. A novel structure is provided in the present invention, which allows the supply of a low gate voltage and has a relatively low Rdson in a P-channel channel type metal-oxide semiconductor gate device. This is shown in Figure 2. The components of this device are similar to those in Figure 1, and are labeled with the same numbers. Note that the source contacts in Figure 2 are the same as the co-pending U.S. Patent Application No. 08 / 299,5 ^ 3. Therefore, 'will be missing a slot 50 ± table? Ti (please read the precautions on the back before filling this page) Printed by the Ministry of Economic Affairs, Intellectual Property Office, Consumer Cooperatives, and the standard of the scale (CMS) A4 (210X297) 1 " 434648 A7 B7 V. Description of the invention () The P + source strip has been etched so that the source electrode 40 contacts the P + source strip 31-3 3, and the lower N-type channel region. N + The + diffusion region 51 can also be placed under the control slot to improve the contact between the aluminum source 40 and the silicon 60. I ---- 1 ---- n II (please read the precautions on the back before filling (This page) According to the present invention, the layered channel diffusion region 22 and the P-epitaxial layer 21 in FIG. 1 are replaced by an N + epitaxial growth layer 60 and grown directly on the P + substrate 20. The N + layer 60 is throughout Has a fixed concentration in the length direction (vertical gradient of 0), and receives different channel structures 23, 24. Its architecture is selected to provide a low threshold voltage VT. The P + sources 30 to 33 diffuse into the N + epitaxial layer 60 Above ^ As a result of the new structure, the threshold voltage can be reduced to allow about 2.5 voltages to fully turn on the device, because the Over the entire length of the adjacent reversible layer, the concentration is quite low and uniform. Moreover, because the resistance component Rcpi in FIG. 1 is removed from the device of FIG. 2, the on-resistance of the device is also reduced. The device of FIG. As shown in Fig. 4, a bidirectional metal-oxide-semiconductor field effect transistor can be manufactured for the device of Fig. 2. Therefore, the device of Fig. 4 is the same as the device of Fig. 2 except that the source contacts only contact the P + source region 30 to 33, and not in contact with the channel area 60. The Ministry of Economic Affairs has printed a single bidirectional metal-oxide-semiconductor field-effect transistor of the structure shown in Figure 4 to employees of the Production Bureau> 7, which uses less silicon area, and The on-resistance is smaller than the on-resistance of two series of metal-oxide-semiconductor field-effect transistors (as shown in Figures 1 and 2) to produce a bidirectionally controlled circuit. Therefore, in the past, two metal-oxide-semiconductor fields that were vertically turned on The effect transistor suction 71 needs to be connected in series between the two terminals 70 and 71 and has a common gate terminal 74 to allow bidirectional control of the circuits of terminals 72 and 73 as shown in Fig. 3. For comparison, as shown in Fig. 5 Shown, device 80, which is A of Figure 4 Provide double paper sizes between terminals 72 and 73. Shizhou China National Standards (CNS) A4 specification (210X 297 Gongchu) 434648 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. However, as shown in Fig. 5, the device 80 (the device of Fig. 4) will provide bidirectional control between the terminals 72 and 73. However, the device and circuit of Figs. 4 and 5 have half of the circuit RDS0N of Fig. 3 and have Silicon storage half. Figures 6 to 10 illustrate the preferred embodiment procedure for manufacturing the device of Figure 2. The same devices in Figs. 1 and 2 as in Figs. 6 to 10 are designated by the same reference numerals. The processing procedure for the initial wafer of a 12 volt P-channel device is doping boron into the P + matrix 20, which has a resistivity of less than 0.005 ohm and a thickness of 3 75 μm. An N + epitaxial layer 60 is grown on the substrate 20, and is doped with phosphorus having a resistivity of 0.17 ohm and a thickness of 2.5 // m. The first main step shown in Figs. 6 and 7 is to form a channel, a mask over the epitaxial layer 60, and etch the channels 23, 24 to a depth of 1200A. Channel sidewalls for the gate oxide are then prepared and an initial sacrificial layer oxidation is performed, leaving the device shown in FIG. 7. At this time, as shown in FIG. 8, gate oxide layers 2'5, 26 are grown inside the channel wall (and the upper silicon surface). Gate oxidation at 950 ° C09 / TCA for 30 minutes. Secondly, as shown in FIG. 8, polycrystalline silicon is grown on the upper surface of the wafer, and deep channels are used as the polycrystalline silicon gates 28 and 29. Polycrystalline silicon with a thickness of about 7500 angstroms is grown. After growing polycrystalline silicon, boron was implanted at a dose of 1E14 and energy of 80 KeV to make it conductive. After implantation, it was toughened and driven in nitrogen at I 050 ° C. A photomask is then added to etch away the polysilicon from above the surface of the activation device (the termination steps are not described here, these steps are traditionally used), and the wafer is then displayed as shown in the positioning diagram. After that, a multi-layer oxidation step was performed in 02 / TCA under 97VC -------- J0____ This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 public and redundant) — ^ 1- ^^^ 1 ^ — ^ 1 II-ti I ^^^ 1 ^^^ 1 ^^^ 1 11 ......... T ^ i, T (Please read the notes on the back before filling this page) 434648 Property of the Ministry of Economic Affairs Bureau employee consumer cooperative printed A7 V. Invention Description () 40 minutes to grow oxides on top of polycrystalline silicon in various channels. The source implantation step is then performed to form a P + implant as shown in FIG. 9, which will be located in the P + source regions 30 to 33 in FIG. 2. The source implant in Figure 9 was implanted with boron at a dose of 2E15 and a dose of 50 KeV. Next, as shown in FIG. 9, TEOS insulating layers 35, 36 are deposited over the wafer to a thickness of 7500 angstroms. Next, as shown in FIG. 10, source driving was performed to drive 30 minutes at 850 degrees c in nitrogen, and the P + source region was driven into Shi Xi. The step acting on the wafer of FIG. 10 results in the structure shown in FIG. 2 and includes a contact mask step to open a contact window after forming the N + + layer 51 to improve the contact between the silicon and the aluminum source metal. The region 51 can be formed by implanting energy of 1E15 and 50KeV. After the proper metal formation is prepared, 8 // m of aluminum is sputtered, and a pre-aluminum metal 40 is applied. Thereafter, the thickness of the wafer 20 is 210 // m by honing, and the back metal or the drain electrode 41 is appropriately deposited to form the device shown in FIG. 2. When performing the above procedure, use a channel with a width of 0.6 Am and a platform with a width of 1.8. Other sizes are also available. Moreover, a square-shaped unit cell may be used, although a strip-shaped design may also be used to form crystals with a size of 75 mils x 90 mils and an 88% active region after a suitable wafer. Large grains with 102 mils (2.591mm) x 157 mils (3.988mm) and a 92% activation zone can also be used. Although the present invention should be explained in terms of preferred embodiments, those skilled in the art need to understand that the above embodiments can be modified and changed without departing from the spirit and perspective of the invention. Therefore, the invention is not limited to the above description. The embodiments are limited by the scope of the attached patent application. ___1 ί ___ The size of this paper is applicable to China Standards (CNS) Α4 size (2) ϋΧ 297 mm) dπ— (Please read the precautions on the back of Is. Before filling this page)