TW432869B - Image capture and transmission system - Google Patents

Image capture and transmission system Download PDF

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Publication number
TW432869B
TW432869B TW088108563A TW88108563A TW432869B TW 432869 B TW432869 B TW 432869B TW 088108563 A TW088108563 A TW 088108563A TW 88108563 A TW88108563 A TW 88108563A TW 432869 B TW432869 B TW 432869B
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TW
Taiwan
Prior art keywords
video data
digital video
signal
facility
circuit
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TW088108563A
Other languages
Chinese (zh)
Inventor
Kengo Tsuzuki
Toshiaki Shinohara
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Matsushita Electric Ind Co Ltd
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Publication of TW432869B publication Critical patent/TW432869B/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/40052—High-speed IEEE 1394 serial bus
    • H04L12/40117—Interconnection of audio or video/imaging devices
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/41—Structure of client; Structure of client peripherals
    • H04N21/422—Input-only peripherals, i.e. input devices connected to specially adapted client devices, e.g. global positioning system [GPS]
    • H04N21/4223—Cameras
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/4302—Content synchronisation processes, e.g. decoder synchronisation
    • H04N21/4305—Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/436—Interfacing a local distribution network, e.g. communicating with another STB or one or more peripheral devices inside the home
    • H04N21/4363—Adapting the video stream to a specific local network, e.g. a Bluetooth® network
    • H04N21/43632—Adapting the video stream to a specific local network, e.g. a Bluetooth® network involving a wired protocol, e.g. IEEE 1394
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/44—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs
    • H04N21/44008—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs involving operations for analysing video streams, e.g. detecting features or characteristics in the video stream
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/45—Management operations performed by the client for facilitating the reception of or the interaction with the content or administrating data related to the end-user or to the client device itself, e.g. learning user preferences for recommending movies, resolving scheduling conflicts
    • H04N21/462—Content or additional data management, e.g. creating a master electronic program guide from data received from the Internet and a Head-end, controlling the complexity of a video stream by scaling the resolution or bit-rate based on the client capabilities
    • H04N21/4622—Retrieving content or additional data from different sources, e.g. from a broadcast channel and the Internet

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Databases & Information Systems (AREA)
  • Studio Devices (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Television Signal Processing For Recording (AREA)

Abstract

An image capture and transmission system includes first and second imaging devices. A timing signal generator produces a timing signal. A common drive circuit operates for driving the first and second imaging devices at equal timings determined by the timing signal. A first signal processor operates for converting an output signal of the first imaging device into first digital video data. A second signal processor operates for converting an output signal of the second imaging device into second digital video data. The first digital video data and the second digital video data are processed into a stream of packets. The packet stream is transmitted to, for example, a network.

Description

經濟部智慧財產局貝工消費合作社印製 432869 A7 _____B7_五、發明説明（丨） 本發明係有關於一種系統，包括一影像捕捉段與一影 像資訊傳輸段》 要提供第一與第二成像裝置及要由該第一與第二成像 裝置傳輸影像資訊件至一养同網路是為可想像的。此一可 想像的系統包括第一與第二時間信號產生器，及第一與第 二驩動電路分別用於該第一與第二成像裝置•該第一驅動 鼙路以回應於該第一時間信號產生器之输出信號而操作該 第一成像裝置。該第二騍動電路以回應於該第二時間信號 產生器之輸出信號而操作該第二成像裝置， 該可想像的系統亦包括第一與第二信號處理器，及第 一與第二發射器•該第一信號處理器將該第一成像裝置之 輸出信號轉換成為第一數位視頻資料*該第一發射器將該 第一數位視頻資料編碼成為一第一封包流*該第一發射器 在使用一第一頻帶與一第一波道输出該第一封包流至該網 路。另一方面，該第二信號處理器將該第二成像裝置之输 出信號轉換成為第二數位視頻資料《該第二發射器將該第 二數位視頻資料編碼成為一第二封包流•該第二發射器在 使用一第二頻帶與一第二波道輸出該第二封包流至該網 路•該第二頻帶與該第二波道與該第一頻帶與該第二波道 不同。 該可想像的系統因其有二個時間信號產生器、二個數 位視頻資料與二個發射器而在結構上趨於複雜* 本發明之一目標為要提供一種具有簡單結構之影像捕 捉及傳輸系統。 (請先閲讀背面之注意事項再 ) 本紙張尺度遑用中國國家橾準（〇阳）八4软/格（210父297公釐） 432869 A7 B7 五、發明説明（2 ) 經濟部智慧財產局員工消費合作社印製 本發明之一第一雇面為提供一種影像捕捉與傅輸系 統，包含第一與第二成像裝置：第一設施用於產生一時間 信號；一共同鼷動電路用於在該第一設施所產生之時間信 號所決定的相同時間騸動該第一與第二成像裝置；一第— 信號處理器用於將該第一成像裝置之输出信號轉換成第一 數位親頻資料；一第二信號處理器用於將該第二成像裝置 之輸出信號轉換成第二數位視頻資料；第二設施用於將該 第一數位視頻資料與該第二數位視頻資料處理成為封包 流；以及第三設施用於傳輸該第二設施所產生之封包流· 本發明之第二層面為根據其第一層面，並提供一種影 像捕捉及傅輸系統，進一步包含一第三成像裝置，及一驩 動電路用於在與驅動該第一與第二成像裝置之不同時間驅 動該第三成像裝置。 本發明之第三靥面為根據其第一層面，並提供一種影 像捕捉及傳輸系統|其中該第三設施包含設施用於輸出該 封包流至一網路，且該第一設施包含設施用於產生該時間 信號與該封包流之輸出至該網略同歩》 本發明之第四層面為根據其第一層面，並提供一種影 像捕捉及傳輸系統，進一步包含設施用於在該第一數位視 頻資料與該第二數位視頻資料所代表之每一框內設定一可 改爱的傳輸開始點•與設施用於藉由該第三設施在該第一 數位視頻資料與該第二數位視頻資料所代表之每一框的該 傳輸開始點開始而促成在該封包流之該第一數位視頻資料 與該第二數位視頻資料的傳輸* 讀 先 閲 面 之 注 項 再 填产 寫 本 頁 本紙張尺度遥用中國《家梂準（CNS ) A4規格（210X297公釐） 4328 6 9 A7 B7 經濟部智慧財產局S工消費合作社印製 五、發明説明（3 ) 本發明之第五層面為根據其第一層面，並提供一種影 像捕捉及傳輸系統，進一步在該第三設施中提供設施用於 在回應於再傳輸要求之信號下再傳输該封包流之一部分* 本發明之第六層面為根據其第一層面，並提供一種彩 像捕捉及傳輸系統，進一歩在該第三設施中提供設施用於 再傅輸該封包流之全部第一數位視頻資料與第二數位視頻 資料。 本發明之第七層面為根據其第一層面，並提供一種影 像捕捉及傳輸系統，其中該第二設施包含設施用於將該第 一數位視頻資料壓縮成為第一壓縮結果之數位視頻資料與 設施用於將該第二數位視頻資料壓縮成為第二壓縮結果之 數位視頻資料，以及設施用於將該第一屋縮結果之數位視 頻資料與該第二壓縮結果之數位視頻資料組合成該封包 流· 本發明之第八層面為根據其第一層面，並提供一種影 像捕捉及傳輸系統，其中該第二設施包含設施用於執行該 第一數位視頻資料與該第二數位視頻資料間之第一計算作 業，並產生第二運算結果之數位視頻資料，設施用於執行 該第一數位親頻資料與該第二數位視頻資料間之第二計算 作業，並產生第二運算結果之數位視頻資料，該第二計算 作業與該第一計算作業不同，設施用於將該第一連算結果 之數位視頻資料壓縮成為第一壓縮結果之數位視頻資料’ 設施用於將該第二運算結果之數位親頻資料壓縮成為第二 壓縮結果之數位視頻資料，以及設施用於將該第一壓縮結 -6- (請先閎讀背面之注$項再ιί!本頁) Γ 本>張尺度遥用中««家搮率（CNS ) A4規格（210X297公釐） 432869 經濟部智慧財產局β工消費合作社印製 五、發明説明（4 ) 果之數位視頻資料與該第二壓縮結果之數位視頻資料組合 成該封包流· 本發明之第九層面為根據其第一靥面·並提供一種影 像捕捉及傳输系統•其中該第二設施包含設施用於在該第 一數位親頻資料與該第二數位視頻資料所代表之每一框內 設定一可改變的有效區域•設施用於選擇對應於每一框中 有效區域之該第一數位視頻資料與該第二數位視頻資料的 的部分，以及設施用於僅將該第一數位視頻資料與該第二 數位視頻資料之被選擇部分置於該封包流內· 本發明之第十層面為根據其第一層面，並提供一種影 像捕捉及傅输系統，其中每一框內之該有效瓸域為長方形 的，且在水平界限位置間延伸及在垂直界限間延伸· 本發明之第十一層面為根據其第一層面，並提供一種 影像捕捉及傳輸系統*進一步包含設施用於就一預定的目 標物捜尋被該第一數位視頻資料與該第二數位視頻資料所 代表之毎一框*以及設施用於在回應於捜尋結果下改變毎 一框內之該有效區域· 本發明之第十二層面為根據其第一層面，並提供一種 影像捕捉及傳輸系統|進一步包含設施用於感應被該第一 數位視頻資料與該第二數位視頻資料所代表之每一框內的 確定物體，並產生感應結果資訊，設施被提供於該第二設 施中用於依照可變的設定狀況設定每一框內之有效區域， 以及設施用於在回應於該感應結果資訊下決定該設定狀 況· -7- (锖先W讀背面之注意事項再^-¾，本頁)Printed by Shellfish Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 432869 A7 _____B7_ V. Description of the Invention (丨) The present invention relates to a system including an image capture section and an image information transmission section. To provide first and second imaging It is conceivable that the device and the image information files to be transmitted by the first and second imaging devices to a support network. This conceivable system includes first and second time signal generators, and first and second moving circuits for the first and second imaging devices, respectively. The first driving circuit responds to the first The output signal of the time signal generator operates the first imaging device. The second moving circuit operates the second imaging device in response to the output signal of the second time signal generator. The imaginable system also includes first and second signal processors, and first and second transmitters. • The first signal processor converts the output signal of the first imaging device into first digital video data * The first transmitter encodes the first digital video data into a first packet stream * the first transmitter The first packet stream is output to the network using a first frequency band and a first channel. On the other hand, the second signal processor converts the output signal of the second imaging device into second digital video data. The second transmitter encodes the second digital video data into a second packet stream. The transmitter uses a second frequency band and a second channel to output the second packet stream to the network. The second frequency band and the second channel are different from the first frequency band and the second channel. The imaginable system is complicated in structure because it has two time signal generators, two digital video data and two transmitters. * One object of the present invention is to provide an image capture and transmission with a simple structure. system. (Please read the precautions on the back first) This paper size is in accordance with Chinese National Standard (0 Yang) 8 4 soft / grid (210 father 297 mm) 432869 A7 B7 V. Description of Invention (2) Intellectual Property Bureau of the Ministry of Economic Affairs One of the first aspects of the invention printed by an employee consumer cooperative is to provide an image capture and transmission system including first and second imaging devices: the first facility is used to generate a time signal; a common motion circuit is used to The first and second imaging devices are activated at the same time as determined by the time signal generated by the first facility; a first-signal processor is used to convert the output signal of the first imaging device into the first digital frequency-frequency data; A second signal processor for converting the output signal of the second imaging device into second digital video data; a second facility for processing the first digital video data and the second digital video data into a packet stream; and The three facilities are used to transmit the packet stream generated by the second facility. The second level of the present invention is based on the first level, and provides an image capture and transmission system, further comprising a The third imaging device and a moving circuit are used to drive the third imaging device at different times from driving the first and second imaging devices. The third aspect of the present invention is based on the first aspect, and provides an image capture and transmission system | wherein the third facility includes facilities for outputting the packet stream to a network, and the first facility includes facilities for Generating the time signal and outputting the packet stream to the network are similar. The fourth level of the present invention is based on the first level, and provides an image capture and transmission system, further including facilities for the first digital video. Data and the second digital video data set a changeable transmission start point in each frame represented by the frame and the facility for using the third facility to place the first digital video data and the second digital video data The start of the transmission of each frame represents the transmission of the first digital video data and the second digital video data in the packet stream. Remotely used by China "Furniture Standard (CNS) A4 (210X297 mm) 4328 6 9 A7 B7 Printed by S Industrial Consumer Cooperatives, Bureau of Intellectual Property, Ministry of Economic Affairs V. Invention Description (3) Fifth of the invention It is based on its first level and provides an image capture and transmission system, further providing facilities in the third facility for retransmitting a portion of the packet stream in response to a signal in response to a retransmission request * The six levels are based on the first level, and provide a color image capture and transmission system, further providing facilities in the third facility for re-transmitting all the first digital video data and second digital video data of the packet stream. . The seventh aspect of the present invention is based on the first aspect, and provides an image capture and transmission system, wherein the second facility includes facilities for compressing the first digital video data into digital video data and facilities for a first compression result. For compressing the second digital video data into digital video data of the second compression result, and for facilities for combining the digital video data of the first shrinking result and the digital video data of the second compression result into the packet stream The eighth aspect of the present invention is based on the first aspect, and provides an image capture and transmission system, wherein the second facility includes facilities for performing the first between the first digital video data and the second digital video data A calculation operation, and generating digital video data of a second operation result, the facility is configured to perform a second calculation operation between the first digital affinity data and the second digital video data, and generate the digital video data of the second operation result, The second calculation operation is different from the first calculation operation, and the facility is used for digital video data of the first continuous calculation result The digital video data compressed into the first compression result 'facility is used to compress the digital frequency data of the second operation result into the digital video data of the second compression result, and the facility is used to compress the first compression result -6- ( Please read the note on the back before reading this page! This page) Γ Copies> Zhang Jiaoyuan in use «« Furniture Ratio (CNS) A4 Specifications (210X297 mm) 432869 Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs β Consumer Consumption Cooperative Fifth, the description of the invention (4) The digital video data of the fruit and the digital video data of the second compression result are combined into the packet stream. The ninth aspect of the present invention is based on the first aspect of the invention, and provides an image capture and transmission Transmission system • where the second facility includes facilities for setting a changeable effective area within each frame represented by the first digital pro-frequency data and the second digital video data • facilities for selecting corresponding to each Part of the first digital video data and the second digital video data in the effective area of the frame, and facilities for placing only the selected part of the first digital video data and the second digital video data The packet stream · The tenth layer of the present invention is based on the first layer, and provides an image capture and Fusu system, in which the effective field in each frame is rectangular, and extends between the horizontal limits and Extends between vertical boundaries. The eleventh level of the present invention is based on the first level and provides an image capture and transmission system * further including facilities for searching for a predetermined target by the first digital video data and The frame * and facilities represented by the second digital video material are used to change the effective area within the frame in response to search results. The twelfth level of the present invention is based on the first level and provides An image capture and transmission system | Furthermore, it includes facilities for sensing a certain object in each frame represented by the first digital video data and the second digital video data, and generating sensing result information. The facility is provided in the first The second facility is used to set the effective area within each frame according to the variable setting status, and the facility is used to determine the setting in response to the sensing result information Status · -7- (锖 Read the precautions on the back first ^ -¾, this page)

T 本紙張尺度通用中國S家揉準（ CNS ) A4現格（210X297公嫠） 132869 A7 B7 五、發明説明（5T The size of this paper is GM China SCN (CNS) A4 (210X297 male) 132869 A7 B7 V. Description of the invention (5

經濟部智慧財產局員工消費合作社印W 本發明之第十三層面為根據其第一層面•並提供一種 影像捕捉及傳輸系統•進一步包含設施用於感應被該第一 數位視頻資料與該第二數位視頻資料所代表之每一框內的 確定物體，並產生感應結果資訊.以及設施用於在回應於 該感應結果資訊下改變每一框內之有效區域。 第1圖為依據本發明第一實施例之影像捕捉及傳輸系 統的方塊圓。 第2圖為第1圖中之時間信號產生器的方塊画· 第3圖為第1圓中之信號處理器的方塊匪· 第4圖為第1圖中之收發機的方塊圖· 第5圖為封包與置於第1圓之系統中之封包內的視頻 資料件之圖。 第6圃為封包與置於依據本發明第二實施例之影像捕 捉及傳输系統中封包內的視頻資料塊之圖· 第7圖為封包與置於依據本發明第三實施例之影像捕 捉及傳糖系統中封包內的視頻資料件之圃。 第8圖為封包與置於依據本發明第四實施例之影像捕 捉及傳输系統中封包內的第一視頻資料及第二視頻資料的 圖· 第9圖為依據本發明第五寊施例之影像捕捉及傳输系 統的方塊圖· 第10圖為依據本發明第六實施例之影像捕捉及傳輸系 統的方塊圖》 第11圃為第10圖中之時間信號產生器的方塊圖* 請 先 Μ 面 之 注 項 本 頁 本紙張尺度適用争國國家梯準<仁邮）戎4规格（210><297公釐） 432869 A7 B7 五、發明説明（6 ) 第12®為第10圖中之收發機的方塊面· 第1 3豳為第1 0圖中之系統的信號與資料之時間範圍 圖 經濟部智慧財產局員工消費合作社印製 第14圖為依據本發明第七實施例之影像捕捉及傳輸系 統的方塊圖。 第15圖為第14圔中之收發機的方塊圖。 第16圖為依據本發明第八實施例之影像捕捉及傳輸系 統的方塊圖· 第17圖為第16困中之收發機的方塊圖· 第18圈為依據本發明第九實施例之影像捕捉及傳输系 統的方塊圃* 第19圖為第18圖中之收發機的方塊圖· 第20圖為依據本發明第十實施例之影像捕捉及傳輸系 統的方塊圓。 第21圖為第20圓中之收發機的方塊圖· 第22圓為依據本發明第十一寊施例之影像捕捉及傳輸 系統的方塊圖》 第23圈為第22圖中之收發機的方塊圖· 第24圖為一框及一有效區域的圖* 第25圖為第23圖中之區域設定電路的方塊圖· 第26圖為本發明之第十二寊施例中撖電腦內一程式段 落的流程圖。 第1圖顳示依據本發明第一實施例之影像捕捉及傳输 系統•第1圖之系統包括成像裝置（影像感應器）1〇1與102 請 先 聞 面 之 注 項 貪 裝 η 線 本紙張尺度逋用中國國家揉丰（CNS ) Α4规格（2ίΟΧ297公* ) 432869 A7 B7 經濟部智慧財產局®工消費合作社印製 五、發明説明（7 ) ，信號處理器103與104，一收發機（一發射器/接收 器）105,一時間信號產生器106,與一驄動電路107· 成像裝置1QI随後循序地有信號處理器103與收發機 105·成像裝置1D2隨後循序地有信號處理器104與收發機 10 5。時間信號產生器106被連接至信號處理器1(13與104， 收發機1Q5·及驅動電路107·驊動電路107被連接至成像 裝置101與10 2。收發機被連接至一網路包括有例如為IEEE 1394序列匯流排* 裝置106產生一時間信號•就如稍後要指出者|裝置 106所產生之時間信號包括一組次時間信號•為一時鐘信 號、一水平同步信號、與一垂直同步信號•裝置106輸出 所產生之時間信號至信號處理器103與104、收發機105、 及驅動電路107 * 驩動電路107在回應於時間信號產生器106之输出信 號下為成像裝置101與102產生一共同驅動信號驅動電 路107输出該驩動信號至成像裝置101與102*因之，驊動 電路107在時間信號產生器106之输出信號所決定的相同 時間操作或驅動成像裝置101與102。 成像裝置101在回應於騸動電路107之输出信號下將 一影像轉換成一對應的類比視頻信號•換言之，成像裝置 101在回應於騄動電路107之輸出信號下實施影像捕捉•成 像裝置101輸出該類比視頻信號至信號處理器103· 成像裝置102在回應於驅動電路107之输出信號下將 一影像轉換成一對應的類比視頻信號•換言之’成像裝置 10- 本紙張尺度適用中國國家橾準（CNS ) A4规格（210X297公釐） 婧 先 閲 背 面 之 注 項 裝 訂 線 869》 - 經濟部智慧財產局貝工消費合作社印製 五、發明説明（8 ) 102在回應於驅動電路107之輸出信號下實施影像捕捉•成 像裝置102輸出該類比視頻信號至信號處理器104· 被成像裝置1G1捕捉之影像與被成像裝置102捕捉之 影像在顆動電路107之輸出信號所決定之相同時間週期地 發生* 信號處理器103在回應於時間信號產生器106之輸出 信號下將成像裝置101之输出信號轉換成一第一數位視頻 資料•該第一數位視頻資料亦被稱為第一親頻資料•信號 處理器103輸出該第一視頻資料至收發機105· 信號處理器104在回應於時間信號產生器106之输出 信號下將成像裝置102之輸出信號轉換成一第二數位親頻 資料*該第二數位視頻資料亦被稱為第二視頻資料•信號 處理器104输出該第二視頻資料至收發機105。 收發機105包括一封包編碼器，將該第一親頻資料與 第二視頻資料在回應於時間信號產生器106之輸出信號下 轉換成封包流•收發機105输出該封包流至網路。 收發機105能由該網路接收非同步的封包*收發機105 將所接收之非同步封包轉換或解碼成其所附載之資訊件· 如第2圖顯示者，時間信號產生器106包括一振盪電 路201，一水平同步信號產生器2G2與一垂直同步信號產生 器203 ·振盪霉路201被連接至水平同步信號產生器202 與垂直同步信號產生器203·水平同步信號產生器202被連 接於垂直同步信號產生器203 · 振通電路201產生具有預定頬率之時鐘信號·振盪電 -11- 本紙張尺度逍用中囷a家揉率icNS了A4規格(2!0X297公釐) (請先Μ讀背面之注 項再本頁 .裝· 訂 -線· Γ 432869 經濟部智慧財產局員工消費合作社印製 A7 _B7_五、發明説明（9 ) 路201輸出該時鐘信號至水平同步信號產生器20 2與垂直 同步信號產生器203。裝置202產生一水平同步信號回應於 該時鐘信號·水平同步信號產生器202例如包括一計數器 回應於該時鐘信號•裝置202輸出該.水平同步信號至垂直 同步信號產生器203。裝置203產生一垂直同步信號回應於 該時鐘信號與該水平同步信號*垂直同步信號產生器203 例如包括一計數器回應於該時鐘信號與該水平同步信號* 振进電路201、水平同步信號產生器2G2與垂直同步信號產 生器203输出該時鐘信號、該水平同步信號與該垂直同步 信號，其為次時間信號，含有被時間信號產生器所產 生及輸出之時間信號· 信號處理器1G3與1 04具有彼此類似的構造•因之， 只有信號處理器1Q3將詳細被解釋•如第3圖顯示者，信 號處理器103包括一A/D (類比對數位）轉換電路301與一信 號處理電路302。A/D轉換電路301被連接至成像裝置 1〇1(見第1圖）、時間信號產生器1〇6(見第1Η)與信號處 理電路302·信號處理電路3Q2被連接至收發機105(見第1 圖）· A/D轉換電路301在回應於由時間信號產生器106所嬪 送之時鐘信號下遭受到成像裝置101之輸出信號的類比對 數位轉換》因之，A/D轉換電路301將成像裝置101之輸出 信號改變成對應的數位視頻資料-A/D轉換電路301輸出該 數位視頻資料至信號處理電路302·信號處理霉路302遭受 到A/D轉換電路301之輸出信號的位準轉換與格式轉換* _____ — 12—_ 本紙張尺度逋用中國國家揉準（CNS ) Α4規格（210X297公釐） 432869 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（1 G ) 因而將A/D轉換電路301之輸出信號改變為具有給定格式 之第一視頻資料。信號處理電路302輸出該第一視頻資料 至收發機105 * 如第4圓顯示者，收發機1〇5包括記憶體401與4 02、 微電腦403、一處理霉路404與一匯流排I/F(介面）電路 405 ·記憶體401被連接於信號處理器1〇3(見第1圖）與處 理電路404 ·記憶通40 2被連接於信號處理器104(見第1 圈）與處理電路404·處理電路404被連接於時間信號產生 器106(見第1圚）與匯流排I/F電路405 ·匯流排I/Fm路 405被連接於該網路•該微電腦40 3被連接於處理電路40 4 與與匯流排I/F電路405 » 由信號處理器103输出之第一視頻資料被儲存於記憶 體401內*由信號處理器104輸出之第二視頻資料.被儲存 於記憶體402內·微電腦403依照儲存於其中之程式控制 處理電路404與與匯流排I/F電路405·該程式被設計來實 施下列的處理，處理電路404在時間信號產生器106之输 出信號所決定的特定時間由記憶體401與402讀出第一視 頻資料與第二視頻資料•處理電路4G4包括一封包編碼器 其在回應於時間信號產生器106之輪出信號下將該第一視 頻資料與該第二視頻資料轉換或編碼•例如，每一封包被 裝載該第一視頻資料之一部分與該第二視頻資料之一部分 的至少之一·較佳的是，每一封包含有代表其中之覗頻資 料的格式之添加後的資訊件、就造成其中之視頻資料的成 像裝置代表其辨鼯號碼的添加後之資訊件、以及代表被其 13- 本紙張尺度適用中國國家搮準（CNS > A4規格（210X297公釐） 請 先 閲 背 面 之 注 項 432869 A7 B7 經濟部智慧財產局貝工消费合作社印製 五、發明説明（11 ) 中之視頻資料所代表之影像部分的位置之添加後的資訊 件*處理電路404輸出該封包流至匯流排I/F電路405 .匯 流排I/Fm路405输出該封包流至該網路· 微電腦403可經由該網路與匯流排1/F電路405在外 部裝置來回捕捉及接收非同步封包· 處理電路404之作業將更詳細地被解釋•就每一框而 言，處理電路404將第一視頻資料分為'V1件（視頻-1資料 件），此處"η”代表一預定的自然數•就如第5圖顯示者， 處理電路4G4循序地將此"η"個視頻-1資料件分別指派至 "η”個封包•就每一框而言，處理電路404將第二視頻資料 分為” η"件（視頻-2資料件）·如第5圈顯示者，處理電路 404循序地將此"η"個視頻-2資料件分別指派至” η"個封 包•因之’如第5圖顯示者，每一封包被裝了一對親頻-1 資料件與視頻-2資料件· 本發明之第二實施例除了下面指出之設計改變外類似 於其第一實施例· 在本發明之第二實施例中，其處理霱路（見第4圖） 如下列般地操作•就每一框而言，處理重路404將第一親 頻資料分為"2πΓ個塊（親頻-1資料塊），其中'’m"代表一個預 定的自然數。就如第6圖顯示者，處理電路404將該等"2m" 個視頻-1資料塊之前親頻-1資料塊（第一個至第ra個視頻 -1資料塊）指派給~第一封包。處理電路將該等"2m"個視頻 -1資料塊之後視頻-1資料塊（第ra + 1個至第2m個視頻-1 資料塊）指派給一第二封包*就每一框而言，處理毽路將第 -14- ----------裝I J · * (請先wflt面之注f項再if本頁 線 Γ 本紙張尺皮適用中HB家操率（CNS > A4规格（210X297公也) 432369 Α7 Β7 五、發明説明（1 2 ) 二視頻資料分為"2m"個塊（視頻-2資料塊）·就如第6圃顯 示者，處理電路將該等"2m”個親頻-2資料塊之前視頻-2資 料塊（第一個至第ra個視頻-2資料塊）指派給該第一封包· 處理電路將該等"2πΓ個視頻-2資料塊之後視頻-2資料塊 (第m+1個至第2m個視頻-2資料塊）指派給該第二封包。如 第6 _中顯示者，在毎一該等第一與第二封包中|視頻-1 資料塊在位置上與視頻-2資料塊交替。 本發明之第三實施例除了下面指出之設計改變外，類 似於其第一實施例* 本發明之第三實施例中，其處理電路404(見第4圓） 如下列般地操作*就每一框而言，處理電路404將第一親 經濟部智慧財產局貝工消费合作社印製 頻資料分為’'η"件（視頻Μ資料件），其中·η"代表一個預定 的自然數。處理電路404將該等"η"視頻-1資料件組成 ”η/2”組，每一組具有二個連續的視頻-1資料件。就如第7 圔顯示者，處理電路404循序地將該等"π/2”組分別指派給 前封包（第一個至第η/2個封包）。因之*如第7圖顯示者， 每一個該等前封包（第一個至第η/2個封包）被填裝二個連 績的視頻-1資料件。就每一框而言，處理電路404將第二 視頻資料分為"η"件（視頻-2資料件處理電路404將該等 ” η"視頻-2資料件組成"η/2"組，每一組具有二個連續的視 頻-2資料件•就如第7圖顯示者，處理電路404循序地將 該等"η/2”組分別指派給後封包（第n/2 + l個至第η個封 包）·因之*如第7圖顯示者每一個該等後封包C第n/2 + l 個至第η個封包）被填裝二個連續的視頻-2資料件。 _________一 15— _ 本紙張又度適用令团國家_準（€阳）戍4規格（210><297公釐） ⑽ 2869 A7 B7 經濟部智慧財產局負工消费合作社印製 五、發明説明（13) 本發明之第四實施例除了下面指出之設計改變外類似 於其第一寅施例· 在本發明之第四實施例中*其處理電路404(見第4圃） 與匯流排I/F電路405(見第4圔）如下列般地操作·處理電 路404將第一視頻資料（視頻-1資料）轉換或編碼成為一第 一封包流。處理霄路404將第二視頻資料（視頻-2資料）轉 換或編碼成為一第二封包流•處理電路404输出該等第一 與第二封包流至匯流排I/F電路405 ·如第8圖顯示者，匯 流排I/F電路405输出該第一封包流至該網路之一第一波 道（波道-A)。匯流排I/F電路405输出該第二封包流至該 網路之一第二波道（波道-B)·該第二波道與該第一波道不 同*如第8圖顯示者，就每一框而言，含有視頻-1資料一 部分之一封包與含有視頻-2資料一部分之一封包由匯流排 I/F電路405被傅輸至該網路· 第9圖顯示依據本發明第五實施例之影像捕捉及傳输 系統•第9_之系統包括成像裝置（影像感應器）601，602· 與6 08，信號處理器603，604與609，一收發機（一發射 器/接收器）605，一時間信號產生器606，及騍動電路607 與 610 · 成像裝置601隨後循序地有信號處理器603與收發機 60 5。成像裝置6Q2隨後循序地有信號處理器604與收發機 60 5。成像裝置608隨後循序地有信號處理器609與收發機 605。時間信號產生器606被連接於信號處理器603，604 與6D9>收發機605及驅動電路607與610·驅動電路607 16- 本紙張尺度逋用中國國家標準（CNS ) A4規格（210X297公釐） 請 先 聞 面 之 注 項 f 裝 訂 線 432869 A7 B7 五、發明説明（14 經濟部智慧財產局貝工消費合作社印製 被連接於成像裝置6Q1與602*驅動電路610被連接於成像 裝置608。收發機605被連接於例如包栝有IEEE 1394序列 匯流排之網路· 成像裝置601，成像裝置602,信號處理器60 3,信號 處理器604,時間信號產生器606與顆動電路607分別類似 於第1圓中之成像裝置i(H，成像裝置102,信號處理器 103,信號處理器104,時間信號產生器106與驊動電路 107 - 裝置606產生一時間信號·被裝置606產生之時間信 號包括一組次時間信號•係為一時鐘信號、一水平同步信 號與一垂直同步信號•裝置606輸出所產生之時間信號至 信號處理器603，604與609，收發機605，及驩動電路607 與 610 - 驩動電路60 7在回應於時間信號產生器6 06之輸出信 號下為成像裝置601與B02產生一共同驩動信號》驊動電 路60 7输出該囅動信號至成像裝置6Q1與602。因之•驅動 電路6 07在時間信號產生器60 6之輸出信號所決定的相同 時間操作或驊勤成像裝置601與602。 蹀動鬣路610在回應於時間信號產生器6 06之輸出信 號下為成像裝置608產生一囅動信號•躕勖電路610輸出 該驊動信號至成像裝置608。成像裝置608用之騸動信號提 供與為成像裝置601與602被驅動信號所提供之時間為不 同的時間*因之，騍勘電路610在與媒動成像裝置601及 602之時間不同的時間操作或驟動成像裝置608。 17- 本紙張尺度遑用中國國家樣準（CNS > Α4洗格（210X297公釐） 請 先 閲 Λ 之 注 項 ί 裝 訂 線 432869 A7 B7 五、發明説明（15) 成像裝置601在回應於驅動電路60 7之輸出信號下將 一影像轉換成對應的類比視頻信號•換西之*成像裝置601 在回應於驅動電路.60 7之輸出信號下實施影像捕捉*成像 裝置601輸出該類比視頻信號至信號處理器603。 成像裝置602在回應於驅動電路607之輸出信號下將 一影像轉換成對應的類比視頻信號•換言之，成像裝置602 在回應於驅動電路6 07之輸出信號下實施影像捕捉•成像 裝置60 2輸出該類比視頻信號至信號處理器604* 被成像裝置601捕捉之影像與被成像裝置602捕捉之 影像在驅動電路607之輸出信猇所決定的相同時間週期性 地出現。 成像裝置608在回應於鄹動電路607之输出信號下將 一影像轉換成對應的類比視頻信號*換言之，成像裝置608 在回應於驩動電路610之输出信號下實施影像捕捉•成像 裝置608輸出該類比視頻信號至信號處理器609 · 被成像裝置608捕捉之影像週期地在一時間出現，其 係由驅動電路610之输出信號所決定，且其與被每一成像 裝置601與602所捕捉之影像的時間不同· 經濟部智慧財產局負工消費合作社印製 信號處理器60 3在回應於時間信號產生器606之輸出 信號下將成像裝置601之輸出信號轉換成為一第一數位視 頻信號。該第一數位視頻信號亦被稱為第一視頻資料。信 號處理器603輸出該第一視頻資料至收發機60 5 · 信號處理器604在回應於時間信號產生器60 6之輸出 信號下將成像裝置602之輸出信號轉換成為一第二數位視 ____- 18-_ 本紙張尺A通用中0®家揉準（^NS ) A4规格（210X2.97公羞) 4I2S69 ； A7 … B7 五、發明説明（ 16 經濟部智慧財產局员工消费合作社印製 頻信號。該第二數位視頻信號亦被稱為第二視頻資料•信 號處理器604输出該第二視頻資料至收發機605 · 信號處理器609在回應於時間信號產生器606之輸出 信號下將成像裝置6Q8之輸出信號轉換成為一第三數位視 頻信號*該第三數位視頻信號亦被稱為第三視頻資料•信 號處理器609輸出該第三視頻資料至收發機60 5。 收發機605包括一封包編碼器，其在回應於時間信號 產生器60 6之輸出信號下將該等第一視頻資料、第二視頻 資料與第三視頻資料轉換或編碼成為一封包流。每一封包 被裝填該第一視頻資料的一部分、該第二視頻資料的一部 分與該第三視頻資料的一部分至少之一·收發機605轅出 該封包流至該網路* 收發機605能由網路接收非同步的封包•收發機605 將所接收的非同歩封包轉換或解碼成為其所負載之資訊 件* 第10圓顯示依據本發明第六實施例之影像捕捉及傳輸 系統•第10圈之系統包括成像裝置（影像感應器）701與 下02，信號處理器704與704，一收發機（發射器/接收 器）70 5, 一時間信號產生器70 6,及一驅動電路707 · 成像裝置7G1隨後循序地有信號處理器703與收發機 705。成像裝置7G2隨後循序地有信號處理器70 4與收發機 70 5。時間信號產生器706被連接於信號處理器7G 3與704， 收發機705,及驅動電路707·驅動電路707被連接於成像 裝置701與702。收發機705被連接於例如包括有IEEE 1394 請 先 閲 A 之 注 項 裝 頁 訂 線 19- 本紙张逋用中準（CNS ) A4规格（210X297公釐} 432869 A7 B7 五、發明説明（1?) 經濟部智慧財產局工消費合作社印製 序列匯流排之網路。 成像裝置701，成像裝置70 2,信號處理器70 3,信號 處理器704,與騸動電路707分別類似於第1圖之成像裝置 101，成像裝置丨02,信號處理器103,信號處理器104,及 驅動電路107 · 一週期開始封包（CSP)在該網路內週期性地被傳輸•收 發機70 5由該網路接收每一個週期開始封包。收發機705 在回應於所接收之週期開始封包下產生一通訊同步信號。 該通訊同步信號與所接收之週期開始封包被同步化。收發 機705輸出該通訊同步信號至時間信號產生器706 » 裝置706在回應於由收發機705所被饋給之該通訊同 步信號下產生一時間信號·就如稍後被指出者’被裝置706 產生之時間信號包括一組次時間信號，即為—時鐘信號' 一水平同步信號與一垂直同步信號*裝置706輪出所產生 之時間信號至信號處理器703與704，收發機705 ’及驅動 電路707。 驅動電路70 7在回應於時間信號產生器706之輸出信 號下為成像裝置701與70 2產生一共同驅動信號*驅動電 路707輸出該驊動信號至成像裝置701與702»因之’驅勖 電路驟動電路70 7在時間信號產生器706之輸出信號所決 定的共同時間操作或騸動成像裝置701與702 * 成像裝置701在回應於驅動電路707之輸出信號下將 一影像轉換成為對應的類比視頻信號*換言之’成像裝置 701在回應於騸動電路707之輸出信號下實施影像捕捉*成 20- 本纸張尺度適用中國《家揉準（CNS > Α4規格（210X297公釐） 請 先 Μ 面 之 注 項 再 令 頁 裝 訂 線 432869 Α7 Β7 經濟部智慧財度局黃工消費合作社印製 五、發明説明（18 ) 像裝置70 1輸出該類比視頻信號至信號處理器703 · 成像裝置702在回應於驊動電路707之輸出信號下將 一影像轉換成為對應的類比視頻信號。換言之，該成像裝 置702在回應於驅動電路707之輸出信號下實施影像捕 捉•成像裝置702輸出該類比視頻信號至信號處理器704* 被成簾裝置7G1捕捉之影像與被成像裝置702捕捉之 影像在驅動電路707之輸出信號所決定的相同時間週期性 地出現》 信號處理器703在回應於時間信號產生器706之輸出 信號下將成像裝置701之输出信號轉換成為一第一數位親 頻信號•該第一數位視頻信號亦被稱為第一視頻資料*信 號處理器7G3輸出該第一視頻資料至收發機705· 信號處理器704在回應於時間信號產生器706之輸出 信號下將成像裝置702之輸出信號轉換成為一第二數位視 頻信號。該第二數位視頻信號亦被稱為第二視頻資料•信 號處理器704輸出該第二視頻資料至收發機7 05 · 收發機7G5包括一封包編碼器，其在回應於時間信號 產生器706之輸出信號下將該第一視頻資料與該第二視頻 資料轉換或編碼成為封包流。收發機705输出該封包流至 該網路· 收發機70S能由該網路接收非同步封包•收發機705 將所接收之非同步封包轉換或解碼成為非所負載之資訊 件· 就如第11圖顯示者，時間信號產生器706包括一振盪 21- 本紙張尺度逋用中繭國家揉準（CNS } Α4規格（2丨ΟΧ 297公釐） 請 先 閲 Λ 之 注 意 事 項 个 夏 裝 訂 線 A7 B7 五、發明説明（19) 電路801，一水平同步信號產生器80 2,與一垂直同步信號 產生器8 03。振盪電路801被連接於水平同步信號產生器 80 2與垂直同步信號產生器8 03。水平同步信猇產生器8 02 被連接於收發機705(見第10圃）與垂直同步信號產生器 803 · 經濟部智慧財產局工消費合作社印製 振盪電路801產生具有預定頻率之一時鐘信號。振盪 電路801輸出該時鐘信號至水平同步信號產生器802與垂 直同步信號產生器803。水平同步信號產生器802由收發機 705接收該通訊同步信號•裝置80 2在回應於該時鐘信號與 該通訊同步信號下產生一水平冏步信號•較佳的是，該水 平同步信號與該通訊同步信號被同步化*該水平同步信號 產生器802例如包括一計數器回應於該時鐘信號與該通訊 同步價號》裝置802輸出該水平同步信號至垂直同步信號 產生器803。裝置803在回應於該時鐘信號與該水平同步信 號下產生一垂直同步信號•該垂直同步信號產生器803例 如包括一計數器回應於該時鐘信號與該水平同步信號*振 盪電路801，水平同步信號產生器802與垂直同步信號產生 器80 3輸出該時鐘信號，該水平同步信號與該垂直同步信 號，其為次時間信號含有被時間信號產生器70 6產生及輸 出之時間信號。 就如第12圖顯示者，收發機705包括記憶體1001與 1002，一微電腦1003·—處理電路1004,與一匯流排I/F(介 面）電路1005·記憶體1001被連接於信號處理器703(見第 10圖）與處理電路1004·記憶體1002被連接於信號處理器 一 22— 本紙張尺度逋用中®國家梯率（CNS ) A4規格（210X297公釐) ' 432869 Α7 Β7 經濟部智慧財產局貝工消費合作社印製 五、發明説明（20 ) 704(見第10圖）與處理電路1004*處理電路1004被連接於 時間信號產生器7〇6(見第1〇圃）與匯流排I/F霪路10 05 · 匯流排I/F電路10 05連接於該網路•微電腦H03被連接 於處理電路1QQ4與匯流排I/F電路1005· 由信號處理器703被輸出之第一視頻資料被館存於記 憶髋1001內·由信號處理器704被輪出之第二視頻資料被 館存於記憶體1 002內·微電腦1 003依照儲存於其內之程 式控制處理電路1004與匯流排I/F電路1 005·該程式被設 計來實施下列處理♦處理電路1004在時間信號產生器706 之輸出信號所決定的特定時間由記憶體1001與1002讀出 該第一親頻資料與該第二視頻資料*處理電路1004包括一 封包編碼器，其在回應於時間信號產生器706之輸出信號 下將該第一視頻資料與該第二視頻資料轉換或編碼成為一 封包流。例如，毎一封包被裝填該第一視頻資料之一部分 與該第二視頻資料之一部分的至少之一·較佳的是，每一 封包含有代表其中之視頻資料的格式添加後的資訊件、代 表造成其中之視頻資料的成像裝置之辨識號碼的添加後的 資訊件、以及代表由其中之視頻資料所代表之影像部分的 位置之添加後的資訊件*處理電路1004输出該封包流至匯 流排I/F電路1005*匯流排I/F電路1QQ5输出該封包流至 該網路· ^ 就如先前所指出者，一週期開始封包（CSP)在該網路內 被週期地傅輸。匯流排I/F電路1005在由該網路接收每一 個週期開始封包。匯流排I/F電路10 05在回應於所接收之 23- 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） Λ 之 注 項The Consumer Property Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs prints the thirteenth level of the present invention according to its first level. It also provides an image capture and transmission system. It further includes facilities for sensing the first digital video data and the second The digital video data identifies the object within each frame and generates sensing result information, and the facility is used to change the effective area within each frame in response to the sensing result information. FIG. 1 is a block circle of an image capturing and transmitting system according to a first embodiment of the present invention. Figure 2 is a block diagram of the time signal generator in Figure 1. Figure 3 is a block diagram of the signal processor in the first circle. Figure 4 is a block diagram of the transceiver in Figure 1. Figure 5 The picture shows the packet and the video data files placed in the packet in the first circle system. Figure 6 shows a packet and a video data block placed in a packet in an image capture and transmission system according to a second embodiment of the present invention. Figure 7 shows a packet and a video capture in a third embodiment of the present invention. And video data files in the sugar transmission system. FIG. 8 is a diagram of a packet and first video data and second video data placed in a packet in an image capture and transmission system according to a fourth embodiment of the present invention. FIG. 9 is a fifth embodiment of the present invention. Block diagram of the image capture and transmission system. Figure 10 is a block diagram of the image capture and transmission system according to the sixth embodiment of the present invention. "Figure 11 is a block diagram of the time signal generator in Figure 10 * Please Note on the first page of this page The dimensions of this paper are applicable to the national standard of the country < Renyou) Rong 4 specifications (210 > < 297 mm) 432869 A7 B7 V. Description of the invention (6) The 12th is the 10th The block diagram of the transceiver in the picture. Figure 13 is the time range of the signals and data of the system in Figure 10. Figure 14 is printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Figure 14 is the seventh embodiment of the present invention. Block diagram of an image capture and transmission system. Fig. 15 is a block diagram of the transceiver in Fig. 14 (a). Fig. 16 is a block diagram of an image capture and transmission system according to an eighth embodiment of the present invention. Fig. 17 is a block diagram of a transceiver in a 16th sleepy state. Fig. 18 is an image capture according to a ninth embodiment of the present invention. Block diagram of the transmission system * Figure 19 is a block diagram of the transceiver in Figure 18 and Figure 20 is a block circle of the image capture and transmission system according to the tenth embodiment of the present invention. Figure 21 is a block diagram of the transceiver in circle 20. Circle 22 is a block diagram of the image capture and transmission system according to the eleventh embodiment of the present invention. Block diagram. Figure 24 is a diagram of a frame and an effective area. Figure 25 is a block diagram of the area setting circuit in Figure 23. Figure 26 is a block diagram of a computer in the twelfth embodiment of the present invention. Flowchart of program blocks. Figure 1 illustrates the image capture and transmission system according to the first embodiment of the present invention. The system of Figure 1 includes imaging devices (image sensors) 101 and 102. Please read the note on the first page to install the η script. Paper scales are printed in China National Standards (CNS) Α4 size (2ίΟΧ297 公 *) 432869 A7 B7 Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs® Industrial and Consumer Cooperatives 5. Description of the invention (7), signal processors 103 and 104, a transceiver (A transmitter / receiver) 105, a time signal generator 106, and an automatic circuit 107. Imaging device 1QI sequentially has a signal processor 103 and transceiver 105. Imaging device 1D2 then has a sequential signal processing.器 104 与 designated transceiver 105. The time signal generator 106 is connected to the signal processor 1 (13 and 104, the transceiver 1Q5, and the driving circuit 107, and the driving circuit 107 is connected to the imaging devices 101 and 102. The transceiver is connected to a network including: For example, for IEEE 1394 serial bus * Device 106 generates a time signal. As will be pointed out later | The time signal generated by device 106 includes a set of sub-time signals. It is a clock signal, a horizontal synchronization signal, and a vertical Synchronization signal • The device 106 outputs the generated time signal to the signal processors 103 and 104, the transceiver 105, and the driving circuit 107. * The moving circuit 107 responds to the output signal of the time signal generator 106 as the imaging devices 101 and 102. A common driving signal is generated to drive the circuit 107 to output the joy signal to the imaging devices 101 and 102. Therefore, the moving circuit 107 operates or drives the imaging devices 101 and 102 at the same time as determined by the output signal of the time signal generator 106. The imaging device 101 converts an image into a corresponding analog video signal in response to the output signal of the automatic circuit 107. In other words, the imaging device 101 is responding to Image capture is performed under the output signal of the moving circuit 107. The imaging device 101 outputs the analog video signal to the signal processor 103. The imaging device 102 converts an image into a corresponding analog video signal in response to the output signal of the driving circuit 107. In other words, 'Imaging device 10- This paper size is applicable to China National Standards (CNS) A4 (210X297 mm). First read the binding line 869 on the back.-Printed by Shelley Consumer Cooperative, Intellectual Property Bureau, Ministry of Economic Affairs (8) Image capture is performed in response to the output signal from the drive circuit 107. The imaging device 102 outputs the analog video signal to the signal processor 104. The image captured by the imaging device 1G1 and the image captured by the imaging device 102 are moving. The same time period determined by the output signal of the circuit 107 occurs * The signal processor 103 converts the output signal of the imaging device 101 into a first digital video data in response to the output signal of the time signal generator 106. The first digital video The data is also referred to as the first frequency data. The signal processor 103 outputs the first video data. To the transceiver 105 · The signal processor 104 converts the output signal of the imaging device 102 into a second digital frequency data in response to the output signal of the time signal generator 106 * The second digital video data is also referred to as the second video The data / signal processor 104 outputs the second video data to the transceiver 105. The transceiver 105 includes a packet encoder, and responds to the first frequency data and the second video data in response to the output signal of the time signal generator 106 Conversion into packet stream • The transceiver 105 outputs the packet stream to the network. Transceiver 105 can receive asynchronous packets from the network * Transceiver 105 converts or decodes the received asynchronous packets into the information pieces attached to it. As shown in Figure 2, the time signal generator 106 includes an oscillation Circuit 201, a horizontal synchronization signal generator 2G2 and a vertical synchronization signal generator 203. Oscillation mold circuit 201 is connected to the horizontal synchronization signal generator 202 and the vertical synchronization signal generator 203. The horizontal synchronization signal generator 202 is connected to the vertical Synchronous signal generator 203 · The oscillation circuit 201 generates a clock signal with a predetermined frequency · Oscillation -11- This paper is used in a small scale, a home kneading rate icNS has A4 specifications (2! 0X297 mm) (please first M Read the note on the back and read this page again. Binding · Order-Line · Γ 432869 Printed by the Consumers ’Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs A7 _B7_ V. Description of Invention (9) Circuit 201 outputs the clock signal to the horizontal synchronization signal generator 20 2 and the vertical synchronization signal generator 203. The device 202 generates a horizontal synchronization signal in response to the clock signal. The horizontal synchronization signal generator 202 includes, for example, a counter in response to the clock signal. Device 202 The horizontal synchronization signal is output to the vertical synchronization signal generator 203. The device 203 generates a vertical synchronization signal in response to the clock signal and the horizontal synchronization signal * The vertical synchronization signal generator 203 includes, for example, a counter in response to the clock signal and the horizontal Synchronization signal * The vibrating circuit 201, the horizontal synchronization signal generator 2G2, and the vertical synchronization signal generator 203 output the clock signal, the horizontal synchronization signal, and the vertical synchronization signal, which are secondary time signals, which are generated by the time signal generator. And output time signals. The signal processors 1G3 and 104 have similar structures to each other. Therefore, only the signal processor 1Q3 will be explained in detail. As shown in Figure 3, the signal processor 103 includes an A / D (analog Logarithmic-to-digital) conversion circuit 301 and a signal processing circuit 302. The A / D conversion circuit 301 is connected to the imaging device 101 (see Fig. 1), the time signal generator 106 (see Fig. 1), and the signal processing circuit. 302. The signal processing circuit 3Q2 is connected to the transceiver 105 (see Fig. 1). The A / D conversion circuit 301 responds to the clock signal sent by the time signal generator 106. The analog signal of the output signal of the imaging device 101 was subjected to digital conversion. Therefore, the A / D conversion circuit 301 changes the output signal of the imaging device 101 to the corresponding digital video data. The A / D conversion circuit 301 outputs the digital video. Data-to-signal processing circuit 302 · Signal processing mold circuit 302 has been subjected to level conversion and format conversion of the output signal of A / D conversion circuit 301 * _____ — 12—_ This paper uses the Chinese National Standard (CNS) Α4 specification (210X297 mm) 432869 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (1 G) Therefore, the output signal of the A / D conversion circuit 301 is changed to the first video data with a given format. The signal processing circuit 302 outputs the first video data to the transceiver 105. * As shown in the fourth circle, the transceiver 105 includes a memory 401 and 402, a microcomputer 403, a processing mold 404, and a bus I / F. (Interface) Circuit 405 · Memory 401 is connected to signal processor 103 (see Figure 1) and processing circuit 404 · Memory Link 40 is connected to signal processor 104 (see circle 1) and processing circuit 404 The processing circuit 404 is connected to the time signal generator 106 (see section 1) and the bus I / F circuit 405. The bus I / Fm circuit 405 is connected to the network. The microcomputer 40 3 is connected to the processing circuit. 40 4 AND bus I / F circuit 405 »The first video data output by the signal processor 103 is stored in the memory 401 * The second video data output by the signal processor 104 is stored in the memory 402 The microcomputer 403 controls the processing circuit 404 and the bus I / F circuit 405 according to a program stored therein. The program is designed to perform the following processing. The processing circuit 404 is at a specific time determined by the output signal of the time signal generator 106. Read out the first video data from the memories 401 and 402 And the second video data. The processing circuit 4G4 includes a packet encoder that converts or encodes the first video data with the second video data in response to the turn-out signal of the time signal generator 106. For example, each packet is Loading at least one of a portion of the first video material and a portion of the second video material. Preferably, each piece of information includes an added piece of information representing the format of the audio data therein, resulting in a video therein. The imaging device of the data represents the information piece after the identification number is added, and the 13- size of this paper is applicable to the Chinese National Standard (CNS > A4 size (210X297 mm)) Please read the note 432869 A7 on the back first B7 Printed by the Shelley Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs V. The added information piece of the position of the image part represented by the video data in the description of invention (11) * The processing circuit 404 outputs the packet stream to the bus I / F Circuit 405. The bus I / Fm circuit 405 outputs the packet stream to the network. The microcomputer 403 can capture and connect to the external device via the network and the bus 1 / F circuit 405. Asynchronous packet · The operation of the processing circuit 404 will be explained in more detail. • For each frame, the processing circuit 404 divides the first video data into 'V1 pieces (video-1 data pieces), here " η " Represents a predetermined natural number. As shown in Figure 5, the processing circuit 4G4 sequentially assigns this " η " video-1 data piece to " η "packets. • For each frame, processing The circuit 404 divides the second video data into “η” pieces (video-2 data pieces). As shown in the fifth circle, the processing circuit 404 sequentially assigns these “η” video-2 data pieces to “η” respectively. Each packet • Because of this, as shown in Figure 5, each packet is loaded with a pair of pro-frequency-1 data pieces and video-2 data pieces. The second embodiment of the present invention is similar except for the design changes indicated below. In its first embodiment · In the second embodiment of the present invention, it processes the loop (see Figure 4) as follows: • For each frame, the processing loop 404 processes the first frequency data. Divided into " 2πΓ blocks (Frequency-1 data block), where "m " represents a pre- A fixed natural number. As shown in Figure 6, the processing circuit 404 assigns the " 2m " video-1 data blocks to the pre-frequency-1 data blocks (the first to ra video-1 data blocks) to the first Packet. The processing circuit assigns these " 2m " video-1 data blocks after the video-1 data block (ra + 1 to 2m video-1 data block) to a second packet * for each frame ， Handling Kushiro will be -14- ---------- install IJ · * (please note the f item on the wflt surface and then the if page line Γ This paper ruler is applicable to HB homework rate (CNS > A4 specifications (210X297) also 432369 Α7 Β7 V. Description of the invention (1 2) The second video material is divided into " 2m " blocks (video-2 data blocks). Just like the 6th display, the processing circuit will These "2m" video frequency-2 data blocks before the video-2 data block (the first to the ra video-2 data blocks) are assigned to the first packet. The processing circuit assigns these " 2πΓ videos The video-2 data block (m + 1th to 2m video-2 data blocks) after the -2 data block is assigned to the second packet. As shown in 6_, one of the first and second In the second packet, the video-1 data block alternates with the video-2 data block in position. The third embodiment of the present invention is similar to its first embodiment, except for the design changes indicated below * The third embodiment of the present invention In the embodiment, the processing circuit 404 (see circle 4) operates as follows. * For each frame, the processing circuit 404 divides the printed data of the Shellfish Consumer Cooperative of the Intellectual Property Bureau of the First Pro-Ministry of Economic Affairs into ' 'η " pieces (video M data pieces), where · η " represents a predetermined natural number. The processing circuit 404 groups these " η " video-1 data pieces into "η / 2" groups, each group having two One continuous video-1 data piece. Just like the 7th displayer, the processing circuit 404 sequentially assigns these " π / 2 "groups to the previous packets (first to n / 2 packets). Therefore * as shown in Figure 7, each of these previous packets (first to n / 2 packets) is filled with two consecutive video-1 data files. For each box, processing The circuit 404 divides the second video data into " η " pieces (the video-2 data piece processing circuit 404 groups these "η " video-2 data pieces into " η / 2 " groups, each group having two consecutive Video-2 data file • As shown in Figure 7, the processing circuit 404 sequentially assigns these " η / 2 "groups to Packets (n / 2 + l to η packets) · Therefore * as shown in Figure 7, each of these subsequent packets C (n / 2 + l to η packets) is filled with two Consecutive video-2 materials. _________ 一 15— _ This paper is again applicable to the order country _ standard (€ yang) 戍 4 specifications (210 > < 297 mm) ⑽ 2869 A7 B7 Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Industrial and Commercial Cooperatives 5. Description of the Invention (13) The fourth embodiment of the present invention is similar to its first embodiment except for the design changes indicated below. In the fourth embodiment of the present invention * its processing circuit 404 ( (See Section 4) and the bus I / F circuit 405 (see Section 4) operates as follows. The processing circuit 404 converts or encodes the first video data (video-1 data) into a first packet stream. The processing channel 404 converts or encodes the second video data (video-2 data) into a second packet stream. The processing circuit 404 outputs the first and second packet streams to the bus I / F circuit 405. The figure shows that the bus I / F circuit 405 outputs the first packet stream to a first channel (channel-A) of the network. The bus I / F circuit 405 outputs the second packet to a second channel (channel-B) of the network. The second channel is different from the first channel. * As shown in FIG. 8, For each frame, a packet containing a part of the video-1 data and a packet containing a part of the video-2 data are input to the network by the bus I / F circuit 405. Figure 9 shows that according to the present invention, the Five embodiments of the image capture and transmission system • The 9th system includes imaging devices (image sensors) 601, 602, and 6 08, signal processors 603, 604, and 609, a transceiver (a transmitter / receiver Device) 605, a time signal generator 606, and automatic circuits 607 and 610. The imaging device 601 sequentially has a signal processor 603 and a transceiver 605. The imaging device 6Q2 then sequentially has a signal processor 604 and a transceiver 605. The imaging device 608 sequentially has a signal processor 609 and a transceiver 605. The time signal generator 606 is connected to the signal processors 603, 604 and 6D9 > the transceiver 605 and the driving circuits 607 and 610. The driving circuit 607 16- This paper size uses the Chinese National Standard (CNS) A4 specification (210X297 mm) Please read the note f above. Gutter 432869 A7 B7 V. Description of the invention (14 Printed by the Shelley Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs and printed on the imaging device 6Q1 and 602 * The driving circuit 610 is connected to the imaging device 608. Transceiver The machine 605 is connected to, for example, a network including an IEEE 1394 serial bus. The imaging device 601, the imaging device 602, the signal processor 60 3, the signal processor 604, the time signal generator 606, and the micro circuit 607 are similar to The imaging device i (H, imaging device 102, signal processor 103, signal processor 104, time signal generator 106, and automatic circuit 107) in the first circle-device 606 generates a time signal · time signal generated by device 606 Includes a set of sub-time signals. It is a clock signal, a horizontal synchronization signal and a vertical synchronization signal. The device 606 outputs the generated time signal to the signal processors 603, 604 and 609. Transceiver 605, and joy circuit 607 and 610-joy circuit 60 7 generate a joy signal for imaging devices 601 and B02 in response to the output signal of time signal generator 6 06 The automatic signal is sent to the imaging devices 6Q1 and 602. Therefore, the driving circuit 6 07 operates or performs the imaging devices 601 and 602 at the same time as determined by the output signal of the time signal generator 60 6. The automatic circuit 610 is responding to The output signal of the time signal generator 6 06 generates an automatic signal for the imaging device 608. The electronic circuit 610 outputs the automatic signal to the imaging device 608. The automatic signal used by the imaging device 608 is provided to the imaging devices 601 and 602. The time provided by the driven signal is different time * Therefore, the survey circuit 610 operates or snaps the imaging device 608 at a time different from the time of the media motion imaging devices 601 and 602. 17- This paper uses China Sample (CNS > Α4 wash grid (210X297mm) Please read the note of Λ first gutter 432869 A7 B7 V. Description of the invention (15) The imaging device 601 is responding to the output signal of the driving circuit 60 7 Convert an image into a corresponding analog video signal. • Change the Western * imaging device 601 to perform image capture in response to the output signal of the driving circuit. 60 7 * The imaging device 601 outputs the analog video signal to the signal processor 603. Imaging device 602 converts an image into a corresponding analog video signal in response to the output signal of the driving circuit 607. In other words, the imaging device 602 performs image capture in response to the output signal of the driving circuit 607. The imaging device 60 2 outputs the analog video. Signal to signal processor 604 * The image captured by the imaging device 601 and the image captured by the imaging device 602 appear periodically at the same time as determined by the output signal of the driving circuit 607. The imaging device 608 converts an image into a corresponding analog video signal in response to the output signal of the moving circuit 607. In other words, the imaging device 608 performs image capture in response to the output signal of the moving circuit 610. The imaging device 608 outputs the Analog video signal to the signal processor 609. The image captured by the imaging device 608 appears periodically at a time, which is determined by the output signal of the driving circuit 610, and it is the same as the image captured by each imaging device 601 and 602. The time is different. The printed signal processor 60 3 of the Intellectual Property Bureau of the Ministry of Economic Affairs and the Consumer Cooperatives converts the output signal of the imaging device 601 into a first digital video signal in response to the output signal of the time signal generator 606. The first digital video signal is also referred to as a first video material. The signal processor 603 outputs the first video data to the transceiver 60 5 · The signal processor 604 converts the output signal of the imaging device 602 into a second digital video in response to the output signal of the time signal generator 60 6 ____- 18-_ This paper rule A is general 0 0 home rubbing (^ NS) A4 specification (210X2.97 public shame) 4I2S69; A7… B7 V. Description of invention (16 Intellectual Property Bureau of the Ministry of Economic Affairs Employee Cooperative Cooperative printed frequency signal The second digital video signal is also referred to as the second video data. The signal processor 604 outputs the second video data to the transceiver 605. The signal processor 609 responds to the output signal of the time signal generator 606. The output signal of 6Q8 is converted into a third digital video signal. The third digital video signal is also called third video data. The signal processor 609 outputs the third video data to the transceiver 60 5. The transceiver 605 includes a packet An encoder that converts or encodes the first video data, the second video data, and the third video data into a packet stream in response to the output signal of the time signal generator 60 6. A packet is filled with at least one of a portion of the first video material, a portion of the second video material, and a portion of the third video material. The transceiver 605 sends the packet to the network. Receiving non-synchronous packets • Transceiver 605 converts or decodes received non-synchronous packets into its loaded information pieces * Circle 10 shows the image capture and transmission system according to the sixth embodiment of the present invention. Circle 10 The system includes imaging devices (image sensors) 701 and 02, signal processors 704 and 704, a transceiver (transmitter / receiver) 70 5, a time signal generator 70 6, and a driving circuit 707. · Imaging The device 7G1 then has a signal processor 703 and a transceiver 705 in sequence. The imaging device 7G2 then has a signal processor 70 4 and a transceiver 70 5. The time signal generator 706 is connected to the signal processors 7G 3 and 704. Machine 705, and driving circuit 707. The driving circuit 707 is connected to the imaging devices 701 and 702. The transceiver 705 is connected to, for example, IEEE 1394. Please read the note binding line 19 of A. This paper 逋CNS A4 specification (210X297 mm) 432869 A7 B7 V. Description of the invention (1?) The network of serial buses printed by the Industrial Property and Consumer Cooperatives of the Ministry of Economic Affairs. Imaging device 701, imaging device 70 2, signal The processor 70 3, the signal processor 704, and the automatic circuit 707 are similar to the imaging device 101, the imaging device 02, the signal processor 103, the signal processor 104, and the driving circuit 107 in FIG. 1, respectively. (CSP) is periodically transmitted in the network. The transceiver 70 5 receives packets from the network to start each cycle. The transceiver 705 generates a communication synchronization signal in response to the start packet in response to the received cycle. The communication synchronization signal is synchronized with the received cycle start packet. The transceiver 705 outputs the communication synchronization signal to the time signal generator 706. The device 706 generates a time signal in response to the communication synchronization signal fed by the transceiver 705. As will be pointed out later, the device 706 The generated time signal includes a set of secondary time signals, namely, a clock signal, a horizontal synchronization signal and a vertical synchronization signal. The time signal generated by the device 706 is output to the signal processors 703 and 704, the transceiver 705, and the driving circuit. 707. The driving circuit 70 7 generates a common driving signal for the imaging devices 701 and 70 2 in response to the output signal of the time signal generator 706. The driving circuit 707 outputs the driving signal to the imaging devices 701 and 702. The snap circuit 70 7 operates or moves the imaging devices 701 and 702 at a common time determined by the output signal of the time signal generator 706 * The imaging device 701 converts an image into a corresponding analog in response to the output signal of the driving circuit 707 Video signal * In other words, the imaging device 701 performs image capture in response to the output signal of the automatic circuit 707 * to 20- This paper size applies to China's "JIAJUN (CNS > Α4 size (210X297mm) please first M The above-mentioned items are printed on the page binding line 432869 Α7 Β7 Printed by the Huanggong Consumer Cooperative of the Bureau of Wisdom and Finance of the Ministry of Economic Affairs 5. Description of the invention (18) The image device 70 1 outputs the analog video signal to the signal processor 703 · The imaging device 702 is An image is converted into a corresponding analog video signal in response to the output signal of the automatic circuit 707. In other words, the imaging device 702 is Image capture is performed under the output signal of Road 707. The imaging device 702 outputs the analog video signal to the signal processor 704. The image captured by the curtain device 7G1 and the image captured by the imaging device 702 are determined by the output signal of the driving circuit 707. Appears periodically at the same time. ”The signal processor 703 converts the output signal of the imaging device 701 into a first digital frequency signal in response to the output signal of the time signal generator 706. The first digital video signal is also called The first video data * signal processor 7G3 outputs the first video data to the transceiver 705. The signal processor 704 converts the output signal of the imaging device 702 into a second digital video in response to the output signal of the time signal generator 706. The second digital video signal is also called the second video data. The signal processor 704 outputs the second video data to the transceiver 7 05. The transceiver 7G5 includes a packet encoder which responds to the time signal generator. The first video data and the second video data are converted or encoded into a packet stream under the output signal of 706. Transceiver 705 The packet flows to the network. Transceiver 70S can receive non-synchronous packets from the network. Transceiver 705 converts or decodes the received non-synchronous packets into unloaded information pieces. As shown in Figure 11 The time signal generator 706 includes an oscillating 21-country standard (CNS} Α4 size (2 丨 〇 × 297 mm) for this paper size. Please read the precautions of Λ first, summer binding line A7 B7 V. Invention Explanation (19) A circuit 801, a horizontal synchronization signal generator 802, and a vertical synchronization signal generator 803. The oscillation circuit 801 is connected to the horizontal synchronization signal generator 80 2 and the vertical synchronization signal generator 80 03. The horizontal synchronizing signal generator 80 02 is connected to the transceiver 705 (see Section 10) and the vertical synchronizing signal generator 803. Printed by the Industrial and Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economics The oscillation circuit 801 generates a clock signal having a predetermined frequency. The oscillation circuit 801 outputs the clock signal to the horizontal synchronization signal generator 802 and the vertical synchronization signal generator 803. The horizontal synchronization signal generator 802 receives the communication synchronization signal by the transceiver 705. The device 80 2 generates a horizontal pacing signal in response to the clock signal and the communication synchronization signal. Preferably, the horizontal synchronization signal communicates with the communication. The synchronization signal is synchronized * The horizontal synchronization signal generator 802 includes, for example, a counter in response to the clock signal and the communication synchronization number. The device 802 outputs the horizontal synchronization signal to the vertical synchronization signal generator 803. The device 803 generates a vertical synchronization signal in response to the clock signal and the horizontal synchronization signal. The vertical synchronization signal generator 803 includes, for example, a counter in response to the clock signal and the horizontal synchronization signal * oscillation circuit 801. The horizontal synchronization signal is generated. The generator 802 and the vertical synchronizing signal generator 80 3 output the clock signal, the horizontal synchronizing signal and the vertical synchronizing signal, which are secondary time signals including the time signal generated and output by the time signal generator 70 6. As shown in Figure 12, the transceiver 705 includes memories 1001 and 1002, a microcomputer 1003 · -processing circuit 1004, and a bus I / F (interface) circuit 1005 · memory 1001 is connected to the signal processor 703 (See Figure 10) and processing circuit 1004 · Memory 1002 is connected to the signal processor 22—this paper size is in use® National Slope (CNS) A4 specification (210X297 mm) '432869 Α7 Β7 Ministry of Economy Wisdom Printed by the Shellfish Consumer Cooperative of the Property Bureau. 5. Description of the invention (20) 704 (see Fig. 10) and processing circuit 1004 * The processing circuit 1004 is connected to the time signal generator 706 (see 10th garden) and the bus. I / F circuit 10 05 · Bus I / F circuit 10 05 is connected to this network • Microcomputer H03 is connected to processing circuit 1QQ4 and bus I / F circuit 1005 · First video output by signal processor 703 The data is stored in the memory hip 1001. The second video data rotated by the signal processor 704 is stored in the memory 1 002. The microcomputer 1 003 controls the processing circuit 1004 and the bus according to the program stored therein. I / F circuit 1 005 · This program is designed to perform the following processing The processing circuit 1004 reads the first frequency data and the second video data from the memories 1001 and 1002 at a specific time determined by the output signal of the time signal generator 706. The processing circuit 1004 includes a packet encoder, which responds The first video data and the second video data are converted or encoded into a packet stream under the output signal of the time signal generator 706. For example, a packet is filled with at least one of a portion of the first video material and a portion of the second video material. Preferably, each of the packets contains information files, The added information piece that caused the identification number of the imaging device of the video data therein, and the added information piece representing the position of the image part represented by the video data therein * The processing circuit 1004 outputs the packet stream to the bus I / F circuit 1005 * bus I / F circuit 1QQ5 outputs the packet stream to the network. ^ As previously indicated, a cycle start packet (CSP) is periodically transmitted in the network. The bus I / F circuit 1005 starts to packetize every cycle received by the network. The bus I / F circuit 10 05 is responding to the received 23- This paper size applies the Chinese National Standard (CNS) A4 specification (210 × 297 mm) Note Item

I 裝 1丁 線 432869 . A7 B7 五、發明説明Ul ) 經濟部智慧財產局興工消费合作社印製 週期開始封包下產生一通訊同步信號。該通訊同步信號與 所接收之週期開始封包被同步化。匯流排I/F電路1005輸 出該通訊同步信號至時間信號產生器706。時間信號產生器 706在回應於該通訊同步信號下產生一水平同步信號•就如 第13圓顯示者，該水平同步信號具有一列脈衝（水平同步 脈衝）與該通訊同步信號中之各別脈衝被同步化。時間信號 產生器70 6輸出該水平同步信號至驅動電路70 7·驅動電路 70 7在回應於該水平同步信號下操作成像裝置701與702· 就如先前所指出者*信號處理器703將成像裝置701之輪 出信號轉換成為一第一數位視頻信號（第一視頻資料或視 頻-1資料）·信號處理器704將成像裝置702之输出信號轉 換成為一第二數位視頻信號（第二視頻資料或視頻-2資 料）· 參照第13圈，信號處理器7.03在回應於水平同步信號 之第一脈衝P1下输出一 1線路對應的視頻-1資料件D11 至收發機70 5·信號處理器704在回應於水平同步信號之第 一脈衝P1下輸出一 1線路對應的視頻-2資料件D21至收發 機705 *收發機70 5產生裝填了該親頻-1資料件D11與該 親頻-2資料件D21之第一封包PKT1 ·收發機705輸出該第 一封包PKT1至該網路之序列匯流排•信號處理器7〇3在回 應於該水平同步信號之一第二脈衝P2下輸出一下輸出一1 線路對應的視頻-1資料件D1 2至收發機705 ·信號處理器 704在回應於該水平同步信號之第一脈衝P2下輸出一 1線 路對應的視頻-2資料件D22至收發機705 >收發機705產 24- 本紙張尺度適用中困踽家榡率（〇阳>人4规格（2丨0><297公釐} 面 之 注 項 尽 頁 裝I installed a line D 432869. A7 B7 V. Description of the invention Ul) Printed by the Industrial and Commercial Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A communication synchronization signal is generated under the start of the packet. The communication synchronization signal is synchronized with the received cycle start packet. The bus I / F circuit 1005 outputs the communication synchronization signal to the time signal generator 706. The time signal generator 706 generates a horizontal synchronization signal in response to the communication synchronization signal. As shown in the 13th circle, the horizontal synchronization signal has a series of pulses (horizontal synchronization pulses) and respective pulses in the communication synchronization signal. Synchronization. The time signal generator 70 6 outputs the horizontal synchronizing signal to the driving circuit 70 7. The driving circuit 70 7 operates the imaging devices 701 and 702 in response to the horizontal synchronizing signal. As previously indicated, the signal processor 703 sends the imaging device The output signal of 701 is converted into a first digital video signal (first video data or video-1 data). The signal processor 704 converts the output signal of the imaging device 702 into a second digital video signal (second video data or Video-2 data) · With reference to lap 13, the signal processor 7.03 outputs a 1-line corresponding video-1 data piece D11 to the transceiver 70 in response to the first pulse P1 of the horizontal synchronization signal. 5 The signal processor 704 is at In response to the first pulse P1 of the horizontal synchronization signal, a 1-line corresponding video-2 data piece D21 is output to the transceiver 705 * transceiver 70 5 generates and fills the pro-frequency-1 data piece D11 and the pro-frequency-2 data The first packet PKT1 of piece D21 · The transceiver 705 outputs the serial packet of the first packet PKT1 to the network. The signal processor 703 outputs the second pulse P2 in response to one of the horizontal synchronization signals. The video-1 data piece D1 corresponding to the 1 line is output to the transceiver 705. The signal processor 704 outputs a video-2 data piece D22 corresponding to the 1 line to the transceiver in response to the first pulse P2 of the horizontal synchronization signal. 705 > Transceiver 705 24- This paper size is suitable for the difficult household furniture rate (〇 阳 > People 4 specifications (2 丨 0 > &297; 297mm))

1T 432869 Α7 Β7 經濟部智慧財產局貝工消貪合作社印製 五、發明説明（22 ) 生裝填了該視頻-1資料件D12與該視頻-2資料件D22之第 二封包PKT2·收發機705輸出該第二封包PKT2至該網路之 序列匯流排。信號處理器703在回應於該水平同步信號之 第三脈衝P3下輸出一 1線路對應的視頻-1資料件M3至收 發機705*信號處理器704在囫應於水平同步信號之第三脈 衝P3下輸出一 1線路對應的視頻-2資料件D23至收發機 705。收發機70 5產生裝填了該視頻-1資料件D1 3與該視頻 -2資料件D23之第三封包PKT3。收發機70 5输出該第三封 包PKT3至該辋路之序列匯流排。道些過程在稍後的階段被 週期性地執行。 其注意到由一共同影像源為來源之二1線路視頻資料 件可被指派至一封包•在此情形下，一水平同步信號之二 脈衝在回應於一週期開始封包下被產生· 週期開始封包與該水平產生器可為’'η: πΓ之時間關 係，此處"η"與"m"分別代表預定的整數· 成像裝置701與702可由三個以上之成像裝置取代* 第10圈之系統的設計可被加到第9圖之系統· 第14豳顯示依據本發明之第七實施例的影像捕捉及傅 输系統•第14画之系統包括成像裝置（影像感應器）1101 與1102,信號處理器1103與1104, 一收發機（發射器/接 收器）1105, 一時間信號產生器1106,及一蹰勖電路U07· 成像裝置1101隨後循序地有信號處理器11 G3與收發 機1105。成像裝置11G2隨後循序地有信號處理器1103與 收發機1105»時間信號產生器1106被連接於信號處理器 — 25- 本紙張尺度逋用中國國家揉i ( CNsYa4规格（2Y〇x297公釐) "" 432869 A7 B7 經濟部智慧財產局S工消費合作社印製 五、發明説明（23) 1103與1104,收發機1105與驅動電路1107*驟動電路1107 被連接於成像裝置1101與1102·收發機1105被連接於例 如包括有IEEE 13 94序列匯流排之網路》 成像裝置1101，成像裝置1102,信號處理器1103,信 號處理器1104,時間信號產生器1106與驊動電路1107分 別類似於第1圓之成像裝置101，成像裝置102,信號處理 器103,信號處理器104,時間信號產生器106與騙動電路 107。 信號處理器1103輸出第一視頻資料至收發機11 05·信 號處理器1104輸出第二視頻資料至收發機1105· 收發機1105包括一封包編碼器，其在回應於時間信號 產生器1106之输出信號下將該第一視頻資料與該第二視頻 資料轉換或編碼成為封包流•收發機U輻出該封包流至 該辋路· 收發機1105能由該網路接收非同步封包•收發機1105 將所接收之非同步封包轉換或解碼成為其所負載之資訊 件· 如第15圖顯示者，收發機1105包括記憶體1201與 1202,一微電腦1203,一處理電路1 204,與一匯流排丨/F(介 面）電路1205·記憶體1201被連接至信號處理器1103(見 第14匾）與處理霄路1204·記憶髄1202被連接於信號處理 器Π04(見第14圖）與處理電路1204 ·處理電路1204被連 接於時間信號產生器11〇6(見第14.圔）與匯流排I/F電路 1 205 *匯流排I/F電路1205被連接於該網路。微電腦1203 -26- 本紙張尺度適用中國國家梂半（CNS ) A4规格（210X297公釐） 請 先 閲 讀 背 ί) 之 注 項 再 432869 A7 B7 五、發明説明（24 ) 經濟部智慧財產局負工消費合作社印製 被連接於處理電路1204與匯流排I/F電路1 205 · 由信號處理器1103被輸出之第一視頻資料被餹存於記 憶體1201內。由信號處理器1104被输出之第二視頻資料 被儲存於記憶體1202內*微電腦1203依照儲存在其內之 程式控制處理電路12IH與匯流排I/F電路1205·該程式被 設計來實施下列的處理*處理電路1204在時間信號產生器 1106之輸出信號所決定的特定時間由記憶體1201與1202 讀出該第一視頻資料與該第二視頻資料•處理電路12 04包 括一封包編碼器，其在回應於時間信號產生器1106之輸出 信號下將該第一親頻資料與該第二視頻資料轉換或編碼成 為一封包流•例如，每一成像裝置被裝填該第一視頻資料 的一部分與該第二視頻資料的一部分的至少之一•較佳的 是，每一封包含有代表其中之視頻資料的格式添加後的資 訊件、代表造成其中之視頻資料的成像裝置之辨識號碼的 添加後的資訊件、以及代表由其中之視頻資料所代表之影 像部分的位置之添加後的資訊件*處理電路1204輸出該封 包流至匯流排I/F電路1 205·匯流排I/F霉路1205輸出該 封包流至該網路· 微電腦1203可經由該網路與匯流排I/F電路1 205在 外部裝置來回地傅輸及接收非同歩封包· 由記憶體1201被讀出之該第一視頻資料的一部分所代 表之一影像部分的位置可被微電腦1203改變*此外’由記 憶體1202被讀出之該第二視頻資料的一部分所代表之一影 像部分的位置可被微電腦1203改變》較佳的是’用於決定 -27- 本紙張尺度逋用中困國家揉率（CNS )八4規*格（210X W7公釐） 請 先 閱 讀. 背， 面 之 注*1T 432869 Α7 Β7 Printed by Shellfish Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (22) The second packet PKT2 · transceiver 705 of the video-1 material D12 and the video-2 material D22 Output the second packet PKT2 to the serial bus of the network. The signal processor 703 outputs a 1-line corresponding video-1 data piece M3 to the transceiver 705 in response to the third pulse P3 of the horizontal synchronization signal. The signal processor 704 responds to the third pulse P3 of the horizontal synchronization signal. The video-2 data piece D23 corresponding to 1 line is output to the transceiver 705. The transceiver 70 5 generates a third packet PKT3 filled with the video-1 data piece D1 3 and the video-2 data piece D23. The transceiver 70 5 outputs a serial bus from the third packet PKT3 to the rim. These processes are performed periodically at a later stage. It noticed that the 2 line 1 video data files from a common image source can be assigned to a packet. In this case, two pulses of a horizontal synchronization signal are generated in response to a cycle start packet. Cycle start packet This level generator can have a time relationship of η: πΓ, where "" η " and " m " represent predetermined integers respectively. Imaging devices 701 and 702 can be replaced by three or more imaging devices. * Circle 10 The design of the system can be added to the system of Fig.9. Fig. 14 shows the image capture and transmission system according to the seventh embodiment of the present invention. The system of Fig. 14 includes imaging devices (image sensors) 1101 and 1102. The signal processors 1103 and 1104, a transceiver (transmitter / receiver) 1105, a time signal generator 1106, and a circuit U07. The imaging device 1101 sequentially has a signal processor 11 G3 and a transceiver 1105. . The imaging device 11G2 has a signal processor 1103 and a transceiver 1105 in sequence. The time signal generator 1106 is connected to the signal processor. — 25- This paper size uses the Chinese national standard i (CNsYa4 specification (2Y〇x297 mm) " " 432869 A7 B7 Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Industrial and Commercial Cooperatives. V. Description of Invention (23) 1103 and 1104, Transceiver 1105 and Drive Circuit 1107 * Snap Circuit 1107 is connected to Imaging Devices 1101 and 1102 The machine 1105 is connected to, for example, a network including an IEEE 13 94 serial bus. The imaging device 1101, the imaging device 1102, the signal processor 1103, the signal processor 1104, the time signal generator 1106, and the automatic circuit 1107 are similar to 1 round imaging device 101, imaging device 102, signal processor 103, signal processor 104, time signal generator 106 and fraud circuit 107. The signal processor 1103 outputs the first video data to the transceiver 11 05 · signal processor 1104 outputs the second video data to the transceiver 1105. The transceiver 1105 includes a packet encoder which responds to the first video data in response to the output signal of the time signal generator 1106. The second video data is converted or encoded into a packet stream. The transceiver U radiates the packet stream to the network. The transceiver 1105 can receive asynchronous packets from the network. The transceiver 1105 converts the received asynchronous packets or Decoding becomes its loaded information piece. As shown in Figure 15, the transceiver 1105 includes memory 1201 and 1202, a microcomputer 1203, a processing circuit 1 204, and a bus 丨 / F (interface) circuit 1205. Memory. The body 1201 is connected to the signal processor 1103 (see plaque 14) and the processing channel 1204. The memory 1202 is connected to the signal processor Π04 (see FIG. 14) and the processing circuit 1204. The processing circuit 1204 is connected to the time signal. The generator 1106 (see section 14. 圔) and the bus I / F circuit 1 205 * The bus I / F circuit 1205 is connected to this network. Microcomputer 1203 -26- This paper standard applies to China's national half ( CNS) A4 specification (210X297 mm) Please read the note of the back) and then 432869 A7 B7 V. Description of the invention (24) Printed by the Consumer Property Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs is connected to the processing circuit 1204 and the busbar I / F circuit 1 205 · Signal processing The first video data output from the device 1103 is stored in the memory 1201. The second video data output by the signal processor 1104 is stored in the memory 1202. The microcomputer 1203 controls the processing circuit 12IH and the bus I / F circuit 1205 according to the program stored therein. The program is designed to implement the following Processing * The processing circuit 1204 reads out the first video data and the second video data from the memories 1201 and 1202 at a specific time determined by the output signal of the time signal generator 1106. The processing circuit 12 04 includes a packet encoder, which In response to the output signal of the time signal generator 1106, convert or encode the first frequency data and the second video data into a packet stream. For example, each imaging device is loaded with a portion of the first video data and the At least one of a part of the second video data. Preferably, each piece contains information including the format of the video data added thereto, and the information of the identification number of the imaging device that caused the video data added. And the added information piece representing the position of the image portion represented by the video data therein * processing circuit 1204 outputs the The packet flows to the bus I / F circuit 1 205. The bus I / F circuit 1205 outputs the packet flow to the network. The microcomputer 1203 can communicate with the bus I / F circuit 1 205 to and from the external device via the network. Fu lost and receiving non-synchronous packets · The position of an image portion represented by a portion of the first video data read out from the memory 1201 can be changed by the microcomputer 1203 * In addition, the first readout from the memory 1202 The position of the image part represented by the second part of the video data can be changed by the microcomputer 1203. It is better to 'use to determine -27- this paper size is used in the difficult countries (CNS) eighty-four rules * grid (210X W7 mm) Please read first. Back, note above *

I 頁 裝 1 丁 線 4328 6 9 A7 B7 經濟部智慧財產局貝工消費合作杜印製 五、發明説明（25) 被由記憶體1201讀出之該第一視頻資料的一部分所代表之 一影像部分的位置之一控制信號與用於決定被由記憶體 1 20 2讀出之該第二視頻資料的一部分代表之一影像部分的 位置之一控制信號，經由該網路與匯流排I/F電路1 205由 該外部裝置被傅輸至該微電腦。在此情形下，該等控制信 號被一非同步封包所負載· 依據一第一例，記憶體1201與1 202分別包括FIFO(先 進先出）記憶體。在該第一親頻資料之段被處理電路1204 所讀出之該FIFO記憶體1201內的位置（館存位霣）可依照 由微電腦1203被輪出至處理電路1204之一控制信號被移 位•或者，處理電路1204存取該FIFO記憶髖1201的時間 可依照由微電腦12G3被输出至處理電路1204之控制信號 被改變•此外，在該第一視頻資料之段被處理鼋路1204所 讀出之該FIFO記憶體1202內的位置（儲存位置）可依照由 微電腦1203被输出至處理電路1204之一控制信號被移 位。或者，處理電路1204存取該FIFO記憶體1202的時間 可依照由微電腦1203被输出至處理電路1204之控制信號 被改變。 依據一第二例，記憶體1201與1202分別包括RAM(隨 機存取記憶體）·在該第一視頻資料之段被處理電路1204 所讀出之該RAM 1201內的位置（儲存位置）可依照由微電腦 1 203被粬出至處理電路1 204之一控制信號被移位•此外， 在該第一視頻資$之段被處理電路1 204所讀出之該RAM 1 202內的位置（儲存位置）可依照由微電腦1 203被輸出至 請 先 閲 背， Si 之 注， 項 再 A 頁 裝 訂 線 2S- 本紙張尺度逋用中國國家梂率（CNS > 格（210X297公嫠） 432869 A7 B7 經濟部暫慧財產局S工消費合作社印製 五、發明説明（26 ) 處理電路1204之一控制信號被移位· 其須注意到成像裝置1101與1102可由三個以上的成 像裝置取代*第14圃之系統的設計可被加到第9圖之系 統- 第16圖顯示本發明之第八實施例的影像捕捉及傅輸系 統。第16圖之系統除了以一收發機105A取代收發機105 (見 第1圖）外與第1圖之系統類似《 就如第17圓顯示者_收發機105A包括記憶體1301與 1302，一微電腦1 303 ,一處理霉路1 304及一匯流排I/FC介 面）電路1 305 ·記憶體13G1被連接於一信號處理器103(見 第16圖）與處理電路1 304·記憶體1302被連接於一信號處 理器1〇4(見第16圖）與處理電路1 304。處理電路1304被 連接於時間信號產生器1〇6(見第16圈）與匯流排I/Fm路 1 305 «匯流排I/F電路1305被連接於一網路·微電腦1303 被連接於處理電路1304與匯流排I/F電路1305 · 由信號處理器103被輪出之第一親頻資料被儲存於記 憶體1301內•較佳的是，記憶體1301具有對應於至少一 框之記錄容量•由信號處理器104被輪出之第二視頻資料 被儲存於記憶體1302內•較佳的是·記憶體1302具有對 應於至少一框之記錄容童·微電腦1303依照儲存於其內之 程式控制處理電路1304與匯流排I/F電路1 305·該程式被 設計來實施下列處理•處理電路1304在時間信猇產生器 106之輸出信號所決定的特定時間由記憶體1301與1302 讀出該第一親頻資料與該第二視頻資料*處理電路1 3〇4包 29- 本紙張尺度逋用中因國家橾準< CNS ) 44规格（210X297公釐） I； 面 之 注· 項 再 頁 裝 訂 線 432869 A7 B7 五、發明説明（27 ) 經濟部智慧財產局貝工消費合作社印製 括一封包編碼器，其在回應於時間信號產生器106之输出 信號下將該第一視頻資料與該第二視頻資料轉換或編碼成 為一封包流•例如|每一封包被裝填該第一視頻資料之一 部分與該第二視頻資料之一部分的至少之一•較佳的是， 每一封包含有代表其中之視頻資料的格式添加後的資訊 件、代表造成其中之視頻資料的成像裝置之辨識號碼的添 加後的資訊件、以及代表由其中之視頻資料所代表之影像 部分的位置之添加後的資訊件•處理電路1304輸出該封包 流至匯流排I/F電路1305·匯流排I/F電路1305輸出該封 包流至該網路· 微電腦1303可經由該網路與匯流排I/F電路1305在 —外部裝置來回地傳输及接收非同步封包* 連接於該網路之接收側決定由第16圖之系統的封包流 內之每一封包是否成功地被接收*若其被決定封包未成功 地被接收，該接收側經由該網路送回一再傳輸要求之一非 同步封包至第16圖之系統。微電腦1303經由匯流排I/F 電路1305接收該再傅輸要求封包《微電腦1 303由所接收 之封包恢復該再傅输要求。微電腦1303在回應於該再傳輸 要求下控制該處理電路13Q4以再次執行該最後封包之傳 輸•此以逐一封包為基礎之檢査與再傳輸可用以逐—框為 基礎之檢査與再傳輸取代。 或者，該第一視頻資料之每一 1框對應部分與該第二 視頻資料之每一1框對應部分可經由處理霉路130 4與匯流 排I/F電路1305由記憶體1301與130 2被再傳输至該網 請 先 閱 讀·背， 面 之 注· 意i 事 I A 今、 頁 裝I Page 1 D Ding 4328 6 9 A7 B7 Printed by Shelley Consumers Cooperation, Intellectual Property Bureau, Ministry of Economic Affairs 5. Description of the Invention (25) An image represented by a part of the first video data read from the memory 1201 A control signal for the position of a part and a control signal for determining the position of a part of an image representing a part of the second video data read out from the memory 1 202, via the network and the bus I / F The circuit 1 205 is input to the microcomputer by the external device. In this case, the control signals are carried by an asynchronous packet. According to a first example, the memories 1201 and 1 202 include FIFO (first in, first out) memory, respectively. The position (store location) in the FIFO memory 1201 read by the processing circuit 1204 in the section of the first pro-frequency data may be shifted according to a control signal that is rotated out by the microcomputer 1203 to the processing circuit 1204 • Or, the time when the processing circuit 1204 accesses the FIFO memory hip 1201 can be changed according to the control signal output from the microcomputer 12G3 to the processing circuit 1204. In addition, the first video data section is read by the processing circuit 1204. The position (storage position) in the FIFO memory 1202 can be shifted according to a control signal output from the microcomputer 1203 to the processing circuit 1204. Alternatively, the time when the processing circuit 1204 accesses the FIFO memory 1202 may be changed according to a control signal output from the microcomputer 1203 to the processing circuit 1204. According to a second example, the memories 1201 and 1202 each include a RAM (random access memory). The location (storage location) in the RAM 1201 read by the processing circuit 1204 during the first video data segment can be determined according to A control signal from the microcomputer 1 203 to one of the processing circuits 1 204 is shifted. In addition, the position (storage location) in the RAM 1 202 read out by the processing circuit 1 204 during the first video data segment. ) It can be output to the microcomputer 1 203 to the Please read the back, the note of Si, and then the A-page gutter 2S- This paper size adopts the Chinese national standard (CNS > grid (210X297 male) 432869 A7 B7 Economy Printed by the Ministry of Temporary Property Bureau, S Industrial Consumer Cooperative, V. Invention Description (26) One of the control signals of the processing circuit 1204 is shifted. It should be noted that the imaging devices 1101 and 1102 can be replaced by three or more imaging devices. The design of the system can be added to the system of Fig. 9-Fig. 16 shows the image capture and transmission system of the eighth embodiment of the present invention. The system of Fig. 16 except that the transceiver 105 is replaced by a transceiver 105A (see Figure 1) Outside and Figure 1 The system is similar to "As shown in the 17th circle_transceiver 105A includes memory 1301 and 1302, a microcomputer 1 303, a processing mold 1 304 and a bus I / FC interface) circuit 1 305 · memory 13G1 is connected A signal processor 103 (see FIG. 16) and a processing circuit 1 304. The memory 1302 is connected to a signal processor 104 (see FIG. 16) and a processing circuit 1 304. The processing circuit 1304 is connected to the time signal generator 106 (see circle 16) and the bus I / Fm circuit 1 305. The «bus I / F circuit 1305 is connected to a network · microcomputer 1303 is connected to the processing circuit 1304 and bus I / F circuit 1305 · The first frequency data that is rotated out by the signal processor 103 is stored in the memory 1301. Preferably, the memory 1301 has a recording capacity corresponding to at least one frame. The second video data rotated by the signal processor 104 is stored in the memory 1302. Preferably, the memory 1302 has a record corresponding to at least one frame. The Rongtong microcomputer 1303 is controlled according to the program stored therein. Processing circuit 1304 and bus I / F circuit 1 305. This program is designed to perform the following processing. Processing circuit 1304 reads out the first time from memory 1301 and 1302 at a specific time determined by the output signal of time signal generator 106. One pro-frequency data and the second video data * Processing circuit 1 304 package 29- National standard in this paper standard use < CNS) 44 specifications (210X297 mm) I; note above Binding line 432869 A7 B7 V. Invention (27) The shelling consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs prints a packet encoder that converts or encodes the first video data and the second video data into one in response to the output signal of the time signal generator 106 Packet stream • For example | Each packet is filled with at least one of a portion of the first video material and a portion of the second video material • Preferably, each of the packets contains formatted information representing the video data added thereto Information file, the added information piece representing the identification number of the imaging device that caused the video data therein, and the added information piece representing the position of the image portion represented by the video data therein. The processing circuit 1304 outputs the packet stream to The bus I / F circuit 1305 and the bus I / F circuit 1305 output the packet stream to the network. The microcomputer 1303 can transmit and receive non-reciprocal signals to and from the external device via the network and the bus I / F circuit 1305. Synchronous packet * The receiving side connected to the network decides whether each packet in the packet stream of the system in Figure 16 is successfully received * If it is determined that the packet has not been completed It is successfully received, and the receiving side sends back an asynchronous packet of repeated transmission requests to the system in FIG. 16 via the network. The microcomputer 1303 receives the retransmission request packet via the bus I / F circuit 1305, and the microcomputer 1303 restores the retransmission request from the received packet. In response to the retransmission request, the microcomputer 1303 controls the processing circuit 13Q4 to perform the transmission of the last packet again. This inspection and retransmission on a packet-by-packet basis can be replaced by inspection and retransmission on a frame-by-frame basis. Alternatively, the corresponding portion of each 1 frame of the first video data and the corresponding portion of each 1 frame of the second video data may be processed by the memories 1301 and 130 2 through the processing mold circuit 130 4 and the bus I / F circuit 1305. Before you transfer to this website, please read it first, memorize it, and note it. IA i

1T 線 本紙張尺度適用中國國家揉率（CNS > A4规格（210X297公釐） 432869 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明说明（28) 路*在此情形下，就算一封包流之一部分未被成功地接收， 其不須有一接收側送回再傳输要求· 其須注意到，成像裝置101與102可被三個以上之成 像裝置取代•第16圖之系統的設計可被加到第9圖之系統 或第14圖之系統》 第18圖顯示本發明之第九實施例的影像捕捉及傅輸系 統》第18圖之系統除了以一收發機10 5B取代收發機105(見 第1圖）外與第1圖之系統類似。 就如第18圖顯示者，收發機10 5B包括記憶體1401與 1402，一微電腦1403，一處理亀路1404，一匯流排I/F(介 面）電路1405,及視頻壓縮器1407與1408·視頻壓縮器1407 被連接於信號處理器1〇3(見第18圖）與記憶體1401間•記 憶體1401被連接於處理電路1404 ·視頻壓縮器1408被連 接於一信號處理器1〇4(見第18圖）與記憶體1402間•記憶 體140 2被連接於處理電路1404·處理電路1404被連接於 一時間信號產生器1〇6(見第18圖）與匯流排I/F電路 1405·匯流排I/F電路1405被連接於一網路·微電腦1403 被連接於處理電路UD4與匯流排I/F霱路1 405。 視頻壓縮器1407由信號處理器103接收第一視頻資 料，並將該第一視頻資料壓縮成為第一壓縮結果之視頻資 料。視頻壓縮器14 07輸出該第一壓縮結果之視頻資料•該 第一壓縮結果之視頻資料被儲存在記憶體1401內。視頻膣 縮器140 8由信號處理器104接收第二視頻資料，並將該第 二視頻資料壓縮成為第二壓縮結果之親頻資料。親頻壓縮 -31- 本紙張尺度逍用中國國家插準（（：?《)八4«1格（2丨0父297公釐} 432869 經濟部智慧財產局"®工消#合作社印製 A7 B7_五、發明説明（29) 器14(J8輸出該第二壓縮結果後之視頻資料•該第二壓縮結 果之視頻資料被儲存在記憶體14D2內•微電腦140 3依照 儲存於其內之程式控制處理電路1404與匯流排I/F電路 1405。該程式被設計來實施下列過程•處理電路1404在時 間信號產生器106之输出信號所決定的特定時間由記憶慷 1401與1402讀出該第一壓縮結果之視頻資料與該第二壓 縮結果之視頻資料•處理電路1404包括一封包編碼器*其 在回應於時間信號產生器106之输出信號下將該第一歷縮 結果之視頻資料與該第二壓縮結果之視頻資料轉換或編碼 成為封包流。例如，每一封包被裝填該第一躔縮結果之視 頻資料的一部分與該第二壓縮結果之視頻資料的一部分的 至少之一·較佳的是，每一封包含有代表其中之視頻資料 的格式之添加後的資訊件、代表造成其中之視頻資料的成 像裝置之辨識號碼的添加後之資訊件、以及代表由其中之 親頻資料所代表之影像部分的位置之添加後的資訊件。處 理電路1404輸出該封包流至匯流排I/F電路1 405·匯流排 I/F電路U05輸出該封包流至該網路· 微電腦1403可經由該網路與匯流排I/F電路14G5在 一外部裝置來回傳输與接收非同步封包· 其須注意到，成像裝置101與102可被三個以上之成 像裝置取代》第18圖之系統的設計可被加到第9圖之系 統，第14圖之系統*或第16圖之系統。 第20圖顯示本發明之第十實施例的影像捕捉及傅输系 統•第20圖之系統除了以一收發機105C取代收發機10 5(見 -32- 本纸張足度遒用中理《家輮準（匸阳）八4规格（210><297公釐) •'4 (請先H讀背面之注$項再A 4頁) r 4328 6 9 at Β7 經濟部智慧財產局貝工消費合作社印製 五、發明説明（3〇 ) 第1圖）外與第1圖之系統類似· 就如第21圖顯示者·收發機10 5C包括記憶體1501與 1 502，一微電腦1 503，一處理電路1504，一匯流排I/F(介 面）電路1 505,親頻壓縮器1507與1508 , 一加入器1509， 及一減去器1510·加入器1 509被連接於信號處理器103 與104(見第20圔）·加入器1 509被連接於視頻壓縮器 1 507 *視頻壓縮器15Q7被連接於記憶體1501*記憶體1501 被連接於信號處理器1504·減去器1510被信號處理器連接 於信號處理器103與104(見第20圖）·減去器1510被連接 於視頻壓縮器15Q8·視頻壓縮器1508被連接於記憶體 1 502。記憶體1 502被連接於處理電路1 504·處理電路1504 被連接於時間信號產生器1〇6(見第20圈）與匯流排I/F電 路1505 *匯流排I/F電路1505被連接於一網路·.微電腦 1 503被連接於處理電路15G4與匯流排I/F電路1 505 * 加入器1 509由信號處理器103接收第一視頻資料*加 入器1509由信號處理器104接收第二視頻資料*裝置1509 將第一視頻資料與第二視頻資料相加成為相加結果之視頻 資料*加入器1 509輸出該相加結果之視頻資料至視頻壓縮 器1507。裝置1507將該相加結果之視頻資料應縮成為第一 壓縮結果之視頻資料。視頻壓縮器Ϊ 507輸出該第一壓縮結 果之視頻資料。該第一壓縮結果之視頻資料被儲存在記憶 體1501內。減去器1510由信號處理器103接收該第一視 頻資料•減去器1510由信號處理器1G4接收骸第二視頻資 料•裝置1510在該第一視頻資料與第二視頻資料間執行減 锖 先 閱 面 之 注 項 再 頁 裝 訂 線 • 33- 4328S9 A7 B7 絰濟部智慧財產局貝工消費合作社印製 五、發明説明（31 ) 法，因而產生相減結果之視頻資料·減去器1510输出該相 減結果之視頻資料至視頻壓縮器1508·裝置15G8將該相減 結果之視頻資料壓縮成為第二壓縮結果之視頻資料•親頻 懕縮器1508賴ί出該第二壓縮結果之視頻資料•該第二壓縮 結果之視頻資料被儲存於記憶體1502內·微電腦1503依 照儲存於其內之程式控制處理電路1504與匯流排I/F電路 1505·該程式被設計來實施下列過程*處理電路1504在時 間信號產生器106之输出信號所決定的特定時間由記憶體 1501與1502讀出該第一壓縮結果之視頻資料與該第二壓 縮結果之視頻資料。處理電路1 504包括一封包編碼器*其 在回應於時間信號産生器106之輸出信號下將該第一應縮 結果之視頻資料與該第二懕綰結果之視頻資料轉換或編碼 成為封包流。例如，每一封包被裝填該第一壓縮結果之視 頻資料的一部分與該第二壓縮結果之視頻資料的一部分的 至少之一。較佳的是，每一封包含有代表其中之視頻資料 的格式之添加後的資訊件、代表造成其中之視頻資料的成 像裝置之辨識號碼的添加後之資訊件、以及代表由其中之 視頻資料所代表之影像部分的位置之添加後的資訊件*處 理電路1 504輸出該封包流至匯流排I/F電路1 505·匯流排 I/F電路1 50 5輸出該封包流至該網路。 微電腦15 03可經由該網路與匯流排I/F電路1 505在 —外部裝置來回傳輸與接收非同步封包· 其須注意到，影像位置修正電路可被提供於加入器 1 509與減去器1510前之級，以去除被輪入至加入器1509 -34- € ί (請先聞讀背面之注^•項再ίίΓ-ψ-頁) 本紙張尺度逋廊中國8家揉準（CNS ) A4規格（210X297公釐) 432869 a? B7 五、發明説明（32) 與1510之第一視頻資料與第二視頻資料間的位置誤差· 其須注意到，成像裝置101與102可被三個以上之成 像裝置取代*第20圖之系統的設計可被加到第9圖之系 統，第14圖之系統或第16圖之系統· 第22圖顯示本發明之第十一實施例的影像捕捉及傅输 系統•第22圖之系統除了以一收發機105D取代收發機 105(見第1圖）外與第1圖之系統類似· 就如第23圃顯示者，收發機105D包括記憶髓1601與 1 602,一微電腦1603,一處理電路1604,及一匯流排I/F(介 面）電路160 5·記憶體16D1被連接於信號處理器103(見第 22圖）與處理電路16 04。記憶體1602被連接於一信號處理 器104(見第22 _)與處理電路1604 ·處理電路1604被連 接於一時間信號產生器1〇6(見第22画）與匯流排I/F電路 1605。匯流排I/F電路1 605被連接於一網路·微電腦1603 被連接於處理電路1604與匯流排I/F電路1605 * 由信號處理器103被輸出之第一視頻資料被館存於記 憶體1601內·由信號處理器104被輸出之第二親頻資料被 儲存於記憶體1602內·微電腦1603依照餾存於其內之程 式控制處理電路1604與匯流排I/F電路1605·該程式被設 計來實施下列過程•處理電路1604在時間信號產生器106 之输出信號所決定的特定時間由記憶體1601與1 602讅出 該第一視頻資料與該第二視頻資料•處理電路16 04包括一 封包編碼器，其在回應於時間信號產生器之输出信號 下將該第一視頻資料與該第二視頻資料轉換或編碼成為封 -35- 本紙張/^度逋用中國國家橾準（〇泌）六4坑格（210><297公釐)1T line paper size applies to China's national kneading rate (CNS > A4 size (210X297 mm) 432869 A7 B7 Printed by Employee Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of invention (28) Road * In this case, even one Part of the packet stream is not successfully received, it does not require a receiving side to send back a retransmission request. · It must be noted that the imaging devices 101 and 102 can be replaced by three or more imaging devices. • The design of the system in Figure 16 Can be added to the system of Figure 9 or the system of Figure 14 "Figure 18 shows the ninth embodiment of the image capture and Fusu system of the present invention" The system of Figure 18 in addition to replacing the transceiver with a transceiver 10 5B 105 (see Figure 1) is similar to the system shown in Figure 1. As shown in Figure 18, the transceiver 105B includes memories 1401 and 1402, a microcomputer 1403, a processing circuit 1404, and a bus I / F (Interface) circuit 1405, and video compressors 1407 and 1408. The video compressor 1407 is connected between the signal processor 103 (see Figure 18) and the memory 1401. The memory 1401 is connected to the processing circuit 1404. Video compressor 1408 is connected to a signal Between the processor 104 (see FIG. 18) and the memory 1402 • the memory 140 2 is connected to the processing circuit 1404 • the processing circuit 1404 is connected to a time signal generator 106 (see FIG. 18) and the bus The bus I / F circuit 1405 and the bus I / F circuit 1405 are connected to a network. The microcomputer 1403 is connected to the processing circuit UD4 and the bus I / F circuit 1 405. The video compressor 1407 is received by the signal processor 103 The first video data and compresses the first video data into the video data of the first compression result. The video compressor 14 07 outputs the video data of the first compression result • The video data of the first compression result is stored in the memory Within 1401. The video shrinker 140 8 receives the second video data from the signal processor 104 and compresses the second video data into the pro-frequency data of the second compression result. Pro-frequency compression -31- National Interpolation ((:?) 8 4 «1 grid (2 丨 0 father 297 mm) 432869 Intellectual Property Bureau of the Ministry of Economic Affairs " ® 工 消 # Cooperative cooperative printing A7 B7_V. Invention description (29) Device 14 (J8 outputs the video data after the second compression result The resulting video data is stored in the memory 14D2. The microcomputer 140 3 controls the processing circuit 1404 and the bus I / F circuit 1405 in accordance with the program stored therein. The program is designed to implement the following processes. The processing circuit 1404 performs the time signal The specific time determined by the output signal of the generator 106 is read by the memory 1401 and 1402 from the video data of the first compression result and the video data of the second compression result. The processing circuit 1404 includes a packet encoder * which responds in Under the output signal of the time signal generator 106, the video data of the first compression result and the video data of the second compression result are converted or encoded into a packet stream. For example, each packet is filled with at least one of a portion of the video data of the first compression result and a portion of the video data of the second compression result. Preferably, each packet contains a format representing the video data therein The added information piece represents the added information piece representing the identification number of the imaging device which caused the video data therein, and the added information piece represents the position of the image portion represented by the parental data therein. The processing circuit 1404 outputs the packet stream to the bus I / F circuit 1 405. The bus I / F circuit U05 outputs the packet stream to the network. The microcomputer 1403 can communicate with the bus I / F circuit 14G5 through the network. External devices transmit and receive asynchronous packets back and forth. It must be noted that the imaging devices 101 and 102 can be replaced by more than three imaging devices. The design of the system in FIG. 18 can be added to the system in FIG. 14 system * or 16 system. Figure 20 shows the image capture and transmission system of the tenth embodiment of the present invention. In addition to replacing the transceiver 105 with a transceiver 105C, the system of Figure 20 (see -32- Furniture standard (Liyang) 8 4 specifications (210 > < 297 mm) • '4 (please read the note on the back and then page A 4) r 4328 6 9 at Β7 Intellectual Property Bureau, Ministry of Economic Affairs Printed by the Consumer Cooperative 5. The invention description (30) (Figure 1) is similar to the system shown in Figure 1 · As shown in Figure 21 · The transceiver 10 5C includes memory 1501 and 1 502, a microcomputer 1 503, A processing circuit 1504, a bus I / F (interface) circuit 1 505, a frequency-friendly compressor 1507 and 1508, a adder 1509, and a subtractor 1510 · adder 1 509 are connected to the signal processor 103 and 104 (see section 20). Joiner 1 509 is connected to video compressor 1 507 * Video compressor 15Q7 is connected to memory 1501 * Memory 1501 is connected to signal processor 1504. Subtractor 1510 is processed by signal The compressor is connected to the signal processors 103 and 104 (see Figure 20). The subtractor 1510 is connected to the video compressor 15Q8. The video compressor 1508 is connected. In the memory 1502. The memory 1 502 is connected to the processing circuit 1 504. The processing circuit 1504 is connected to the time signal generator 106 (see circle 20) and the bus I / F circuit 1505. The bus I / F circuit 1505 is connected to A network .. Microcomputer 1 503 is connected to processing circuit 15G4 and bus I / F circuit 1 505 * Joiner 1 509 receives first video data from signal processor 103 * Joiner 1509 receives second signal from signal processor 104 The video data * device 1509 adds the first video data and the second video data into the video data of the addition result * adder 1509 outputs the video data of the addition result to the video compressor 1507. The device 1507 should reduce the video data of the addition result into the video data of the first compression result. The video compressor Ϊ 507 outputs the video data of the first compression result. The video data of the first compression result is stored in the memory 1501. The subtractor 1510 receives the first video data by the signal processor 103. The subtractor 1510 receives the second video data by the signal processor 1G4. The device 1510 performs subtraction between the first video data and the second video data. Read the remarks on the page and then the binding line • 33- 4328S9 A7 B7 Printed by Shelley Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Invention Description (31) method, which produces the video data of the subtraction result · Subtractor 1510 output The video data of the subtraction result is sent to the video compressor 1508. The device 15G8 compresses the video data of the subtraction result into the video data of the second compression result. • The video data of the second compression result is stored in the memory 1502. The microcomputer 1503 controls the processing circuit 1504 and the bus I / F circuit 1505 according to the program stored therein. The program is designed to implement the following processes. * Processing circuit 1504 reads the video data of the first compression result and the second compression result from the memories 1501 and 1502 at a specific time determined by the output signal of the time signal generator 106 Video material. The processing circuit 1 504 includes a packet encoder * which, in response to the output signal of the time signal generator 106, converts or encodes the video data of the first compression result and the video data of the second result into a packet stream. For example, each packet is filled with at least one of a portion of video data of the first compression result and a portion of video data of the second compression result. Preferably, each piece contains an added piece of information representing the format of the video data therein, an added piece of information representing the identification number of the imaging device that caused the video data therein, and a video data representative of The information information after the position of the representative image part is added * The processing circuit 1 504 outputs the packet stream to the bus I / F circuit 1 505 · the bus I / F circuit 1 50 5 outputs the packet stream to the network. Microcomputer 15 03 can transmit and receive asynchronous packets to and from external devices via this network and bus I / F circuit 1 505. It should be noted that the image position correction circuit can be provided in adder 1 509 and subtractor. Prior to 1510, in order to remove the turn into the adder 1509 -34- € ί (please read the note on the back ^ • item and then ίΓ-ψ-pages) This paper scale gallery 8 Chinese standards (CNS) A4 specifications (210X297 mm) 432869 a? B7 V. Position error between the first video data and the second video data of the invention description (32) and 1510 · It should be noted that the imaging devices 101 and 102 can be used by more than three The imaging device replaces the design of the system of Fig. 20, which can be added to the system of Fig. 9, the system of Fig. 14 or the system of Fig. 16. Fig. 22 shows the image capture and Fu Loss System • The system in Figure 22 is similar to the system in Figure 1 except that the transceiver 105 is replaced by a transceiver 105D (see Figure 1). As shown in Figure 23, the transceiver 105D includes a memory 1601 and 1 602, a microcomputer 1603, a processing circuit 1604, and a bus I / F (interface) circuit 160 5 The memory 16D1 is connected to the signal processor 103 (see Fig. 22) and the processing circuit 16 04. The memory 1602 is connected to a signal processor 104 (see page 22_) and the processing circuit 1604. The processing circuit 1604 is connected to a time signal generator 106 (see page 22) and the bus I / F circuit 1605. . The bus I / F circuit 1 605 is connected to a network · microcomputer 1603 is connected to the processing circuit 1604 and the bus I / F circuit 1605 * The first video data output by the signal processor 103 is stored in the memory In 1601, the second frequency data output by the signal processor 104 is stored in the memory 1602. The microcomputer 1603 controls the processing circuit 1604 and the bus I / F circuit 1605 according to the program stored therein. The program is Designed to implement the following processes: The processing circuit 1604 extracts the first video data and the second video data from the memories 1601 and 1 602 at a specific time determined by the output signal of the time signal generator 106. The processing circuit 16 04 includes a A packet encoder that converts or encodes the first video data and the second video data into a packet in response to an output signal of a time signal generator. ) Six 4 pits (210 > < 297 mm)

In ^^1 1^1 SWlll 1^1 A3 • \ <請先聞讀背面之注意事項再h个I) 訂 線· 經濟部智慧財產局員工消费合作社印製 A7 B7 432869 五、發明説明（33 ) 包流•例如，每一封包被裝填該第一壓縮結果之視頻資料 的一部分與該第二壓縮結果之視頻資料的一部分的至少之 一》較佳的是，每一封包含有代表其中之視頻資料的格式 之添加後的資訊件、代表造成其中之視頻資料的成像裝置 之辨識號碼的添加後之資訊件、以及代表由其中之視頻資 料所代表之影像部分的位置之添加後的資訊件*處理電路 1604輸出該封包流至匯流排I/F電路16fl5 *匯流排I/F電 路1 60 5輸出該封包流至該網路· 微電腦16Q3可經由該網路匯流排1/F電路1605在一 外部裝置來回傳輸與接收非同步封包· 處理電路1604包括一區域設定電路或掩蔽電路 1606。區域設定電路1 606決定被每一第一視頻資料與第二 視頻資料所代表之毎一框內的有效區域ER。如第24 ,圖顯示 者|該有效區域ER為一長方形。該有效區域ER在水平界 限位置（水平界限像素位置值）H1與H2間延伸。該有效菡域 ER在垂直界限位置（垂直界限像素位置值）VI與V2間延 伸· 就如第25圃顯示者，區域設定電路1606包括計數器 1801 與 1802，比較器 1 803 與 1804，及一 AND 電路 1805 » 計數器1801與1802被連接於時間信號產生器106·計數器 1801與1802被連接於比較器1803。比較器1803被連接於 微電腦1603與AND電路1805 ·計數器1802被連接於比較 器1804 ·比較器1804被連接於微電腦1603與AND亀路 1 805。AND電路1805被連接於記憶體1601與1602 · -36- 本紙张尺度逍用中國國家揉準yCNsTA4it格（210X297公釐） HI §1· if— ^^1· ^—1» * f * Λ· (請先聞讀背面之注意事項再4育) 訂 線 經濟部智慧財產局8工消费合作社印製 Α32β69 Α7 Β7 經濟部智慧財產局貝工消費合作社印製 五、發明説明（34 ) 計數器1801由時間信號產生器106接收一時鐘信號與 一水平同步信號•裝置1801對該時鐘信號之脈衝計數•計 數器1801輸出一計數結果信號至比較器1803,其代表在每 一框內之目前存取的水平點（一目前被掃描之水平點）·計 數器1801在回應於該水平同步信號之每一脈衝下被重置· 比較器1803被微電腦1 603通知該等水平界限位置H1與 H2·比較器1803決定被計數器1801之轍出信號所代表之 目前被存取的水平黏是否介於水平界限位置H1與H2間* 當該目前被存取之水平點為介於水平界限位置H1與H2間 時，比較器1803輸出一"1"信號（一高位準信號）至AND甯 路1805·否則，比較器1803输出一 0"電路（一低位準倌號） 至AND電路1 805 · 計數器180 2由時間信號產生器106接收該水平同歩信 號•此外，計數器1 802由時間信號產生器106接收一垂直 同步信號。裝置1802就該水平同步信號之脈衝計數。計數 器1802輸出一計數結果信號至比較器1804,其代表每一框 內之目前被存取之垂直點（一目前被掃描之垂直點）·計數 器180 2在回應於該垂直同步信號之每一脈衝下被重置•比 較器1804被微電腦1 60 3通知該等垂直界限位置VI與V2· 比較器1 804決定被計數器1802之輸出信號所代表之目前 被存取的垂直點是否介於垂直界限位置VI與V2間。當該 目前被存取之垂直點為介於垂直界限位置VI與V2間時， 比較器1804轎出一 "Γ信號（一高位準信號）至AND電路 1 805。否則，比較器1 804輸出一"〇"電路（一低位準信號） -37- 本紙張尺度適用中國國家揉率（ CNS ) A4规格（210X297公釐） ----------裝-- * ^ · C. (锖先閲讀背面之注意事項再\ V頁) 訂 線 f432_ A7 B7 經濟部智慧財產局員工消费合作社印製 五、發明説明（35 ) 至AND電路1805 · 當比較器1803與1804之輸出信號二者為"Γ時，即當 目前被存取之點為在有效區域ER內時，ADN電路18 05輸出 一寫出賦能信號為"1"(一高位準狀態）至記憶體1601與 1602 ·否則，AND電路1805轜出一寫出賦能信號為'ΜΓ( — 低位準狀態）至記憶體1601與1602 ·當該寫出賦能信號為 Hl"時，該第一視頻資料至記憶體1601之寫出被允許《當 該寫出賦能信號為時，該第一親頻資料至記憶體1601 之寫出被禁止*當該寫出賦能信號為”Γ時，該第二親頻資 料至記憶體1602之寫出被允許•當該寫出賦能信號為"0" 時，該第二視頻資料至記憶髋1602之寫出被禁止· 因之，對應於該有效區域ER之第一視頻資料的每一部 分被選擇，且僅有該第一視頻資料之被選擇部分被傅输至 該網路*而且，對應於該有效區域ER之第二親頻資料的每 一部分被遠擇，且僅有該第二視頻資料之被選擇部分被傅 輸至該網路· 不同的有效區域可分別就該第一視頻資料與該第二視 頻資料被設定•在此情形中，處理電路1604被提供二個區 域設定電路，其分別與該第一視頻資料與該第二視頻資料 相覼· 其須注意，成像裝置101與102可被三個以上之成像 裝置取代•第22圖之系統的設計可被加到第9圖之系統， 第14圖之系統，第16圖之系統，或第18圖之系統· 本發明之第十二實施例除了此後所指出之設計改變外 38- 本紙張尺度逍用中«國家樣準（CNS ) Α4规格（2〖0Χ297公釐） 請 先 聞 面 之 注 項 再 Λ 裝 1Τ 線 432869 A7 B7 五、發明説明（36) 為類似於其第十一實施例· 在第十二實施例中，微電腦1603(見第23圃）由處理電 路1604(見第23圖）接收該第一視頻資料與該第二視頻資 料*微電腦1603處理該第一視頻資料與該第二視頻資料以 就一預定的目標物體搜尋因而所代表之框•微電腦1 603產 生一第一捜尋結果之資訊件指出該目標物體在一框中是為 出現與否*在該目標物體在一框出現的情形中，微電腦1603 產生一第二捜尋結果資訊件指出該目標物體之位置與大 小·微電腦1 603在回應於所產生之第一與第二捜尋結果的 資訊件下決定該有效區域ER=明確地說，微電腦160 3在回 應於所產生之第一與第二搜尋結果資訊件下決定該等水平 界限位置H1與H2 ·及垂直界限位置VI與V2。 其須注意到先前提及之目標物體搜尋過程可由一專用 的視頻資料處理器所實施。同時，先前提及之決定有效區 域ER的過程|即先前提及之決定水平界限位置H1與H2及 垂直界限位置VI與V2的過程可由專用的區域指派電路所 實施· 第26圖為與決定該有效區域ER有關之微電腦16 03內 一段程式的流程圖* 就如第26圔顯示者，該段程式之第一步驟2101為將 該有效區域ER設定為一預定的起始區域*在步驟2101後’ 該程式前進到步驟2102 · 步驟2102在例如以該第一與第二捜尋結果資訊件為基 礎來決定該有效區域ER為可接受的或不可接受的·當該有 -39- 本紙張尺度適用中國國家橾準（CNS > A4規格（210X297公釐） i_i_l-^^I9 ^bi 1* (請先聞讀背面之注意事項再填寫本頁) -----飞訂· -線r 經濟部智慧財產局員工消費合作社印製 432869 A7 B7 經濟部智慧財產局貝工消費合作社印製 五、發明説明（37) 效區域被決定為可接受的時，該程式由步驟21 02離開，然 後此程式段目前的執行週期結束。在此情形中，該可接受 的有效區城ER被實際地使用。當該有效區域ER被決定為 不可接受的時，該程式由步驟2101前進到步驟2103· 步驟2103在回應於該第一與第二捜尋結果資訊件下將 該有效區域ER更新•明確地說，步驟2103在回應於該第 一與第二捜尋結果資訊件下更新水平界限位置Η1與Η2及 垂直界限位置VI與V2·有效區域ER之更新包括至少在位 置或大小的至少之一移動該有效區域ER或改變該有效區域 ER·較佳的是，該有效區域ER之更新被設計來朝向該有效 區域ER之中心相對地移動該目標物體*在歩驟2103後， 該程式回到步驟2102 · 依據一第一例，該起始的該有效區域ER與由信號處理 器1G3與104(見第22圆）所輸出之每一第一視頻資料與第 二視頻資料所代表的整個框相符*該有效區域ER在回應於 該目樓物髏之位置與大小下由該起始區域被改變或移勖* 依據一第二例，該起始的該有效區域ER與一框內的上 層邊緣區域相符•該有效區域ER由該起始區域被移動’使 得該目標物體將以此為中心· 其須注意到，成像裝置101與1〇2(見第22圖）可用三 個以上的成像裝置取代·用於決定該有效區域ER之控制資 訊可經由該網路與匯流排I/F電路1605(見第23圃）被傳輸 •至微電腦1 603(見第23圖）· 本發明之第十三實施例除了此後所指出之設計改變外 -40- (锖先聞讀背面之注意Ϋ項再填寫本頁)In ^^ 1 1 ^ 1 SWlll 1 ^ 1 A3 • \ < Please read the precautions on the back before h. I) Ordering · Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 432869 V. Description of the invention ( 33) Packet flow • For example, each packet is filled with at least one of a portion of the video data of the first compression result and a portion of the video data of the second compression result. Preferably, each packet contains The information piece after the format of the video data is added, the information piece after the addition represents the identification number of the imaging device that caused the video data therein, and the information piece after the addition represents the position of the image part represented by the video data * The processing circuit 1604 outputs the packet stream to the bus I / F circuit 16fl5 * The bus I / F circuit 1 60 5 outputs the packet stream to the network. The microcomputer 16Q3 can pass through the network bus 1 / F circuit 1605 in An external device transmits and receives non-synchronized packets. The processing circuit 1604 includes an area setting circuit or a masking circuit 1606. The area setting circuit 1 606 determines an effective area ER within a frame represented by each of the first video material and the second video material. As shown in Figure 24, the effective area ER is a rectangle. This effective area ER extends between the horizontal limit positions (horizontal limit pixel position values) H1 and H2. The effective range ER extends between the vertical limit position (vertical limit pixel position value) VI and V2. Just like the 25th display, the area setting circuit 1606 includes counters 1801 and 1802, comparators 1 803 and 1804, and an AND. Circuit 1805 »The counters 1801 and 1802 are connected to the time signal generator 106. The counters 1801 and 1802 are connected to the comparator 1803. The comparator 1803 is connected to the microcomputer 1603 and the AND circuit 1805. The counter 1802 is connected to the comparator 1804. The comparator 1804 is connected to the microcomputer 1603 and the AND circuit 1 805. The AND circuit 1805 is connected to the memories 1601 and 1602. -36- This paper is scaled to the Chinese standard yCNsTA4it (210X297 mm) HI §1 · if— ^^ 1 · ^ -1 »* f * Λ · (Please read the precautions on the back before you educate.) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, printed by the 8th Industrial Cooperative Cooperative A32β69 Α7 Β7 Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, the Shelled Consumer Cooperative, V. Description of the invention (34) Counter 1801 is provided by The time signal generator 106 receives a clock signal and a horizontal synchronization signal. The device 1801 counts the pulses of the clock signal. The counter 1801 outputs a counting result signal to the comparator 1803, which represents the current access level in each frame. Point (a horizontal point currently being scanned). The counter 1801 is reset at each pulse in response to the horizontal synchronization signal. The comparator 1803 is notified by the microcomputer 1 603 to the horizontal limit positions H1 and H2. The comparator 1803 decides Whether the currently accessed level is represented by the horizontal limit positions H1 and H2 as represented by the signal from the counter 1801. When the currently accessed level is between the horizontal limit positions H1 and H2, The comparator 1803 outputs a "1" signal (a high-level signal) to AND Ning Road 1805. Otherwise, the comparator 1803 outputs a 0 " circuit (a low-level signal) to the AND circuit 1 805 · the counter 180 2 by time The signal generator 106 receives the horizontal synchronizing signal. In addition, the counter 1 802 receives a vertical synchronization signal from the time signal generator 106. The device 1802 counts the pulses of the horizontal synchronization signal. The counter 1802 outputs a counting result signal to the comparator 1804, which represents the currently accessed vertical point (a currently scanned vertical point) in each frame. The counter 180 2 responds to each pulse of the vertical synchronization signal. The comparator 1804 is notified by the microcomputer 1 60 3 of these vertical limit positions VI and V2. The comparator 1 804 decides whether the currently accessed vertical point represented by the output signal of the counter 1802 is at the vertical limit position. Between VI and V2. When the currently accessed vertical point is between the vertical limit positions VI and V2, the comparator 1804 outputs a " Γ signal (a high level signal) to the AND circuit 1805. Otherwise, the comparator 1 804 outputs a "quota" circuit (a low level signal) -37- This paper size applies to the Chinese National Kneading Rate (CNS) A4 specification (210X297 mm) --------- -Equipment-* ^ · C. (锖 Read the precautions on the back first, then \ V) Thread f432_ A7 B7 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (35) to AND circuit 1805 · When When both the output signals of the comparators 1803 and 1804 are " Γ, that is, when the currently accessed point is within the effective area ER, the ADN circuit 18 05 outputs a write enable signal as " 1 " (a High level state) to the memory 1601 and 1602 · Otherwise, the AND circuit 1805 outputs a write enable signal as' ΜΓ (— low level state) to the memory 1601 and 1602 · When the write enable signal is Hl " When the writing of the first video data to the memory 1601 is allowed, "When the writing of the enabling signal is, the writing of the first pro-frequency data to the memory 1601 is prohibited. * When the writing of the enabling signal When “Γ”, the writing of the second frequency data to the memory 1602 is allowed. • When the write enable signal is & quo When t; 0 ", the writing of the second video data to the memory hip 1602 is prohibited. Therefore, each part of the first video data corresponding to the effective area ER is selected, and only the first video data The selected part is inputted to the network * and each part of the second-frequency data corresponding to the effective area ER is selected remotely, and only the selected part of the second video data is inputted to the network · Different effective areas can be set for the first video data and the second video data respectively. In this case, the processing circuit 1604 is provided with two area setting circuits, which are respectively related to the first video data and the first video data. The two video materials are similar. It should be noted that the imaging devices 101 and 102 can be replaced by three or more imaging devices. The design of the system in Fig. 22 can be added to the system in Fig. 9, the system in Fig. 14, and the 16 Figure system, or Figure 18 system · The twelfth embodiment of the present invention, in addition to the design changes pointed out below 38- This paper size is in use «National Sample Standard (CNS) A4 Specification (2 〖0 × 297mm ) Please listen to the note before Λ installed 1T line 432869 A7 B7 V. Description of the invention (36) is similar to its eleventh embodiment · In the twelfth embodiment, the microcomputer 1603 (see the 23rd garden) is composed of the processing circuit 1604 (see the 23rd figure) Receive the first video data and the second video data * The microcomputer 1603 processes the first video data and the second video data to search for a predetermined target object and thus represents a frame • The microcomputer 1 603 generates a first search The result information file indicates whether the target object is in a frame or not. * In the case where the target object appears in a frame, the microcomputer 1603 generates a second search result information file indicating the position and size of the target object. The microcomputer 1 603 determines the effective area in response to the information pieces of the first and second search results generated. ER = Specifically, the microcomputer 160 3 responds to the generated first and second search results information pieces. The horizontal limit positions H1 and H2 and the vertical limit positions VI and V2 are determined. It should be noted that the previously mentioned target object search process can be implemented by a dedicated video data processor. At the same time, the previously mentioned process of determining the effective area ER | that is, the previously mentioned process of determining the horizontal limit positions H1 and H2 and the vertical limit positions VI and V2 can be implemented by a dedicated area assignment circuit. The flow chart of a program in the microcomputer 16 03 related to the effective area ER * As shown in Section 26 圔, the first step 2101 of the program is to set the effective area ER to a predetermined starting area * After step 2101 'The program proceeds to step 2102. Step 2102 determines whether the effective area ER is acceptable or unacceptable based on the first and second search result information files, for example. Applicable to China National Standards (CNS > A4 (210X297mm) i_i_l-^^ I9 ^ bi 1 * (Please read the precautions on the back before filling out this page) ----- Fly-booking · -Line r Printed by the Intellectual Property Bureau's Consumer Cooperatives of the Ministry of Economic Affairs 432869 A7 B7 Printed by the Intellectual Property Bureau of the Ministry of Economy's Intellectual Property Bureau Shellfish Consumer Cooperatives V. Invention Description (37) When the effective area is determined to be acceptable, the program exits from step 21 02, then This section is currently The execution cycle ends. In this case, the acceptable effective area ER is actually used. When the effective area ER is determined to be unacceptable, the program proceeds from step 2101 to step 2103. Step 2103 is in response to Update the effective area ER under the first and second search results information. Specifically, step 2103 updates the horizontal limit positions Η1 and Η2 and the vertical limits in response to the first and second search results information. Position VI and V2. Update of the effective area ER includes moving the effective area ER or changing the effective area ER at least one of the position or size. Preferably, the update of the effective area ER is designed to face the effective area. The center of ER moves the target object relatively * After step 2103, the program returns to step 2102. According to a first example, the starting effective area ER and the signal processors 1G3 and 104 (see circle 22) ) Each output of the first video data is consistent with the entire frame represented by the second video data. * The effective area ER is changed or moved from the starting area in response to the position and size of the crossbones *According to a second example, the starting effective area ER is consistent with the upper edge area within a frame. The active area ER is moved from the starting area 'so that the target object will be centered on it. It must be noted The imaging devices 101 and 102 (see FIG. 22) can be replaced by three or more imaging devices. The control information used to determine the effective area ER can be passed through the network and the bus I / F circuit 1605 (see page 23). (Principle) is transmitted to the microcomputer 1 603 (see FIG. 23). The thirteenth embodiment of the present invention is in addition to the design changes pointed out later. -40- (锖 Please read the note on the back before filling in this page)

本紙張尺度遙用中國國家揉率（CNS ) A4規格（2丨0X297公釐} 432869 A7 A7 B7 五、發明説明（38) 與第十二賨施例為類似的* 該第十三實施例包括一裝置具有一感知功能以偵測將 被捕捉之物體影像•例如|該物體為一人物•該感知功能 提供所偵測之物體的資訊。在該第十三實施例中，該有效 區域ER在回應於所偵測之資訊下被決定。 其須注意到，一物體之資訊可經由該網路由一外部裝 置被傳輸。 元件標 號對照 表 元件編號 譯 名 元件編號 譯 名 101 成像裝置 302 信號處理電路 102 成像裝置 401 記憶體 103 信號處理器 402 記憶體 104 信號處理器 403 微電暉 105 收發機 404 處理電路 105Α 收發機 405 匯流排I/F電路 105Β 收發機 601 成像裝置 105C 收發機 602 成像裝置 105D 收發機 603 信號處理器 106 時間信號產生器 604 信號處理器 107 驅動電賂 605 收發機 201 振盪電路 606 時間信號產生器 202 水平同步信號產生器 607 騸動電路 203 垂直同步信號產生器 608 成像裝置 301 A/D轉換電路 609 信號處理器 -41- 本紙张尺度遙用中困國家搮準（CNS ) Α4規格（210Χ297公釐） (請先閲讀背面之注項再填客本頁) τ^ΐτΙΓ· 線 經濟部智慧財產局員工消費合作社印製 432869 A7 B7 五、發明説明（39) 經濟部智慧財產局員工消費合作社印製 元件標 號對照 表 元件編號 譯 名 元件編號 譯 名 610 驅動電路 1105 收發機 701 成像裝置 1106 時間信號產生器 702 成像裝置 1107 驩動電路 703 信號處理器 1201 記憶體 704 信號處理器 1202 記憶體 705 收發機 1203 微電腦 706 時間信號產生器 1204 處理電路 707 驅動電路 1205 匯流排I/F鼋路 801 振盪電路 1301 記憶體 802 水平同步信號 1302 記憶體 產生器 1303 微電腦 803 垂直同步信號 1304 處理電路 產生器 1305 匯流排I/F電路 1001 記憶體 1401 記憶體 1002 記憶體 1402 記憶體 1003 微電腦 1403 微電腦 1004 處理電路 1404 處理電路 1005 匯流排I/F電路 1405 匯流排I/F電路 1101 成像裝置 1407 視頻壓縮器 1102 成像裝置 1408 視頻壓縮器 1103 信號處理器 1501 記憶體 1104 信號處理器 1502 記憶體 -42- 本紙張尺度適用中國國家橾準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) 432869 A7 B7 經濟部智慧財產局員工消贲合作社印製 五、發明説明（ 40) 元件標號對照表 元件編號 譯 名 元件編號 譯 名 1503 微電腦 1504 處理電路 1505 匯流排I/F電路 1507 視頻壓縮器 1508 視頻壓縮器 1509 加入器' 1510 減去器 1601 記憶體 1602 記憶體 1603 微電腦 1604 處理電路 1605 匯流排I/F電路 1606 區域設定電路 1801 計數器 1802 計數器 1803 比較器 1804 比較器 1805 AND電路 2101 步驟 2102 步驟 2103 步滕 秦 -43— 本紙張尺度適用中國囲家標準（CNS > A4规格（210X 297公釐）This paper is scaled to the Chinese National Kneading Rate (CNS) A4 specification (2 丨 0X297 mm) 432869 A7 A7 B7 V. Description of the invention (38) Similar to the twelfth embodiment * The thirteenth embodiment includes A device has a sensing function to detect an image of an object to be captured. For example, the object is a person. The sensing function provides information about the detected object. In the thirteenth embodiment, the effective area ER is in It is decided in response to the detected information. It should be noted that information of an object can be transmitted to an external device via the network. Component number comparison table Component number Translation name Component number translation name 101 Imaging device 302 Signal processing circuit 102 Imaging Device 401 Memory 103 Signal processor 402 Memory 104 Signal processor 403 Micropower 105 Transceiver 404 Processing circuit 105A Transceiver 405 Bus I / F circuit 105B Transceiver 601 Imaging device 105C Transceiver 602 Imaging device 105D Transceiver 603 signal processor 106 time signal generator 604 signal processor 107 driving bridge 605 transceiver 201 oscillating circuit 606 Inter-signal generator 202 Horizontal synchronizing signal generator 607 Swing circuit 203 Vertical synchronizing signal generator 608 Imaging device 301 A / D conversion circuit 609 Signal processor -41- This paper is a standard for remotely used countries (CNS) Α4 Specifications (210 × 297 mm) (Please read the note on the back before filling in this page) τ ^ ΐτΙΓ · Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 432869 A7 B7 V. Invention Description (39) Intellectual Property Bureau of the Ministry of Economic Affairs Employee Consumer Cooperatives Printed Component Numbers Cross Reference Table Component Number Translated Component Number Translated Name 610 Drive Circuit 1105 Transceiver 701 Imaging Device 1106 Time Signal Generator 702 Imaging Device 1107 Joy Circuit 703 Signal Processor 1201 Memory 704 Signal Processor 1202 Memory 705 Transceiver 1203 Microcomputer 706 Time signal generator 1204 Processing circuit 707 Driving circuit 1205 Bus I / F circuit 801 Oscillation circuit 1301 Memory 802 Horizontal synchronization signal 1302 Memory generator 1303 Microcomputer 803 Vertical synchronization signal 1304 Processing circuit generator 1305 bus I / F circuit 100 1 memory 1401 memory 1002 memory 1402 memory 1003 microcomputer 1403 microcomputer 1004 processing circuit 1404 processing circuit 1005 bus I / F circuit 1405 bus I / F circuit 1101 imaging device 1407 video compressor 1102 imaging device 1408 video compressor 1103 signal processor 1501 memory 1104 signal processor 1502 memory -42- This paper size applies to China National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling this page) 432869 A7 B7 Printed by the staff of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed by the cooperative. V. Description of the invention (40) Component label comparison table Component number Translation name Component number translation 1503 Microcomputer 1504 Processing circuit 1505 Bus I / F circuit 1507 Video compressor 1508 Video compressor 1509 Adder '1510 Subtractor 1601 Memory 1602 Memory 1603 Microcomputer 1604 Processing Circuit 1605 Bus I / F Circuit 1606 Area Setting Circuit 1801 Counter 1802 Counter 1803 Comparator 1804 Comparator 1805 AND Circuit 2101 Step 2102 Step 2103 Step Teng Qin - 43— The paper size is in accordance with Chinese standards (CNS > A4 size (210X 297mm)

Claims (1)

432869 A8 B8 C8 D8 經濟部智慧財產局員工消f合作杜印製 六、申請專利範圍 1. —種影像捕捉及傳輸系統，包含： 第一與第二成像裝置； 第一設施用於產生一時間信號； 一共同驊動電路用於在該第一設施所產生之時間信 號所決定的相同時間驅動該第一與第二成像裝置； 一第一信號處理器用於將該第一成像裝置之輸出信 號轉換成第一數位視頻資料； 一第二信號處理器用於將該第二成像裝置之輸出信 號轉換成第二數位視頻資料； 第二設施用於將該第一數位視頻資料與該第二數位 視頻資料處理成為封包流；以及 第三設施用於傳輸該第二設施所產生之封包流· 2. 如申請專利範圍第1項所述之影像捕捉及傅输系統，進 一步包含一第三成像裝置，及一驅動電路用於在與驅動 該第一與第二成像裝置之不同時間驅動該第三成像裝 置。 3. 如申請專利範圍第1項所述之影像捕捉及傅輸系統.，其 中該第三設施包含設’施用於輸出該封包流至一網路|且 該第一設施包含設施用於產生該時間信號與該封包流之 輪出至該網路同步》 4. 如申請專利範圍第1項所述之影像捕捉及傳輸系統，進 —步包含設施用於在該第一數位視頻資料與該第二數位 視頻資料所代表之每一框內設定一可改變的傳輸開始 點，與設施用於藉由該第三設施在該第一數位視頻資料 -44 - -1 I · 11 (請先閲讀背面之注意事項再ίνί本頁) -¥ 訂. 線- 本紙張尺度遶用中國國家標準（CNS)A4規格（210 X 297公釐〉 432869 \mt 'Λ B8 CS D8 經4部皙慧財.4局員工消費合作社印製 六、申請專利範圍 1 與該第二數位視頻資料所代表之每一框的該傳輸開始點 開始而促成在該封包流之該第一數位視頻資料與該第二 數位視頻資料的傳輸。 5. 如申請專利範圍第〗項所述之影像捕捉及傳輸系統，進 一步在該第三設施中提供設施用於在固應於再傳輸要求 之信號下再傳輸該封包流之一部分。 6. 如申請專利範圍第1項所述之影像捕捉及傳輸系統，進 一步在該第三設施中提供設施用於再傳輸該封包流之全 部第一數位視頻資料與第二數位視頻資料。 7. 如申請專利範圍第1項所述之影像捕捉及傳輸系統，其 中該第二設施包含設施用於將該第一數位視頻資料壓縮 成爲第一壓縮結果之數位視_資料與設施用於將該第二 數位視頻資料壓縮成爲第二壓縮結果之數位視頻資料， 以及設施用於將該第一壓縮結果之數位視頻資料與該第 二壓縮結果之數位視頻資料組合成該封包流β 8. 如申請專利範圍第1項所述之影像捕捉及傳輸系統，其 中該第二設施包含設施用於執行該第一數位視頻資料與 該第二數位視頻資料間之第一計算作業，並產生第一運 算結果之數位視頻資料，設施用於執行該第一數位視頻 資料與該第二數位視頻資料間之第二計算作業，並產生 第二運算結果之數位視頻資料，該第二計算作業與該第 一計算作業不同，設施用於將該第一運算結果之數位視 頻資料壓縮成爲第一壓縮結果之數位視頻資料，設施用 於將該第二運算結果之數位視頻資料壓縮成爲第二壓縮 -45 - 木紙張尺度邊用中8國家樣準{CNS)M現格（210 乂 297公缝、 I —^1· I 11 _11 1 1 Λ1— 1 - - - - ....... -- 1 · (請先闐讀背面之注意事項再4.寫本頁) A8 B8 C8 D8 經濟部中央樣準局—工消费合作社印製 '中請專利範圍 結果之數位視頻資料，以及設施用於將該第一應縮結果 之數位視頻資料與該第二壓縮結果之數位視頻資料組合 成該封包流* 9·如申請專利範圔第1項所述之影像捕捉及傳輸系統，其 中該第二設施包含設施用於在該第一數位視頻資料與該 第二數位視頻資料所代表之每一框內股定一可改爱的有 效區域，設施用於選擇對應於每一框中有效區域之該第 一數位視頻資料與該第二數位視頻資料的的部分，以及 設施用於僅將該第一數位親頻資料與該第二數位視頻資 料之被選擇部分置於該封包流內》 10. 如申請專利範画第9項所述之影像捕捉及傅輸系統*其 中每一框內之該有效區域為長方形的，且在水平界限位 置間延伸及在垂直界限間延伸。 11. 如申請専利範画第9項所述之影像捕捉及傅轅系統，進 一步包含設施用於就一預定的目標物搜尋被該第一數位 視頻資料與該第二數位視頻資料所代表之每一框，以及 設施用於在回應於捜尋結果下改變每一框內之該有效區 域* 12. 如申請專利範圍第9項所述之影像捕捉及傳输系統|進 一步包含設施用於感應被該第一數位視頻資料與該第二 數位視頻資料所代表之每一框內的確定物髓1並產生感 應結果資訊，設施被提供於該第二設施中用於依照可變 的設定狀況設定每一框內之有效區域 > 以及設施用於在 回應於該感應結果資訊下決定該設定狀況》 -46 - 本紙張尺度逋用中國國家樣準（CNS ) A4规格（210X297公釐) (請先閱讀背面之注^^項再h 本肓) -裝‘ -線 r 432869 A8 B8 C8 D8 經濟部中央樣準局員工消費合作社印裝 七、申請專利範圍 13.如申請專利範圍第9項所述之影像捕捉及傳输系統，進一 步包含設施用於感應被該第一數位視頻資料與該第二數位 視頻資料所代表之每一框內的確定物體，並產生感應結果 資訊，以及設施用於在回應於該感應結果資訊下改變每一 框內之有效區域。 一 47 — 本紙張尺度逋用中國國家梂车（CNS ) Α4规格（2!0><297公嫠） (锖先Μ讀背面之注^'項再填寫本頁)432869 A8 B8 C8 D8 Employees of Intellectual Property Bureau of the Ministry of Economic Affairs, cooperation and printing. 6. Application for patent scope 1.-An image capture and transmission system, including: first and second imaging devices; the first facility is used to generate a time A signal; a common moving circuit for driving the first and second imaging devices at the same time determined by the time signal generated by the first facility; a first signal processor for output signals from the first imaging device Conversion into first digital video data; a second signal processor for converting the output signal of the second imaging device into second digital video data; a second facility for converting the first digital video data and the second digital video The data processing becomes a packet stream; and the third facility is used to transmit the packet stream generated by the second facility. 2. The image capture and transmission system described in item 1 of the patent application scope further includes a third imaging device, And a driving circuit for driving the third imaging device at different times from driving the first and second imaging devices. 3. The image capture and transmission system described in item 1 of the scope of the patent application, wherein the third facility includes a facility for outputting the packet stream to a network | and the first facility includes a facility for generating the The time signal is synchronized with the rotation of the packet stream to the network. "4. The image capture and transmission system described in item 1 of the scope of the patent application, further includes facilities for the first digital video data and the first digital video data. A variable transmission start point is set in each frame represented by the digital video data, and the facility is used for the first digital video data -44--1 I · 11 by the third facility (please read the back first) Note on this page again ννί)-¥ Order. Thread-This paper uses Chinese National Standard (CNS) A4 specifications (210 X 297 mm) 432869 \ mt 'Λ B8 CS D8 Printed by the Bureau ’s Consumer Cooperatives 6. The scope of patent application 1 and the start of the transmission of each frame represented by the second digital video material starts to facilitate the first digital video material and the second digital video in the packet stream Transmission of data 5. If requested The image capture and transmission system described in item No. of the patent scope further provides facilities in the third facility for retransmitting a part of the packet stream under the signal fixed to the retransmission request. The image capture and transmission system described in item 1 further provides facilities in the third facility for retransmission of all of the first digital video data and second digital video data of the packet stream. In the image capture and transmission system, the second facility includes a facility for compressing the first digital video data into a digital video result of the first compression. The data and facilities are used for compressing the second digital video data into a first The digital video data of the second compression result, and the facility for combining the digital video data of the first compression result and the digital video data of the second compression result into the packet stream β 8. As described in item 1 of the scope of patent application An image capture and transmission system, wherein the second facility includes a facility for performing a process between the first digital video data and the second digital video data A calculation operation and generating digital video data of a first operation result, and the facility for performing a second calculation operation between the first digital video data and the second digital video data, and generating digital video data of a second operation result, The second calculation operation is different from the first calculation operation. The facility is configured to compress the digital video data of the first operation result into the digital video data of the first compression result, and the facility is used to compress the digital video data of the second operation result. Compression becomes the second compression -45-Wood paper scale edge use in China 8 countries (CNS) M standard (210 乂 297 cm, I — ^ 1 · I 11 _11 1 1 Λ1— 1----.. .....-1 · (Please read the precautions on the back before writing 4. Write this page) A8 B8 C8 D8 Digital Video of the Patent Scope Results in “Printed by the Central Sample Bureau of the Ministry of Economic Affairs-Industrial and Consumer Cooperatives” Data and facilities used to combine the digital video data of the first compression result with the digital video data of the second compression result into the packet stream * 9. Image capture and transmission as described in item 1 of the patent application System where the first The facility includes facilities for defining a valid area that can be changed in each frame represented by the first digital video material and the second digital video material. The facility is used to select the area corresponding to the valid area of each frame. Parts of the first digital video material and the second digital video material, and facilities for placing only the selected portion of the first digital pro-frequency data and the second digital video material in the packet stream "10. Such as The image capture and fusu system described in item 9 of the patent application for painting * wherein the effective area in each frame is rectangular, and extends between the horizontal limit positions and between the vertical limit positions. 11. The image capturing and fusing system described in item 9 of the application for the Fanli painting, further comprising facilities for searching a predetermined target for each of the objects represented by the first digital video data and the second digital video data. A frame, and facilities for changing the effective area within each frame in response to search results * 12. The image capture and transmission system described in item 9 of the scope of patent application | further includes facilities for sensing The first digital video data and the second digital video data determine the pulp 1 in each frame and generate the sensing result information, and facilities are provided in the second facility for setting each of them according to a variable setting condition. The effective area within the frame> and the facility is used to determine the setting status in response to the information of the sensing result "-46-This paper size uses the Chinese National Standard (CNS) A4 size (210X297 mm) (please first Read the note on the back ^^ item and then this 肓) -installation '-line r 432869 A8 B8 C8 D8 Printed by the Consumer Cooperatives of the Central Procurement Bureau of the Ministry of Economic Affairs The image capture and transmission system described above further includes facilities for sensing a certain object in each frame represented by the first digital video data and the second digital video data, and generating sensing result information, and the facilities are used for The effective area within each frame is changed in response to the sensing result information. I 47 — This paper uses China National Automobile (CNS) Α4 specification (2! 0 > < 297 gong) (Please read the note ^ 'on the back before filling this page)
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CN1179550C (en) 2004-12-08
US20050100101A1 (en) 2005-05-12
US7239663B2 (en) 2007-07-03
CA2276949A1 (en) 2000-01-10
CA2276949C (en) 2002-04-23
US6625220B1 (en) 2003-09-23
EP0971547A3 (en) 2005-07-20
AU715404B1 (en) 2000-02-03
JP2000032327A (en) 2000-01-28
CN1243383A (en) 2000-02-02
EP0971547A2 (en) 2000-01-12

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