TW432564B - Package structure of flexible substrate - Google Patents

Package structure of flexible substrate Download PDF

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Publication number
TW432564B
TW432564B TW87120701A TW87120701A TW432564B TW 432564 B TW432564 B TW 432564B TW 87120701 A TW87120701 A TW 87120701A TW 87120701 A TW87120701 A TW 87120701A TW 432564 B TW432564 B TW 432564B
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TW
Taiwan
Prior art keywords
flexible substrate
scope
package structure
chip
flexible
Prior art date
Application number
TW87120701A
Other languages
Chinese (zh)
Inventor
Pei-Hua Tsau
You-Lan He
Original Assignee
Vanguard Int Semiconduct Corp
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Priority to TW87120701A priority Critical patent/TW432564B/en
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Publication of TW432564B publication Critical patent/TW432564B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32057—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

The package structure of flexible substrate of the present invention comprises an integrated circuit chip, a flexible substrate, interface material, and a plurality of conductive bumps. The flexible substrate is disposed below the chip and has a plurality of conductive wires. The flexible substrate further includes a plurality of through holes passing through the flexible substrate. The interface material is disposed between the chip and the flexible substrate. The conductive bumps are disposed below the flexible substrate and are electrically connected to the plurality of conductive wires to enable the chip to electrically connect to the outside.

Description

r F4 325 6 4 A7 B7 五、發明説明（ 發明領斑： 本發明係與一種封裴結構有關，特別是有關於一種軟 性基板之封裝結構，以應用於積體電路晶月封裝的應用之 中。 經濟部中央標準局員工消費合作杜印聚 t明背景： 在眾多如個人電腦 '大型主機、通訊設備、及各種消 費性電子產品等電子***的應用之中，封裝结構在提供系 統内部連結的應用上扮演著極為重要的角色，藉由封裝的 過程，可於系統内部的各個元件及晶月間形成電性的連 接，以達成系統設計上的功能與需求。為了確保系統的功 flb及操作特性’在封裝時的效能及設計上所需考量的首要 問題即是可靠度的問題。 隨著半導艘工業數十年來的研究與發展，積體電路晶 片上凡件的積集度亦有快迷的提昇，以增加單一晶片上的 疋件數目’並提耳其功能’因此相對也使得晶片上對外連 接的接點數大為增加’相對於此，封裝的結構在設計亦需 加以改良’以配合晶片在微小面積上接點密度及數目的增 加。在封裝技術過去的發展之中，已產生多種可應用於量 產上的不同技術’例如應用於晶片與封裝結構間連結的覆 晶（flip-chip)結構及捲帶自動黏著（tape aut〇mated b〇nding; TAB)技術；而在第一級的單晶片封裝應用上，則有如雙排 接腳（dual-in-line; DIP)封裝、四方扁平封裝（quad fUt pack; 本紙張尺度適用中國國家標準（CNS > Α4規格U10X2?7公疫） -----^----w-I^------1Γ------^ V - ' (請先聞讀背面之注意事項7^寫本頁) 「14 32 5 6 4 五、發明説明（） A7 -r F4 325 6 4 A7 B7 V. Description of the invention (Inventive spot: The present invention is related to a sealing structure, especially a packaging structure of a flexible substrate, which is used in the application of integrated circuit crystal moon package Du Yinju, Consumer Cooperation of the Central Standards Bureau of the Ministry of Economics Background: Among many applications of electronic systems such as personal computers, mainframes, communication equipment, and various consumer electronics products, the packaging structure provides It plays a very important role in the application. Through the packaging process, electrical connections can be formed between the various components and crystal moons in the system to achieve the functions and requirements of the system design. In order to ensure the system's functional flb and operating characteristics 'The primary issue that needs to be considered in packaging efficiency and design is the issue of reliability. With decades of research and development in the semi-conductor industry, the accumulation of all components on integrated circuit chips is also fast. To increase the number of components on a single chip, and increase its function, so the number of external connections on the chip is relatively large. In addition, “in contrast, the package structure also needs to be improved in design” to match the increase in the density and number of contacts on the chip in a small area. In the past development of packaging technology, a variety of applications that have been applied to mass production have been produced. “Different technologies” such as flip-chip structure and tape autombonding (TAB) technology applied to the connection between the chip and the package structure; and in the first-level single-chip package application , Such as dual-in-line (DIP) packaging, quad flat packaging (quad fUt pack; this paper size applies to Chinese national standards (CNS > Α4 size U10X2? 7 public epidemic) ----- ^ ---- wI ^ ------ 1Γ ------ ^ V-'(Please read the precautions on the back 7 ^ Write this page) "14 32 5 6 4 V. Description of the invention ( ) A7-

補无I (請先閲讀背面之注意事項再填寫本頁) QFP)、接腳格狀矩陣 （Pin-grid array; PGA)、捲帶自動黏 著（tape automated bonding; TAB)、及球腳格狀陣列（ball grid array; BGA>等技術的應用，以在日益縮減的尺寸下， 以較低的成本來提供可靠的電性連結β 在高密度及晶片級尺寸的封裝（chip scale package; CSP) 的應用之中，球腳格狀陣列（BG A)及微采級球腳格狀陣列（# -BG Α)是最為重要的封裝製程之―，在不限制本發明之精 神及應用範圍之下，以下即以球腳格狀陣列的封裝結構為 例’介紹本發明之背景。 參見第一圖所示封裝結構的側視示意圖，積體電路晶 片係封裝於封裝外殼12之内，圖中之晶片10係以接 點面朝下的反面方式放置，也就是所謂的覆晶式封裝結 構，在封裝外殼12的下方有多個銲錫球（扣丨心!· ball)i4， 經濟部智慧財產局貝工消費合作社印製 以產生封裝晶片1 0的對外連接，而位於晶片！ 〇下方的軟 性電路捲帶（flexible circuit tape)16，則用以形成晶片ι〇 上接觸墊與銲錫球14問的電性連接，晶片1 〇與軟性電路 搂帶1 6之間則以介面材質1 8相隔，以調適晶片丨〇與其 未來接合之電路板（printed circuit board; PCB)〖9兩者在熱 膨脹係數上的差異，避免應力問題的發生，進而提升導電 凸塊的可靠度；一般而言’介面材質18可使用軟性或具 缓衝特性的材質，例如目前較常應用的彈性緩衝材 (elastomer)，除此之外，介面材質is亦可同時具有黏著的 特性，以增加晶片10與軟性電路捲帶16兩者間接著的可 靠度· 參見第二圖所示，為另一種封裝結構的側視示意囷， 本紙張尺度適用中國困家搮準（CNS ) A4規格（210X297公鏖） A7 "bt7 補充 丨| II _ 「腳4 325 6 4 五、發明説明（） 積體電路晶片20係封裝於封裝外殼22之内，圖中之晶片 20則以接點面朝上的正面方式放置，在封裝外殼22的下 方有多個銲錫球24以產生封裝晶片的對外連接，在圖示 的結構中，晶X 20係封裝於軟板26之上，例如軟性的印 刷電路板等，並以封裝外殼22包覆於其上方及四周’而 接合線28則用以形成晶片20上接觸墊與銲錫球24間的 電性連接，晶片20與軟性基板26之間則以介面材質29 相隔，以提供晶片2 0與軟性基板2 6兩者之間的黏著力， 而相同於第一圖中的介面材質18，介面材質29亦可使用 軟性或具緩衝特性的材質1以調.適晶片 20與相接合之電 路板兩者在熱膨脹係數上的差異，避免應力問題的發生。 然而，在上述结構的封裝過程之中，經常在介面材質 18及28中會有捕陷空氣之空孔的產生，使材質的密度降 低，介面的強度亦受到影響，此外，由於目前封裝製程中 所應用的介面材質多數皆為會吸收濕氣的材料，而介面材 質中的濕氣往往會在後續所進行的熱回流（thermal reflow) 過程中受熱蒸發，導致體積的膨脹而由介面材質中破裂穿 出，使晶片與其下方基板間的接著特性或介面強度因而受 到破壞，導致封裝強度及可靠度的大幅下降。 I -I In 1 -- - - i f I 1 I --- -I - -- 1 丁 · ，T (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家梯準（CNS ) A4洗格（2丨0 X 297公釐） r *4325^4 五、發明説明（） 發明目的及概述： 本發明的目的為提供一種軟性基板之封裝結構。 本發明的另一目的為提供一種應用於積禮電路晶片封 裝的軟性基板封裝結構。 本發明的另一目的為提供一種軟性基板之封裝結構’ 可防止傳統軟性基板封裝時空孔缺陷所造成之介面強度下 降的問題。 本發明的再一目的為提供一種軟性基板之封裝結構’ 可防止傳統軟性基板封裝時，介面材質吸濕且受熱膨脹後 導致破裂或強度下降等的問題。 本發明中之軟性基板封裝結構可包含積體電路晶片、 軟性基板、介面材質、以及多個導電凸塊等；軟性基板位 於晶片之下方，其内並包含許多的導電連線’軟性基板並 具有多個穿過軟性基板之貫穿孔；介面材質則介於晶片及 軟性基板之間；而導電凸塊則位於軟性基板之下方’並與 複數個導電連線形成電性連接以提供晶片之對外電性連 接。而在所介紹的實施例之中，上述之軟性基板可包含軟 性電路捲帶或是軟性印刷電路板等的軟板材質，以封裝晶 片 '並提供良好而可靠的電性連結。 I m 1 I II— ! I -:---- t ---- - I--[ - - - I *1TI ..... ! —ϊ I ! __ (請先閲讀背面之注意事項-"'寫本頁) 經濟部中央標準局員工消費合作社印繁 本紙張尺度適用中國國家標準（CNS } A4規格（210X297公釐） f IT4 3256 4 A7 _____________B7 五、發明説明（） 圃式簡單說明： 第一®顯示使用軟性電路捲帶的封裝結構之侧視示意 圖。 第二圊顯示使用軟性基板的封裝結構之側視示意圖。 第三圖顯示本發明中之封裝結構應用於軟性電路捲帶 封裝製程的側視示意圈。 第四圖顯示本發明中之封裝結構應用於軟性基板封裝 製程的側視示意圖。 發明詳細說明： 本發明中提供一種软性基板之封裝結構，藉由在晶片 下方的軟性基板形成貫穿孔，可使封裝製程中的空氣能有 效的被排除’消除傳統封裝結構中介面材質中的空孔缺陷 問題’以解決強度因而下降的問題，而在貫穿孔的結構設 計之下’可進一步使晶片與基板間接合的強度增加’增進 產品的良率及可靠度。 經濟部中央標準局員工消費合作社印製 在高密度及晶片級尺寸的封裝（chip scale package; CSP) 的應用之中，球腳格狀陣列（BGA)及微米級球腳格狀陣列（4 -BGA)是最為重要的封裝製程之一，因此，在不限制本發 明之精神及應用範園之下，以下即以球腳格狀降列的封裝 結構為例’介紹本發明之實施。參見第三圊所示，為本發 明中之封裝結構應用之一例的侧視示意圖，本發明中之封 裝結構可包含積體電路晶片30、軟性基板32、介面材質34、 本紙張尺度適用中國國家標準（CNS > A4規格（210X29*7公釐） ,4 325 6 4 一________λί B7 五、發明説明（ 平V* ΓΓ w .:、、 ) 釉无 經濟部智慧財產局員工消費合作社印製 以及多數個的導電凸塊36。 積想電路晶片3 〇係為尚未進行封裝之裸晶片，以藉 由封裝結構形成與外界的其他元件、晶片或電路i成連結； 軟性基板32則位於晶片30之下方，此例中軟性基板可 為軟性電路捲帶（flexib丨e circuit tape)，為了提供"必要的電 性連結，軟性電路捲帶32内包含許多的導電連線，軟性電 路播帶32並具有多個穿過其表面之貫穿孔，如圖中所示之 貫穿孔32a及32b，一般而言，貫穿孔可形成於各導電線 路之間的間隙處，而不致破壞到原來軟性電路捲帶32上的 導電線路，以本例而言，貫穿孔之直徑可約為〇 〇2公厘至 1公厘之間，其較佳值可約為〇.丨公厘。以本例中軟性電 路播帶32的材質而言，這些貫穿孔可利用化學方式的蝕刻 法 '機械式的鑽扎法、或機械式的打孔法等不同的方法加 以形成。 介面材質34則介於晶片30及軟性電路捲帶32之間， 以本例而言，介面材質34可使用具彈性或是緩衝性質較 佳的材質，以調適晶片30與未來所需接著之電路板兩者 之間因熱膨脹係數不同所產生的應力問題，一般而言，介 面材質1 8可使用軟性或具緩衝特性的材質，以本例而言， 可使用目前較常應用的彈性緩衝材（elastomer)，彈性緩衝 材一般皆為矽基類（silicone-based)或樹脂類的材質；藉由 介面材質34的作用’可緩和晶片30與電路板兩者之間因 溫度變化所產生之熱應力’消除應力所導致的缺陷問題β 除此之外’介面材質34亦可具有黏著的特性或加入黏著 性的材質，以增加晶片3 0與軟性電路捲帶3 2兩者間接著 本紙浪尺度逍用中國困家橾準（CNS ) Α4规格（210Χ 297公釐） -η —^—1 ^^^1 Hu I —^ϋ —^ϋ nn ml— (請先閲讀背面之注意事項再填寫本頁)No I (please read the notes on the back before filling this page) (QFP), pin-grid array (PGA), tape automated bonding (TAB), and ball-shaped grid Application of technologies such as ball grid array; BGA > to provide reliable electrical connection at a reduced cost at a reduced cost β in high density and chip scale package (CSP) Among the applications, ball grid array (BG A) and micro-mining ball grid array (# -BG Α) are the most important packaging processes-without limiting the spirit and scope of the invention The following is a description of the background of the present invention by taking the package structure of a ball-foot grid array as an example. Referring to the schematic side view of the package structure shown in the first figure, the integrated circuit chip is packaged within the package housing 12, The chip 10 is placed with the contact side facing down, which is a so-called flip-chip package structure. There are multiple solder balls (buttons and balls) i4 under the package shell 12. The Intellectual Property Bureau of the Ministry of Economic Affairs Printed by Shelley Consumer Cooperative to produce packaging The external connection of the wafer 10 is located on the wafer! The flexible circuit tape 16 below the wafer is used to form the electrical connection between the contact pads on the wafer ι and the solder balls 14, and the wafer 10 is flexible. The circuit belts 16 are separated by interface materials 18 to adjust the difference between the thermal expansion coefficient of the chip and its future printed circuit board (PCB) [9] to avoid stress problems. In order to improve the reliability of the conductive bumps, in general, the interface material 18 can be made of soft or cushioning materials, such as the currently commonly used elastic cushioning material (elastomer). In addition, the interface material is also At the same time, it has adhesive characteristics to increase the reliability of indirect contact between the wafer 10 and the flexible circuit tape 16. See the second figure for a side view of another package structure. This paper is suitable for Chinese families. Standard (CNS) A4 specification (210X297 male) A7 " bt7 supplement 丨 | II _ "pin 4 325 6 4 V. Description of the invention () The integrated circuit chip 20 is packaged in the package housing 22, as shown in the figure The chip 20 is placed in a front-facing manner with the contacts facing upward. There are a plurality of solder balls 24 below the packaging housing 22 to generate external connections of the packaged wafers. In the structure shown, the crystal X 20 is packaged on a flexible board 26 Above, for example, a flexible printed circuit board, etc., and the package shell 22 is covered above and around it ', and the bonding wire 28 is used to form an electrical connection between the contact pads on the chip 20 and the solder balls 24, and the chip 20 and The flexible substrate 26 is separated by an interface material 29 to provide the adhesion between the chip 20 and the flexible substrate 26. The interface material 18 is the same as the interface material 18 in the first figure. The material 1 with cushioning characteristics adjusts the difference in thermal expansion coefficient between the chip 20 and the bonded circuit board to avoid stress problems. However, in the packaging process of the above structure, air traps are often generated in the interface materials 18 and 28, which reduces the density of the material and affects the strength of the interface. In addition, due to the current packaging process, Most of the interface materials used are materials that can absorb moisture, and the moisture in the interface material is often heated and evaporated during the subsequent thermal reflow process, which causes the volume to expand and break from the interface material. Penetration causes damage to the bonding characteristics or interface strength between the wafer and the substrate below it, resulting in a significant reduction in package strength and reliability. I -I In 1---if I 1 I --- -I--1 Ding, T (Please read the precautions on the back before filling out this page) Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs The paper size is applicable to China National Standards (CNS) A4 (2 丨 0 X 297 mm) r * 4325 ^ 4 V. Description of the invention () Purpose and summary of the invention: The purpose of the present invention is to provide a flexible substrate packaging structure . Another object of the present invention is to provide a flexible substrate package structure applied to Jie Li circuit chip packaging. Another object of the present invention is to provide a packaging structure of a flexible substrate ', which can prevent the problem of a decrease in interface strength caused by a hole defect in a conventional flexible substrate package. Yet another object of the present invention is to provide a packaging structure of a flexible substrate ', which can prevent problems such as cracking or strength reduction due to moisture absorption and thermal expansion of the interface material when the conventional flexible substrate is packaged. The flexible substrate packaging structure in the present invention may include an integrated circuit chip, a flexible substrate, an interface material, and a plurality of conductive bumps, etc .; the flexible substrate is located below the wafer, and includes a plurality of conductive wiring 'flexible substrates and having Multiple through-holes through the flexible substrate; the interface material is between the wafer and the flexible substrate; and the conductive bumps are located below the flexible substrate 'and form an electrical connection with a plurality of conductive connections to provide external power to the chip Sexual connection. In the introduced embodiment, the above-mentioned flexible substrate may include a flexible circuit material such as a flexible circuit tape or a flexible printed circuit board to encapsulate the wafer and provide a good and reliable electrical connection. I m 1 I II—! I-: ---- t -----I-[---I * 1TI .....! —Ϊ I! __ (Please read the precautions on the back- " 'write this page) The paper standard printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs is printed in accordance with the Chinese national standard (CNS) A4 (210X297 mm) f IT4 3256 4 A7 _____________B7 5. Description of the invention : The first ® shows a schematic side view of a packaging structure using a flexible circuit reel. The second 圊 shows a schematic side view of a packaging structure using a flexible substrate. The third image shows a packaging structure in the present invention applied to a flexible circuit reel packaging The schematic side circle of the manufacturing process. The fourth figure shows a schematic side view of the packaging structure of the present invention applied to a flexible substrate packaging process. Detailed description of the invention: The present invention provides a packaging structure of a flexible substrate. The formation of through-holes in the flexible substrate can effectively eliminate the air in the packaging process from "eliminating the problem of void defects in the interface material in traditional packaging structures" to solve the problem of reduced strength. The count "can further increase the strength of the bonding between the wafer and the substrate" to improve the yield and reliability of the product. The Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs printed high-density and chip-scale package (chip scale package; CSP) ) Applications, ball grid array (BGA) and micron ball grid array (4-BGA) is one of the most important packaging processes. Therefore, without limiting the spirit and application of the invention Next, the following describes the implementation of the present invention by taking a ball-shaped grid-like degraded packaging structure as an example. Refer to the third figure, which is a schematic side view of an example of the packaging structure application in the present invention. The structure can include integrated circuit chip 30, flexible substrate 32, interface material 34, the paper size is applicable to Chinese national standards (CNS > A4 specification (210X29 * 7 mm), 4 325 6 4 a ________ λί B7 V. Description of the invention (Ping V * ΓΓ w.: ,,) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs and a large number of conductive bumps 36. The imaginary circuit chip 30 is a bare chip that has not been packaged. The package structure forms a connection with other external components, chips, or circuits; the flexible substrate 32 is located below the wafer 30. In this example, the flexible substrate can be a flexible circuit tape (flexib 丨 e circuit tape). In order to provide " Necessary electrical connection. The flexible circuit tape 32 contains many conductive connections. The flexible circuit tape 32 has a plurality of through holes through its surface, such as the through holes 32a and 32b shown in the figure. Generally, In other words, the through-holes can be formed at the gaps between the conductive lines without damaging the conductive lines on the original flexible circuit tape 32. In this example, the diameter of the through-holes can be about 0.02 mm to Between 1 mm, its preferred value may be about 0.1 mm. In terms of the material of the flexible circuit broadcast tape 32 in this example, these through holes can be formed by different methods such as a chemical etching method, a mechanical drilling method, or a mechanical drilling method. The interface material 34 is between the chip 30 and the flexible circuit tape 32. In this example, the interface material 34 can make the appliance flexible or a material with better cushioning properties to adapt the chip 30 and the circuit to be connected in the future. The stress problems caused by the different thermal expansion coefficients between the two boards. Generally speaking, the interface material 18 can use soft or cushioning materials. In this example, the currently commonly used elastic cushioning materials ( elastomer), the elastic buffer material is generally silicon-based (silicone-based) or resin-based material; the role of the interface material 34 'can ease the thermal stress between the chip 30 and the circuit board due to temperature changes 'Remove the defect problems caused by stress β'. In addition, the interface material 34 can also have adhesive properties or add adhesive materials to increase the chip 3 0 and the flexible circuit tape 3 2 indirectly. Use Chinese Standards (CNS) Α4 (210 × 297 mm) -η — ^ — 1 ^^^ 1 Hu I — ^ ϋ — ^ ϋ nn ml— (Please read the notes on the back before filling this page )

_______________15¾ 的可靠度。 藉由軟性電路捲帶32内貫穿孔的形成，可於封裝製 程中提供空氣排虫的通道’防止因空氣捕陷於介面材質34 中所造成的空孔問題，進一步的，由於在封裝時部分的介 面材質34可流入貫穿孔内，而與軟性電路捲帶32形成較 佺的機械***互連結，可大幅增加晶片3〇與软性電路捲帶 32兩者間接著的強度。在後續的熱回流製程中’介面材質 ?4中吸收的濕氣在受熱蒸發後’可進一步藉由貫穿孔將氣 體排除，因此可消除傳統製程中因氣體擴張對介面材質所 造成的強度破壞問題。 導電凸塊36則形成於軟性電路捲帶32之下方，並與 軟性電路捲帶32内的導電連線形成電性的連接，以提供晶 片30對外的電路連接；本例中導電凸塊36可使用最常應 用於球腳格狀陣列及微米級球腳格狀陣列中的銲錫球方式 加以形成。 除了上述所介紹的各元件之外，封裝結構並包含封裝 外较38，以用於封裝整個晶片30，形成完整的封裝結構， 如圊中所示，封裝外殼38即由底面及四周將晶片30封住。 參見第四圖所示，為本發明中之封裝結構應用於一軟 板上的另一實施例的侧視示意圖，軟性基板4<)於本例中為 —軟板材質，例如軟性的印刷電路板（flexible printed circuit)等，封裝結構同樣可包含積體電路晶片30、介面材 質44、以及多數個的導電凸塊 軟板4 0係位於晶片3 0之下方，本例争由晶片3 0至 導電凸塊36間所必需的電性連結可透過軟板40加以提供， 本紙張尺度逍用中國®家搮準（CNS ) A4規格（210X297公釐） . ; - - » I HI m I HI 1^( nn (讀先H讀背面之注意事項再填寫本頁) 經濟部智慧財產局負工消资合作社印敦 經濟部中央標準局舅工消費合作社印製 A7 'Γ4 32 5 6 4_B7 五、發明説明（） 因此軟板40内可包含許多的導電連線，軟板40並具有多 個穿過其表面之貫穿孔’如圖中所示之貫穿孔4〇3及40b， 同樣的，貫穿孔可形成於各導電線路之間的間隙處，而不 致破壞到原來軟板40上的導電線路’以本例而言，貫穿孔 之直徑可約為0.02公厘至1公厘之間’其較佳值可約為 公厘。以本例中軟板40的材質而言，這些多數個貫穿孔可 利用化學方式的蝕刻法、機械式的鑽孔法、或機械式的打 孔法等不同的方法加以形成。 介面材質44則介於晶片3 0及軟板40之間，以本例 而言，介面材質44可使用具黏著特性的材質’以作為黏 著晶片30與軟板40的接合劑’增加兩者間接合的可靠度； 此外，當介面材質 44加入或使用具彈性或是緩衝性質較 佳的材質時，亦可調適晶片30與未來接著之電路板兩者 之間因熱膨脹係數不同所產生的應力問題，而藉由介面材 質44的作用，可緩和晶片3 0與電路板間因溫度變化所產 生的熱應力，消除應力所導致的缺陷問題。 藉由軟板40内貫穿孔的形成，可於封裝製程中提供 空氣排出的通道，防止因空氣捕陷於介面材質44中所造成 的空孔問題，進一步的，由於在封裝時部分的介面材質44 可流入貫穿孔内，而與軟板 40形成較佳的機械***互連 結，可大幅增加晶片3 0與軟板4 0兩者間接著的強度。在 後續的熱回流製程中’介面材質44中吸收的濕氣在受熱蒸 發後，可進一步藉由貫穿孔將氣體排除，因此可消除傳統 製程中因氣體擴張對介面材質所造成的強度破壞問題。 導電凸塊36則形成於軟板40之下方’並與軟板40 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨0 X 297公釐} ------^---N — ------ίτ------ii (請先閲讀背面之注意事項-S寫本頁}_______________ 15¾ reliability. The formation of through-holes in the flexible circuit reel 32 can provide a passage for air worms during the packaging process to prevent the problem of voids caused by air trapped in the interface material 34. Further, due to the partial The interface material 34 can flow into the through-hole and form a relatively mechanical interaction with the flexible circuit reel 32, which can greatly increase the indirect strength of both the chip 30 and the flexible circuit reel 32. In the subsequent thermal reflow process, the moisture absorbed in the interface material 4 is heated and evaporated, and the gas can be further eliminated through the through hole, so the problem of strength damage caused by the expansion of the gas to the interface material in the traditional process can be eliminated. . The conductive bump 36 is formed below the flexible circuit reel 32 and forms an electrical connection with the conductive connection in the flexible circuit reel 32 to provide external circuit connection of the chip 30. In this example, the conductive bump 36 may It is formed using the solder ball method most commonly used in ball-foot grid arrays and micron-scale ball-foot grid arrays. In addition to the components described above, the package structure also includes a package package 38 for packaging the entire chip 30 to form a complete package structure. As shown in Figure 封装, the package shell 38 consists of the bottom surface and the periphery of the chip 30. Sealed. Refer to the fourth figure, which is a schematic side view of another embodiment of the packaging structure of the present invention applied to a flexible board. The flexible substrate 4 <) in this example is a flexible board material, such as a flexible printed circuit. The package structure can also include integrated circuit chip 30, interface material 44, and a plurality of conductive bump soft boards 40, which are located below wafer 30. In this example, wafers 30 to 30 The necessary electrical connection between the conductive bumps 36 can be provided through the flexible board 40. This paper size is in accordance with China® Furniture Standard (CNS) A4 specification (210X297 mm).;--»I HI m I HI 1 ^ (nn (read first, read the notes on the back, and then fill out this page) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumers and Consumers Cooperatives, India, and the Central Standards Bureau, Ministry of Economic Affairs, and the Consumers Cooperatives, printed A7 'Γ4 32 5 6 4_B7 V. Invention Explanation () Therefore, the flexible board 40 may include many conductive wires. The flexible board 40 has a plurality of through-holes passing through its surface. The through-holes 403 and 40b are shown in the figure. Similarly, the through-holes Can be formed at the gap between conductive lines without The conductive line damaged to the original flexible board 40 'in this example, the diameter of the through hole may be between about 0.02 mm and 1 mm', and its preferred value may be about mm. In this example, the flexible board For the material of 40, these through holes can be formed by different methods such as chemical etching, mechanical drilling, or mechanical drilling. The interface material 44 is between the wafer 30 and Between the flexible boards 40, in this example, the interface material 44 can make the material of the adhesive characteristics of the appliance 'as the bonding agent for the adhesive wafer 30 and the flexible board 40' to increase the reliability of the bonding between the two; In addition, when the interface material is 44 When adding or using a material with elasticity or better cushioning properties, the stress problems caused by the different thermal expansion coefficients between the chip 30 and the next circuit board in the future can also be adjusted. With the effect of the interface material 44, It can alleviate the thermal stress caused by the temperature change between the chip 30 and the circuit board, and eliminate the defects caused by the stress. By forming the through holes in the flexible board 40, it is possible to provide a channel for air exhaust during the packaging process to prevent Air capture It is trapped in the hole problem caused by the interface material 44. Further, since a part of the interface material 44 can flow into the through hole during packaging, and forms a better mechanical interactive connection with the soft board 40, the chip 30 can be greatly increased. Indirect strength with the soft board 40. In the subsequent thermal reflow process, the moisture absorbed in the 'interface material 44' can be eliminated by the through-holes after being heated and evaporated, so it can eliminate the cause in the traditional process. The problem of strength damage caused by gas expansion to the interface material. Conductive bumps 36 are formed below the flexible board 40 and are aligned with the flexible board 40. The paper size applies the Chinese National Standard (CNS) A4 specification (2 丨 0 X 297 mm). } ------ ^ --- N — ------ ίτ ------ ii (Please read the notes on the back-S first write this page}

_____3 2 5 6 4 五、發明説明（ 内的導電連線形成電性的連接，以提供晶片3 〇對外的電路 連接；本例中導電凸塊36同樣可使用最常應用於球腳格狀 陣列及微米級球腳格狀陣列中的銲錫球方式加以形成。 除了上述所介紹的各元件之外，封裝結構並包含封裝 外殼46，以用於封裝整個晶片3〇，形成完整的封裝結構， 如圖中所示’封裝外殼46即由上方及四周將晶月3〇封聚 於軟板42之上。 因此’藉由本發明中之封裝結構，可應用於各種使用 軟性基材的封裝製程，消除傳統結構中的空孔及濕氣蒸發 等問題，增進封裝結搆的強度及可靠度。 本發明以一較佳實施例說明如上，僅用於藉以幫助了 解本發明之實施，非用以限定本發明之精神，而熟悉此領 域技藝者於領悟本發明之精神後，在不脫離本發明之精神 範圍内，當可作些許更動潤飾及等同之變化替換，其專利 保護範圍當視後附之申請專利範圍及其等同領域而 .- I -I- ί - ii I- ^^1 I ^^1 tn I -I si f請先閲讀背面之注意事項再填窝本頁) 經濟部智慧財產局員工涓費合作社印製 1¾. -紙 本_____3 2 5 6 4 V. Description of the invention (The conductive wires inside form an electrical connection to provide the chip 3 〇 External circuit connection; in this example, the conductive bumps 36 can also be used most commonly in ball-foot grid arrays. In addition to the components described above, the package structure also includes a package shell 46 for packaging the entire wafer 30 to form a complete package structure, such as As shown in the figure, the 'encapsulation shell 46 encapsulates the crystal moon 30 on the flexible board 42 from above and around. Therefore,' the packaging structure in the present invention can be applied to various packaging processes using flexible substrates, eliminating Problems such as voids and moisture evaporation in traditional structures improve the strength and reliability of the packaging structure. The present invention is described above with a preferred embodiment, and is only used to help understand the implementation of the present invention, and is not intended to limit the present invention. After knowing the spirit of the present invention, those skilled in the art can make some modifications and equivalent changes without departing from the spirit of the present invention. The scope of protection depends on the scope of the attached patent application and its equivalent fields.-I -I- ί-ii I- ^^ 1 I ^^ 1 tn I -I si f Please read the precautions on the back before filling in the book Page) Printed by Cooperatives of Employees of Intellectual Property Bureau, Ministry of Economic Affairs 1¾.-Paper

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Claims (1)

公告衣 ΐF432564 r :、申請專範圍f%1·，、修正^一 補无| ! 申請專利範gf : •一種軟性基板封裝結構，至少包含： 一積體電路晶片； 一軟性基板位於該晶片之下方，該軟 數個導電連線，該軟性基板並具有複數個 之貫穿孔； 性基板内包含複 穿過該軟性基板 介面#質介於該晶片及該軟性基板之間；及 複數個導電凸塊於該軟性基板之下方，該複數個 凸塊並與該複數個導電連線形成電性連 料乩命从 死於-¾ ae片之 厶如申請專利範圍第丨項之軟性基板封裝結構， 含一封裝外殼以用於封裝該晶片。 :ί--衣---------訂 (請先閱讀背面之注意事項再填寫本頁) 經濟部智达財產局員工消費合作社印製 .如申請專利範圍第1項之軟性基板封裝結構，其中 上述之軟性基板至少包含一軟性電路捲帶。 4.如申請專利範圍第1項之軟性基板封裝結構，其中 上述之軟性基板至少包含一軟性印刷電路板。 5 .如申請專利範圍第1項之軟性基板封裝結構，其中 上述之複數個貫穿孔之直徑約為〇 〇2公厘至1公厘之間。 6.如申請專利範圍第1項之軟性基板封震結構，其中 本紙張尺度逋用中國國家標準（CNS ) Α4洗格（210X 297公釐） A& B8 C8 D8 广 14325 6 4 六、申請專利範園 述複數個貫穿孔係形成於複數個導電線路之間。 卜卞1如11請專利範圍$ 1項之軟性基板封裝結構，其中 擤楗fr I 個貫穿孔係利用化學蝕刻法，機械鑽孔法、及 機械打孔法其令一種方式加以形成。 8.如申請專利範圍帛！項之軟性基板封裝結構，其中 上乂之介面材質至少包含彈性緩衝材（elastomer)。 申請專利範圍帛ι項之軟性基板封裝結構其中 上述之介面材質至少包含黏著性材質。 10·:申請專利範圍$丨項之軟性基板封裝結構，其中 上述之導電凸塊至少包含銲錫球。 1】. —種軟性基板封裝結構，至少包含： 一積體電路晶片； 軟性基板位於該晶片之下方，該軟性基板至少包含 一軟性f路搂帶及-敕Μ刷電路板其t之-，該軟性基 板内包含複數個導電連$，該軟性基板並具有複數個穿過 該軟性基板之貫穿孔； 一介面材質介於該晶片及該軟性基板之間； 複數個導電凸塊於該軟性基板之下方，該複數個導電 凸塊並與該複數個導電連線形成電性連接以提供該晶片之 對外電性連接；及 12 本紙张尺度逋用中國國家梯準（CNS) Α4現格（210X2S·7公羡） . ...衣—-------ΐτ-- ί請先聞讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 A8 Bg CS D8 F4 325 6 4 申請專利範圍 一封裝外殼以用於封裝該晶片 1 2 .如申請專利範圍第1 1項之軟性基板封裝結構’ 中上述之複數個貫穿孔之直徑約為〇〇2公厘至丨 其 間》 么厘之 i3.如申請專利範圍第11項之軟性基板封裝結構’ 中上述之複數個貫穿孔係形成於複數個導電線路之間。其 1 4 .如申請專利範圍第I 1項之軟性基板封裝結構复 中上述之複數個貫f礼係利用化學蝕刻法、機械^孔法其 及機械打孔法其中一種方式加以形成。 15. 如申請專利範圍第11項之軟性基板封裝結構，其 中上述之介面材質至少包含彈性緩衝材（elast〇nier)。 16. 如申請專利範圍第11項之軟性基板封裝結構，其 中上述之介面材質至少包含黏著性材質。 - · ^^1 —^1 —^ϋ u I - 11 ί - 1 « - -i— I —I HI TW (請先閎讀背面之洼意事項再填窝本頁) 第 圍 範 利 專 請 申 如 經濟部智慧財/4局員工消費合作社印製 構 結 裝 封 板 基 性 軟 之球 項錫 1 旱 I 含 包 少 至 塊 凸 電 導 之 述 上 中 其 本紙张尺度適用中國國家揉率（CNS } A4洗格（210X297公釐）Announcement F432564 r :, application scope f% 1 ,, amendment ^ supplementary no |! Patent application gf: • a flexible substrate package structure, including at least: an integrated circuit chip; a flexible substrate is located on the chip Underneath, the soft conductive wires have a plurality of through holes; the flexible substrate includes a plurality of through-holes of the flexible substrate interface #quality between the wafer and the flexible substrate; and a plurality of conductive protrusions Block is located under the flexible substrate, the plurality of bumps and the plurality of conductive lines form an electrically conductive material, and die from -¾ ae sheet, such as the flexible substrate package structure in the scope of the patent application, A package housing is included for packaging the chip. : ί--clothing -------- Order (please read the precautions on the back before filling out this page) Printed by the Consumer Cooperative of the Zhida Property Bureau of the Ministry of Economic Affairs, such as the application of the flexible substrate in the first scope of the patent The package structure, wherein the flexible substrate includes at least one flexible circuit tape. 4. The flexible substrate package structure according to item 1 of the scope of patent application, wherein the above flexible substrate includes at least one flexible printed circuit board. 5. The flexible substrate packaging structure according to item 1 of the scope of patent application, wherein the diameter of the plurality of through holes is about 0.02 mm to 1 mm. 6. As for the soft substrate seismic isolation structure in the scope of application for patent No. 1, in which the paper size adopts Chinese National Standard (CNS) A4 Washing (210X 297 mm) A & B8 C8 D8 Guang 14325 6 4 Fan Yuanshu formed a plurality of through-holes between a plurality of conductive lines. [1] The flexible substrate package structure with a patent scope of $ 1 as claimed in item 11, where 擤 楗 fr I through-holes are formed by a chemical etching method, a mechanical drilling method, and a mechanical drilling method. 8. If the scope of patent application is 帛! The soft substrate packaging structure of the item, wherein the interface material of the upper part includes at least an elastic buffer (elastomer). The flexible substrate package structure of the scope of the patent application, wherein the interface material mentioned above includes at least an adhesive material. 10 ·: A flexible substrate package structure with a patent application scope of $ 丨, wherein the above-mentioned conductive bumps include at least solder balls. 1].-A flexible substrate package structure, including at least: an integrated circuit wafer; a flexible substrate is located below the wafer, and the flexible substrate includes at least a flexible f circuit tape and-敕 M brush circuit board- The flexible substrate includes a plurality of conductive links, and the flexible substrate has a plurality of through holes passing through the flexible substrate; an interface material is interposed between the wafer and the flexible substrate; a plurality of conductive bumps are on the flexible substrate Below, the plurality of conductive bumps form an electrical connection with the plurality of conductive connections to provide external electrical connection of the chip; and 12 paper sizes use China National Standard (CNS) A4 (210X2S) · 7 public envy). ... clothing -------- ΐτ-- ί Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A8 Bg CS D8 F4 325 6 4 The scope of patent application is a package shell for packaging the chip 12. For example, the above-mentioned plurality of through holes in the flexible substrate package structure in the scope of patent application No. 11 is about 0.02 mm to 丨In between? The I3. The patentable scope of application of the flexible substrate package structure as item 11 'in the above-mentioned plurality of through holes are formed between the conductive lines in a plurality of lines. 14. As described in the flexible substrate package structure item No. 1 of the scope of the application for patent, the above-mentioned plural processes are formed by one of the chemical etching method, the mechanical hole method, and the mechanical hole method. 15. For a flexible substrate package structure with the scope of patent application No. 11, wherein the interface material mentioned above includes at least an elastic cushioning material (elastonier). 16. If the flexible substrate package structure of item 11 of the patent application scope, wherein the interface material mentioned above includes at least an adhesive material. -· ^^ 1 — ^ 1 — ^ ϋ u I-11 ί-1 «--i— I —I HI TW (please read the meanings on the back before filling in this page) Shenruo Ministry of Economic Affairs, Wisdom Finance / 4 Bureau employee consumer cooperatives printed structured sealing boards based on soft ball spheres tin 1 dry I Containing as little as a block of convex conductance As mentioned above, the paper size is applicable to the Chinese national rubbing rate ( CNS} A4 wash case (210X297 mm)
TW87120701A 1998-12-14 1998-12-14 Package structure of flexible substrate TW432564B (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI396265B (en) * 2009-07-21 2013-05-11 Powertech Technology Inc Chip package structure and its method
US9215804B2 (en) 2012-11-21 2015-12-15 Hannstar Display Corporation Circuit stack structure

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI396265B (en) * 2009-07-21 2013-05-11 Powertech Technology Inc Chip package structure and its method
US9215804B2 (en) 2012-11-21 2015-12-15 Hannstar Display Corporation Circuit stack structure

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