TW432334B - Virtual computer certification platform - Google Patents
Virtual computer certification platform Download PDFInfo
- Publication number
- TW432334B TW432334B TW88104749A TW88104749A TW432334B TW 432334 B TW432334 B TW 432334B TW 88104749 A TW88104749 A TW 88104749A TW 88104749 A TW88104749 A TW 88104749A TW 432334 B TW432334 B TW 432334B
- Authority
- TW
- Taiwan
- Prior art keywords
- simulation
- microprocessor
- virtual computer
- chip
- peripheral
- Prior art date
Links
Landscapes
- Debugging And Monitoring (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
Description
432334 五、發明說明(1) — 本案為一種虛擬驗證平臺’尤指虛擬電腦驗證平臺。 針對虛擬電腦驗證工作平臺相關之技術研發,在我們 提出此模擬架構之前,有韓國自行開發使用於驗證lntel 80486相谷微處理機的虛擬電腦平臺。該平臺採用的概 念及技術在於Instruction-Based的模擬方式,以單一指 令週期完成時間來模擬及計算週邊裝置該完成之工作事 件。此模擬方式的優點在於快速執行模擬微處理機指令 行為。而其缺點則是:(一)缺乏微處理機與週邊協定 訊號正確性的驗證;(二)架構於其平臺上的微處理機設計 需為以類似C程式語言實作的行為模式設計(Behavi〇r Model ),其與實際微理機晶片電路相去甚遠;(三)因架 構上採用指令週期模擬方式,故而無法提供微處理機在暫 存器轉換描述層次(RTL Lev e 1),及閘級電路描述層次 (Gate Level)上的驗證功能;(四)其下層架構不是以單一 元件功能模擬,造成擴充系統整體週邊裝置或更改週邊以 配合不同微處理機驗證的困難;(五)無法提供週邊裝置 訊號反應及狀態,以提供對微處理機晶片電路的偵錯能 力。 本發明目的係實現一個軟體虛擬電腦驗證平臺,以輔 助微處理機的設計、系統軟體及低階控制韌體的提早開 發、或電腦週邊晶片的開發。 本發明係首先成功地應用於驗證英特爾(Intel) x86 相容的微處理機微架構及其後續發展,對於其它微處理機 的開發也具有相同的重要輔助。432334 V. Description of the invention (1) — This case is a virtual verification platform ', especially a virtual computer verification platform. For the research and development of technology related to the verification platform of virtual computer, before we proposed this simulation architecture, there was a virtual computer platform developed by South Korea to verify the Intel 80486 Aitani microprocessor. The concept and technology used in this platform lies in the Instruction-Based simulation method, which uses a single instruction cycle completion time to simulate and calculate the work events that peripheral devices should complete. The advantage of this simulation method is that the execution of simulated microprocessor instruction behavior is fast. The disadvantages are: (1) lack of verification of the correctness of the signals between the microprocessor and the surrounding protocols; (2) the microprocessor design on the platform needs to be designed in a behavioral model implemented in a similar C programming language (Behavi 〇r Model), which is far from the actual microcomputer chip circuit; (3) because the instruction cycle simulation method is used in the architecture, it is impossible to provide the microprocessor description description level (RTL Lev e 1), and the gate Level circuit description level (Gate Level) verification function; (4) its underlying architecture is not simulated with a single component function, causing difficulties in expanding the overall peripheral device of the system or changing the periphery to match the verification of different microprocessors; (5) unable to provide Peripheral device signal response and status to provide debugging capabilities for microprocessor chip circuits. The purpose of the present invention is to implement a software virtual computer verification platform to assist the design of microprocessors, the early development of system software and low-level control firmware, or the development of computer peripheral chips. The invention was first successfully applied to verify the Intel x86 compatible microprocessor microarchitecture and its subsequent development, and it also has the same important assistance for the development of other microprocessors.
五、發明說明(2) 、ril〇g硬體摇述語言完成之微處理機此工 新系統開發/移植,職S等低階動體開發的 入式系統開發更:S系統開發週期的提前’ &點對於嵌 此驗證平臺亦可提供驗證新開發電腦週邊晶片 的有效換擬驗證環境。 為達上述目的,本案提出之虛擬電腦驗證平臺係包 含: ,一虛擬電腦模擬系統,其係用於模擬一電腦主機板及 週邊裝置的一功能、一界面協定與一時序,以提供: (一)一微處理機晶片設計於一行為模式(Behavi〇r Mode) 暫存器轉換描述模式(RTL Mode)及一閘級模式 (Gate Mode)等三種層次上的整合驗證與除錯,(二)—系 統軟體及一韌體的開發、除錯與驗證環境,(三)一電腦週 邊晶片的模擬與驗證環境以及 一組線上除錯辅助工具,係電連接至該虛擬電腦模擬 系統,用以於該微處理機模擬時,利用即時修改該週邊裝 置内容來輔助該微處理機除錯。 如所述之微處理機設計的驗證平臺,其中該虛擬電腦 模擬系統係可包含: 一整合微處理機晶片與虛擬電腦模擬系統的特殊函數 ,該特殊函數提供一個一般化的通用界面,以便使得以一 Veri log程式實作的該微處理機晶片設計可輕易地將該微 處理機界面訊號透過UNIX的一行程間通信(inter_pr〇cessV. Description of the invention (2) The development and transplantation of the new system of the microprocessor completed by the ri0g hardware description language. The development of the in-line system of the low-level moving body development such as the S system is more advanced: the advancement of the S system development cycle. '& Point can also provide an effective replacement verification environment for verifying newly developed computer peripheral chips embedded in this verification platform. In order to achieve the above purpose, the virtual computer verification platform proposed in this case includes: a virtual computer simulation system which is used to simulate a function, interface agreement and a timing of a computer motherboard and peripheral devices to provide: (a ) A microprocessor chip is designed for integration verification and debugging at three levels: a Behavior Mode register description mode (RTL Mode) and a gate mode (Gate Mode). (2) — System software and a firmware development, debugging and verification environment, (c) a computer peripheral chip simulation and verification environment and a set of online debugging assistance tools, which are electrically connected to the virtual computer simulation system for During the microprocessor simulation, the peripheral device content is modified in real time to assist the microprocessor in debugging. As described in the microprocessor design verification platform, the virtual computer simulation system may include: a special function that integrates a microprocessor chip and a virtual computer simulation system, and the special function provides a generalized general interface so that The microprocessor chip design implemented by a Veri log program can easily communicate the microprocessor interface signals through UNIX's inter-stroke communication (inter_pr〇cess
^1323 3 ^______ 五、發明說明(3)^ 1323 3 ^ ______ V. Description of the invention (3)
Communicat i on)機制,傳給在另—個行程上執行的虛擬電 腦周邊晶片模擬系統; 一内嵌入微處理機晶片的共用時序電路,該電路負責 產生該虛擬電腦模擬系統及該微處理機晶片之間的同步時 序,並收集該微處理機每個時序週期產生的界面訊號後 於每個同步時序週期的正緣及負緣,以該特殊函數傳送至 該微處理機晶片外部的該虛擬電腦模擬系統,並等待妹 '果 以達同步及資料傳送的雙重目地; ° ’ 一整合每個獨立模擬週邊晶片元件的週邊晶片模擬子 系統,此週邊晶片模擬子系統以物件導向規劃方式整合各 模擬晶片元件以提供該虛擬電腦模擬系統的週邊控制晶片 組功能、界面協定及時序; —整合每個獨立模擬週邊裝置元件的週邊裝置模擬子 系統,此週邊裝置模擬子系統以物件導向規劃方式整合各 模擬裝置元件以提供該虛擬電腦模擬系統的週邊裝置功 能;以及 一匯流排命令解譯器,此匯流排命令解譯器負責解譯 來自於該微處理機晶片的協定訊號命令,並依其要求轉送 命令要求至該週邊晶片模擬子系統。 如所述之微處理機設計的驗證平臺,其中該特殊函數 係為vpm_call()。 如所述之微處理機設計的驗證平臺,其中該線上除錯 輔助工具可包含: a 一視窗操作界面,此視窗操作界面以C + +程式配合—Communicat i on) mechanism, which is passed to the virtual computer peripheral chip simulation system executed on another trip; a shared sequential circuit embedded with a microprocessor chip, which is responsible for generating the virtual computer simulation system and the microprocessor chip Synchronize the timing between them, and collect the interface signals generated by each timing cycle of the microprocessor, and then send the positive and negative edges of each synchronization timing cycle to the virtual computer outside the microprocessor chip by using the special function. Simulate the system and wait for the dual purpose of synchronization and data transmission; ° 'A peripheral chip simulation subsystem that integrates each independent analog peripheral chip component. This peripheral chip simulation subsystem integrates each simulation in an object-oriented planning manner. Chip components to provide the peripheral control chipset functions, interface protocols and timing of the virtual computer simulation system;-integrate the peripheral device simulation subsystem of each independent simulation peripheral device component, this peripheral device simulation subsystem integrates each with an object-oriented planning Simulating device components to provide peripheral equipment of the virtual computer simulation system Function; and a bus command interpreter, the command interpreter is responsible for this bus interpret the command signal from the microprocessor chip agreements and requirements according to their transfer to the periphery of the wafer command requires analog subsystem. The verification platform of the microprocessor design as described, wherein the special function is vpm_call (). As mentioned in the verification platform of microprocessor design, the online debugging aids may include: a window operation interface, this window operation interface is matched with C ++ program—
第7頁 43 23 3 4 五、發明說明⑷ " X-ffindows 、一 Motif程式庫、一 Unix標準系統服務程式 庫以及部份Per】程式語言、__Tci/Tk所實作而成,負責 該虛擬電腦驗證平臺整體的一顯示與一輸出入操作界面; 一顯不及線上即時修改記憶體内容的編輯器,用以隨 時於該微處理機晶片模擬時期即時修改; 一顯示及線上即時修改硬碟内容的編輯器,用以隨時 於該微處理機晶片模擬時期即時修改一硬碟模擬元件内容 的工具; 一組硬碟低階當理工具,此硬碟低階管理工具有讀出 一虛擬硬碟硬體參數表、低階格式化硬碟的功能; 一組MS-DOS 5_0相容的檔案系統管理工具此MS d〇s 5 · 0相容的擋案系統管理工具可用於在沒有作業系統執行 於本虛擬電腦模擬系統及微處理機晶片之上時,對該虛擬 電腦模擬系統的硬碟作規劃(par t i t i on & Labe 1 i ng)、 MS-DOS檔案格式化(Formatting)、檔案拷貝、樓案刪 除、目錄建立、目錄刪除等檔案系統操作,此功能有助於 該虛擬電腦模擬系統的作業系統裝置(Installati〇n) ·以 及 , BIOS a日片寫入工具,此Bi〇s晶片寫入工具用以將一 新的BIOS程式的ROM映像檔(ROM Image File)寫入虛擬電 腦模擬系統的模擬晶片中,以使該新的B I 〇 §執^於該虛擬 電腦模擬系統及該微處理機晶片之上。 如所述之軟體虛擬電腦驗證平臺,其中該虛擬電腦模 擬系統及該微處理機,在應用上,可用來作為一系統軟體Page 7 43 23 3 4 V. Description of the invention quot " X-ffindows, a Motif library, a Unix standard system service library and some Per] programming language, __Tci / Tk implementation, responsible for the virtual A display and an input / output operation interface of the computer verification platform as a whole; an editor that can not modify the memory content online in real time for real-time modification during the simulation period of the microprocessor chip; a display and online modification of the hard disk content in real time Editor for real-time modification of the contents of a hard disk simulation component at any time during the simulation period of the microprocessor chip; a set of low-level management tools for the hard disk, this low-level management tool for reading a virtual hard disk Hardware parameter table, low-level formatted hard disk function; a set of MS-DOS 5_0 compatible file system management tools This MS dos 5 · 0 compatible file system management tool can be used to run without an operating system On the virtual computer simulation system and the microprocessor chip, plan the hard disk of the virtual computer simulation system (par titi on & Labe 1 i ng), format the MS-DOS file (Format ting), file copying, file deletion, directory creation, directory deletion and other file system operations. This function helps the operating system device (Installati〇n) of the virtual computer simulation system, and the BIOS a Japanese film writing tool, This Bi0s chip writing tool is used to write a new BIOS image ROM image file into the simulation chip of the virtual computer simulation system, so that the new BI 〇§ will be executed on the virtual computer Simulation system and the microprocessor chip. The software virtual computer verification platform as described above, wherein the virtual computer simulation system and the microprocessor can be used as a system software in application
432334 五、發明說明(5) (包括作業系統,及B I os等)的開發及除錯之工具。 如所述之軟體虛擬電腦驗證平臺,其中該虛擬電腦模 擬系統係結合C ++所完成者。 如所述之軟體虛擬電腦驗證平臺,其中該微處理機係 以Ver i 1 〇g所完成者。 如所述之軟體虛擬電腦驗證平臺,其中該虛擬電腦模 擬系統及該微處理機,在應用上,來作為該電腦系統中, 新開發的電腦週邊晶片的驗證環境。 如所述之軟體虚擬電腦驗證平臺,其中該電腦為一個 人電腦。 本案得藉由下列圖式及詳細說明,俾得一更深入之了 解: 圖(一):本案虛擬電腦驗證平臺之觀念性邏輯方塊 圖。 圖(二):本案虛擬電腦驗證平臺之邏輯方塊圖。 圖(三):本案虛擬電腦驗證平臺。 圖(四).本案虛擬電腦驗證平臺之虛擬硬碟模擬元 件。 、 圖(五)··本案虛擬電腦驗證平臺之虛擬硬碟模擬元 件。 、 圖(六):虛擬電腦驗證平臺之虛擬記憶體模擬元件。 圖(七):虛擬電腦與Verilog模擬器的溝通界面動 圓(八):VP Μ一 CALL工作流程圖432334 Fifth, the invention description (5) (including operating systems, and B I os, etc.) development and debugging tools. The software virtual computer verification platform as described, wherein the virtual computer simulation system is completed in conjunction with C ++. The software virtual computer verification platform as described above, wherein the microprocessor is completed with Veri 10g. As described in the software virtual computer verification platform, the virtual computer simulation system and the microprocessor are applied as a verification environment for newly developed computer peripheral chips in the computer system. The software virtual computer verification platform as described, wherein the computer is a personal computer. This case can be understood in more depth through the following diagrams and detailed descriptions: Figure (1): Conceptual logical block diagram of the virtual computer verification platform in this case. Figure (II): The logical block diagram of the virtual computer verification platform in this case. Figure (C): The virtual computer verification platform in this case. Figure (IV). Virtual hard disk simulation components of the virtual computer verification platform in this case. Figure (5) · The virtual hard disk simulation component of the virtual computer verification platform in this case. Figure (6): Virtual memory simulation components of the virtual computer verification platform. Figure (7): The communication interface between the virtual computer and the Verilog simulator.
第9頁 432334Page 9 432334
圖式主要圖號如 1 1 :虛擬调遠Hi I WL %遭裝置 12 模擬主機板 13 作業系統 14 工作站 15 1 r-T 貫體硬碟元件 16 實體監視器 1 7 鍵盤週邊元件 21 匯流排解譯器 設計模ί Ϊ :鵰驗各證平件臺單:整體系統規劃係採用物件導向 該實體元件之功能;;:=一程式物件實作,以模擬 正確週邊功能^的界驗^號命Λ及狀/,以期提供 =各元件採用物件模擬方式設計,以便使程式界貝面 月 ’易於修改、維護及抽換各程式物件以配合模擬 環境需求之變更。 ' 系統運作之觀念如圖(一)所示:在此觀念圖中,主要包 含虛擬週邊裝置11、模擬主機板12、Sun s〇laris作業系 統13、Sun工作站硬體丨4、實體硬碟元件15、實體監視器 16及鍵盤週邊元件17等’其呈現出本虛擬電腦驗證平臺的 模擬系統工作的大致概觀。 圖中最右邊的方塊所表示的是微處理機121,該微處 理機121為以Verilog硬體描述語言完成的行為模式微處理 機(Behavior Model),或暫存器狀態轉換描述模式微處 理機(RTL Model),或閘級描述模式微處理機(Gate Level Model)。The main drawing numbers in the diagram are as follows: 1 1: Virtual remote control Hi I WL% device 12 analog motherboard 13 operating system 14 workstation 15 1 rT hard drive component 16 physical monitor 1 7 keyboard peripheral components 21 bus interpreter Design model Ϊ Ϊ: Carry out inspection of each piece of flat table: The overall system planning system uses objects to guide the function of the physical component;; == a program object implementation to simulate the correct peripheral function ^ boundary check ^ number of orders Λ and State /, with a view to provide = each component is designed with object simulation, so that the programming community can easily modify, maintain and exchange various program objects to meet the needs of the simulation environment. '' The concept of system operation is shown in Figure (1): In this concept map, it mainly includes virtual peripherals 11, analog motherboard 12, Sun Solaris operating system 13, Sun workstation hardware 丨 4, physical hard disk components 15. Physical monitor 16 and keyboard peripheral elements 17 and the like, which present a rough overview of the operation of the simulation system of the virtual computer verification platform. The rightmost box in the figure represents a microprocessor 121. The microprocessor 121 is a behavior model microprocessor (Behavior Model) or a register state transition description model microprocessor completed in Verilog hardware description language. (RTL Model), or Gate Level Model microprocessor.
第10頁 4 3 23 3 4 五、發明說明(7) 中間擴圓㊉區塊表示本模H统# €邊控制晶片組及 匯流排界面1 22 ’其包含個人電腦晶片組1221、記憶體控 制器1 2 22及中斷/資料處理器1 223。此區塊122内部各元工件 為以C + +實作之模擬元件所組成。 區塊122、1 21之間的訊息溝通是以ϋΝΙχ提供之 Message Passing (UNIX ipC 的—種)機制及 CadencePage 10 4 3 23 3 4 V. Description of the invention (7) The middle expansion circle indicates that the module H system # € edge control chipset and bus interface 1 22 'It contains a personal computer chipset 1221, memory control Processor 1 2 22 and interrupt / data processor 1 223. Each component in this block 122 is composed of analog components implemented in C ++. The message communication between blocks 122 and 1 21 is based on the Message Passing (UNIX ipC) mechanism and Cadence provided by ϋΝχ
Veri log提供之PLI界面完成。這兩部份亦即構成本模擬 系統的個人電腦主機板模擬部份。 圖中最左邊的方塊表示本驗證平臺中模擬系統的虛擬 週邊裝置11,其包含VPC週邊ill、R0M元件112及虛擬元件 驅動器113。此虛擬裝置π模擬實體裝置所擁有的可能功 能動作與狀態,並適時以UNIX系統服務呼叫(System Service Call)去驅動適當的實體裝置(如從實體鍵盤取得 鍵盤掃描碼等),及接收模擬不同步,不定時交談式裝置的 資訊。此區塊1 1與中間的個人電腦晶片組1 2 2 1區塊之間 的Λ息交換乃是採用UNIX系統的Message Passing機制完 成。 圖(二)所示為本虛擬電腦驗證平臺中模擬系統的元件 邏輯方塊。圖中匯流排(BUS)解譯器21為銜接微處理機121 與模擬主機板1 2的主要元件,此元件是由兩個匯流排界面 元件、纟η 〇而成,此兩部伤元件分別是:(一)由V e r i ]_ 〇 g 硬體描述語言實作的匯流排界面訊號前端轉換模組;(二) 由C + +程式語言實作的匯流排界面訊號後 端解譯模組。匯流排界面的種類可依微處理機的不同而改The PLI interface provided by Veri log is completed. These two parts also constitute the simulation part of the personal computer motherboard of this simulation system. The leftmost box in the figure represents the virtual peripheral device 11 of the simulation system in the verification platform, which includes the VPC peripheral ill, the ROM component 112, and the virtual component driver 113. This virtual device π simulates the possible functional actions and states possessed by a physical device, and timely drives the appropriate physical device (such as obtaining a keyboard scan code from a physical keyboard) with a UNIX System Service Call, and receives simulated simulations. Synchronized, occasional chat device information. The exchange of Λ information between this block 11 and the middle personal computer chipset block 221 is completed using the Message Passing mechanism of the UNIX system. Figure (2) shows the logic blocks of the simulation system in the virtual computer verification platform. In the figure, the bus interpreter 21 is the main component connecting the microprocessor 121 and the analog motherboard 12. This component is composed of two bus interface components, 纟 η 〇, and the two damaged components are respectively Yes: (1) Bus interface signal front-end conversion module implemented by Veri] _〇g hardware description language; (II) Bus interface signal back-end interpretation module implemented by C ++ programming language . The type of bus interface can be changed depending on the microprocessor
第11頁 4 3 2 - 五、發明說明(8) 變。目前本驗證平臺只有Socket 7供選擇,將來可以包 含更多的種類的匯流排界面元件。 本發明之虛擬電腦驗證平臺採用以時序為基準的 (Clock-Based)的模擬方式,此方式的實作方法在如下所 述。模擬系統與微處理機晶片電路需擁有共同的參考時 序。此時序的產生方式有兩種方式,一是由本虛擬電腦的 模擬系統從外部透過我們自己開發的特硃函數vpm_caU() 主動提供給微處理機作為參考時序。一是由微處理機内 部延伸的時序產生器產生同步時序,並藉由我們的 vpm一ca 1 1 ()函數通知外部模擬系統而達到同步模擬的功 能。 、 在本虛擬電腦驗證平臺的模擬系統中,採用了後者的 模擬方式,由微處理機延伸的同步時序電路(此電路為模擬 系統的Socket-7匯流排界面元件)於每同步時序週期的正 緣,負緣時期固定送出模擬f料及同步訊息給虛擬 微處理機模擬系統。任何由外部觸發的訊息資料包括、 ,式輸出入(如鍵盤輸入),元件觸發事件(如硬碟 號’及/統管理中斷S M1)之訊息資料都將由模擬元;以; =收集後於每個同步週期的正緣及負緣時期傳送至τ微 各元件 定為原則, 之實作以模擬其實體晶片動作 以C + +程式語言實現其物件,透 、命令及界面協 過本虛擬電腦平Page 11 4 3 2-V. Description of Invention (8). At present, this verification platform only has Socket 7 for selection. In the future, it can include more types of bus interface components. The virtual computer verification platform of the present invention adopts a clock-based simulation method. The implementation method of this method is described below. The analog system and the microprocessor chip circuit need to have a common reference timing. There are two ways to generate this timing. The first is that the simulation system of this virtual computer provides the microprocessor with the special timing function vpm_caU () developed by us as a reference timing. The first is to generate synchronous timing by the timing generator extended inside the microprocessor, and to notify the external simulation system through our vpm-ca 1 1 () function to achieve the function of synchronous simulation. In the simulation system of the virtual computer verification platform, the latter simulation method is adopted. The synchronous timing circuit (the circuit is the Socket-7 bus interface element of the simulation system) extended by the microprocessor is positive at each synchronous timing cycle. In the negative and positive margin periods, the simulation data and synchronization messages are sent to the virtual microprocessor simulation system. Any externally-triggered message data, including,, input and output (such as keyboard input), component-triggered events (such as hard disk number 'and / system management interrupt S M1) will be simulated by the analog element; The principle of transmitting positive and negative edges to each component of the τ micro-period in each synchronization cycle is set as a principle. The implementation is to simulate its physical chip movement and implement its objects in the C ++ programming language. level
43 23 ^ 4 五、發明說明(9) 臺制定之子系統訊息溝通界面與整個模擬系統整合。 元件具有其偵錯及訊息資料收集顯示修改之功& 對於微處理機晶片電路本身及界面協定之驗證與 了相當豐富的資訊,並且線上修改單一週邊元件資= 的功能對於微處理機晶片電路除錯能力有相當好的效 以記憶體元件的例子來說,當我們在須錯微處理機的 執行模式轉換時(在Intel x86相容微處理機中 真實模式至保護模式的能力),我們可以輕易的從存有於^己 憶體元件中的系統表格中觀察轉換模式之間,表格的 是否正常。若有問題,我們可嘗試暫時性於線上執行時 期,更改其系統表格記錄以助微處理機先行往前執行 否尚有其它錯誤存在,而使微處理機的偵錯時間盡可能疋地 鈿短。這些偵錯能力更是有助於作業系統及β丨〇s等低階軟 體開發領域。 _ 在開發這些系統軟體上,我們不只能在微處理機實體 晶片尚未製成前,即可著手系統軟體的開發、移植與 提供系統軟體開發上豐富的系統偵錯訊息。如此應用虛擬 電腦驗證平臺來開發系統軟體的觀念,是具有其獨創性。 本虛擬電腦驗證平臺具有四個主要的模擬技術,分別 是基準時序的模擬方式 '獨立晶片元件行為模擬的物件導 向模擬設計方式、結合C + +程式元件與Verilog程式元件的 :般化溝通界面函數:Vpni_call◦、以及微處理機模擬設 计。此四個主要模擬技術使得週邊晶片的設計者可任意選 擇以C + + /C或Ver i 1 og等高階程式語言來實現他們新設計的43 23 ^ 4 V. Description of the invention (9) The subsystem communication interface developed by the platform is integrated with the entire simulation system. The component has the function of debugging and information data collection and display & verification of the microprocessor chip circuit itself and the interface agreement with a wealth of information, and the function of online modification of a single peripheral component asset = for the microprocessor chip circuit Debugging capabilities have a pretty good effect. Take the example of memory components. When we switch the execution mode of the error-prone microprocessor (the ability of real mode to protected mode in Intel x86 compatible microprocessors), we You can easily observe whether the form is normal between the conversion patterns from the system forms stored in the 己 memory body element. If there is a problem, we can try to temporarily change the system form record during the online execution period to help the microprocessor execute ahead. If there are other errors, the debug time of the microprocessor is as short as possible. . These debugging capabilities are especially helpful for the development of low-level software such as operating systems and β 丨 0s. _ In developing these system software, we can not only start system software development, transplantation, and provide rich system debugging information in system software development before the microprocessor physical chip is not yet completed. The concept of applying a virtual computer verification platform to develop system software is unique. The virtual computer verification platform has four main simulation technologies, namely the reference timing simulation method, the object-oriented simulation design method of independent chip component behavior simulation, and the combination of C ++ program components and Verilog program components: generalized communication interface functions : Vpni_call◦, and microprocessor simulation design. These four main analog technologies allow designers of peripheral chips to choose any high-level programming language such as C ++ / C or Veri og to implement their new
第13頁 4 3 23 ?"Page 13 4 3 23? &Quot;
五、發明說明(ίο) 並整合進我們的虛擬電腦驗證平臺,以驗 晶片電路模擬, 證其新設計是否能正確的控制週邊及與微處理機等正培地 合作。 此虛擬電腦驗證平臺採用X-Windows操作界面,以 Mot if視窗元件架構出具立體感,易操作的視窗界面。其應 用於一微處理機設計驗證的操作界面外觀如圖(三)所示二 圖中左上方的Power按鈕,主要作用在於啟動與關閉微處理 機模擬系統,平常時按下Power按紐將會產生新的工作行 程(process)以啟動 Cadence Verilog Simulator 去編擇及 執行微處理機的RTL Code (或Behavior Code,或 Gate-Level Code),並同時間啟動虛擬電腦驗證平臺令模 擬系統的各元件模擬^ 、 若在執行微處理機行為模擬中,按下power按赵將關閉 微處理機的模擬動作及模擬系統中各元件的模擬動作。圖 中最右上角的Re set按鈕之作用相當於實體個人電腦主機 的RESET鍵功能。按下Reset按鈕將造成虛擬電腦送出 Reset況號給微處理機及虛擬電腦之模擬系統,以通知各 模擬元件,要求各相關模擬元件處理相對應的RE SET動作。 在圖(二)右邊所排列的按知用於控制模擬中微處理機 系統的模擬行為。如在圖(三)右邊所示的Sin按鈕,可模擬 主機系統的SMI外部中斷,強迫微處理機進入系統管理模 在圖(三)右邊所示的Tools按鈕更可叫出許多有用的Fifth, the invention description (ίο) and integrated into our virtual computer verification platform to verify the chip circuit simulation, to verify whether the new design can correctly control the surroundings and cooperate with microprocessors and other fields. This virtual computer verification platform uses X-Windows operation interface, and uses Mot if window component architecture to produce a three-dimensional, easy-to-operate window interface. The appearance of the operation interface applied to a microprocessor design verification is shown in Figure (3). The Power button in the upper left of the two figures is mainly used to start and close the microprocessor simulation system. Pressing the Power button normally will Generate a new process to start Cadence Verilog Simulator to program and execute the RTL Code (or Behavior Code, or Gate-Level Code) of the microprocessor, and start the virtual computer verification platform at the same time to simulate the components of the system Simulation ^, If you are performing a microprocessor behavior simulation, press the power button to turn off the simulation of the microprocessor and the simulation of each component in the simulation system. The function of the reset button in the upper right corner of the figure is equivalent to the function of the RESET key of a physical personal computer host. Pressing the Reset button will cause the virtual computer to send a reset status to the microprocessor and the simulation system of the virtual computer to notify each analog component and request each relevant analog component to handle the corresponding RE SET action. The knowledge arranged on the right side of figure (II) is used to control the simulation behavior of the microprocessor system in the simulation. The Sin button shown on the right side of the figure (3) can simulate the external interruption of the SMI of the host system, forcing the microprocessor to enter the system management mode. The Tools button shown on the right side of the figure (3) can also call many useful
第14頁 432334 五、發明說明(π) 辅助工具,如虛擬硬碟的低階格式化(Format),MS-DOS相 容的FAT擋案系統 partition,Labeling, Format,及 BIOS安裝等等輔助工具。 ^ 雖然本虛擬電腦驗證平臺是於Sun電腦工作站上的 Solaris作業系統及χ-Windows的環境下發展出來,但由於 各元件界面清楚,且未用到太多系統相關的特殊系統服務 呼叫,故易於將本虛擬電腦驗證平臺原始碼移植至其它作 業系統及硬體上。並且各部份所使用到的UNIX Message Passing之IPC機制可輕易轉成Socket界面的網路協定, 而使虛擬電腦驗證平臺不再是需與Cadence veril()g Simulator同在一臺電腦上執行,而可以透過網路來共同 完成工作。 、 因此本案之技術特徵在於:一、具採用物件導向設計 模式規劃本模擬系統·,二、基準時序的模擬方式 (Clock-Based );三、實際模擬各別週邊裝置及晶片動 作;四、新週邊晶片的驗證環境;五、X_Wind〇ws操作界 面;以及六、高移植性。 本案之實作如下: (1) 一般化的C + + /C程式模擬元件與Verilog程式模擬 元件的溝通函數Vpm_ca〖l() vpm_call()函數本身以C高階程式語言實作而成D 此函數利用。3(^1^6提供的\^1^1(^?1^(?1'叫1^11111111^Page 14 432334 V. Description of the invention (π) Auxiliary tools, such as low-level format of the virtual hard disk (Format), MS-DOS compatible FAT file system partition, Labeling, Format, and BIOS installation and other auxiliary tools . ^ Although this virtual computer verification platform was developed under the Solaris operating system and χ-Windows environment on Sun computer workstations, it is easy because the components have clear interfaces and do not use too many special system service calls related to the system. Transplant the source code of this virtual computer verification platform to other operating systems and hardware. And the IPC mechanism of UNIX Message Passing used by each part can be easily converted into the network protocol of the Socket interface, so that the virtual computer verification platform no longer needs to be executed on the same computer as Cadence veril () g Simulator. And they can work together through the Internet. Therefore, the technical features of this case are: 1. The simulation system is planned with an object-oriented design pattern. 2. The simulation method of reference timing (Clock-Based). 3. The actual simulation of each peripheral device and chip action. 4. The new Verification environment for peripheral chips; five, X_Windows operation interface; and six, high portability. The implementation of this case is as follows: (1) The communication function between the general C ++ / C program simulation component and the Verilog program simulation component Vpm_ca 〖l () vpm_call () The function itself is implemented in the high-level C programming language D This function use. \ ^ 1 ^ 1 (^? 1 ^ (? 1 'called 1 ^ 11111111 ^
Language interface)界面標準函數與Vern〇g Simulator 合作將Veri log型式的參數萃取出來,並轉化成c的參數型Language interface) interface standard function cooperates with Vernog Simulator to extract the parameters of Veri log type and convert them into parametric type of c
第15頁 432334 五、發明說明(12) 式,然後加以格式化處理以轉成二元化標準字串,之後再 利用UNIX作業系統所提供的訊息傳遞(Message passing) 之系統服務呼叫功能,以等待式(B1 o c k i n g)方式傳給執行 中的C + +個人電腦模擬系統,並等待個人電腦模擬系統的 回覆訊息。 當個人電腦模擬系統回覆此次溝通訊息的結果時, vpm_cal 1 ()函數尚需將結果處理轉化成Verilog型式的參 數,再將結果回傳至Verilog的Simulator。如圖(七)所 示,最左邊的橢圓型區塊表示虛擬電腦模擬系統之裝置模 擬子系統的執行工作,中間的橢圓型區塊表示Veri log模 擬器的晶片模擬子系統執行工作,最上方的方塊表示將被 Verilog模擬器讀入、解譯、執行的微處理機程式碼。 在虛擬電腦系統執行時,V e r i 1 〇 g模擬器會讀入並且 解澤執行械處理機的程式瑪,當程式碼呼 時,Verilog模擬器會呼叫我們撰寫的vpm_cal丨〇函數, vpm_cal 1()將會取出必要參數,將之封裝成訊息之後如圖 (七)中間的虛線箭頭所示,將訊息以訊息傳遞方式送至 UNIX作業系統,再由UNIX作業系統送至等待命令來臨的虛 擬電腦模擬系統執行工作(P r 〇 C e s s )。 虛擬電腦模擬系統的命令解譯器接到命令後,將依命 令要求,送至相關的處理模擬元件處理,待有結果後,會如 圖(七)所示的外虛線送結果訊息給UNIX作業系統,再由作 業系統傳回給等待結果的vpm_call〇。 —call〇收到 結果後,處理格式轉換後,交給Veri log模擬器以完成整Page 15 432334 V. Description of the invention (12), then format it to convert it into a binary standard string, and then use the system service call function of Message passing provided by the UNIX operating system to The waiting (B1 ocking) method is transmitted to the running C ++ personal computer simulation system and waits for a reply message from the personal computer simulation system. When the personal computer simulation system responds with the results of this communication message, the vpm_cal 1 () function needs to process the results into Verilog-type parameters, and then return the results to Verilog's Simulator. As shown in Figure (7), the leftmost oval block represents the execution of the device simulation subsystem of the virtual computer simulation system, and the middle oval block represents the execution of the chip simulation subsystem of the Veri log simulator. The box indicates the microprocessor code that will be read, interpreted, and executed by the Verilog simulator. When the virtual computer system is executed, the Veri 10g simulator will read in and resolve the program code of the execution processor. When the code is called, the Verilog simulator will call the vpm_cal 丨 〇 function we wrote, vpm_cal 1 ( ) Will take the necessary parameters, encapsulate it into a message, and then send the message to the UNIX operating system in a message-passing manner as shown by the dashed arrow in the middle of figure (7), and then send the message to the virtual computer waiting for the command The simulation system performs work (PrOcess). After receiving the command, the command interpreter of the virtual computer simulation system will send it to the relevant processing simulation component according to the command request. After the result is obtained, the result message will be sent to the UNIX operation as shown in the outer dashed line in Figure (7). The system then returns the vpm_call to the waiting result. —Call〇 After receiving the result, after processing the format conversion, hand it to the Veri log simulator to complete the whole process.
432334 五、發明說明(13) —- 個vpm—c一all()的工作。vpm_caU ()的工作流程如圖(八)所 示;在三個參數值準備妥當後,vpm —call即建立IPC埠, 並進行信息交換,取得回覆參數。 (2)以時序為基準的模擬方式 在摄處理機晶片模擬電路上加上延伸之時序電路,該 電路只須負責兩件事:(一)產生微理機與虛擬電腦模擬^ 統共,的時序週期;(二)於每個共用時序週期的正緣及負 緣固定送出微處理機界面訊號,並同步地等待虛擬電腦模 擬系統的回覆資訊。於正負緣送出界面訊號的協定使、 擬電腦模擬系統可同時適用於事件驅動模式 业 (Event-Driven)及週期基準模式(Cycle_Based)的微 機晶片電路設計。 (3 )以獨立C+ +程式元件模擬週邊元件 每一個虛擬電腦模擬系統的元件均以一組程式以物件 方式確切地模擬該元件的實體功能、命令執行、界面協定 及時序。透過整合這些元件之功能,我們可架構出與實體 個人電腦系統相似的系統環境。 (4 )並行執行微處理機模擬程式、週邊晶片組模擬程 式、及週邊週置模擬程式 本虛擬電腦驗證平臺的模擬系統採用UNIX等多工作業 系統的多工方式(Multi-tasking),以ϋ行方式同時啟動' Veri log模擬器去執行微處理機的模擬工作,同—時我們 也啟動了虛擬電腦的週邊晶片組模擬程式,以及虛擬電腦 的週邊裝置模擬程式。這三者之間分別利用我們設計的432334 V. Description of the invention (13) —- a work of vpm-c-all (). The work flow of vpm_caU () is shown in Figure (8). After the three parameter values are ready, vpm —call establishes the IPC port and exchanges information to obtain the reply parameters. (2) The timing-based simulation method adds an extended timing circuit to the analog circuit of the camera processor chip. This circuit is only responsible for two things: (1) generating a microcomputer and a virtual computer simulation. Timing cycle; (2) The microprocessor interface signal is fixedly sent at the positive and negative edges of each shared timing cycle, and synchronously waits for the response information of the virtual computer simulation system. The agreement to send interface signals on the positive and negative edges enables the pseudo-computer simulation system to be suitable for both the event-driven and the cycle-based microcomputer chip circuit design. (3) Simulation of peripheral components with independent C ++ program components Each component of the virtual computer simulation system uses a set of programs to accurately simulate the physical functions, command execution, interface agreement and time sequence of the component. By integrating the functions of these components, we can construct a system environment similar to a physical personal computer system. (4) The simulation system of the microprocessor simulation program, the peripheral chipset simulation program, and the peripheral simulation program is executed in parallel. The simulation system of the virtual computer verification platform adopts the multi-tasking method of multi-tasking systems such as UNIX. In the same way, the Veri log simulator was started to perform the simulation of the microprocessor. At the same time, we also launched the peripheral chipset simulation program of the virtual computer and the peripheral device simulation program of the virtual computer. Each of these three uses our design
第17頁 43 23 3 4Page 17 43 23 3 4
vpm —ca丨丨()及UN丨X作業系統提供的訊息傳遞的功能來達到 同步及資訊溝通的能力。 本案特點及功效如下: (〇此虛擬電腦驗證平臺已經實作並應用於驗證一開 發中的X86相容微處理機,在微架構,行為模式、暫存器轉 換描述模式、及邏輯閘模式的發展過程中,發揮 少的角色。 ’ ' (2 )本虛擬電腦驗證平臺有高移植性、擴充性、 組性。 、 1 ' 本案之市場價值及相關產品之競爭性: 兹就本專利的市場價值及與其它相類似產品間之競爭 性,簡述如下: A. 功能相類似之產品說明: al.微處理機設計驗證市場方面:微處理機設計驗證 市場上,目前為止尚未有與本專利設計之軟體模擬驗證平 臺功能相似的商用套裝軟體。在微處理機設計驗證上,目 前業者採用的驗證方式’不外乎採用硬體仿真方式,自行 開發或訂製自有的低頻主機板’然後再連接上微處理機硬 體線路仿真器來處理微處理機界面協定與控制訊號問題。 或採用一組軟體工作人員來專門開發自有的軟體模擬環 境。 a2·系統軟體及低階控制韌體開發市場方面:系統軟 體及低階控制韌體開發市場上,較成功的產品當屬Beacon 公司所針對X86系列相容的嵌入式系統所開發的系列產vpm —ca 丨 丨 () and UN 丨 X operating system provide message transfer function to achieve the ability of synchronization and information communication. The features and functions of this case are as follows: (0) This virtual computer verification platform has been implemented and used to verify the development of an X86 compatible microprocessor. In the microarchitecture, behavior mode, register description mode, and logic gate mode development In the process, it plays a lesser role. '' (2) This virtual computer verification platform has high portability, scalability, and organization. 1 'Market value of this case and the competitiveness of related products: The market value of this patent is hereby given. Competitiveness with other similar products is briefly described as follows: A. Description of products with similar functions: al. Microprocessor design verification market: In the microprocessor design verification market, there has not yet been a design with this patent. The software simulation verification platform has similar commercial suite software. In the microprocessor design verification, the verification method currently used by the industry 'is nothing more than the use of hardware simulation to develop or customize its own low-frequency motherboard.' Connected to the microprocessor hardware circuit simulator to deal with the microprocessor interface protocol and control signal problems. Or use a group of software workers To develop its own software simulation environment. A2 · System software and low-level control firmware development market: In the system software and low-level control firmware development market, the more successful products are compatible with the X86 series of Beacon Corporation. Series of embedded products
432334 五 '發明說明(15) 品,如 VisutalProbe x8 6 Simulator[2]等。該產品的特 色在於可在Dos/Windows95/WindowsNT上,快速;j;莫擬 在指令及匯流排層次的動作。 a3.電腦週邊晶片開發等市場方面:依國内最大晶片 組廉商的資料顯不’目則市%上尚未有輔助晶片組設計用 的?re Silicon的驗證工具。目前採用的步驟方式為:制 訂或研究規格(Speci f icat i on)、製作或取得晶片組測試 向量(Test Vectors)、晶片製造(IC fabrication)、製作 晶片評估板(Eva la t ion Board)、在晶片評估板上啟動作 業系統、執行測試程式、嘗試不同的微處理機、記憶體及 I/O的組合,然後以邏輯分析儀等工具除錯。就這些&晶片 廠商而言,他們期待能有設計工具可提供:(一)生產前 評估’以縮短設計週期;(二)驗證協定(Pr〇t〇c〇is); (三)調整設計參數(如Buffer Size);(四)做最佳化; (五)效能評估。 β·市場價值與競爭性: 低成本、低價位:就微處理機設計,系統軟體及 :鸣控制韌體開發,及電腦週邊晶片開發等市場而言,本 供業者硬體模擬平臺之外的另類選擇。卩本專利開 二體模擬平臺除具有相近似於硬體模擬平臺精確模擬 月匕卜,更具有價格低廉之絕對優勢g μ. ^操作、較穩定的測試環境:相較於硬體模擬平 利乂 ΐί利開發之軟體模擬平臺具有更易於操作的便 今易處理上傳、下载程式(不像硬體仿真平臺,432334 Five 'invention (15) products, such as VisutalProbe x8 6 Simulator [2] and so on. The characteristic of this product is that it can be operated on Dos / Windows95 / WindowsNT, fast; j; not intended to operate at the command and bus level. a3. In terms of computer peripheral chip development and other markets: According to the data of the largest chipset maker in China, is there no market for auxiliary chipset design yet? re Silicon's verification tool. The current steps are: formulating or researching specifications (Speci f icat i on), making or obtaining chip set test vectors (Test Vectors), wafer fabrication (IC fabrication), making wafer evaluation boards (Eva lat ion board), Start the operating system on the chip evaluation board, execute the test program, try different combinations of microprocessors, memory and I / O, and then debug with tools such as logic analyzers. For these & chip vendors, they look forward to having design tools to provide: (a) pre-production evaluation to shorten the design cycle; (b) verification agreement (Protto); (c) adjustment of design Parameters (such as Buffer Size); (4) optimization; (5) performance evaluation. β · Market Value and Competitiveness: Low Cost and Low Price: In terms of microprocessor design, system software, and development of Ming control firmware, and computer peripheral chip development, other than the hardware simulation platform of this supplier Alternative choice.除 This patented two-body simulation platform has the absolute advantage of low price in addition to the accurate simulation of a moon dagger similar to a hardware simulation platform. G μ. ^ Operation and stable test environment: Compared with hardware simulation, it is more profitable. The software simulation platform developed by 乂 ΐί 利 has easier to handle and easy to handle uploading and downloading programs (unlike the hardware simulation platform,
432334 五、發明說明(16) 等重新燒錄EEPROM或FLASH ROM等),且可線上修改程式。 對於類似於界面接觸不良等不必要的錯誤,更是可被本軟 體模擬平臺排除,以使開發業者更專注於真正的功能及時 序測試。而當系統錯誤造成當機時,其對各元件完整儲存 執行訊息狀態的特點,更是有助於系統的除錯,且可容易 地重建出當時造成系統錯誤的環境。 _b3'更①整的模擬環境1就嵌入式系統軟體開發市場 而吕,目前已有如國外Beac〇n等公司開發的模擬平臺。如 Beacon 開發的 VisualPr〇be χ86 SimuUt〇r 等產品雖可提 供嵌入式系統軟體開發業者於指令及匯流排層次的模擬。 但,其只可支援功能上的模擬,無法提供業者更精確的時 序上的驗證。《而’此時序上的驗證卻常是業者最頭痛的 部份。再則,對系週邊資訊的的收集,VisualPr〇be χ86 simulat〇r只能收集有限的部份’如記憶體内容等而已’ 對大型嚴謹的系統而言’實在是有其不足之慮。 b4·更精確、可調整式的系統模擬:如 xj6 Sjm^ulator等產品採用的是整體系統完全以匚或€ + +等 :Ϊ ί:ί:而成’故而使的其模擬程式每次都得依新系 氺,έ,赴辦ρ冑^。以微處理機而言,新規格微處理開發出 ^ x業者需根據新得到微處理機規格重寫微處 t應:挺邱::此作法造成的結果是浪費時間人力,且微處 Τ = 確性有待確認。而本專利開發之平臺則 :m門發::體描述語言的方式,此方式可直接使用微處 理機開心過程產出微理機電%,業者不必重寫模擬部份。432334 V. Description of the invention (16), such as re-flashing EEPROM or FLASH ROM, etc.), and the program can be modified online. Unnecessary errors, such as poor interface contact, can be ruled out by the software simulation platform, so that developers can focus more on real functions and timely testing. And when a system error causes a crash, its complete storage and execution of the message status of each component is helpful to the system's debugging, and it can easily reconstruct the environment that caused the system error at that time. _b3 'more ① The entire simulation environment 1 is the embedded system software development market. There are currently simulation platforms developed by companies such as Beacon. Products such as VisualPr0be χ86 SimuUtr developed by Beacon can provide embedded system software developers with simulations at the command and bus level. However, it can only support functional simulation and cannot provide a more accurate timing verification for the operator. "And 'this timing verification is often the most painful part of the industry. In addition, for the collection of peripheral information, VisualPróbe χ86 simulat〇r can only collect a limited portion 'such as memory content, etc.' For large and rigorous systems, it has its shortcomings. b4 · More accurate and adjustable system simulation: products such as xj6 Sjm ^ ulator use the whole system completely based on 匚 or € + +, etc .: Ϊ ί: ί: Therefore, the simulation program every time You have to follow the new system, and go to do ρ 胄 ^. In terms of microprocessors, new specifications of microprocessors have been developed. Operators need to rewrite microprocessors according to the newly acquired microprocessor specifications. T should: Tingqiu :: The result of this approach is a waste of time and labor, and microprocessing T = Accuracy is yet to be confirmed. The platform developed by this patent is: mmenfa :: body description language. This method can directly use microprocessors to produce micromechanical electromechanical%. The industry does not need to rewrite the analog part.
第20頁 432334 五、發明說明(17) b5.更廣泛的應用市場、本專利開發的虛擬電腦驗證 平臺可同時適用於微處理機設計,系統軟體及低階控制韌 體開發,及電腦週邊晶片開發等市場,這不是現有任何一 種電腦設計輔助軟體套件所能做到的。 最後總結如下: 一、產業界之利用領域 本案之虛擬個人驗證平臺可以提供產業界三個利用 域: (1 )提供一個微處理機設計的驗證平臺,輔助微架 設計的驗證。可以對其行為模式,暫存器轉換描述模式及 邏輯閘模式提供完整的系統環境,卩便彳充分的驗證。 (2) 提供一先期發展平臺,來輔助新型系統軟體( 括作業系統及BIOS等)的開發及除錯工具。 (3) 提供新開發電腦週邊晶片的模擬及驗證工具與環 二、所欲解決之問題 本案之虛擬電腦驗證平臺解決下列六個主要技術問 (1)基準式時序模擬方法。 (2 )獨立晶片元件行為模擬的物件導向模擬方法。 (3) 微處理機的模擬環境。 的 (4) 結合C++程式模擬元件與VerU〇g程式模擬元件 溝通資訊與整合,以完成模擬工作。 (5) X-Wind〇Ws視窗圖形操作界面。Page 20 432334 V. Description of the invention (17) b5. A wider application market, the virtual computer verification platform developed by this patent can be applied to microprocessor design, system software and low-level control firmware development, and computer peripheral chips Development and other markets, this is not possible with any existing computer design assistance software suite. The final conclusions are as follows: 1. Utilization fields in the industry The virtual personal verification platform in this case can provide three utilization fields in the industry: (1) Provide a verification platform for microprocessor design to assist the verification of micro-frame design. It can provide a complete system environment for its behavior mode, register description mode and logic gate mode, and it can be fully verified. (2) Provide a pre-development platform to assist in the development and debugging of new system software (including operating systems and BIOS, etc.). (3) Provide simulation and verification tools and environment for newly developed computer peripheral chips. 2. Problems to be solved The virtual computer verification platform in this case solves the following six main technical issues. (1) Reference timing simulation method. (2) An object-oriented simulation method for simulating the behavior of independent chip components. (3) The simulation environment of the microprocessor. (4) Combining C ++ program simulation components and VerU〇g program simulation components to communicate information and integrate to complete the simulation work. (5) Graphic operation interface of X-Wind〇Ws window.
第21頁 432334 五、發明說明(18) * (6 )容易增刪以及修改模擬元件,以組成新的模擬系Page 21 432334 V. Description of the invention (18) * (6) It is easy to add, delete and modify analog components to form a new analog system.
統D 三、解決問題之技術 ^基準式時序模擬系統需要一個共同的系統時序,我們 採用微處理機内部延伸的時序產生器來產生同步時序,以 通知模擬系統的模擬元件。 另外,採用物件導向設計模式,以單獨程式物件模擬 各個週邊晶片元件,如ATA Control ler晶片,硬碟等個 人電腦常見之週邊裝置及晶片功能及協定,並在各模擬元 件加入儲存及萃取偵錯必要訊息及動態記錄新開發之微處 理機及週邊裝置的狀態。 微處理機可以三種模式來展現於平臺中:行為模式、 暫存器轉換描述模式或邏輯閘模式。此三種模式採用高階 硬體描述語言(如Verilog)來建立模擬系統。 " 在解決以不同程式語言描述的硬體模擬元件間資訊溝 通及整合模擬問題上,我們採用UNI X提供之 IPC(Inter-Process Communication) ^Cadence Verilog 提供之PLKProgramming Language Interface);並且發 展出適用於一般協定使用的通信函數vpm_call(),以協 助使用高階硬體描述語言(如Verilog)所描述的微處理機 與使用高階程式語言實現的週邊模擬元件整合。 至於X-Windows視窗圖形操作界面,我們以M〇tif視 窗元件架構出具立體感,易操作的視窗面。 採用獨立元件模擬單獨實體元件的技術,以及物件導System D III. Problem-solving technology ^ The benchmark timing simulation system requires a common system timing. We use a timing generator extended inside the microprocessor to generate synchronous timing to inform the analog components of the simulation system. In addition, the object-oriented design mode is used to simulate each peripheral chip component with a single program object, such as ATA Controller chips, hard disks and other personal computer common peripheral devices and chip functions and protocols, and add storage and extraction debugging to each analog component Necessary information and dynamic recording of the status of newly developed microprocessors and peripherals. The microprocessor can be displayed in the platform in three modes: behavior mode, register description mode or logic gate mode. These three modes use high-level hardware description languages (such as Verilog) to build simulation systems. " In solving the problem of information communication and integration simulation between hardware analog components described in different programming languages, we use IPC (Inter-Process Communication) provided by UNI X ^ PLKProgramming Language Interface provided by Cadence Verilog; and developed the applicable The communication function vpm_call () used in the general protocol is to assist the integration of a microprocessor described in a high-level hardware description language (such as Verilog) with a peripheral analog component implemented in a high-level programming language. As for the X-Windows graphical user interface, we use the Motif window component architecture to create a three-dimensional, easy-to-operate window surface. The technology of using independent components to simulate individual solid components, and object guidance
第22頁 432334 五、發明說明(19) 向規劃的方式,使得整體模擬環境具有一組一制化的元件 溝通協定界面。此種作法使得我們的虛擬電腦模擬系統具 有容易整合新模擬元件或從模擬系統移除元件之調適功 能。 本案得由熟悉本技藝之人士任施匠思而為諸般修飾, 然皆不脫如附申請專利範圍所欲保護者。Page 22 432334 V. Description of the invention (19) The way of planning, so that the overall simulation environment has a set of elements and communication interfaces. This approach makes our virtual computer simulation system easy to integrate with new analog components or remove components from the analog system. This case may be modified by any person skilled in the art, but none of them can be protected as attached to the scope of patent application.
第23頁 432334 五、發明說明(20) 參考資料: [1 ] Joon-Seo Yim, Yoon-Ho Hwang, Chang-Jae Park, Hoon Choi, Woo-Seung Yang, Hun-Seung Oh, In-Cheol Park and Chong-Min Kyung, "A C-Based RTL Design Verification Methodology for Complex Microprocessor", 34th DAC, pp.83-88, 1998.Page 23 432334 V. Description of the Invention (20) References: [1] Joon-Seo Yim, Yoon-Ho Hwang, Chang-Jae Park, Hoon Choi, Woo-Seung Yang, Hun-Seung Oh, In-Cheol Park and Chong-Min Kyung, " A C-Based RTL Design Verification Methodology for Complex Microprocessor ", 34th DAC, pp.83-88, 1998.
[2] Beacon Development Tools, Visual Probe x86 Simulator, Product Brief, 1998.[2] Beacon Development Tools, Visual Probe x86 Simulator, Product Brief, 1998.
第24頁Page 24
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW88104749A TW432334B (en) | 1999-03-25 | 1999-03-25 | Virtual computer certification platform |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW88104749A TW432334B (en) | 1999-03-25 | 1999-03-25 | Virtual computer certification platform |
Publications (1)
Publication Number | Publication Date |
---|---|
TW432334B true TW432334B (en) | 2001-05-01 |
Family
ID=21640077
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW88104749A TW432334B (en) | 1999-03-25 | 1999-03-25 | Virtual computer certification platform |
Country Status (1)
Country | Link |
---|---|
TW (1) | TW432334B (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7907531B2 (en) | 2005-06-13 | 2011-03-15 | Qualcomm Incorporated | Apparatus and methods for managing firmware verification on a wireless device |
TWI381180B (en) * | 2008-10-03 | 2013-01-01 | Holtek Semiconductor Inc | Circuit Simulation System |
-
1999
- 1999-03-25 TW TW88104749A patent/TW432334B/en not_active IP Right Cessation
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7907531B2 (en) | 2005-06-13 | 2011-03-15 | Qualcomm Incorporated | Apparatus and methods for managing firmware verification on a wireless device |
TWI381180B (en) * | 2008-10-03 | 2013-01-01 | Holtek Semiconductor Inc | Circuit Simulation System |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN110865971B (en) | System and method for verifying SOC chip | |
US6539522B1 (en) | Method of developing re-usable software for efficient verification of system-on-chip integrated circuit designs | |
CN115841089B (en) | System-level chip verification platform and verification method based on UVM | |
JP2753464B2 (en) | Hardware-software debugger | |
CN102508753B (en) | IP (Internet protocol) core verification system | |
CN112463497A (en) | Platform is verified to SPI based on UVM | |
CN116414526A (en) | Simulation device and method based on virtual machine | |
US6487699B1 (en) | Method of controlling external models in system-on-chip verification | |
CN117422026B (en) | RISC-V architecture-based processor verification system | |
US20050144436A1 (en) | Multitasking system level platform for HW/SW co-verification | |
US20100274550A1 (en) | Integrated development structure having virtual inputs/outputs for embedded hardware/software | |
CN112764981A (en) | Cooperative test system and method | |
TW432334B (en) | Virtual computer certification platform | |
CN116306392A (en) | Chip simulation device, method, electronic device and storage medium | |
CN116340150A (en) | Reusable register performance interactive verification system based on UVM and application thereof | |
JPH08314760A (en) | Program development supporting device | |
El-Moursy et al. | Efficient embedded SoC hardware/software codesign using virtual platform | |
CN113204929A (en) | Method for realizing AHB VIP based on SV and UVM, electronic device and storage medium | |
US11295052B1 (en) | Time correlation in hybrid emulation system | |
JP2005510787A5 (en) | ||
CN118395918A (en) | Chip simulation method and device based on software and hardware, test terminal and medium | |
KR101683636B1 (en) | Mixing circuit simulation system and method | |
Karmitsa | Pre-validation of SoC via hardware and software co-simulation | |
Kurula | A FRAMEWORK FOR EARLY SYSTEM-ON-CHIP CO-VALIDATION | |
CN118428290A (en) | TIMER register debugging method based on SWD digital model |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
GD4A | Issue of patent certificate for granted invention patent | ||
MM4A | Annulment or lapse of patent due to non-payment of fees |