TW427065B - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device Download PDF

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Publication number
TW427065B
TW427065B TW087115024A TW87115024A TW427065B TW 427065 B TW427065 B TW 427065B TW 087115024 A TW087115024 A TW 087115024A TW 87115024 A TW87115024 A TW 87115024A TW 427065 B TW427065 B TW 427065B
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Taiwan
Prior art keywords
channel
potential
power supply
semiconductor integrated
integrated circuit
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TW087115024A
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Chinese (zh)
Inventor
Hiroyuki Makino
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356008—Bistable circuits ensuring a predetermined initial state when the supply voltage has been applied; storing the actual state when the supply voltage fails

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)
  • Dram (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

The object of the present invention is to prevents the loss of data kept in the node due to the leakage current of a MOSFET that constitutes a latch circuit 20 when the latch circuit 20 is configured as an internal circuit. In the solution, a diode 31 is connected between a power source 27 and VA 1.8 and also, a diode 32 is connected between VB 1.12 and a GND 11. Also, substrate potentials of p-channel MOSFETs 2, 3, 21 and 22 which constitute two-input NAND gate 1 and a latch circuit 20 are connected to the source 27, and also the substrate potentials of n-channel MOSFETs 4, 5, 23 and 24 are connected to the GND 11.

Description

4 270 6 54 270 6 5

C:\ProgramFiles\Patent\7008-2184-P.ptd第 4 頁 五、 發明說明（1) 本發明 係 有 關於以 低消 耗 電 力化為目的之半 導 體 積體 電 路 裝置。 近年來 隨 著攜帶 機器 的 發 展，而對半導體 積 體 電路 裝 置 而言， 為 了 使電池 持久 而 謀求低消耗電力 化 0 用以 實 現低消耗 電 力 化的手 法可 舉 出 使動作電壓下降 者 〇 由於 消 耗 電力係 由 電 壓與電 流的 乘 積 所給定的，故藉 由 降 低動 作 電 壓而可 減 低 電壓及 電流 兩 者 ，而一般而言， 對 於 消耗 電 力 具有雙 乘 效 果。 然而， 構 成 半導體 積體 電 路 裝置的M0SFET係 具 有 若降 低 電 源電壓 則 動作特 性惡 化 進而回應速度降 低 的 特 性 〇 為了改 善 此 特性惡 化， 而 臨 限電壓亦有必要 配 合 電源 電 壓 的降低 而 降 低，但 實際 上 不可能使臨限電 壓 與 電源 電 壓 成比例 降 低 。此乃 若臨 限 電 壓降低，則M0SFET 之 不導 通 時 的漏電 電 流 增大， 而增 加 消 耗電力之故。為 了 解 決此 問 題 ，而習 知 係 使用以 下的 手 法 0 第17圖 係 顯 示依據 例如 曰 本 開平7-212218公 報 所 揭露 之 習 知低電 壓 動 作之半 導體 積 體 電路裝置的電路 圖 * 如此 的 電 路係由MT-CJiOS(Mul ti- threshold C0MS)所構成 〇 在圖中 1為二輸入NAND閘 ;2、3 為P 通道M0SFET > 4 5 為N通道M0SFET。6 為P通道M0SFET，其連接於電源7與 供 電 線8(以 下 稱為VA1 ·) 之 間 ’且藉由控制信 號 9而動 作 ; 10為N通道M0SFET ，其連接於接地電位節點1 K 以 下， 稱 為GND11 ) 之 間 ，且藉 由控 制 信 號1 3而動作，又 此 等P通 道M0SFET6 及N 通 道MOSFET10 的 臨 限電壓的絕對值 係 被 設定 五 '發明說明（2) 一 成較構成一輸入NAND閘1的p通道m〇sfet2、3及N通道 M0SFET4 、5大。 且P通道M0SFET2、3的基板電位係連接於νΑ1 ·8 ^通 道M0SFET4、5的基板電位係連接於vbi ·ΐ2，Ρ通道 M0SFET6的基板電位係連接於電源7，ν通道m〇sfeT1 0的基 板電位係連接於GND11。 又第1 8圖係顯示構成習知順序電路之半導體積體電路 裝置的電路’且此此的電路係構成將二個反相器的輸出及 輸入交叉連接之所謂的鎖扣電路。 在圖中’20為鎖扣電路；21、22為P通道MOSFET ; 23 · 24為N通道MOSFET。其他的構造係與第17圖所示的構 造相同，？通道別5?£16及1^通道1*05[£110的臨限電壓的絕 對值係被設定成較構成鎖扣電路20的P通道MOSFET21、22 及N 通道MOSFET23、24 大。 其次，說明其動作。 於第17圖中，於使二輸入N AND閘1動作時，使控制信 號9成為「L」位準’而作為其反相信號的控制信號I〗成為 「H」位準。因此，P通道MOSFET6及N通道MOSFET10均成為 導通’且VA1 * 8被上拉至電源7的位準，而VBl . 1 2被下拉 至GND11的位準。此結果’二輸入NAND閘1係作通常之nand 電路的動作。此時’由於MOSFET2~5被設定成較小之臨限 電壓的絕對值，故電源7即使為低電壓，亦可高速地動 作。 於不使用二輸入NAND閘1時，控制信號成為「H」位C: \ ProgramFiles \ Patent \ 7008-2184-P.ptd page 4 V. Description of the invention (1) The present invention relates to a semiconductor integrated circuit device for the purpose of reducing power consumption. With the development of portable devices in recent years, for semiconductor integrated circuit devices, in order to make the battery last longer, low power consumption is required. 0 Methods to achieve low power consumption include those that reduce the operating voltage. Electric power is given by the product of voltage and current. Therefore, both the voltage and current can be reduced by reducing the operating voltage. Generally speaking, the power consumption has a double effect. However, the MOSFET system constituting a semiconductor integrated circuit device has a characteristic that if the power supply voltage is reduced, the operating characteristics are deteriorated and the response speed is reduced. In order to improve this characteristic deterioration, the threshold voltage must also be reduced in conjunction with the reduction of the power supply voltage. It is impossible to reduce the threshold voltage in proportion to the power supply voltage. This is because if the threshold voltage is reduced, the leakage current when the M0SFET is not conducting will increase, and the power consumption will increase. In order to solve this problem, the conventional system uses the following method. Fig. 17 shows a circuit diagram of a semiconductor integrated circuit device based on a conventional low-voltage operation disclosed in, for example, Japanese Patent Publication No. 7-212218. MT-CJiOS (Mul ti-threshold COMS). In the figure, 1 is a two-input NAND gate; 2, 3 are P-channel M0SFETs; 4 5 are N-channel M0SFETs. 6 is a P-channel M0SFET, which is connected between the power source 7 and the power supply line 8 (hereinafter referred to as VA1 ·) 'and operates by a control signal 9; 10 is an N-channel M0SFET, which is connected to a ground potential node below 1 K, (Referred to as GND11), and operates by the control signal 1 3, and the absolute values of the threshold voltages of these P-channel M0SFET6 and N-channel MOSFET10 are set to five. Description of the invention (2) It is more than one input The p-channels m0sfet2, 3 and N-channels MOSFET4, 5 of NAND gate 1 are large. The substrate potentials of P channels M0SFET2 and 3 are connected to νΑ1 · 8 ^ The substrate potentials of channels M0SFET4 and 5 are connected to vbi · ΐ2, the substrate potential of P channel M0SFET6 is connected to power supply 7, and the substrate of ν channel m0sfeT1 0 The potential is connected to GND11. Fig. 18 shows a circuit of a semiconductor integrated circuit device constituting a conventional sequential circuit ', and the circuit here constitutes a so-called lock circuit in which the output and input of two inverters are cross-connected. In the figure, '20 is the latch circuit; 21 and 22 are P-channel MOSFETs; 23 · 24 are N-channel MOSFETs. The other structures are the same as those shown in Figure 17. The absolute values of the threshold voltages of the channel types 5? £ 16 and 1 ^ channel 1 * 05 [£ 110 are set to be larger than the P-channel MOSFETs 21 and 22 and the N-channel MOSFETs 23 and 24 constituting the latch circuit 20. Next, the operation will be described. In Fig. 17, when the two-input N AND gate 1 is operated, the control signal 9 is set to the "L" level 'and the control signal I as its inverted signal is set to the "H" level. Therefore, both the P-channel MOSFET6 and the N-channel MOSFET10 are turned on ', and VA1 * 8 is pulled up to the level of the power source 7, and VBl.12 is pulled down to the level of GND11. As a result, the two-input NAND gate 1 operates as a normal nand circuit. At this time, since the MOSFETs 2 to 5 are set to a smaller absolute value of the threshold voltage, the power supply 7 can operate at a high speed even with a low voltage. When two-input NAND gate 1 is not used, the control signal becomes "H"

C:\Program Files\Patent\7008-2184-P.ptd第 5 頁 五 '發明說明（3) 準，而作為其反相信號的控制信號1 3成為「L」位準。此 時，P通道M0SFET6及N通道MOSFET10均成為不導通，而 VA1 . 8及VB1 . 1 2係分別由電源7及GND1 1切離。由於p通道 M0SFET6及N通道MOSFET10之臨限電壓的絕對值均設定成較 P通道M0SFET2、3及N通道M0SFET4、5大，故可抑制漏電電 流變小。 一般而言’由於MOSFET之閘極•源極間電壓在臨限電 壓以下的區域’源極.汲極間的漏電電流係相對於閘極電 麗成指數函數地增加’故藉由於M0SFET2〜5及M0SFET6、1〇 的臨限電壓具有差值’而可大幅地減少不使用時的漏電電 流。且其中’以内部電路為二輸入NAND閘當作一例，但是 此内部電路係即使構成其他邏輯電路及記憶電路等之半導 體積體電路裝置之任何種數及尺小的電路，亦可達成相同 的論點。 由於習知低電壓動作電路具有如上述的構造，故造成 以下的問題點。亦即，内部電路的輸出係藉由輸入的組合 來決定’例如’如二輸入NAND閘1之組合電路的場合係正 常地動作’但如具有依據過去之輸入條件之功能之鎖扣電 路之順序電路的場合係會造成故障。 第1 8圖係設有順序電路以當作内部電路，在圖中，鎖 扣電路2 0係由具有絕對值較小之臨限電壓的ρ通道C: \ Program Files \ Patent \ 7008-2184-P.ptd page 5 5 'Explanation of the invention (3), and the control signal 1 3 which is the inverted signal thereof becomes the "L" level. At this time, both the P-channel MOSFET 6 and the N-channel MOSFET 10 become non-conducting, while VA1. 8 and VB1. 1 2 are cut off by the power supply 7 and GND1 1 respectively. Since the absolute values of the threshold voltages of p-channel M0SFET6 and N-channel MOSFET10 are set to be larger than those of P-channel M0SFET2, 3 and N-channel M0SFET4, 5, the leakage current can be suppressed to be smaller. In general, 'the area between the gate and source of the MOSFET is below the threshold voltage'. The leakage current between the drain and the drain increases exponentially with respect to the gate voltage. Therefore, M0SFET2 ~ 5 The threshold voltages of M0SFET6 and M10 have a difference value ', which can greatly reduce the leakage current when not in use. And 'the internal circuit is taken as an example of the two-input NAND gate, but this internal circuit can achieve the same circuit even if it has any number and small size of semiconductor integrated circuit devices such as other logic circuits and memory circuits. argument. Since the conventional low-voltage operating circuit has a structure as described above, the following problems arise. That is, the output of the internal circuit is determined by the combination of inputs. 'For example,' if the combination circuit of the two-input NAND gate 1 operates normally ', but if the order of the latch circuit has a function based on past input conditions Circuits can cause malfunctions. Figure 18 is a sequence circuit as an internal circuit. In the figure, the latch circuit 20 is a ρ channel with a threshold voltage with a smaller absolute value.

MjSFET21、22及Ν通道M0SFET23、24所構成，且節點25及 節點26係成為一對保持節點，其一者成「H」位準時，而 另一者成為「L」位準，以保持其值。控制信號9為「[」MjSFET21, 22, and N channels M0SFET23, 24, and nodes 25 and 26 become a pair of holding nodes, one of which becomes "H" level, and the other becomes "L" level to maintain its value . Control signal 9 is "["

427065 五、發明說明（4) ---- 位準，1控制信號13為「11」位準，而使鎖扣電路2〇動作 時，正常地保持值於節點2 5及節點2 6，且由於p通道 M0SFET21、22及N通道MOSFET23、24之臨限電壓的絕對值 較小’可高速地施行對節點25及節點26的寫入、讀取。但 是若於控制信號9成為「η」位準，而控制信號丨3成為 「L」位準之鎖扣電路2 〇的非動作時減低漏電流，則於ρ通 道M0SFET21、22及Ν通道M0SFET2 3 '24之不導通時的漏電 電流係較Ρ通道M0SFET6及Ν通道MOSFET10之不導通時的漏 電電流多’故不能保持資料於節點2 5及節點2 6。 因為，例如，節點25為「Η」位準，而節點26為「L」 位準’則Ρ通道M0SFET22及Ν通道MOSFET23成為不導通，且 Ρ通道M0SFET21及Ν通道M0SFET24成為導通，但是由於流過 Ρ通道MOSFET22及Ν通道M0SFET23的漏電電流，而使rHj 位準之節點2 5的電位降低’且「l」位準之節點2 6的電位 上昇。此現象係繼績至節點2 5及節點2 6的電位相等為止， 而其結果，保持於節點2 5及節點2 6的資料遺失。 由於習知半導體積體電路裝置係如以上所構成，故於 構成鎖扣電路來當作内部電路的場合，由於構成此鎖扣電 路20之MOSFET的漏電電電’而造成保持於節點的資料遺失 的問題。 本發明之目的係為了解決上述問題而提供半導體積體 電路裝置’其即使於構成順序電路以當作内部電路的場 合’亦可阻止構成此順序電路之MOSFET的漏電電流，而可 繼續保持資料。427065 V. Description of the invention (4) ---- level, 1 control signal 13 is "11" level, and when the lock circuit 20 is operated, the value is normally maintained at nodes 2 5 and 2 6 and Because the absolute values of the threshold voltages of the p-channel MOSFETs 21 and 22 and the N-channel MOSFETs 23 and 24 are relatively small, writing and reading to the nodes 25 and 26 can be performed at high speed. However, if the control signal 9 becomes the "η" level and the control signal 3 becomes the "L" level of the latch circuit 2 during non-operation, the leakage current is reduced, then the ρ channels M0SFET21, 22 and the N channel M0SFET2 3 'The leakage current when the 24 is non-conducting is more than the leakage current when the P-channel MOSFET6 and N-channel MOSFET 10 are non-conducting', so the data cannot be kept at nodes 25 and 26. Because, for example, node 25 is at the "Η" level and node 26 is at the "L" level, the P-channel M0SFET22 and N-channel MOSFET23 become non-conducting, and the P-channel M0SFET21 and N-channel M0SFET24 become conductive. The leakage current of the P-channel MOSFET 22 and the N-channel MOSFET 23 reduces the potential of the node 25 at the rHj level, and the potential of the node 26 at the "l" level rises. This phenomenon continues until the potentials at nodes 25 and 26 are equal, and as a result, the data held at nodes 25 and 26 is lost. Since the conventional semiconductor integrated circuit device is constituted as above, when the latch circuit is constituted as an internal circuit, the data held at the node is lost due to the leakage current of the MOSFET constituting the latch circuit 20 problem. An object of the present invention is to provide a semiconductor integrated circuit device 'for solving the above-mentioned problems, which prevents the leakage current of the MOSFET constituting the sequential circuit even when it constitutes a sequential circuit as an internal circuit', and can keep the data.

C:\Prograra Files\Patent\7008-2184-P.ptd第 7 頁 427065 五、發明說明¢5) 依據本發明的半導體積體電路裝置，包括 源，具有較第二電源高的電位；第—開關元件， 第一電源與第一供電線之間；第二龆關化杜 ^ 第一電 接於此 第二電源與第二供電線之間；第一電壓下降電路接=== 上述第一電源與第一供電線之間；第二電壓下降電路，連 接於上述第二電源與第二供電線之間；以及順序電路，連 接於上述第一供電線與上述第二供電線之間，且由P通道 MOSFET及N通道M0SFET所構成’而此p通道㈣SFET的基板端 子連接於上述第一電源，同時此N通道MOSFET的基板端子 連接於上述第二電源。 依據本發明的半導體積體電路裝置，第一開關元件係 由具有較構成順序電路之P通道MOSFET之臨限電壓的絕對 值大的臨限電壓的P通道M0SFET所構成，且第二開關元件 係由具有較構成順序電路之N通道MOSFET之臨限電壓的絕 對值大的臨限電壓的N通道MOSFET所構成。 依據本發明的半導體積體電路裝置，第一電源係具有 第一電位與較此第一電位高的第二電位的兩種類的電位， 通常被設定成此第一電位，且第一開關元件及第二開關元 件均於不導通狀態時被設定成第二電位。 依據本發明的半導體積體電路裝置，第一電源的兩種 類的電位係自一電源由電壓變換器所產生。 依據本發明的半導體積體電路裝置，包括：第一電 源，具有較第二電源高的電位；第三電源，具有較此第一 電源高的電位；第一P通道MOSFET ’連接於此第一電源與C: \ Prograra Files \ Patent \ 7008-2184-P.ptd page 7 427065 V. Description of the invention ¢ 5) The semiconductor integrated circuit device according to the present invention includes a source having a higher potential than the second power source; The switching element, between the first power source and the first power supply line; the second switch is connected between the second power source and the second power supply line; the first voltage drop circuit is connected Between a power supply and a first power supply line; a second voltage drop circuit connected between the second power supply and the second power supply line; and a sequence circuit connected between the first power supply line and the second power supply line, and It is composed of a P-channel MOSFET and an N-channel MOSFET, and the substrate terminal of the p-channel ㈣SFET is connected to the first power source, and the substrate terminal of the N-channel MOSFET is connected to the second power source. According to the semiconductor integrated circuit device of the present invention, the first switching element is composed of a P-channel MOSFET having a threshold voltage greater than the absolute value of the threshold voltage of the P-channel MOSFET constituting the sequential circuit, and the second switching element is It is composed of an N-channel MOSFET having a threshold voltage larger than the absolute value of the threshold voltage of the N-channel MOSFET constituting the sequential circuit. According to the semiconductor integrated circuit device of the present invention, the first power source has two types of potentials, a first potential and a second potential higher than the first potential, and is generally set to the first potential, and the first switching element and The second switching elements are all set to a second potential when they are not conducting. According to the semiconductor integrated circuit device of the present invention, two types of potentials of the first power source are generated from a power source by a voltage converter. A semiconductor integrated circuit device according to the present invention includes: a first power source having a higher potential than the second power source; a third power source having a higher potential than the first power source; a first P-channel MOSFET 'connected to the first Power and

C:\ProgramFiles\Patent\7008-2184-P.ptd第 8 頁 427065 五、發明說明（6) 第一供電線之間；第二P通道M0SFET，連接於上述第一電 源與第一節點之間；第三P通道M0SFET，連接於上述第— 節點與上述第三電源之間；第一 N通道M0SFET，連接於上 述第一電源與第二供電線之間；第一電壓下降電路，連接 於上述第一節點與第一供電線之間；第二電壓下降電路， 連接於上述第一電源與第一供電線之間；以及順序電路， 連接於上述第一供電線與上述第二供電線之間，且由具有 較上述第一至第三P通道M0SFET之臨限電壓的絕對值小的 臨限電壓的P通道M0SFET及具有較上述第—n通道M0SFET之 臨限電壓的絕對值小的臨限電壓的N通道mosfeT所構成， 而此P通道M0SFET的基板端子連接於上述第一節點，同時 此N通道M0SFET的基板端子連接於上述第二電源。 依據本發明的半導體積體電路裝置，苐一p通道 M0SFET係具有較上述第二及三P通道M〇SFET之臨限電壓的 絕對值小的臨限電壓’且控制此第一p通道M〇SFET之「H」 位準之閘極信號的電位被設定成較第一電源的電位高。 依據本發明的半導體積體電路裝置，其中第一及第二 電壓下降電路係由任意個二極體元件串聯的電路所構成。 依據本發明的半導體積體電路裝置，第一及第二電壓 下降電路係由將M0SFET的開極與及極相連而串聯任;個此 M0SFET的電路所構成。 依據本發明的半導體積體電路裝置，控制第一和第二 P通道M0SFET的閘極信號及控制第三p通道M〇SFET和第一 n 通道M0SFET的間極信號中之至少—者為相同的閘極信號。C: \ ProgramFiles \ Patent \ 7008-2184-P.ptd page 8 427065 V. Description of the invention (6) Between the first power supply line; the second P channel M0SFET is connected between the first power supply and the first node The third P-channel M0SFET is connected between the first node and the third power supply; the first N-channel M0SFET is connected between the first power supply and the second power supply line; the first voltage drop circuit is connected to the above Between a first node and a first power supply line; a second voltage drop circuit connected between the first power supply and the first power supply line; and a sequence circuit connected between the first power supply line and the second power supply line And a P-channel M0SFET having a threshold voltage smaller than the absolute value of the threshold voltage of the first to third P-channel M0SFETs and a threshold having a smaller absolute value than the absolute value of the threshold voltage of the -n-channel M0SFET The N-channel mosfeT of the voltage is configured, and the substrate terminal of the P-channel MOSFET is connected to the first node, and the substrate terminal of the N-channel MOSFET is connected to the second power source. According to the semiconductor integrated circuit device of the present invention, the first p-channel MOSFET has a threshold voltage smaller than the absolute value of the threshold voltage of the second and third P-channel MOSFETs, and controls the first p-channel M. The potential of the gate signal of the "H" level of the SFET is set higher than the potential of the first power source. According to the semiconductor integrated circuit device of the present invention, the first and second voltage drop circuits are constituted by circuits in which any number of diode elements are connected in series. According to the semiconductor integrated circuit device of the present invention, the first and second voltage drop circuits are formed by connecting the open pole and the positive pole of the MOSFET in series; each of the MOSFET circuits. According to the semiconductor integrated circuit device of the present invention, at least one of controlling the gate signals of the first and second P-channel MOSFETs and controlling the intermediate-pole signals of the third p-channel MOSFET and the first n-channel MOSFET is the same Gate signal.

C:\PrograinFiles\Patent\7008-2184-P.ptd第 9 頁 4 270 65 五、發明說明（7) ' ’~~ 依據本發明的半導體積體電路裝置，第一和第二電壓 下降電路中至少一者係由臨限電壓之絕對值不同的㈣sfet 所構成。 依據本發明的半導體積體電路裝置，第一電源係自第 三電源由電壓變換器所產生。 依據本發明的半導體積體電路裝置，第三電源係自第 一電源由電壓變換器所產生。 【發明的實施例】 以下’說明本發明的實施例。 第一實施例 第1圖係顯示依據本發明之第一實施例之半導體積體 電路裝置的電路圖’在圖中’1為二輸入N A ND間；2、3為P 通道M0SFET ; 4、5為N通道M0SFET。且20為鎖扣電路（順序 電路）；21、22 為 P 通道 M0SFET ;23、24 為N 通道MOSFET。 6為P通道M0SFETC第一開關元件），其連接於電源（第 一電源）27與供電線（以下，稱為VA1 ·(第一供電線））8之 間，且藉由控制信號而動作；1〇為N通道M0SFET，其連接 於接地電位節點（以下，稱GND(第二電源））11與供電線（以 下，稱VB1 ·(第二供電線））之間，且藉由控制信號丨3而動 作’又此等P通道M0SFET6及N通道MOSFET10之臨限電壓的 絕對值係設定成較構成二輸入NAND閘1及鎖扣電路20的P通 道MOSFET2、3、21、22 及N 通道MOSFET4、5、23、24 大。 31為二極體（第一電壓下降電路），其陽極連接於電源 27，而陰極連接於VA1 .8 ;32為二極體（第二電壓下降電 iiHi mm C:\ProgramFiles\Patent\7008-2184-P.ptd第 10 頁 427065_ 五、發明說明⑻ 一 路）’其陽極連接於VB1 . 12，而陰極連接於gndii。 且P通道M0SFET22、3、6、21、22的基板電壓係連接 於電源27，而N通道M0SFET4、5、10、23、24的基板電1 係連接於GND1 1。 其次，說明其動作。 於二輸入NAND閘1及鎖扣電路20的動作時，電源23的 電壓為低電壓（第一電壓），使控制信號9成為「L」位準， 而作為其反相信號的控制信號1 3成為「η」位準。因此，p 通道MOSFET6及Ν通道MOSFET10均成為導通，且VA1 .8係被 上拉至電源2 7的位準為止，而VB1 ·12係被下拉正(JND1 1為 止。此結果’二輸入NAND閘1及鎖扣電路20作通常的動 作，且由於臨限電壓的絕對值被設定成較小，故可高速地 動作。又於此時’二極體31 '32係由於其陽極與陰極間電 壓均成為0V，故完全不影響二輸入NAND閘1及鎖扣電路2〇 的動作。 其次，於二輸入NAND閘1及鎖扣電路20不使用時，使 控制信號9成為「Η」位準，而作為其反相信號的控制信號 13成為「L」位準，同時使電源27變化成高電位（第二電 位）。因此，Ρ通道MOSFET6及Ν通道MOSFET10均成為不導 通，而由於在小臨限電壓之二輸入N AND閘1及鎖扣電路2〇 的漏電電流，故VA1 .8及VB1 ’12的電位均被上拉，而上 昇至二極體31、32導通的電位為止。 第2圖係顯示於第1重要部份之電位的時序圖，於圖 中，8a為VA1 .8的電位；12a為VB1 .12的電位；27a為電C: \ PrograinFiles \ Patent \ 7008-2184-P.ptd page 9 4 270 65 V. Description of the invention (7) '~~ According to the semiconductor integrated circuit device of the present invention, in the first and second voltage drop circuits At least one of them is composed of ㈣sfet with different absolute values of the threshold voltage. According to the semiconductor integrated circuit device of the present invention, the first power source is generated from the third power source by a voltage converter. According to the semiconductor integrated circuit device of the present invention, the third power source is generated from the first power source by a voltage converter. [Embodiments of the invention] Hereinafter, embodiments of the invention will be described. First Embodiment FIG. 1 is a circuit diagram showing a semiconductor integrated circuit device according to a first embodiment of the present invention. In the figure, “1” is between two input NA and ND; “2” and “3” are P-channel MOSFETs; “4” and “5” are N-channel M0SFET. And 20 is a latching circuit (sequence circuit); 21 and 22 are P-channel M0SFETs; 23 and 24 are N-channel MOSFETs. 6 is a P-channel M0SFETC first switching element), which is connected between a power source (first power source) 27 and a power supply line (hereinafter, referred to as VA1 · (first power supply line)) 8 and operates by a control signal; 10 is an N-channel M0SFET, which is connected between a ground potential node (hereinafter, referred to as GND (second power supply)) 11 and a power supply line (hereinafter, referred to as VB1 · (second power supply line)), and is controlled by a control signal 丨3, and the absolute value of the threshold voltage of these P-channel M0SFET6 and N-channel MOSFET10 is set to be more than that of P-channel MOSFET2, 3, 21, 22, and N-channel MOSFET4 constituting the two-input NAND gate 1 and the latch circuit 20 , 5, 23, 24. 31 is a diode (first voltage drop circuit), the anode is connected to the power source 27, and the cathode is connected to VA1.8; 32 is the diode (second voltage drop circuit iiHi mm C: \ ProgramFiles \ Patent \ 7008- 2184-P.ptd, page 10 427065_ V. Description of the invention ⑻ All the way) 'The anode is connected to VB1. 12 and the cathode is connected to gndii. The substrate voltages of the P-channel M0SFET22, 3, 6, 21, and 22 are connected to the power source 27, and the substrate electrical 1 of the N-channel M0SFET4, 5, 10, 23, and 24 are connected to GND1 1. Next, the operation will be described. During the operation of the two-input NAND gate 1 and the latch circuit 20, the voltage of the power source 23 is a low voltage (the first voltage), so that the control signal 9 becomes the "L" level, and the control signal 1 is its inverted signal. Become the "η" level. Therefore, both the p-channel MOSFET6 and the N-channel MOSFET10 are turned on, and the VA1.8.8 series is pulled up to the level of the power supply 27, while the VB1.12 series is pulled down (up to JND1 1. This result is 'two-input NAND gate' 1 and the latch circuit 20 perform normal operations, and the absolute value of the threshold voltage is set to be small, so it can operate at high speed. At this time, the 'diode 31' 32 is due to the voltage between its anode and cathode Both become 0V, so it does not affect the operation of the two-input NAND gate 1 and the lock circuit 20 at all. Secondly, when the two-input NAND gate 1 and the lock circuit 20 are not used, the control signal 9 is set to the "Η" level. The control signal 13 which is its inverted signal becomes the "L" level and changes the power source 27 to a high potential (second potential). Therefore, both the P-channel MOSFET 6 and the N-channel MOSFET 10 become non-conducting. The second limit voltage is input to the leakage current of the N AND gate 1 and the lock circuit 20, so the potentials of VA1.8 and VB1 '12 are both pulled up and rise to the potential at which the diodes 31 and 32 are turned on. The diagram shows the timing diagram of the potential in the first important part. In the diagram, 8a VA1 .8 potential; 12a of the potential VB1 .12; 27a electrically

C:\Prograin Files\Patent\7008-2184_P.ptd第 11 頁 427065 五、發明說明C9) 源27之電位之變化的形情 1 時）。又電源27的電源電壓係例如， 非致广 ι，〇ν ’高電壓時為3.3V，而二極體31、°32的電壓時為 =成=間…11 ’電㈣及….8均成為υν,οΓ.· m2均上昇，且丄δ電係〜27Λ昇至3·3ν， .8 VA1 8係成為較電源27僅低二極體 ί 電位’而VB1 .12係成為較_!僅高二 極體32之導通電壓V2的電位。 般而5 ，一極體係若陽極與陰極間的電位超過導通 電壓’則電流流過，而具有大體以導通電壓來將陽極與陰 極間的電壓予以箝位的性質，故VA1 . 8 iVB1 . 12的上昇 大體以上述電位來抑制。此結果，於不使用時之VA i 8及 VB1 . 12的電位分別成為2. 7V及0· 6V。其中，若注意到構 成二輸入NAND閘1及鎖扣電路20的M0SFET，則P通道 MOSFET2、3、21、22係其源極節點均連接於VA1 .8，而基 板電位連接於電源27，故基板電位成為較源極電位高〇. 6V 的狀能（反偏壓狀態）。又N通道MOSFET5、23、24係其源極 節點均連接於VB1 · 12，而基板電位連接於GNDn，故基板 電位成為較源極電位低0 . 6 V的狀能（反偏壓狀態）。 僅N通道M0SFET4源極連接於N通道M0SFET5的汲極節 點’但N通道MOSFET5的汲極節點持續等於VB1 . 12的電 值，或較其高’故N通道M0SFET1之源極與基板電位的電位 差成為0. 6以上，而成為較N通道MOSFET5、23、24強的反C: \ Prograin Files \ Patent \ 7008-2184_P.ptd page 11 427065 V. Description of the invention C9) Change of the potential of the source 27 (1 hour). The power supply voltage of the power source 27 is, for example, non-inductive, νν 'at high voltage is 3.3V, and when the voltage of the diodes 31 and ° 32 is ==== 11 ... Υν, οΓ. · M2 both rise, and the 丄 δ electrical system ~ 27Λ rises to 3 · 3ν, .8 VA1 8 series becomes only lower than the power source 27 diode, and VB1 .12 series becomes more than _! Only The potential of the on-voltage V2 of the high diode 32. In general, if the potential between the anode and the cathode exceeds the on-voltage in a one-pole system, a current flows, and the on-voltage is used to clamp the voltage between the anode and the cathode, so VA1. 8 iVB1. 12 The rise of 抑制 is generally suppressed by the above-mentioned potential. As a result, the potentials of VA i 8 and VB1. 12 when not in use are 2.7V and 0.6V, respectively. Among them, if it is noted that the M0SFET constituting the two-input NAND gate 1 and the latch circuit 20, the source nodes of the P-channel MOSFETs 2, 3, 21, and 22 are all connected to VA1.8, and the substrate potential is connected to the power source 27, so The substrate potential is 0.6 V higher than the source potential (reverse bias state). In the N-channel MOSFETs 5, 23, and 24, the source nodes are connected to VB1 · 12 and the substrate potential is connected to GNDn. Therefore, the substrate potential becomes 0.6 V lower than the source potential (reverse bias state). Only the source of the N-channel M0SFET4 is connected to the drain node of the N-channel M0SFET5 ', but the drain node of the N-channel MOSFET5 continues to be equal to or higher than VB1. 12, so the potential difference between the source of the N-channel M0SFET1 and the substrate potential Become 0.6 or more, and become stronger than N-channel MOSFET 5, 23, 24

C:\ProgramFiles\Patent\7008-2184-P.ptd第 12 頁C: \ ProgramFiles \ Patent \ 7008-2184-P.ptd page 12

4270 6 F 五、發明說明（10) ---, 偏壓狀態。 一般而言，於M0SFET中，若反偏壓的電壓施加於 與基板間’則相較於使源極與基板間成為同電位的場二極 臨限電壓的絕對值上昇，而具有若反偏壓值增加，則:’ 電壓的絕對值的上昇量亦增加的性質。因此，於第丨圖限 示的構造’於不使用時，構成二輸入NAND閘1及鎖扣電路 20的M0SFET的臨限電壓均較動作時高，而此結果， ^我低 漏電電流。且VA 1 · 8及VB1 · 1 2係藉由二輸入NAND閘1及鎖 扣電路2 0的漏電電流及二極體3 1、3 2而保持於一定電位’ 故二輸入NAND閘1的輸出入節點及鎖扣電路2〇之記憶節點 的電位均保持目前的狀態，而不會使記憶節點的資料消 失。 如上述’依據此第一實施例，於動作時，藉由構成— 輸入NAND閘1及鎖扣電路20之小臨限電壓的MOSFET，而可 高速地動作。且於不使用時，構成二輸入N AND閘1及鎖扣 電路20的MOSFET的臨限電壓均較動作時高，而其結果，可 減低漏電電流。又由於V A1 . 8及VB1 . 1 2係藉由二輸入 NAND閘1及鎖扣電路20的漏電電流及二極體31、32而保持 於一定電位，故二輸入NAND閘1的輸出入節點及鎖扣電略 2 0之記憶節點的電位均保持目前的狀態，而可防止記憶節 點的資料消失。 且在上述第一實施例中，於不使用時’3.3V的高電壓 施加於電源27，但是即使於不使用時’亦可與動作時的電 位相同，且即使於此場合，亦可減少漏電電流’同時二輪4270 6 F V. Description of the invention (10) ---, Bias state. Generally speaking, in a M0SFET, if a reverse bias voltage is applied between the substrate and the substrate, the absolute value of the threshold voltage of the field two poles will increase compared to the case where the source and the substrate become the same potential. When the voltage value is increased, the property that the absolute value of the voltage is also increased. Therefore, when the structure shown in Fig. 丨 is not in use, the threshold voltage of the M0SFETs constituting the two-input NAND gate 1 and the latch circuit 20 are both higher than during operation, and as a result, the leakage current is low. And VA 1 · 8 and VB1 · 1 2 are maintained at a certain potential by the leakage current of the two-input NAND gate 1 and the lock circuit 20 and the diodes 3 1 and 3 2. Therefore, the output of the two-input NAND gate 1 The potentials of the input node and the memory node of the lock circuit 20 are maintained in the current state, and the data of the memory node will not disappear. As described above, according to the first embodiment, during the operation, the MOSFET can be operated at a high speed by constituting a MOSFET with a small threshold voltage input to the NAND gate 1 and the latch circuit 20. When not in use, the threshold voltages of the MOSFETs constituting the two-input N AND gate 1 and the latch circuit 20 are higher than during operation, and as a result, the leakage current can be reduced. Since V A1. 8 and VB1. 1 2 are maintained at a certain potential by the leakage current of the two-input NAND gate 1 and the lock circuit 20 and the diodes 31 and 32, the output and input nodes of the two-input NAND gate 1 And the potentials of the memory nodes of the lock lock strategy 20 are maintained in the current state, which can prevent the data of the memory nodes from disappearing. Moreover, in the first embodiment described above, a high voltage of '3.3V is applied to the power source 27 when not in use, but even when not in use', it can have the same potential as during operation, and even in this case, leakage can be reduced Current 'simultaneous two rounds

4 2 7 Ο 6 5 五、發明說明（11) 入NAND間1的輸出入節點及鎖扣電路2〇之記憶節點的電位 均保持目前的狀態，而可防止記憶節點的資料消失。 又於上述第一實施例中，雖然說明控制信號9與控制 信號1 3為互相反相的場合，但是若滿足上述動作，則亦可 為互相獨立的信號。 第二實施例 第3圖係顯示依據本發明之第二實施例之半導體積體 電路裝置的電路圖，於圖中，33為與二極體31串聯的二極 體（第一電壓下降電路）；34為與二極體32串聯的二極體 (第二電壓下降電路）。 其他的構造係與第一實施例相同，故省略重複的說 明。 其次’說明其動作。 如第3圖所示，藉由二極體31、33之兩個的串聯 '二 極體32、34之兩個的串聯，而使於不使用時之VA1 . 8及 VB1 _ 1 2的電位相較於第一實施例來變化。 第4圖係顯示於第3圖之重要部份之電位的時序圖，於 圖中’二極體31、33的導通電壓VI及二極體32、34的導通 電壓V2均成為二個二極體份的導通電壓，故成為1.2V，而 其結果’於不使用時之VA1 .8及VB1 .12的電位成為2. IV 及1·2V 。 因此，構成二輸入N AND閘1及20的MOSFET係於不使用 時的臨限電壓較第一實施例的場合高，此結果，可更減低 漏電電流。且於此時，於VA1 · 8及VB1 . 12之間係為了保4 2 7 Ο 6 5 V. Description of the invention (11) The potentials of the input and output nodes of the NAND cell 1 and the memory nodes of the latch circuit 20 remain in the current state, which can prevent the data of the memory nodes from disappearing. Also in the first embodiment described above, the case where the control signal 9 and the control signal 13 are mutually inverted is described, but if the above-mentioned operation is satisfied, the signals may be independent of each other. Second Embodiment FIG. 3 is a circuit diagram showing a semiconductor integrated circuit device according to a second embodiment of the present invention. In the figure, 33 is a diode (first voltage drop circuit) connected in series with the diode 31; 34 is a diode (second voltage drop circuit) connected in series with the diode 32. The other structures are the same as those of the first embodiment, so redundant explanations are omitted. Next, its operation will be described. As shown in Figure 3, the potential of VA1. 8 and VB1 _ 1 2 when not in use is caused by the series connection of two of the diodes 31 and 33 and the connection of two of the diodes 32 and 34. Compared with the first embodiment. Figure 4 is a timing diagram showing the potentials of the important parts of Figure 3. In the figure, the 'on voltage VI of the diodes 31 and 33 and the on voltage V2 of the diodes 32 and 34 both become two diodes. The body's on-voltage is 1.2V, and as a result, the potentials of VA1.8 and VB1.12 when not in use are 2.IV and 1.2V. Therefore, the MOSFETs constituting the two-input N AND gates 1 and 20 have higher threshold voltages when not in use than in the case of the first embodiment. As a result, the leakage current can be further reduced. And at this time, between VA1 · 8 and VB1. 12 for protection

C:\Program Files\Patent\7008-2184-P.ptd第 14 頁 427065 五、發明說明（12) 持0. 9V的電位差，而内部節點亦保持，進而不會使鎖扣電 路20的資料消失。 如上述，依據此第二實施例，較第一實施例的場合更 可減低不使用時的漏電電流，而可實現低消耗電力化。 且依據此第二實施例，雖然串聯兩個二極體，但亦可 串聯任意個’而調整導通電壓，以達到同樣的效果。 第三實施例 第5圖係顯示依據本發明之第三實施例之半導體積體 電路裝置的電路’於圖中’35、36為閘極與汲極相連的p 通道MOSFET( MOSFET，第一電壓下降電路），且串聯此等p 通道MOSFET3 5、36。且37、38為閘極與汲極相連的N通道 MOSFET(MOSFET，第二電壓下降電路），且串聯此等N通道 MOSFET37 、 38 ° 其他的構造係與第一實施例相同，故省略重複的說明。 其次，說明其動作。 第5圖係將於第二實施例的二極體3丨、33置換成p通道 MOSFET35、36，且將二極體32、34置換成N通道 MOSFET37 、 38 。 一般而言’具有正臨限電壓的N通道M0SFET或具有負 臨限電壓的P通道MOSFET係藉由將汲極與閘極連接而可將 臨限電塵當作成為導通電壓的二極體，故藉由此第三實施 例所形成的構造，而可實現與第二實施例相同的動作。且 不必要設置特殊的二極體元件，而可僅以M〇SFET來構成全 電路’且藉由於製造時調整臨限電壓而可製作任意的導通C: \ Program Files \ Patent \ 7008-2184-P.ptd page 14 427065 V. Description of the invention (12) The potential difference of 0.9V is maintained, and the internal nodes are also maintained, so that the data of the lock circuit 20 will not disappear. . As described above, according to the second embodiment, it is possible to reduce the leakage current when not in use compared to the case of the first embodiment, and it is possible to achieve low power consumption. And according to this second embodiment, although two diodes are connected in series, any number of 'can be connected in series to adjust the on-voltage to achieve the same effect. Third Embodiment FIG. 5 shows a circuit of a semiconductor integrated circuit device according to a third embodiment of the present invention. In the figure, 35 and 36 are p-channel MOSFETs (MOSFETs, first voltages) connected to a gate and a drain. Drop circuit), and these p-channel MOSFETs 3, 36 are connected in series. In addition, 37 and 38 are N-channel MOSFETs (MOSFETs, second voltage drop circuits) whose gates and drains are connected, and these N-channel MOSFETs 37 and 38 are connected in series. The other structures are the same as those of the first embodiment, so redundant descriptions are omitted. Instructions. Next, the operation will be described. FIG. 5 shows that the diodes 3 and 33 of the second embodiment are replaced with p-channel MOSFETs 35 and 36, and the diodes 32 and 34 are replaced with N-channel MOSFETs 37 and 38. Generally speaking, an N-channel MOSFET with a positive threshold voltage or a P-channel MOSFET with a negative threshold voltage can treat the threshold electric dust as a diode that becomes the on-voltage by connecting the drain to the gate. Therefore, with the structure formed by this third embodiment, the same operation as that of the second embodiment can be realized. And it is not necessary to provide a special diode element, but the entire circuit can be constituted by only MOSFET 'and arbitrary conduction can be made by adjusting the threshold voltage during manufacture

CAProgramFiles\Patent\70〇8-2184-P.ptd第 15 頁 4 270 6 5 五、發明說明（13) 電壓。 如上述’依據此第三實施例，藉由P通道M0SFET35、 3 6及N通道M0SFET3 7、38，而可達到與第二實施例相同的 效果。不必要設置特殊的二極體元件，而可僅以M0SFET來 構成全電路，進而可易於製造。 且雖然在此第三實施例中，顯示藉由p通道 MOSFET2 5、36來實現電源27側，且藉由N通道M0SFET37、 38來實現GND11側的場合，但是p通道M〇SFET及n通道 M0SFET可任意組合’且僅以任一者亦可得到相同的效果。 又P通道M0SFET及N通道M0SFET之串聯的個數亦可任意 個’亦可依據既定的導通電壓來選擇串聯的個數。 此外’雖然在第三實施例中，使用大臨限電壓的 M0SFET 來當作 P 通道 m〇sfeT35、36 及 N 通道 M0SFET37、38， 但是亦可使用小臨限電壓的M〇SFET。 第四實施例 第6圖係顯示依據本發明之第四實施例之半導體積體 電路裝置的電路圖，在圖中，41為dC_dc變換器（電壓變換 器），其依據控制信號43的值來將電源42的電位變換成既 定的電位’而輸出至電源27 β 其他的構造係與第一實施例相同，故省略其說明。 其次’說明其動作。 第6圖係於第—實施例中，使用DC-DC變換器41來實現 動作時及不使用時之電源27的電位。例如若於動作時， 使控制信號43成為「η」位準’而於不使用時成為「L」位CAProgramFiles \ Patent \ 70〇8-2184-P.ptd page 15 4 270 6 5 V. Description of the invention (13) Voltage. As described above, according to this third embodiment, the same effects as those of the second embodiment can be achieved by the P-channel MOSFETs 35, 36, and the N-channel MOSFETs 3, 38. It is not necessary to provide a special diode element, and the entire circuit can be constituted by only the MOSFET, which can be easily manufactured. And in this third embodiment, it is shown that the power source 27 side is realized by p-channel MOSFETs 2 and 36, and the GND11 side is realized by N-channel MOSFETs 37 and 38, but the p-channel MOSFET and n-channel MOSFET Any combination can be used, and the same effect can be obtained with only one of them. The number of P-channel M0SFETs and N-channel M0SFETs connected in series may be any number, and the number of series connected may be selected according to a predetermined on-state voltage. In addition, although in the third embodiment, a MOSFET with a large threshold voltage is used as the P-channel MOSFETs 35, 36 and N-channel MOSFETs 37, 38, a MOSFET with a small threshold voltage may also be used. Fourth Embodiment FIG. 6 is a circuit diagram showing a semiconductor integrated circuit device according to a fourth embodiment of the present invention. In the figure, 41 is a dC_dc converter (voltage converter), and it is converted according to the value of the control signal 43. The potential of the power source 42 is converted into a predetermined potential 'and output to the power source 27 β. The other structures are the same as those of the first embodiment, and a description thereof is omitted. Next, its operation will be described. Fig. 6 shows the potential of the power source 27 when the DC-DC converter 41 is used and when it is not used in the first embodiment. For example, if the control signal 43 is set to the "η" level 'during operation and to the "L" position when not in use

C:\Program FileS\Patent\7〇〇8_2184_P ptd第 16 頁 427065 五、發明說明（14) 準’則控制信號43為「Η」位準時，使電源27成為低電 位’且Ρ通道M0SFET6成Ν通道MOSFET10成為導通狀態，藉 以實現電壓的高速動作’同時於控制信號43為r L」位準 時’使電源27成為高電位，且ρ通道M〇SFET6及ν通道 M0SFET 1 0成為不導通狀態，藉以實現第一實施例所述之漏 電電流的減低。 如上述’依據此第四實施例，可施加既定電位於電源 27 ’而可實現第一實施例的動作。 且電源27的電位亦可與上述低電位或高電位中任一者 同電位’而控制信號43亦可與控制信號9或控制信號1 3相 同的信號。又第二實施例及第三實施例亦可適用於此第四 實施例，而可得到相同的效果。 第五實施例 第7圖係顯示依據本發明之第五實施例之半導體積體 電路裝置的電路圖，在圖中，51為電源（第一電源）；52為 具有較此電源51南之電位的電源（第三電源）。6為連接於 電源51與VA1 .8之間的P通道M0SFET(第一P通道M0SFET); 5 3為連接於電源5 1與電源（第一節點）2 7之間的P通道 M0SFET (第二P 通道M0SFET)，且P 通道M0SFET6、53 的基板 電位係連接於電源27。54為連接於電源27與電源52之間的 P通道M0SFET(第三P通道M0SFET)，且P通道MOSFET54的基 板電位係連接於電源52。10為連接於GND11與VB1 . 12之間 的N通道MOSFET(第一N通道MOSFET)，且N通道MOSFET1 0的 基板電位係連接於GND11。C: \ Program FileS \ Patent \ 7〇〇8_2184_P ptd page 16 427065 V. Description of the invention (14) When the control signal 43 is at the "Η" level, the power source 27 will be at a low level and the P channel M0SFET6 will be Ν. The channel MOSFET 10 is turned on to realize high-speed operation of the voltage, and at the same time, the control signal 43 is at r L "on time" to make the power source 27 high, and the ρ channel MOSFET6 and ν channel M0SFET 1 0 are turned off. The reduction of the leakage current described in the first embodiment is achieved. As described above, according to the fourth embodiment, a predetermined electric power can be applied to the power source 27 and the operation of the first embodiment can be realized. Also, the potential of the power source 27 may be the same potential as any one of the above-mentioned low potential or high potential, and the control signal 43 may be the same signal as the control signal 9 or the control signal 13. The second embodiment and the third embodiment can also be applied to this fourth embodiment, and the same effect can be obtained. Fifth Embodiment FIG. 7 is a circuit diagram showing a semiconductor integrated circuit device according to a fifth embodiment of the present invention. In the figure, 51 is a power source (first power source); 52 is a potential having a potential 51 south of the power source. Power supply (third power supply). 6 is the P-channel M0SFET (the first P-channel M0SFET) connected between the power supply 51 and VA1.8; 5 3 is the P-channel M0SFET (the second P-channel M0SFET) connected between the power supply 5 1 and the power supply (first node) 2 7 P-channel M0SFET), and the substrate potential of P-channel M0SFET6, 53 is connected to power source 27. 54 is the P-channel M0SFET (third P-channel M0SFET) connected between power source 27 and power source 52, and the substrate potential of P-channel MOSFET 54 It is connected to the power source 52. 10 is an N-channel MOSFET (first N-channel MOSFET) connected between GND11 and VB1. 12. The substrate potential of the N-channel MOSFET 10 is connected to GND11.

C:\Program Files\Patent\7008-2184-P.ptd第 17 頁 427065 五、發明說明（15) 且55、56為控制信號’控制信號55係與控制信號丨3相 同’而控制信號56係與控制信號9相同。 其他構造係與第一實施例相同，故省略其重複的說 明。 其次，說明其動作。 於二輸入NAND閘1及鎖扣電路2〇動作時，控制信號 13、55成為「H」位準’而控制信號9、56成為rL」位 準。此時’ P通道MOSFET6、53及N通道MOSFET10成為導通 狀態，而P通道M0SFET54成為不導通狀態。因此，電源27 及VA1 . 8均被施加電源5 1的低電位，同時施加GND1 1的電 位於VB1 . 12。所以’二輸入NAND閘1及鎖扣電路2〇係施行 與於第一實施例之動作時同樣之低電壓的高速動作。 其次，於不使用時，控制信號1 3、55成為「L」位 準，而控制信號9、56成為「H」位準。此時，p通道 MOSFET6、53及N通道MOSFET10成為不導通狀態，而p通道 MOSFET54成為導通狀態。因此，施加電源52的高電位於電 源2 7 ’而與於第一實施例的不使用時同樣地可減低二輸入 NAND閘1及鎖扣電路20的漏電電流。 如上述，依據此第五實施例，僅以附加p通道 MOSFET53、54的单純電路’而可不使用如第四實施例之可 改變輸出電壓的DC-DC變換器41，進而可實現第一實施例 的動作，且可得到同樣的效果。 且依據此第五實施例，雖然說明控制信號1 3、55及控 制信號9、5 6互相反相的場合，但是若滿足上述動作，則C: \ Program Files \ Patent \ 7008-2184-P.ptd page 17 427065 V. Description of the invention (15) and 55 and 56 are control signals 'control signal 55 is the same as control signal 3' and control signal 56 is Same as control signal 9. The other structures are the same as those of the first embodiment, so the repeated explanations are omitted. Next, the operation will be described. When the two-input NAND gate 1 and the latch circuit 20 operate, the control signals 13, 55 become the "H" level 'and the control signals 9, 56 become the rL "level. At this time, the 'P-channel MOSFETs 6, 53 and the N-channel MOSFET 10 are turned on, and the P-channel MOSFET 54 is turned off. Therefore, both the power source 27 and VA1. 8 are applied with the low potential of the power source 51, while the power applied to GND1 1 is located at VB1. 12. Therefore, the two-input NAND gate 1 and the latch circuit 20 perform the same low-voltage high-speed operation as that in the first embodiment. Secondly, when not in use, the control signals 1 and 55 become the "L" level, and the control signals 9 and 56 become the "H" level. At this time, the p-channel MOSFETs 6, 53 and the N-channel MOSFET 10 are turned off, and the p-channel MOSFET 54 is turned on. Therefore, the high power applied to the power source 52 is located at the power source 27 ', and the leakage current of the two-input NAND gate 1 and the latch circuit 20 can be reduced in the same manner as when the first embodiment is not used. As described above, according to the fifth embodiment, only the simple circuit of the p-channel MOSFETs 53 and 54 is added, and the DC-DC converter 41 that can change the output voltage as in the fourth embodiment can be omitted, thereby realizing the first implementation. Example, and the same effect can be obtained. And according to this fifth embodiment, although the case where the control signals 1 3, 55 and the control signals 9, 5 6 are opposite to each other will be described, if the above operations are satisfied, then

C:\Progr咖 Files\Patent\7008-2184-P.ptd第 18 頁 4270 65 五、發明說明（16) -- 亦可為獨立的信號’而可得到同樣的效果。 第六實施例 第8圖係顯示依據本發明之第六實施例之半導體積體 電路裝置的電路圖，此第六實施例係於第7圖中使p通道 M0SFET成為與較P通道MOSFET53、54小之臨限電壓之%邑對 值的P通道M0SFET2、3等相同的p通道M〇SFET (第—p通道 MOSFET)101 者。 、 又於二輸入NAND閘1及鎖扣電路2〇不使用時（非致能 時），將控制P通道MOSFET101之「H」位準之閘極信糂=電 位設定成較電源51的電位高。 如上述’依據此第六實施例’與第五實施例同樣地可 減低P通道M0SFET1 01之不導通時的漏電電流，同時藉由臨 限電壓之絕對值小的P通道MOSFET101，而使導通時的電流 量較第五實施例的場合大，而可使p通道MOSFET101的尺寸 變小’因此而可使半導體積體電路裝置的晶片尺寸變小。 第七實施例 第9圖係顯示依據本發明之第七實施例之半導體積體 電路裝置的電路圖，在圖令，藉由共同的控制信號9來控 制P通道M0SFET6、53，且藉由與控制信號9反相之共同的 控制信號13來控制P通道MOSFET54及N通道MOSFET10。 其他構造係與第五實施例相同，故省略其重複說明。 如上述，依據此第七實施例，不會減損第五實施例的 效果，而可減低控制信號的數目，故可使半導體積體電路 裝置的晶片低面積化。C: \ Progr Coffee Files \ Patent \ 7008-2184-P.ptd page 18 4270 65 V. Description of the invention (16)-The same effect can be obtained for independent signals. Sixth Embodiment FIG. 8 is a circuit diagram showing a semiconductor integrated circuit device according to a sixth embodiment of the present invention. This sixth embodiment is shown in FIG. 7 to make the p-channel MOSFET smaller than the p-channel MOSFETs 53 and 54. The threshold value of the threshold voltage is the same as the p-channel MOSFET (p-channel MOSFET) 101 of the P-channel MOSFETs 2, 3 and the like. When the two-input NAND gate 1 and the lock circuit 20 are not used (when not enabled), the gate signal that controls the “H” level of the P-channel MOSFET 101 is set to be higher than the potential of the power source 51 . As described above, according to the sixth embodiment, the leakage current during the non-conduction of the P-channel M0SFET1 01 can be reduced in the same manner as the fifth embodiment. At the same time, the P-channel MOSFET 101 with a small absolute value of the threshold voltage can be turned on. The amount of current is larger than that of the fifth embodiment, so that the size of the p-channel MOSFET 101 can be reduced, and thus the wafer size of the semiconductor integrated circuit device can be reduced. Seventh Embodiment FIG. 9 is a circuit diagram showing a semiconductor integrated circuit device according to a seventh embodiment of the present invention. In the drawing, the P channel MOSFETs 6, 53 are controlled by a common control signal 9, and The common control signal 13 whose signal 9 is inverted is used to control the P-channel MOSFET 54 and the N-channel MOSFET 10. The other structures are the same as those of the fifth embodiment, and their repeated description is omitted. As described above, according to the seventh embodiment, the effects of the fifth embodiment are not degraded, but the number of control signals can be reduced, so that the area of a chip of a semiconductor integrated circuit device can be reduced.

C:\ProgramFUes\Patent\7008-2184-P.ptd第 19 頁 4270 65 五、發明說明（17) ' 第八實施例 第10圖係顯示依據本發明之H施例之半導體積體 電路裝置的電路圖’如3圖所示，此第八實施例係於第9圖 中將二極體31、33串聯，且將二極體32、34串聯。 如上述’依據此第八實施例，藉由將二個二極體串 聯，而如第二實施例所示，於不使用時，可較第六實施例 更減低漏電電流。 第九實施例 第11圖係顯示依據本發明之第九實施例之半導體積體 電路裝置的電路圖，如第5圖所示，此第九實施例係於第 11圖中將P通道M0SFET35、36串聯’且將N通道MOSFET37、 3 8串聯。 如上述，依據此第九實施例，不必要設置特殊的二極 體元件’而可僅以M0SFET來構成全電路，進而可易於製 造。 第十實施例 第1 2圖係顯示本發明之第十實施例之半導體積體電路 裝置的電路圖，此第十實施例係於第5圖中使P通道 MOSFET35、36成為臨限電壓之絕對值大的p通道 MOSFET(MOSFET) 11 1及臨限電壓之絕對值小的p通道 M0SFET(M0SFET)112、113，且使 N 通道 M0SFET37、38 成為C: \ ProgramFUes \ Patent \ 7008-2184-P.ptd page 19 4270 65 V. Description of the invention (17) 'Eighth embodiment Fig. 10 shows a semiconductor integrated circuit device according to the H embodiment of the present invention. As shown in FIG. 3, the eighth embodiment is a circuit diagram in which diodes 31 and 33 are connected in series and diodes 32 and 34 are connected in series in FIG. 9. As described above, according to the eighth embodiment, by connecting two diodes in series, as shown in the second embodiment, when not in use, the leakage current can be further reduced compared to the sixth embodiment. Ninth Embodiment FIG. 11 is a circuit diagram showing a semiconductor integrated circuit device according to a ninth embodiment of the present invention. As shown in FIG. 5, this ninth embodiment is shown in FIG. In series' and the N-channel MOSFETs 37, 38 are connected in series. As described above, according to this ninth embodiment, it is not necessary to provide a special diode element ', and the entire circuit can be constituted by only the MOSFET, and it can be easily manufactured. Tenth Embodiment FIG. 12 is a circuit diagram showing a semiconductor integrated circuit device of a tenth embodiment of the present invention. This tenth embodiment is shown in FIG. 5 in which the P-channel MOSFETs 35 and 36 are absolute values of the threshold voltage. The large p-channel MOSFET (MOSFET) 11 1 and the p-channel M0SFET (M0SFET) 112 and 113 having a small absolute value of the threshold voltage, and the N-channel M0SFET 37 and 38 become

臨限電壓之絕對值小的['1通道叩8[£1'(1408?£1')114、115及 臨限電壓之絕對值小的N通道M0SFET(M0SFET)116 D 如上述，依據此第十實施例，藉由併用臨限電壓之絕The absolute value of the threshold voltage is small ['1 channel 叩 8 [£ 1' (1408? £ 1 ') 114, 115 and the N-channel M0SFET (M0SFET) 116 D with a small absolute voltage threshold is as above, according to this In the tenth embodiment, the threshold voltage is used in combination

C:\Prograra Files\Patent\7008-2184-P.ptd第 20 頁 427065 五、發明說明（18) 對值大的M0SFET及臨限電壓之絕對值小的m〇sfet，而可將 電壓下降值設定成較細，因此，可更精密地達成消耗電力 化。 第十一實施例 第1 3圖係顯示依據本發明之第十—實施例之半導體積 體電路裝置的電路圖’在匕第十一實施例係於第以圖中，自 電源52藉由DC-DC變換器（電麼變換器）57來產生電源51的 電位。 如上述依據此第_[貫施作J，由使電源5 1較電源5 2 低電壓，故DC-DC變換F57係士、& ^ 兴盜…保成為以高電壓為輸入而低電 壓為輸出的低電壓產生電路，而技丄^ ^, 电吩而耠由來自外部的電源輸入 僅當作電源52的單一電源，進而死_ Λ# η ^说 <句可仵到與第五實施例同樣 的效果》 第十二實施例 第14圖係顯示依據本發明之第十二實施例之半導體積 nr 路裝置電路圖’此第十二實施例係自電源51藉由 DC-DC變換器（電壓變換器)58來產生電源52的電位。 如上述，依據此第十二實尬 ,_ c 夏施例’由使電源5 1較電源52 低電壓’故DC-DC變換器58传出达 π 1 μ 1 μ + +成為以低電壓為輸入而高電 而碡由來自外部的電源輸入 僅當作電源52的單一電源，淮而 认&β 鄉進而可得到與第五實施例同樣 的效果。 第十三實施例 第15圖係顯示依據本發明之结 β之第十三實施例之半導體積C: \ Prograra Files \ Patent \ 7008-2184-P.ptd page 20 427065 V. Description of the invention (18) The value of the M0SFET with a large value and the absolute value of the threshold voltage with a small absolute value of m0sfet can decrease the voltage. Since it is set thinner, power consumption can be made more precise. Eleventh Embodiment FIG. 13 is a circuit diagram showing a semiconductor integrated circuit device according to the tenth embodiment of the present invention. In the eleventh embodiment, the first embodiment is shown in the figure, from the power source 52 through DC- A DC converter (electrical converter) 57 generates a potential of the power source 51. According to the above, according to the _ [Constant implementation of J, since the power supply 5 1 is lower than the power supply 5 2, the DC-DC conversion F57 series, & ^ thieves ... Guaranteed to use high voltage as input and low voltage as The output of the low-voltage generation circuit, and the technology ^ ^, electric phenomenon, and only by the external power input as a single power supply 52, and then die _ Λ # η ^ said < sentence can be related to the fifth implementation The same effect as in the example is shown in the twelfth embodiment. FIG. 14 is a circuit diagram of a semiconductor product nr circuit device according to the twelfth embodiment of the present invention. This twelfth embodiment is a power supply 51 by a DC-DC converter ( Voltage converter) 58 to generate the potential of the power source 52. As mentioned above, according to this twelfth embarrassment, _ c Xia Shi example 'from making the power supply 5 1 lower than the power supply 52', so the DC-DC converter 58 sends out π 1 μ 1 μ + + The input power is high, and the external power supply input is only used as a single power source for the power source 52. Therefore, the same effect as that of the fifth embodiment can be obtained. Thirteenth Embodiment FIG. 15 shows a semiconductor product of the thirteenth embodiment according to the knot β of the present invention.

C:\ProgramFiles\Patent\7008-2184-P. ptd第 21 頁 427065C: \ ProgramFiles \ Patent \ 7008-2184-P. Ptd page 21 427065

體電路裝置的電路圖，在圖令， 於不使用時具有3· 3V之電位的電满於動作時具有1· 〇V而 GND(第二電源）為於動作時且=卓―電源）；11為 2.7V之電位的VA1 _ 8 ; VB1 ·丨\有K〇v而於不使用時具有 使用時具有0.6V之電位的VB1 . 作時具有㈣而於不 η。 ，此專乃與第1圊所示者相 且61為具有與第15圖所示 同之電位的電源（第四電源），Α ^路之次級的電路相 輸入節點’例如輸入第〗圖所示之·、_· ° 62為輸入信號的 路20的輸出信號。之-輸人咖閉1或鎖扣電 63~68 為 Ρ 通道 MOSFFT . RQ ία ^ μ ^ , 、，b9〜74為Ν通這MOSFET ; Ρ通道 MOSFET63、64之臨限電壓的絕對值係被設定成較p通道 MOSFET65-68小。且N通道M0SFET69〜72之臨限電壓的絕對 值係設定成較N通道MOSFET73、74小。 又P通道MOSFET63和N通道MOSFET69以及P通道 MOSFET64 和 N 通道 MOSFET70 均串聯於 VA1 ·8 與 VB1 .12 之 間’且此等Ρ通道M0SFET63、64的基板端子連接於GND11， 同時此等Ν通道MOSFET69、70的基板端子連接於GND11，並 藉由此等電路而自輸入節點62輸入二輸入N AND閘1或鎖扣 電路20的輸出信號，而構成檢測「H」位準或「L」位準的 位準檢測電路。 再者，P通道MOSFET65和N通道MOSFET71以及P通道 MOSFET6 6和N通道MOSFET72均串聯於電源61與VB1 . 12之 間，且此等P通道MOSFET65、66的基板端子連接於電源The circuit diagram of the body circuit device, when the command is not in use, has a potential of 3 · 3V when it is fully charged, and has 1.0 · V when it is in operation, and GND (second power supply) is when it is in operation and = Zhuo-power supply); 11 VA1 _ 8 with a potential of 2.7V; VB1 · 丨 \ with KOV and VB1 with a potential of 0.6V when not in use. It has ㈣ and not η when in operation. This is the phase corresponding to the one shown in Fig. 1 and 61 is a power source (fourth power supply) with the same potential as shown in Fig. 15. The secondary circuit phase input node of the circuit A ^ is for example the input diagram. As shown, ··· ° 62 is the output signal of the channel 20 of the input signal. No.-input 1 or latching 63 ~ 68 is P-channel MOSFFT. RQ ία ^ μ ^,, b9 ~ 74 are N-pass MOSFETs; the absolute value of the threshold voltage of P-channel MOSFETs 63 and 64 is Set smaller than p-channel MOSFETs 65-68. The absolute value of the threshold voltage of the N-channel MOSFETs 69 to 72 is set to be smaller than that of the N-channel MOSFETs 73 and 74. P-channel MOSFET63 and N-channel MOSFET69 and P-channel MOSFET64 and N-channel MOSFET70 are all connected in series between VA1 · 8 and VB1.12 ', and the substrate terminals of these P-channel M0SFET63, 64 are connected to GND11, and these N-channel MOSFET69 The substrate terminals of 70 and 70 are connected to GND11, and through these circuits, the input signal of the two-input N AND gate 1 or the latch circuit 20 is input from the input node 62 to constitute the detection of the "H" level or the "L" level Level detection circuit. Furthermore, the P-channel MOSFET 65 and the N-channel MOSFET 71 and the P-channel MOSFET 66 and the N-channel MOSFET 72 are all connected in series between the power source 61 and VB1.12, and the substrate terminals of these P-channel MOSFETs 65 and 66 are connected to the power source.

C:\Program Files\Patent\7008-2184-P.ptd第 22 頁 4270 6 5 五、發明說明 61 ’同時此等N通道M0SFET71、72的基板端子連接於 GND1 1，並藉由此等電路來構成依據節點77 ' 78的信號而 使位準檢測電路所檢測的位準為「Η」位準的期間變^成 電源6 1的電位，且「L」位準的期間成為VB1 . 1 2的電位的 第一位準變換電路（位準變換電路）。 此外’ P通道MOSFET67和N通道MOSFET73以及p通道 M0SFET6 8和N通道M0SFET74均串聯於電源61與GND11之間， 且此等P通道M0SFET67、68的基板端子連接於電源61，同 時此等N通道M0SFET73、74的基板端子連接於GND11，並藉 由此等電路來構成依據節點79、8〇的信號而使位準檢測電曰 路所檢測的位準為「Η」位準的期間成為電源6丨的電位， 且L」位準的期間變換成GND11的電位，進而自節點79、 80輸出至次級之電路的第二位準變換電路（位準變換電 路）。 、 其次，說明其動作。 在習知的電路中’通常例如以3· 3V等的單一電壓來動 作’而而信號的輸出入位準亦全部為〇~33V，進而在如本 發明之實施例的動作時及不使用時不會造成信號位準的變 化。如第一實施例的第2圖所示，在第一實施例中，例如 於動作時’信號的位準為〇〜丨，而於不使用時為〇. 6〜2. 7V ’故葭將此原樣地輸入至習知之次級的電路，則輸入部 的電路不正常地動作’而造成故障，或流過不必要的〇[電 々IL ’進而增大消耗電力。此第十三實施例的介面電路係用 以防止如此之故障及消耗電力的增大，而將第一實施候例C: \ Program Files \ Patent \ 7008-2184-P.ptd page 22 4270 6 5 V. Description of the invention 61 'At the same time, the substrate terminals of these N-channel M0SFETs 71 and 72 are connected to GND1 1 and are connected by these circuits. The period in which the level detected by the level detection circuit is at the "Η" level is changed to the potential of the power source 61 according to the signal of the node 77 '78, and the period at the "L" level becomes VB1. 1 2 Potential first level conversion circuit (level conversion circuit). In addition, the P-channel MOSFET67 and N-channel MOSFET73 and the p-channel M0SFET6 8 and N-channel M0SFET74 are connected in series between the power source 61 and GND11, and the substrate terminals of these P-channel M0SFET67, 68 are connected to the power source 61, and these N-channel M0SFET73 The substrate terminals of 74 and 74 are connected to GND11, and these circuits are used to form signals according to nodes 79 and 80, so that the period when the level detected by the level detection circuit is "Η" becomes a power source 6 丨And the period of L "level is converted to the potential of GND11, and then output from the nodes 79 and 80 to the second level conversion circuit (level conversion circuit) of the secondary circuit. Next, the operation will be described. In conventional circuits, 'usually operates with a single voltage such as 3.3V', and the input and output levels of signals are all 0 to 33V, and thus, when operating as in the embodiment of the present invention and when not in use No change in signal level. As shown in FIG. 2 of the first embodiment, in the first embodiment, for example, the level of the signal is 0 to 丨 when in operation, and 0.6 to 2. 7V ′ when not in use. If this is inputted to a conventional secondary circuit as it is, the circuit of the input section does not operate normally and causes a malfunction, or unnecessary power flows through the electric current [IL] to increase power consumption. The interface circuit of this thirteenth embodiment is to prevent such a failure and increase in power consumption, and the first embodiment

C:\Program Files\Patent\7008-2184-P.ptd第 23 頁 427065 五、發明說明（21) 至第十二實施例的電路所產生的信號穩定地變換成習知電 路的信號位準。 首先，於動作時’輸入節點62成為「H」位準1. 〇v、 「L」位準0V的信號’故藉由p通道M〇SFET63&N通道 MOSFET69所構成的反相電路，而將具有相同信號位準的反 相信號輸出至節點75。此反相信號係藉由p通道M〇sFET64 及N通道MOSFET70所構成的反相電路而再被反相，而以與 節點6 2、7 5相同的信號位準輸出至節點7 6。因此，節點7 5 及節點76成為互補信號’且分別輸入至n通道M〇SFET7i、 72 〇 P通道M0SFET6 5、66係分別連接於電源61與N通道 M0SFET71、72之間’且具有閘極與汲極互相交叉連接的構 成’故節點77 '78的信號位準成為「L」位準〇V、「H」位 準3_3V。因為，若節點75為「H」位準，而節點76為「L」 位準’則N通道M0SFET71成導通狀態，而N通道M0SFET72成 為不導通狀態’故導通77被下拉至「L」位準，其結果，p 通道MOSFET66成為導通狀態，而節點78被上拉至電源65的 3.3V。因此，p通道MOSFET65成為不導通，而節點77被下 拉至VB1 · 12之位準的0V。 若節點75成為「L」位準’而節點76成為「H」位準， 則藉由同樣的動作，而將節點77上拉至電源61的3. 3V，而 卽點78下拉至VB1 ·12的位準。亦即，由p通道m〇sfET65、 66及Ν通道M0SFET71、72所構成的電路係可被當作使「l」 位準成為VB1 .12 ’而「Η」位準成為電源61之位準的信號C: \ Program Files \ Patent \ 7008-2184-P.ptd page 23 427065 V. Description of invention (21) The signals generated by the circuits of the twelfth embodiment are stably transformed into signal levels of conventional circuits. First, at the time of operation, 'the input node 62 becomes a signal of "H" level 1.0V and "L" level 0V'. Therefore, an inverting circuit constituted by a p-channel MOSFET 63 & N-channel MOSFET 69 is used. An inverted signal having the same signal level is output to the node 75. This inverting signal is inverted by an inverting circuit composed of p-channel MOSFET64 and N-channel MOSFET70, and is output to node 76 at the same signal level as nodes 6 2 and 7 5. Therefore, the nodes 7 5 and 76 become complementary signals and are input to the n-channel MOSFETs 7i and 72 〇P-channel MOSFETs 6 and 66, respectively, which are connected between the power source 61 and the N-channel MOSFETs 71 and 72 'and have a gate and The structure of the drain electrodes being connected to each other, therefore, the signal levels of the nodes 77 and 78 become "L" level 0V and "H" level 3_3V. Because if the node 75 is at the “H” level and the node 76 is at the “L” level, then the N-channel M0SFET71 becomes a conducting state, and the N-channel M0SFET72 becomes a non-conducting state. As a result, the p-channel MOSFET 66 is turned on, and the node 78 is pulled up to 3.3V of the power source 65. Therefore, the p-channel MOSFET 65 becomes non-conducting, and the node 77 is pulled down to 0V at the level of VB1 · 12. If the node 75 becomes the "L" level and the node 76 becomes the "H" level, the node 77 is pulled up to 3.3 V of the power source 61 by the same action, and the point 78 is pulled down to VB1 · 12 Level. That is, the circuit system composed of p-channels MOSFET65, 66 and N-channels MOSFETs 71, 72 can be regarded as having the "l" level as VB1.12 'and the "Η" level as the power source 61 level. signal

C:\Program Files\Patent\7008-2184-P.ptd第 24 頁 427065 五、發明說明（22) 予以輸出的位準變換電路。 其次’就P通道MOSFET67、68而言，若節點77成為 「L」位準’而節點78成為「H」位準，則p通道M0SFET67 成為導通狀態，而P通道M0SFET68成為不導通狀態，故導 通79被上拉至「H」位準，其結果，ν通道M0SFET74成為導 通狀態，而節點80被下拉至GND1 1之位準的〇ν。因此，ν通 道MOSFET73成為不導通，而節點79被上拉至電源61之位準 的3_ 3V。若節點77成為「Η」位準，而節點78成為「L」位 準，則藉由同樣的動作，而將節點79下拉至GND 11之位準 的0V ’而節點80上拉至電源61之的位準3· 3V。亦即，由Ρ 通道MOSFET6 7、68及Ν通道M0SFET73、74所構成的電路係 可被當作使「L」位準成為VB1 .12 ’而「η」位準成為電 源61之位準的信號予以輸出的位準變換電路。 如上述，於動作時，第15圖所示的介面電路係被當作 使「L」位準成為VB1 .12的位準，而「H」位準成為vai . 8的位準的信號予以變換成使「l」位準成為GNDn的位 準’而「H」位準成為電源61的位準的位準變換電路而動 作。且不導通狀態的MOSFET係全部使源極的電位與開極的 電位相等而動作，故不會有不必要的DC電流流過，而可實 現低消耗電力的動作。 其次’如第2圖所示，於不使用時，vai .8成為 2. 7V，而VB1，12成為〇. 6V，但是此介面電路的動作係與 上述者相同，而僅内部節點的位準變化。亦即，節點6 2 '、 75、76的電位係於「L」位準成為VB1 . 12的0, 6V，而C: \ Program Files \ Patent \ 7008-2184-P.ptd page 24 427065 V. Description of the invention (22) Level conversion circuit to be output. Secondly, as far as P-channel MOSFETs 67 and 68 are concerned, if node 77 becomes "L" level and node 78 becomes "H" level, p-channel M0SFET67 becomes conductive and P-channel M0SFET68 becomes non-conductive. 79 is pulled up to the “H” level. As a result, the ν channel MOSFET 74 is turned on, and the node 80 is pulled down to 0 ν at the GND1 1 level. Therefore, the v-channel MOSFET 73 becomes non-conducting, and the node 79 is pulled up to 3_3V of the level of the power source 61. If node 77 becomes the "Η" level and node 78 becomes the "L" level, then by the same action, the node 79 is pulled down to 0V 'at the GND 11 level and the node 80 is pulled up to the power source 61 The level is 3.3V. That is, a circuit composed of P-channel MOSFETs 67, 68 and N-channel MOSFETs 73, 74 can be regarded as a signal that makes the "L" level VB1.12 'and the "η" level the level of the power source 61. Output level conversion circuit. As mentioned above, in operation, the interface circuit shown in FIG. 15 is regarded as the signal that changes the level of "L" to VB1.12 and the level of "H" to vai.8. The level conversion circuit operates such that the "1" level becomes the level of GNDn and the "H" level becomes the level of the power source 61. In addition, all non-conducting MOSFETs operate with the source potential equal to the potential of the open electrode, so that no unnecessary DC current flows, and low power consumption operation can be realized. Secondly, as shown in Figure 2, when not in use, vai .8 becomes 2.7V, and VB1,12 becomes 0.6V, but the operation of this interface circuit is the same as the above, and only the level of the internal node Variety. That is, the potentials of the nodes 6 2 ′, 75, and 76 are at the “L” level and become 0, 6V of VB1. 12 and

427065 五、發明說明（23) 「H」位準成為VA1 ‘8的2.7V，其結果，節點77、78的電 位係於「L」位準成為VB1 .12的0.6V，而「H」位準成為 電源61的3.3V。且節點79、70的電位係於「L」位準成^ GND11的0V，而「H」位準成為電源61的3. 3V。又於此時， 於臨限電壓之絕對值小的M0SFET63、64及69〜72係全部施 加反相偏壓於基板，故臨限電壓的絕對值增加，而減低 電電流。再者，其他M0SFET係被設定成大的臨限電壓的嘵 對值’故漏電電流小。因此，於不使用時，此介面電路 與動作時同樣地’被當作使「L」位準成為VB1 . 12的位糸 準，而「H」位準成為VA1 . 8的位準的信號予以變換成使 「L」位準成為GND11的位準’而「H」位準成為電源61的 位準的位準變換電路而動作。此外，亦可抑制於不使用 的漏電電流。 如上述’依據此第十三實施例’介面電路係於動作時 及不使用時兩者’將輸入信號的位準變換成N通道m〇Sfet 成為GND11的位準’而「Η」位準成為電源61的3 3V的信 號，因此，藉由此輸出信號，而可使習知次級的電路^定 地動作《且不導通狀態的M0SFET係全部使源極的電位^閘 極的電位相等而動作，故不會有不必要的DC電流流過，、且 可減低不使用時的漏電電流，而可實現低消耗電力 作。 第十四實施例 第1 6圖係顯示依據本發明之第十四實施例之構成介面 電路之半導體積體電路裝置的電路圖，在圖中，8卜84為？427065 V. Description of the invention (23) The "H" level becomes 2.7V of VA1 '8. As a result, the potentials of nodes 77 and 78 are at the "L" level to 0.6V of VB1.12, and the "H" level It will become 3.3V of power supply 61. And the potentials of the nodes 79, 70 are at 0V of the "L" level to ^ GND11, and the "H" level becomes 3.3V of the power source 61. At this time, the MOSFETs 63, 64, and 69 ~ 72, which have a small absolute value of the threshold voltage, are all applied with a reverse bias voltage to the substrate, so the absolute value of the threshold voltage increases, and the electric current is reduced. In addition, other MOSFETs are set to have a large threshold value of the threshold voltage, so that the leakage current is small. Therefore, when not in use, this interface circuit is the same as when it is in operation. It is regarded as the signal that the "L" level becomes the level of VB1. 12 and the "H" level becomes the level of VA1. 8 The level conversion circuit converts the "L" level to the level of GND11 'and the "H" level to the level of the power source 61 and operates. In addition, it is possible to suppress unused leakage current. As described above according to the 'thirteenth embodiment', the interface circuit is both in operation and when not in use 'to convert the level of the input signal into the N channel m0Sfet to the level of GND11' and the "Η" level becomes The 3 3V signal of the power supply 61, therefore, by outputting the signal, the conventional secondary circuit can be operated steadily. The non-conducting M0SFET system all makes the source potential ^ the gate potential equal. Operation, so no unnecessary DC current flows, and can reduce the leakage current when not in use, and can achieve low power consumption operation. Fourteenth Embodiment FIG. 16 is a circuit diagram showing a semiconductor integrated circuit device constituting an interface circuit according to a fourteenth embodiment of the present invention. In the figure, 8? 84?

26頁 427065 五、發明說明（24) 通道MOSFET ;85~88 為N通道MOSFET ;P通道M0SFET81、82 之臨限電壓的絕對值係被設定成較P通道M0SFET83、84 小。且N通道MOSFET85〜88之臨限電壓的絕對值係設定成較 N 通道MOSFET69、70 大 ° 且P通道MOSFET81和N通道MOSFET85以及P通道 M0SFET82和N通道M0SFET86均串聯於VA1 ·8與GND11之間， 且此等Ρ通道MOSFET81、82的基板端子連接於電源27，同 時此等Ν通道M0SFET85、86的基板端子連接於(JND11，並藉 由此等電路來構成依據節點8 9、9 1的信號而使位準檢測電 路所檢測的位準為「H j位準的期間成為VA1 . 8的電位， 且「L」位準的期間變換成GND11的電位的第三位準變換電 路（位準變換電路）。 ' 又Ρ通道MOSFET83和Ν通道MOSFET87以及ρ通道 MOSFET84和Ν通道MOSFET88均串聯於電源61與“^丨之間， 且此等Ρ通道M0SFET83、84的基板端子連接於電源61，同 時此等Ν通道MOSFET87、88的基板端子連接於gndii，並藉 由此等電路來構成依據節點91、92的信號而使位準檢測電 路所檢測的位準為「Η」位準的期間成為電源61的電位， 且「L」位準的期間變換成GND11的電位，進而自節點93、 94輸出至次級之電路的第四位準變換電路（位準變換 路）。 其他的構造係與第十三實施例相同，故省略其重 m 〇 ' 其次’說明其動作。Page 26 427065 V. Description of the invention (24) Channel MOSFET; 85 ~ 88 are N-channel MOSFETs; the absolute value of the threshold voltage of P-channel M0SFET81, 82 is set to be smaller than that of P-channel M0SFET83, 84. And the absolute value of the threshold voltage of N-channel MOSFETs 85 ~ 88 is set to be larger than N-channel MOSFETs 69 and 70, and P-channel MOSFET 81 and N-channel MOSFET 85 and P-channel M0SFET82 and N-channel M0SFET86 are connected in series between VA1 · 8 and GND11 The substrate terminals of these P-channel MOSFETs 81 and 82 are connected to the power source 27, and the substrate terminals of these N-channel MOSFETs 85 and 86 are connected to (JND11), and the signals according to nodes 8 9, 9 1 are formed by these circuits. A third level conversion circuit (level conversion) that makes the period detected by the level detection circuit "H j level become the potential of VA1.8, and the period of" L "level is converted to the potential of GND11 Circuit). The P-channel MOSFET 83 and the N-channel MOSFET 87 and the p-channel MOSFET 84 and the N-channel MOSFET 88 are all connected in series between the power source 61 and "^ 丨, and the substrate terminals of these P-channel MOSFETs 83 and 84 are connected to the power source 61, and at the same time, The substrate terminals of the N-channel MOSFETs 87 and 88 are connected to gndii, and the circuits are used to form signals according to the nodes 91 and 92 so that the level detected by the level detection circuit becomes "Η". Electricity And the period of the "L" level is converted to the potential of GND11, and then output from the nodes 93 and 94 to the fourth level conversion circuit (level conversion circuit) of the secondary circuit. Other structures are implemented in the thirteenth implementation. The example is the same, so the weight m o is omitted, and the operation will be described next.

427065 五、發明說明（25) 第16圖所不的介面電路係於第15圖所示的介面電路 中，將設於後級的第二位準變換電路設於前級，以當作第 3準變換且將設於前級的第二 後級，以當作第四位準變換電路。 干雙供也 ,因此’在設於前級的第三位準變換電路中，使位準檢 測電路所檢測的位準為「Η ^ ΑΑ «η ΒΒ 〇 ^增& Η」位準的期間成為Μ i . 8的電 」.’、期間變換成GND1 1的電位。且在設於後 級的第四位準變換電路中，估 為「H」位準的期間成：電二位丄檢/電路賴測的位準 取馬電源6 1的電位，且「L ,位準的期 間變換成GND11的電位。 」 如上述’依據此第十四實施例，介面電路係吁得到與 第十-實施例相同的信號來當作輸出信號，且藉由此輸出 信號，而可使習知次級的.電路穩定地動作。又不導通狀態 的M0SFET係全部使源極的電位與開極的電位相等而動作， 故不會有不必要的DC電流流過’ 2可減低不使用時的漏電 電'"IL ’而可實現低消耗電力的動作。 【發明效果】 如上述’依據本發a月’可減低順序電路的漏電電流’ 同時全部在目前的狀態下保持此順序電路之記憶節點的電 位’而可防止記憶節點的資料消失。 依據本發明，藉由構成順序電路之小臨限電壓的 M0SFET，而可高速地動作。 依據本發明，可施加強的反相偏壓於構成順序電路的 M0SFET，而可極度地減低此順序電路的漏電電流，同時可427065 V. Description of the invention (25) The interface circuit not shown in Figure 16 is in the interface circuit shown in Figure 15, and the second level conversion circuit provided in the subsequent stage is set in the previous stage as the third stage. The quasi-conversion and the second post-stage set in the previous stage are regarded as the fourth-level quasi-conversion circuit. Dry dual supply also, so 'in the third level conversion circuit provided in the previous stage, the level detected by the level detection circuit is set to a period of "Η ^ ΑΑ« η ΒΒ 〇 ^ Increase & Η " The electric voltage "." Of M i. 8 is converted to the potential of GND1 1 during the period. And in the fourth level conversion circuit provided in the subsequent stage, the period estimated as the “H” level is: the level of the electrical two-bit detection / circuit measurement takes the potential of the horse power source 61, and “L, The period of the level is converted to the potential of GND11. "As described above, 'According to the fourteenth embodiment, the interface circuit calls for the same signal as the tenth embodiment to be used as an output signal, and by using this output signal, The conventional secondary circuit can be operated stably. The non-conducting M0SFETs all operate with the source potential equal to the potential of the open electrode, so no unnecessary DC current flows. '2 can reduce leakage current when not in use' " IL 'and can Achieve low power consumption operation. [Effects of the Invention] As described above, the “leakage current of the sequential circuit” can be reduced according to the above-mentioned “a month” and the potential of the memory node of the sequential circuit is maintained in the current state, thereby preventing the data of the memory node from disappearing. According to the present invention, a MOSFET with a small threshold voltage constituting a sequential circuit can operate at high speed. According to the present invention, a strong reverse bias voltage can be applied to a MOSFET constituting a sequential circuit, and the leakage current of the sequential circuit can be extremely reduced, and meanwhile,

4k7G65 五、發明說明（26) 防止記憶節點的資料消失。 依據本發明，藉由電壓變換器而可容易地產生第一電 源的二種類的電位 依據本發明，僅附加第二及第三P通道MOSFET之單純 的電路，而不使用電壓變換器，進而可容易地供給第一電 源及第二電源的電位。 依據本發明，可使第一P通道MOSFET的尺寸變小，藉 此而可使半導體積體電路裝置的晶片尺寸變小。 依據本發明，可容易地調整導通電壓，而可更減低順 序電路之不使用時的漏電電流，進而可實現低消耗電力 化。 依據本發明’可容易地調整導通電壓，而可更減低順 序電路之不使用時的漏電電流，進而可實現低消耗電力 化。且不必要設置特殊的二極體元件，而僅以M〇SFET來構 成全電路，進而可容易地製造。 依據本發明，可使可減低閘極信號數目用之半導體積 體電路的晶片低面積化。 依據本發明’藉由併用臨限電壓絕對值大的M〇SFET及 臨限電壓之絕對值小的MOSFET，可設定電壓下降值更細 化，因此可更精密地達成低消耗電力化。 依據本發明，可將來自外部的電源輸入當作第三電 源’而可容易地製造。 【圖式簡單說明】 第1圖係顯示依據本發明之第—實施例之半導體積體4k7G65 V. Description of the Invention (26) Prevent the data of the memory node from disappearing. According to the present invention, two types of potentials of the first power source can be easily generated by the voltage converter. According to the present invention, only the simple circuits of the second and third P-channel MOSFETs are added, without using a voltage converter. The potentials of the first power source and the second power source are easily supplied. According to the present invention, the size of the first P-channel MOSFET can be made smaller, thereby making it possible to make the chip size of the semiconductor integrated circuit device smaller. According to the present invention, the on-voltage can be easily adjusted, and the leakage current when the sequence circuit is not in use can be further reduced, thereby achieving low power consumption. According to the present invention, the on-voltage can be easily adjusted, and the leakage current when the sequence circuit is not in use can be further reduced, thereby achieving low power consumption. Moreover, it is not necessary to provide a special diode element, and only the MOSFET is used to form a full circuit, which can be easily manufactured. According to the present invention, the area of a chip of a semiconductor integrated circuit for reducing the number of gate signals can be reduced. According to the present invention, by using a MOSFET with a large absolute threshold voltage and a MOSFET with a small absolute threshold voltage in combination, the voltage drop value can be set more finely, so that the power consumption can be reduced more precisely. According to the present invention, an external power supply input can be used as the third power supply and can be easily manufactured. [Brief Description of the Drawings] FIG. 1 shows a semiconductor body according to the first embodiment of the present invention.

C:\ProgramFiles\PatentV7008-2184-P.ptd第 29 頁 五、發明說明C27) 電路裝置的電路圖。 第2圖係顯示於第1圖之重要部份之電位的時序圖。 第3圖係顯示依據本發明之第二實施例之半導體積體 電路裝置的電路圖。 第4圖係顯示於第3圖之重要部份之電位的時序圖。 第5圖係顯示依據本發明之第三實施例之半導體積體 電路裝置的電路圖。 第6圖係顯示依據本發明之第四實施例之半導體積體 電路裝置的電路圖。 第7圖係顯示依據本發明之第五實施例之半導體積體 電路裝置的電路圖。 第8圖係顯示依據本發明之第六實施例之半導體積體 電路裝置的電路圖。 第9圖係顯示依據本發明之第七實施例之半導體積體 電路裝置的電路圖。 第1 0圖係顯示依據本發明之第八實施例之半導體積體 電路裝置的電路圖。 第11圖係顯示依據本發明之第九實施例之半導體積體 電路裝置的電路圖。 第1 2圖係顯示依據本發明之第十實施例之半導體積體 電路裝置的電路圖。 第1 3圖係顯示依據本發明之第十一實施例之半導體積 體電路裝置的電路圖。 第14圖係顯示依據本發明之第十二實施例之半導體積 C:\ProgramFiles\Patent\7008_2184-P. ptd第 30 頁 427065 五、發明說明（28) 體電路裝置的電路圖。 第1 5圖係顯示依據本發明之第十三實施例之半導體積 體電路裝置的電路圖。 第1 6圖係顯示依據本發明之第十四實施例之半導體積 體電路裝置的電路圖。 第17圖係顯示依據習知之低電壓動作之半導體積體電 路裝置的電路圖。 第1 8圖係顯示構成習知之順序電路之半導體積體電路 裝置的電路圖。 【符號說明】 6~P通道M0SFET(第一開關元件，第一p通道M0SFET); 8〜供電線（第一供電線）；1〇〜N通道M〇SFET(第二開關元 件’第一N通道M0SFET) ; U〜接地電位節點（第二電源）； 12供電線（第二供電線）；2〇〜鎖扣電路（順序電路）；21、 22~P通道MOSFET23 · 24〜N通道M0SFET ; 27〜電源（第一電 源，第一節點）；31、33~二極體（第一電壓下降電路）； 32、34〜二極體（第二電壓下降電路）；π、36〜P通道 MOSFET(MOSFET，第一電壓下降電路）；37、38〜N通道 MOSFET(MOSFET，第二電壓下降電路）；41、57、58〜dc_dc 變換器（電壓變換器）；51〜電源（第一電源）；52〜電源（第 一電源），53-P通道M0SFET(第二p通道M〇SFET) ; 54〜p通道 M0SFET(第三P通道M0SFET) ;61〜電源（第四電源）；63、 64~P通道M0SFET(位準檢測電路）；65、66p通道 M0SFET(位準變換電路，第一位準變換電路）；67、68邛通 C:\Program Files\Patent\7008-2184-P. ptd 第 3?^ 4270 65 五、發明說明（29) 道MOSFET(位準變換電路，笛― 通道MOSFET(位準檢測電路）、變換電路）’· 69、7〇〜N 總以+妨姑 电路）’ U、72〜N通道MOSFET(位準 S燧拖雷改 位準變換電路）；73、74〜N通道MOSFET(位 準變換電路’第二位準變換電路）；8 MOSFET(位準變換電路，第三位準變換電路）；83魯p通 道MOSFETC位準變換電路，第四位準變換電路）；85、86~n 通道MOSFET(位準變換電路，第三位準變換電路）；87、 88〜N通道MOSFET(位準變換電路，第四位準變換電 路）10 卜P 通道MOSFET(第一p 通道MOSFET) ; 111 至113~P 通 道MOSFET(MOSFET) ;114 至 116〜N 通道MOSFET(MOSFET)。C: \ ProgramFiles \ PatentV7008-2184-P.ptd page 29 5. Description of the invention C27) The circuit diagram of the circuit device. Figure 2 is a timing diagram showing the potentials of the important parts of Figure 1. Fig. 3 is a circuit diagram showing a semiconductor integrated circuit device according to a second embodiment of the present invention. FIG. 4 is a timing chart showing the potentials in the important part of FIG. 3. Fig. 5 is a circuit diagram showing a semiconductor integrated circuit device according to a third embodiment of the present invention. Fig. 6 is a circuit diagram showing a semiconductor integrated circuit device according to a fourth embodiment of the present invention. Fig. 7 is a circuit diagram showing a semiconductor integrated circuit device according to a fifth embodiment of the present invention. Fig. 8 is a circuit diagram showing a semiconductor integrated circuit device according to a sixth embodiment of the present invention. Fig. 9 is a circuit diagram showing a semiconductor integrated circuit device according to a seventh embodiment of the present invention. Fig. 10 is a circuit diagram showing a semiconductor integrated circuit device according to an eighth embodiment of the present invention. Fig. 11 is a circuit diagram showing a semiconductor integrated circuit device according to a ninth embodiment of the present invention. Fig. 12 is a circuit diagram showing a semiconductor integrated circuit device according to a tenth embodiment of the present invention. Fig. 13 is a circuit diagram showing a semiconductor integrated circuit device according to an eleventh embodiment of the present invention. FIG. 14 is a circuit diagram showing a semiconductor product C: \ ProgramFiles \ Patent \ 7008_2184-P. Ptd page 30 427065 according to the twelfth embodiment of the present invention. V. Description of the invention (28) A circuit diagram of a body circuit device. Fig. 15 is a circuit diagram showing a semiconductor integrated circuit device according to a thirteenth embodiment of the present invention. Fig. 16 is a circuit diagram showing a semiconductor integrated circuit device according to a fourteenth embodiment of the present invention. Fig. 17 is a circuit diagram showing a semiconductor integrated circuit device operating according to a conventional low voltage. Fig. 18 is a circuit diagram showing a semiconductor integrated circuit device constituting a conventional sequential circuit. [Symbol description] 6 ~ P channel M0SFET (first switching element, first p channel M0SFET); 8 ~ power supply line (first power supply line); 10 ~ N channel M0SFET (second switching element 'first N Channel M0SFET); U ~ ground potential node (second power supply); 12 power supply line (second power supply line); 20 ~ lock circuit (sequence circuit); 21, 22 ~ P channel MOSFET23 · 24 ~ N channel M0SFET; 27 ~ power supply (first power supply, first node); 31,33 ~ diode (first voltage drop circuit); 32,34 ~ diode (second voltage drop circuit); π, 36 ~ P channel MOSFET (MOSFET, first voltage drop circuit); 37, 38 ~ N channel MOSFET (MOSFET, second voltage drop circuit); 41, 57, 58 ~ dc_dc converter (voltage converter); 51 ~ power supply (first power supply) ; 52 ~ power supply (first power supply), 53-P channel M0SFET (second p channel M0SFET); 54 ~ p channel M0SFET (third P channel M0SFET); 61 ~ power supply (fourth power supply); 63, 64 ~ P channel M0SFET (level detection circuit); 65, 66p channel M0SFET (level conversion circuit, first level conversion circuit); 67, 68 邛 pass C : \ Program Files \ Patent \ 7008-2184-P. Ptd No. 3? ^ 4270 65 V. Description of the invention (29) Channel MOSFET (level conversion circuit, flute-channel MOSFET (level detection circuit), conversion circuit) ' · 69, 7〇 ~ N always use + nugu circuit) 'U, 72 ~ N channel MOSFET (level S 燧 mine torpedo level conversion circuit); 73, 74 ~ N channel MOSFET (level conversion circuit's first 2 level conversion circuit); 8 MOSFET (level conversion circuit, third level conversion circuit); 83 Lu p-channel MOSFETC level conversion circuit, fourth level conversion circuit); 85, 86 ~ n channel MOSFET (bit Quasi conversion circuit, third level conversion circuit); 87, 88 ~ N channel MOSFET (level conversion circuit, fourth level conversion circuit) 10 b P channel MOSFET (first p channel MOSFET); 111 to 113 ~ P Channel MOSFET (MOSFET); 114 to 116 ~ N channel MOSFET (MOSFET).

C:\PrograraFiles\Patent\7008-2184-P.ptd第 32 頁C: \ PrograraFiles \ Patent \ 7008-2184-P.ptd page 32

Claims (1)

4 2 7 Ο 6 5 案號 R71lRri9/( 補充 六、申請專利範圍 第一開關元件，連接於此第一電源與第一供電線之 1- 一種半導體積體電路裝置，包括： 第—電源’具有較第二電源高的電位 間； 第二開關元件，連接於上述第二電源與第二供電線之 間； 第一電壓下降電路，連接於上述第一電源與第一供電 線之間； 第二電壓下降電路’連接於上述第二電源與第二供電 線之間；以及 順序電路’連接於上述第一供電線與上述第二供電線 之間，且由Ρ通道MOSFET及Ν通道MOSFET所構成，而此ρ通 道MOSFET的基板端子連接於上述第一電源，同時此^通道 MOSFET的基板端子連接於上述第二電源。 2. 如申請專利範圍第1項所述的半導體積體電路裝 置’其中第一開關元件係由具有較構成順序電路之Ρ通道 MOSFET之臨限電壓的絕對值大的臨限電壓的ρ通道JJOSFET 所構成’且第一開關元件係由具有較構成順序電路之Ν通 道MOSFET之臨限電壓的絕對值大的臨限電壓的Ν通道 MOSFET所構成。 3. 如申請專利範圍第1項所述的半導體積體電路裝 置，其中第一電源係具有第一電位與較此第一電位高的第 二電位的雨種類的電位’通常被設定成此第一電位，且第 一開關元件及第二開關元件均於不導通狀態時被設定成第4 2 7 Ο 6 5 Case No. R71lRri9 / (Supplementary VI. Patent application scope First switching element connected to this first power supply and first power supply line 1- A semiconductor integrated circuit device comprising: A potential higher than the second power source; a second switching element connected between the second power source and the second power supply line; a first voltage drop circuit connected between the first power source and the first power supply line; the second The voltage drop circuit is connected between the second power supply and the second power supply line; and the sequence circuit is connected between the first power supply line and the second power supply line, and is composed of a P-channel MOSFET and an N-channel MOSFET. The substrate terminal of the p-channel MOSFET is connected to the above-mentioned first power source, and at the same time, the substrate terminal of this p-channel MOSFET is connected to the above-mentioned second power source. A switching element is constituted by a p-channel JJOSFET having a threshold voltage that is larger than the absolute value of the threshold voltage of a P-channel MOSFET constituting a sequential circuit ', and the first switching element It is composed of an N-channel MOSFET with a threshold voltage larger than the absolute value of the threshold voltage of the N-channel MOSFET constituting the sequential circuit. 3. The semiconductor integrated circuit device according to item 1 of the scope of patent application, wherein A power system having a first potential and a second potential higher than the first potential of the rain type is usually set to this first potential, and the first switching element and the second switching element are both turned off when they are not conducting. Set as 第33頁 1999.11.15.033 427065 _____年 fi 曰一_堡孟_____ 六、申請專舰® --- 二電位。 4·如申請專利範圍第2項所述的半導體積體電路裝 置’其中第一電源係具有第一電位與較此第一電位高的第 二電位的兩種類的電位，通常被設定成此第一電位，且第 一開關το件及第二開關元件均於不導通狀態時被設定成第 二電位。 5. 如申凊專利範圍第3項所述的半導體積體電路裝 置’、中第—電源的兩種類的電位係自一電源由電壓變換 器所產生。 6. 如中請專利範圍第4項所述的半導體積體電路裝 f ’其中第一電源的兩種類的電位係自一電源由電壓變換 器所產生。 7. 種半導體積體電路裝置，包括： 第電源’具有較第二電源高的電位； 第二電源，具有較此第一電源高的電位； 第一P通道M0SFET，連接於此第一電源與第一供電線 之間； ‘ 第二P通道M0SFET，連接於上述第一電源與第一節點 之間； 第三P通道M0SFET，連接於上述第一節點與上述第三 電源之間； 第一N通道M0SFET，連接於上述第二電源與第二供電 線之間； 第一電壓下降電路，連接於卜、+、结 ^ _ 迓接於上述苐一節點與第一供電Page 33 1999.11.15.033 427065 _____year fi is a _ baomeng _____ Six, apply for special ship ® --- two potential. 4. The semiconductor integrated circuit device according to item 2 of the scope of the patent application, wherein the first power source has two types of potentials having a first potential and a second potential higher than the first potential, and is usually set to the first potential. A potential, and the first switching element and the second switching element are both set to a second potential when they are not conducting. 5. As described in item 3 of the patent application, the semiconductor integrated circuit device 'and the first two types of potentials of the power source are generated from a power source by a voltage converter. 6. The semiconductor integrated circuit device f 'described in item 4 of the Chinese Patent Application, wherein the two types of potentials of the first power source are generated from a power source by a voltage converter. 7. A semiconductor integrated circuit device comprising: a first power source having a higher potential than a second power source; a second power source having a higher potential than the first power source; a first P-channel MOSFET connected to the first power source and Between the first power supply line; 'the second P-channel MOSFET is connected between the first power supply and the first node; the third P-channel MOSFET is connected between the first node and the third power supply; the first N The channel M0SFET is connected between the second power supply and the second power supply line; the first voltage drop circuit is connected to the bus, +, and junction ^ _ 迓 is connected to the first node and the first power supply 一年 月 修正 4 2 70 6 5^ 六、申請專利範圍 線之間； 第二電壓下降電路’連接於上述第二電源與第二雨 線之間；以及 — 順序電路’連接於上述第一供電線與上述第二供電線 之間’且由具有較上述第一至第三p通道M〇SFET之臨限電 壓的絕對值小的臨限電壓的p通道M〇SFET及具有較上述第 一N通道M0SFET之臨限電壓的絕對值小的臨限電壓的^通道 M0SFET所構成，而此p通道M〇SFET的基板端子連接於上述 第一節點，同時通道M0SFET的基板端子連接於上 二電源。 ^ 8·如申請專利範圍第7項所述的半導體積體電路裝 置，其中第一P通道M0SFET係具有較上述第二及三p通 M0SFET之臨限電壓的絕對值小的臨限電壓，且 ?通道_以之「H」位準之閘極信號的電位被 ^ 一電源的電位高。 义战敉弟 9. 如申請專利範圍第i、2、3、4、5、6 體積體電路裳置，其中第一及第二電壓下或降 由氐意個一極體元件串聯的電路所構成。 10. 如申請專利範圍第i、2、3、4、5、6、7或 ，的半導體積體電路裝置，其中第一及第二電壓下降電路 :ί 的閑極與汲極相連而串聯任意個此膽fet的 置二請/利範圍第7項所述的半導體積體電路裝 置，其中“!第—和第二P通道M〇sm的間極信號及控制 1999.11.15.035 427065 ___室號87115024__年田 g_修正____ 六、申請專利範圍 第三P通道M0SFET和第一N通道M0SFET的開極信號中之至少 —者為相同的閘極信號。 1 2.如申請專利範圍第1 〇項所述的半導體積體電路裝 置’其中第一和第二電壓下降電路中至少一者係由臨限電 壓之絕對值不同的M0SFET所構成。 13·如申請專利範圍第7項所述的半導體積體電路裝 置’其中第一電源係自第三電源由電壓變換器所產生。 14. 如申請專利範圍第7項所述的半導體積體電路裂 置，其中第二電源係自第一電源由電壓變換器所產生。 15. —種半導體積體電路裝置，包括： 第一供電線耦接至第一節點； 第二供電線； 第一P通道M0SFET耦接於上述第一節點和上述第二供 電線之間，以提供第一電位給上述第二供電線； 邏輯電路耦接至上述第二供電線，依上述第二供 之第一電位而動作；上述邏輯電路包括第通道’、 M0SFET ,上述第二p通道M0SFET之基板電極耦 一供電線；以及 工处弟 電壓產生電路耦接於上 產生第二電位，且當上述第 提供上述第二電位給上述第 上述第一供電線之電位。 述第一和第二供電線之間，以 一P通道M0SFET不導通時，則 二供電線；上述第二電位小於 ]6.如申請專利範圍第15項所 猙，装φ， 诂啻蔽方江办 ^心千^篮積體電路裝 置，兵T，上迷電壓產生電路句紅 加-把ΛΑ 匕括一個一極體、或複數個One year and month correction 4 2 70 6 5 ^ VI. Between patent application lines; second voltage drop circuit 'connected between the second power supply and the second rain line; and-sequence circuit' connected to the first supply Between the electric wire and the above-mentioned second power-supply line, and having a threshold voltage smaller than the absolute value of the threshold voltage of the first to third p-channel MOSFET The threshold voltage of the channel M0SFET is smaller than the threshold voltage of the channel M0SFET, and the substrate terminal of the p-channel MOSFET is connected to the first node, and the substrate terminal of the channel M0SFET is connected to the upper power supply. ^ 8. The semiconductor integrated circuit device according to item 7 of the scope of the patent application, wherein the first P-channel MOSFET has a threshold voltage smaller than the absolute value of the threshold voltage of the second and three p-pass MOSFETs, and ? Channel_ The potential of the gate signal at the "H" level is ^-the potential of the power supply is high. Volunteers 9. If the scope of application for patents is i, 2, 3, 4, 5, 6, the volume body circuit is installed, where the first and second voltages are lowered or lowered by a circuit body of a unipolar element in series Make up. 10. If the semiconductor integrated circuit device i, 2, 3, 4, 5, 6, 7, or 5 in the scope of the patent application, the first and second voltage drop circuits: the idle pole of the ί is connected to the drain and connected in series arbitrarily The semiconductor integrated circuit device described in item 7 of the above-mentioned application / interest range, wherein the "!-And the second P channel M0sm interphase signal and control 1999.11.15.035 427065 ___room number 87115024__ 年 田 g_MODIFY__ VI. Patent application scope At least one of the open-pole signals of the third P-channel M0SFET and the first N-channel M0SFET is the same gate signal. 1 2. If the scope of patent application is the first The semiconductor integrated circuit device according to item 〇, wherein at least one of the first and second voltage drop circuits is composed of MOSFETs having different absolute values of threshold voltages. 13. As described in item 7 of the scope of patent application "Semiconductor integrated circuit device" wherein the first power source is generated by a voltage converter from a third power source. 14. The semiconductor integrated circuit described in item 7 of the patent application is split, and the second power source is from the first power source Produced by a voltage converter. The conductive body circuit device includes: a first power supply line coupled to a first node; a second power supply line; a first P-channel MOSFET is coupled between the first node and the second power supply line to provide a first potential The second power supply line is provided; the logic circuit is coupled to the second power supply line and operates according to the first potential of the second supply; the logic circuit includes a substrate electrode coupling of the first channel ', M0SFET, and the second p-channel M0SFET. A power supply line; and a voltage generating circuit of the office is coupled to generate a second potential, and when the first provides the second potential to the potential of the first first power supply line; between the first and second power supply lines; When a P-channel M0SFET is not conducting, then two power supply lines; the above-mentioned second potential is less than] 6. Install φ as shown in item 15 of the scope of patent application, and shield the Fangjiang Office ^ heart thousand ^ basket integrated circuit Device, soldier T, add voltage-generating circuit sentence red plus-put ΛΑ dagger on a pole, or plural 4 2 ~7 Ο 6 5 案號 87115〇24_年月 曰-一__it£：--- 六、申請專利範圍 串接之二極體。 17. 如申請專利範圍第15項所述之半導體積體電路裝 置，其中，上述電壓產生電路包括一個MOSFET、或複數個 串接之MOSFET。 18. 如申請專利範圍第15項所述之半導體積體電路裝 置，其中，上述電壓產生電路包括複數個串接之MOSFET ; 在上述複數個MOSFET中，至少有，個MOSFET之臨界電壓絕 對值小於其餘MOSFET的臨界電壓絕對值。 19. 如申請專利範圍第15項所述之半導體積體電路裝 置’其中，當上述第一p通道MOSFET導通時，上述第一供 電線具有第一電位，當上述第一p通道MOSFET不導通時， 上述第一供電線具有大於上述第一電位之第三電位。 20. 如申請專利範圍第19項所述之半導體積體電路裝 置，更包括： 第三Ρ通道MOSFET耦接於上述第一節點和上述第一供 電線之間； 第四p通道MOSFET耦接於第二節點和上述第一供電線 之間，上述第三和第四p通道MOSFET係互補交替地導通， 其中，上述第一電位係施加給上述第一節點，上述第三電 位係施和給上述第二節點。 21. 如申請專利範圍第2〇項所述之半導體積體電路裝 置，其中’上述第一p通道MOSFET臨界電壓之絕對值不同 於上述第三p通道MOSFET臨界電壓之絕對值。 22. 如申請專利範圍第21項所述之半導體積體電路裝4 2 ~ 7 Ο 6 5 Case No. 87115〇24_Year Month--__ it £: --- VI. Patent Application Scope Diodes connected in series. 17. The semiconductor integrated circuit device according to item 15 of the scope of patent application, wherein the voltage generating circuit includes a MOSFET or a plurality of MOSFETs connected in series. 18. The semiconductor integrated circuit device according to item 15 of the scope of the patent application, wherein the voltage generating circuit includes a plurality of MOSFETs connected in series; among the plurality of MOSFETs, at least, the absolute value of the threshold voltage of the MOSFETs is less than Absolute threshold voltage of other MOSFETs. 19. The semiconductor integrated circuit device according to item 15 of the scope of patent application, wherein when the first p-channel MOSFET is turned on, the first power supply line has a first potential, and when the first p-channel MOSFET is not turned on The first power supply line has a third potential that is greater than the first potential. 20. The semiconductor integrated circuit device described in item 19 of the scope of patent application, further comprising: a third p-channel MOSFET is coupled between the first node and the first power supply line; a fourth p-channel MOSFET is coupled between Between the second node and the first power supply line, the third and fourth p-channel MOSFETs are turned on complementary and alternately, wherein the first potential is applied to the first node, and the third potential is applied to the first node. Second node. 21. The semiconductor integrated circuit device according to item 20 of the scope of patent application, wherein the absolute value of the threshold voltage of the first p-channel MOSFET is different from the absolute value of the threshold voltage of the third p-channel MOSFET. 22. The semiconductor integrated circuit device as described in the scope of patent application No. 21 第37頁 1999.11. 15. 〇37 42 70 6 5案號__年月 日 佟t__ 六、申請專利範圍 置，其中，上述第一及第三p通道W0SFET中，當具有較高 臨f電壓絕對值之p通道M〇SFET導通時，則其閘極上施加 有高於上述第一電位之特定電位。 23. 如申請專利範圍第15項所述之半導體積體電路裝 置’其中’上述邏輯電路係為組合邏輯電路、或是順序邏 輯電路。 24. 如申請專利範圍第15項所述之半導體積體電路裝 置’更包括： 第一反向器接收上述邏輯電路之輸出信號，用以將上 述輸出信號之邏輯值反向而輸出第—信號； 不一反向器接收上述第一反向器輸出之第一信號，用 以將上述第一信號之邏輯值反向而輸出第二信號； ' 第二供電線’其上施加有第四電位；以及 位準轉換電路雜接至上述第三供電線，用以將對應於 上述第一和第二信號之一的H位準電位轉換為另一H位準電 位’上述另一 Η位準電位和上述第四電位相同。 25·如申請專利範圍第24項所述之半導體積體電路裝 置’其中’上述第一反向器包括：第五1)通道}#1〇別£11，上 述第五Ρ通道M0SFET具有源極耦接至上述第二供電線、及 與上述第一供電線耦接之基板電極： 上述第二反向器包括：第六Ρ通道M0SFET，上述第六ρ 通道M0SFET具有源極耦接至上述第二供電線、及與上述 一供電線耦接之基板電極。 26.如申請專利範圍第24項所述之半導體積體電Page 37 1999.11. 15. 〇37 42 70 6 5 Case No. __ month month date t__ Sixth, the scope of application for patents is set, in which the first and third p-channel WSFETs, when having a higher absolute f voltage absolute When the value of the p-channel MOSFET is turned on, a specific potential higher than the above-mentioned first potential is applied to its gate. 23. The semiconductor integrated circuit device according to item 15 of the scope of the patent application, wherein the logic circuit is a combination logic circuit or a sequential logic circuit. 24. The semiconductor integrated circuit device described in item 15 of the scope of the patent application further includes: a first inverter receiving the output signal of the logic circuit to invert the logic value of the output signal and output a first signal ; Different inverters receive the first signal output by the first inverter, and are used to invert the logic value of the first signal to output a second signal; a second potential is applied to the second power supply line; And a level conversion circuit coupled to the third power supply line to convert the H-level potential corresponding to one of the first and second signals to another H-level potential, and to the other H-level potential. Same as the fourth potential. 25. The semiconductor integrated circuit device described in item 24 of the scope of the patent application, wherein the above-mentioned first inverter includes: the fifth 1) channel} # 1〇Do not £ 11, the fifth P-channel M0SFET has a source The second electrode is coupled to the second power supply line and the substrate electrode coupled to the first power supply line: The second inverter includes a sixth P-channel M0SFET, and the sixth p-channel M0SFET has a source coupled to the first Two power supply lines, and a substrate electrode coupled to the first power supply line. 26. The semiconductor integrated circuit described in item 24 of the scope of patent application 第38頁 1999.11.15. 038 修正Page 38 1999.11.15.038 correction 、申請專利範圍 其中，上述位準轉換電路包括： 第七P通道MOSFET，並Α 極耗接第三節，點，以及；第原四極么接/述第三_ 八.、弟四即點耦拯. 第八Ρ通道MOSFET，其源極接之閉極， 極耦接上述第四節點，以及盥上.、+接上述第二供電線，汲 第一η通道MOSFET耦接至上械 二_即點耗接之閑極； 至上述第一反向器之輸出；〜二即點’其閘極耦接 第二η通道M0SFET耦接至上塊敏 ^ 至上述第二反向器之輸出； 四節點，其閘極耦接 其中，具有上述另一H位準電 ^ 和弟四節點之一所輸出。 之說係由上述第三2. The scope of the patent application includes the above-mentioned level conversion circuit including: the seventh P-channel MOSFET, and the A pole is connected to the third section, the point, and; The eighth P-channel MOSFET, whose source is connected to the closed electrode, is connected to the fourth node, and connected to the second power supply line, and the first n-channel MOSFET is coupled to the upper two. The idle pole connected to the point; to the output of the first inverter; the second point is that its gate is coupled to the second n-channel M0SFET and the output of the second block is connected to the output of the second inverter; four nodes Its gate is coupled to it and has the output of the other H-level voltage and one of the four nodes. The third is 1999. Π. 15.0391999. Π. 15.039
TW087115024A 1997-11-19 1998-09-09 Semiconductor integrated circuit device TW427065B (en)

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