經濟部中央標率局員X消費合作社印聚 42693 3 A7 _ B7 五、發明説明（1 ) 發明背景 本發明與電子半導體裝置有關，且更特別與電容器結 構及製造如此結構之方法有關。 對半導體記憶體需求的增加以及競爭的壓力，需要有 較高密度之以一個電晶體加上一個電容器為基礎的積體電 路動態隨機存取記憶體（DRAM)。但標準矽氧化物及氮介電 質之縮小尺電容器所呈現出的問題包括儲存於胞元中電荷 量的減少。因此，DRAM的製造者正研發其它的介電貧來 增加電容器之介電常數，以及其它胞元的結構以增加電容 器之面積。例如’美國專利申請序號USP 5, 554, 557揭示 一柵棚式電容器DRAM胞元具有粗链多元石夕的低電極以增 加電容器之面積。此專利揭示在560°C分解硅沉積粗糙多 元矽並以約為200毫托（mT)的壓力產生一最大厚度為50-150奈米（nm)之半球顆粒薄層。接著均勻的沉積矽氮化物 介電質、氧化物/氮化物/氧化物、或戊氧基鈕化物，並以 沉積之多元矽的頂部電極完成電容器》Member of the Central Bureau of Standards, Ministry of Economic Affairs, X Consumer Cooperative, 42693 3 A7 _ B7 V. Description of the Invention (1) Background of the Invention The present invention relates to electronic semiconductor devices, and more particularly to capacitor structures and methods of manufacturing such structures. The increasing demand for semiconductor memory and the pressure of competition require higher density integrated circuit dynamic random access memory (DRAM) based on a transistor plus a capacitor. However, problems with standard silicon oxide and nitrogen dielectric downsized capacitors include a reduction in the amount of charge stored in the cell. Therefore, DRAM makers are developing other dielectrics to increase the dielectric constant of capacitors and other cell structures to increase the area of capacitors. For example, 'US Patent Application Serial No. USP 5, 554, 557 discloses that a shed cell DRAM cell has a low electrode with thick chain polylithium to increase the area of the capacitor. This patent discloses decomposing silicon to deposit coarse polysilicon at 560 ° C and producing a thin layer of hemispherical particles with a maximum thickness of 50-150 nanometers (nm) at a pressure of about 200 millitorr (mT). Then uniformly deposit silicon nitride dielectric, oxide / nitride / oxide, or pentoxide button compound, and complete the capacitor with the top electrode of the deposited poly silicon "
Ino 等人於 Rugged Surface Polycrystalline Film Deposition and its Application in a Stacked Dynamic Random Access Memory Capacitor Electrode, 14 J. Vac. Sci Tech. B 751(1996)文中描述（圖14)粗糙多元矽電容器薄層厚度的 範圍*為40-150奈米(nm)，其厚度最佳為lOOiim。 發明概述 本發明提供一厚度小於40奈米之HSG矽層（粗糙 多元矽），但因在單爐操作高成核密度沉積加上氣相 本紙張尺度適用中國國家榇準（CNS ) A4規格（210X297公釐） ^— (請先閲讀背面之注意事項再填寫本頁) 訂 鯉濟部中央標準局員Η消費合作杜印袈 / <- 4 ^89 3 3 a7 〜^______ 五、發明説明（2·) 顆粒外形增進及摻質使其表面面積至少增加2倍《粗 繞多元石夕較佳實施例形成表面面積增進的一（動態記 憶體胞元）電容器電極，且電容器介電質沉積而不將 電極曝露於氧氣源β 圖例簡述 下列圖例用作啟發性之說明》 圖la-b為記憶體胞元較佳實施例之剖面及正視圖。 圖2a-f以剖面正視圓說明一較佳實施例方法步驟。— 圖3a-c說明成核及顆粒。 圖4顯示成核密度。 圓5a-b說明顆粒鼓起》 圖6顯示面積之增進。 較佳實施例之說明 概述 較佳實施例增進電容器電極（極板）面積但使用小顆粒 高密度保持限定厚度的半球的顆粒（HSG)矽（粗糙多元）。 較佳實施例方法首先在條件下形成小顆粒但高面積密度之 HSG矽；其次，氣相增進顆粒加上摻雜HSG矽；且接著立 即形成初始電容器介電質而不曝露於氧氣源。使用小顆粒 HSG石夕限制電谷器電極之實際厚度，使鄰近及多重電容器 電極間得以有較小的間隔。氣相摻雜允許基本顆粒外形增 進但使得表面較易感受不希望的氧化，因此立即開始介電 質之形成而產生了較為不均勻之電容器介電質層。 圓la-b以剖面及平面.正祝圓說明一較隹實施例之多元 -4 - 本紙張尺度通用T囷國家標準（CNS ) A4说格（210X297公釐） ϋ^— I -:11 ml aR. - - - - l--_ I 1 一—r 0¾.-° (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局負工消費合作社印製 42693 3 A7 _________ B7 _ 一 ______ .. 五'發明説明（3 ) 石夕垂直圓柱1〇4(其上具有延伸冠狀外形）具jjSG矽102 之DRAM胞元1〇〇 ,加上多元矽基底1〇5形成電容器胞元 之低電極β介電質1〇6順應HSG矽1〇2的表面及介於HSG 矽顆粒間多元矽1〇4-i〇5的部分。雖然其它如TiN的材料 可使用’多元矽108形成電容器電極的頂部（共同）。通路 電晶體（閘極Π0源極112及汲極114)經由多元矽梗122 連接位元線12〇至低電容器電極；位元線122與圖la之 平面平行，且僅有一分支使之與汲極114接觸如圖h所 示。/主意胞元1〇〇與鄰近胞元1〇〇’間的分隔，是由Η% 1〇2 及HSG 102’間的最小間隔來決定的，且此為頂部電極1〇8 的最小厚度。例如，冠狀多元矽1〇4可為85奈米厚，HSG 矽102顆粒可鼓起約30-40奈米高，氧化之氮化矽（N〇)介 電質106可為6奈米厚，且鄰近胞元間之頂部電極1〇8最 小厚度約為100奈米。因此如果HSG矽顆粒為70奈米高， 則頂部電極108之最小厚度必需減少至2〇奈米且變得不 可靠。 圖2a-f以基底部分之記憶體胞元100刮面正視圖說明 DRAM的製造步驟如下。 (a)由珍基底開始（或絕緣基底上的石夕）以窄渠溝絕緣以 及CMOS週邊雙井加上記憶體陣列井。執行臨界調整植入 (胞元電晶體及各種週邊電晶體可能不同），並形成閉極介 電質。沉積鍍硅化鎢多元矽閘極材料及二氧化妙層，接著 將該層樣式化以形成頂部覆蓋氧化物之閘極u〇加上遇邊 本紙張尺度適用中國國家標準（CNS } A4現格（210X297公釐） •n ^^1 ^^1 I - I- — i - - 士.£/ - ill I i \~ *vs (請先閲讀背面之注項再填寫本頁〕 426933 A7 ----B7 五、發明説明（4 ) 電晶體閛極及閘極層中間接合；參見圖2a。 ⑸執行輕度摻雜㈣植人，且接著以_加上各向 異的仙在_形錢牆介電f ^引人施子以形成源極 112及及極U4包括週邊源極/没極以完成電晶體層。以 平面化介電質層（諸如BPSG)覆蓋此結構；參見圖此。 (c) 在平面化之介電質上以光刻法定義㈣孔（通道） 至源極112。在挣雜的多元石夕上包覆沉積並回姑形成孔之 梗部122»其次，在平面化之介電質上以光刻法定義钱刻 孔至淡極114。在摻雜的多元石夕且接著在娃化鎮頂蓋上包 覆>儿積，並將之樣式化形成位元線12〇連接至汲極114。 形成平面的位7G線介電質可包含—止钱層（例如氧化物及 氮化物的止蝕層）；參見圖2c β (d) 沉積一摻雜多元矽層，其終將成為胞元ι〇〇垂直多 疋矽冠狀水平基底之一部分；接著以光刻在多元矽的梗部 122定義出孔。此外，可將多元矽邊牆（披覆沉積加上各 向異性蝕刻）施加於孔上以提供圓形邊角及較小的直徑。 接著以多元矽作為蝕刻光罩，以蝕刻平面化位元線介電質 至梗部122 ;參見圖2d » 經濟部中央標準局員工消费合作社印聚 ί請先閱讀背面之注意事項再填寫本W } (e) 沉積一連接至梗部122之摻雜多元矽層且終將形成 冠狀的水平基底之剩餘部分β接著一介電質層並光刻定義 *冠狀基底β姓刻此介電質及多元矽以產生覆蓋介電質的冠 狀基底；參見圖2e。 (0均勻的在摻雜的（以磷化氣）多元矽上沉積，此造成 與多το石夕基底105曝露的端點接觸。以各向呉性蝕刻多元 本紙張尺度適用中國國家^ (CNS) A4規格（ϋχ297公釐） 42693 3 A7 B7 ~ · - ____ _____ _ .. 五、發明説明（5 ) 矽移去多元矽的水平部分（在基底介電質的頂部以及基底 間的位元線介電質）β可使用以氣為基礎的電漿蝕刻，此 在介電質及基底端形成冠狀的邊牆。其次，剝除介電質留 下以水平基底支撐的無阻礙直立冠：此剝除可停止於止蝕 次層。圖2f顯示位元線介電質表面的止姓狀況；亦可曝 露埋藏冠狀基底的止蝕層而增加電極面積。 (g)在曝露的冠狀多元矽表面及基底上，以及無可避 免曝露之位元線介電質上生長HSG矽。在（多元）矽上HSG 矽的生長以兩個階段發生：首先為核化，接著核心生長合 併成顆粒。因此，在冠狀多元矽的核化HSG矽以及基於在 571°C時450sccm分解的桂化物流，經由一含有碎晶圓的 沉積腔以成核密度約為1.76义10|1/〇1121 —分鐘，產生12 奈米厚的核心；參見圖3a，顯示核心的TEM視圖》當然， 產生此高成核密度確實之硅化物流量及溫度，將視腔的幾 何形狀、壓力及總晶圓面積而定。事實上，囷4說明各種 處理腔條件及薄層厚度的核化密度。例如，一 571eC兩分 鐘約為230sccm的硅化物流量產生一約為17奈米厚的核 心層且其核化密度約為4. 9x10lG/cm2。 持績2. 5分鐘在571eC以450sccm的硅烷流中生長HSG 石夕’以產生一層厚度最大約為3〇奈米的顆粒β圖3b顯示 此等顆粒，此與圖3a中的大小相同*>當然，如果此層顆 粒持續生長至諸如75奈米的厚度，則此密度將產生一顆 粒朝向矽固體層合併的薄層，且此表示面積增進的降低。 注意理論上密閉封裝半球·體面積之增加與半球體之高度無 本—尺度it财關轉 ---------裝------訂 (請先閲讀背面之注意事項再填寫本頁) Μ濟部中央標準局貝工消費合作社印製 42693 3 A7 B7 經濟•部中央橾準局貝工消費合作社印製 五、發明説明（6 關；因此小密閉封裝半球體提供相同的增加面積但形成之 厚度較薄。相對的，前述低成核密度範例中有如圖3C中 所钦述相同30奈米厚度敉少但較大的顆粒，與囷3a-b中 的大小相同。 (h) 以光蝕刻遮罩冠部並蝕刻在位元線介電質上之hsg 石夕以確保鄰近冠間的分隔。或者，可使用未遮罩的各向異 性矽姓刻；此將減少冠的高度但保持表面之粗糙度β冠及 基底包含摻雜於其上的多元矽及加上表面上未摻雜的-HSG 石夕。在移除光阻後清洗晶圓以除去自然氧化物；未摻雜之 HSG矽不會如在其下摻雜磷的多元矽般容易氧化。 (i) 強化HSG矽顆粒外形加上以磷摻雜顆粒，首先將晶 圓在氫氣（H2)環境下以850。〇烘烤30-60分鐘，此舉移去 任何殘餘自然氧化物加上由其下多元矽丨04/100移至顆粒 102上的矽原子，並澎脹相關於其下多元矽之顆粒。面積 增強（電氣量測形成之電容器）因數由原始顆粒約為2.2増 加至鼓起顆例的約為2.7。參見圖5a-b分別顯示外形強 化前後。接著由氫氣環境轉換至磷酸氫（pjjy的環境】分 鐘；磷酸氫在矽的表面分解且將磷擴散至顆粒中造成一表 面摻雜磷的濃度大於2xl02Vcm3。 (j) 任何自由表面磷，諸如可能發生於顆粒間的罅咪， 及由先前步驟高度摻雜的顆粒提供氧化極具反應性的位 置。確實，天然氧化物快速的在大量掺雜的砂上生長’典 型的厚度在卜3奈米的範圍；如此之氧化物（介電常數為 2. 5-3. 5)將降低使用6奈*氧化之錢化物電容器的實際 ΜΛ張尺度適用中國國家標準（CNS M4規格（210X297公楚） (請先Μ讀背面之注意事項再填寫本頁) 裝 42693 3 A7 ----~~—________B7_ 五、發明説明（7 ) 介電常數。(介電常數為6.8之4.5奈米之氮化物被介電 常數為3.9之2奈来的熱氧化物所覆蓋）。此外，以祕 加上氧表面反應之石夕氮化物介電質的沉積具有氧化物核化 之潛伏時間但在矽上有最少的潛伏期 ;因此在氧化之矽表 面沉積之氮化物較在清潔之矽上為薄。此較薄的氮化物（例 如2-2·5奈米而非4 5奈米）可能過薄無法在氮化物的氧 化期間防止其下顆粒之氧化。因此，在顆粒之磷化氮氣相 沉積之後’立即將ί冗積腔排空並降溫至74(rc，並流過去 氣化硅烷及氨以沉積矽氮化物介電質至4 5奈米的厚度。 或者’晶圓可由真空之磷摻雜腔移至矽氮化物沉積腔中。 接著將氮化物在850°c的蒸氣中氧化，以在氮化物上形成 約為2奈米的氧化物加上插頭針孔；此完成介電質。 (k) 沉積在摻雜多元矽中且將之樣式化以形成頂部電 容器電極。 (l) 形成中間層介電質及申間接合；此也連接上一 DRAM 中的週邊電路。 HSG生長 經濟部中央標準局員工消費合作社印製 - T^l^i - JII4i flu nn 一eJ (請先閱讀背面之注意事項再填寫本頁) 當HSG顆粒生長且薄層變厚，顆粒開始合併。顆粒之 生長增加傾斜顆粒邊牆面積但顆粒之合併免除了邊牆，因 此有一如圖6所述之最大總表面面積。事實上，在氣相期 間以電氣量測粗糙多元矽作為低電極之電容器》之面積增進 因數摻雜，圖6顯示顆粒外形增進之後面積增進因數（總 粗縫表面積對原始平面面積比）。圖6電容器之生長條件 與前圖3c範例中所述之低成核密度HSG生長條件相同。 本紙張尺度適用中國國家橾準（CNS ) A4規格（210X297公着） ΑΊ 42693 3 Β7 五、發明说明（8 ) 事實上，圖3c顯示由合併所造成之顆粒側向延伸。將圖 3b之側向緊密顆粒與圖3c之顆粒比較，由於較低之合併， 由較大量之顆粒邊牆面積之較小厚度層（例如30奈米 厚），較佳實施例高成核密度應有較大面積増進因數。 修訂 較佳實施例可用不同的方式修訂，以具有顆粒增進之 薄粗糙多元矽（例如30奈米之厚度），在氣相摻雜及無氧 中間介質形成期間，仍保有高面積增進因數之特性。— 例如，處理的條件可以改變，矽氮化物介電質沉積可 用快速熱氮化（NH3在1000°C)形成一薄的氮化物阻擋層， 其後為一氧化物為基礎的介電質（諸如Ta205)沉積。 此外，粗糙多元矽電極電容器可為浮點及控制閘極間 一 EEPR0M中的耦合電容器’或一般線性電路或其它耦合 之電容器》 i^i i ^^^1 ^^^1 r l^i f — I In \ , «3. --•' (請先閲讀背面之注意事項再填寫本頁) 經濟部中央樣準局貝工消費合作社印製 -10- 本紙張尺度適用中國圉家標準（CNS > A4規格（210X 297公釐）Ino et al. Described Rugged Surface Polycrystalline Film Deposition and its Application in a Stacked Dynamic Random Access Memory Capacitor Electrode, 14 J. Vac. Sci Tech. B 751 (1996) (Figure 14). * Is 40-150 nanometers (nm), and its thickness is preferably 100 μm. SUMMARY OF THE INVENTION The present invention provides a HSG silicon layer (rough polysilicon) with a thickness of less than 40 nanometers. However, due to the high nucleation density deposition in a single furnace and the gas phase, the paper size is applicable to China National Standard (CNS) A4 (210X297). (Mm) ^ — (Please read the notes on the back before filling out this page) Order from the Central Standards Bureau of the Ministry of Economic Affairs and Consumer Cooperation Du Yin 袈 / <-4 ^ 89 3 3 a7 ～ ^ ______ 5. Description of the invention (2 ·) Improved particle shape and dopant to increase the surface area by at least 2 times. "The rough-wound polylithium stone preferred embodiment forms a (dynamic memory cell) capacitor electrode with an improved surface area, and the capacitor dielectric is not deposited. Exposing the electrode to an oxygen source β Brief description The following legend is used as a heuristic explanation. Figures la-b are cross-sections and front views of a preferred embodiment of a memory cell. Figures 2a-f illustrate the method steps of a preferred embodiment with a cross-sectional front view circle. — Figures 3a-c illustrate nucleation and particles. Figure 4 shows the nucleation density. Circles 5a-b illustrate particle bulging. Figure 6 shows the increase in area. Description of the preferred embodiment Overview The preferred embodiment increases the area of the capacitor electrode (electrode plate) but uses small particles. High density keeps hemispherical particle (HSG) silicon (rough multiple) with a defined thickness. The preferred embodiment method firstly forms HSG silicon with small particles but high area density under the conditions; secondly, the gas phase enhancement particles are added with HSG silicon doped; and then the initial capacitor dielectric is immediately formed without being exposed to the oxygen source. The use of small particles of HSG Ishiki limits the actual thickness of the valley electrode, so that there is a small gap between adjacent and multiple capacitor electrodes. Gaseous doping allows the shape of the basic particles to be increased but makes the surface more susceptible to undesired oxidation, so the formation of the dielectric immediately begins and a more heterogeneous capacitor dielectric layer is created. The circle la-b is a cross section and a plane. The circle is a circle to illustrate the diversity of a comparative example -4-the paper standard is universal T 囷 national standard (CNS) A4 grid (210X297 mm) ϋ ^-I-: 11 ml aR.----l --_ I 1 1-r 0¾.- ° (Please read the notes on the back before filling out this page) Printed by the Central Consumers Bureau of the Ministry of Economic Affairs, Consumer Cooperatives 42693 3 A7 _________ B7 _ A ______ .. 5 'Description of the invention (3) Shi Xi vertical cylinder 1104 (with extended crown shape on it) DRAM cell 100 with jjSG silicon 102, plus multiple silicon substrate 105 to form a capacitor cell The low-electrode β-dielectric material 106 conforms to the surface of HSG silicon 102 and the portion of polysilicon 104-105 between HSG silicon particles. Although other materials such as TiN can be used to form the top (common) of the capacitor electrode. The pass transistor (gate Π0 source 112 and drain 114) connects the bit line 120 to the low-capacitor electrode through a multi-element silicon stem 122; the bit line 122 is parallel to the plane of FIG. The pole 114 contacts as shown in Figure h. The separation between the idea cell 100 and the neighboring cell 100 ′ is determined by the minimum interval between Η% 102 and HSG 102 ′, and this is the minimum thickness of the top electrode 108. For example, crown polysilicon 104 can be 85 nanometers thick, HSG silicon 102 particles can swell about 30-40 nanometers high, and oxidized silicon nitride (N0) dielectric 106 can be 6 nanometers thick. The minimum thickness of the top electrode 108 between adjacent cells is about 100 nm. Therefore, if the HSG silicon particles are 70 nanometers high, the minimum thickness of the top electrode 108 must be reduced to 20 nanometers and become unreliable. Figures 2a-f illustrate the manufacturing steps of the DRAM with a scratched front view of the memory cell 100 in the base portion. (a) Beginning with a Jane substrate (or Shi Xi on an insulating substrate) with a narrow trench insulation and CMOS peripheral double wells plus a memory array well. Perform a critical adjustment implant (the cell transistor and various peripheral transistors may be different) and form a closed-electrode dielectric. Deposition of tungsten silicide-plated multiple silicon gate material and a wonderful dioxide layer, and then pattern this layer to form a gate electrode covering the top oxide u 〇 In addition, the paper dimensions are applicable to Chinese national standards (CNS} A4) ( 210X297 mm) • n ^^ 1 ^^ 1 I-I- — i--Taxi. £ /-ill I i \ ~ * vs (Please read the note on the back before filling this page] 426933 A7 --- -B7 V. Description of the invention (4) Intermediate junction of the transistor 闸 and gate layers; see Figure 2a. ⑸ Carry out lightly doped ㈣ implantation, and then add _ plus anisotropic fairy in _ shaped money wall The dielectric f ^ attracts people to form the source 112 and the electrode U4 includes a peripheral source / non-electrode to complete the transistor layer. The structure is covered with a planarized dielectric layer (such as BPSG); see figure here. c) The photolithography method is used to define the countersunk holes (channels) to the source electrode 112 on the planarized dielectric. The mixed polylithic stones are coated and deposited to form the pores of the holes 122 »Secondly, on the plane The lithographic method is used to define the money engraved holes to the light pole 114. The doped polylithic stone is then covered with the top layer of the baby town and patterned. The bit line 120 is connected to the drain 114. The planar bit 7G line dielectric may include a stop layer (such as an oxide and nitride stop layer); see FIG. 2c. The heterogeneous polysilicon layer will eventually become a part of the cellular ιOO vertical polysilicon crown-shaped horizontal base; then, holes are defined in the polysilicon's stem 122 by photolithography. In addition, the polysilicon side wall (covered by Deposition plus anisotropic etching) is applied to the holes to provide rounded corners and smaller diameters. Then polysilicon is used as an etching mask to etch the planarized bit line dielectric to the stem 122; see Figure 2d »Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Please read the precautions on the back before filling in this W} (e) Depositing a doped multiple silicon layer connected to the stem 122 and eventually forming a crown-shaped horizontal substrate The remaining β is followed by a dielectric layer and lithographically defined. * Coronary substrate β is engraved with this dielectric and polysilicon to produce a coronary substrate covering the dielectric; see Figure 2e. (0 uniformly doped (with Phosphating gas) deposited on multiple silicon, which results in The exposed end of the bottom 105 is in contact with each other. It is anisotropically etched multiple times. The paper size is applicable to the Chinese national standard (CNS) A4 (ϋχ297 mm) 42693 3 A7 B7 ~ ·--____ _____ _ .. 5. Description of the invention (5 ) Silicon removes the horizontal portion of the polysilicon (the dielectric on top of the substrate dielectric and the bit line dielectric between the substrates) β can be etched using a gas-based plasma, which forms a crown on the dielectric and substrate ends Secondly, the stripping of the dielectric leaves an unobstructed upright crown supported by a horizontal base: this stripping can stop at the stop erosion sublayer. Fig. 2f shows the surviving condition on the surface of the bit line dielectric; the anti-corrosion layer buried in the coronal substrate can also be exposed to increase the electrode area. (g) HSG silicon is grown on the exposed surface and substrate of the coronal polysilicon, and on the inevitably exposed bit line dielectric. The growth of HSG silicon on (multiple) silicon occurs in two stages: first, nucleation, then core growth merges into particles. Therefore, the nucleated HSG silicon in the coronal polysilicon and the chlorinated stream based on 450sccm decomposition at 571 ° C pass through a deposition chamber containing broken wafers with a nucleation density of about 1.76 10 10 | 1 / 〇1121-minute A core with a thickness of 12 nanometers is produced; see Figure 3a, showing a TEM view of the core "Of course, the silicide flow and temperature at which this high nucleation density is generated will depend on the geometry, pressure, and total wafer area of the cavity . In fact, 囷 4 illustrates various processing chamber conditions and nucleation densities of thin layer thickness. For example, a 571eC silicide flow rate of about 230 sccm for two minutes produces a core layer with a thickness of about 17 nanometers and a nucleation density of about 4.9x10lG / cm2. Achievement of 2.5 minutes growing HSG Shi Xi 'at 571eC in a stream of 450 sccm silane to produce a layer of particles with a maximum thickness of about 30 nm β Figure 3b shows these particles, which are the same size as in Figure 3a * & gt Of course, if this layer of particles continues to grow to a thickness of, for example, 75 nanometers, this density will produce a thin layer of particles that merge toward the silicon solid layer, and this indicates a decrease in area increase. Note that in theory, the increase in the area of the sealed package hemisphere and the height of the hemisphere has no basis. (Fill in this page) Printed by the Shellfish Consumer Cooperative of the Central Standard Bureau of the Ministry of Economic Affairs, 42693 3 A7 B7 Printed by the Shellfish Consumer Cooperative of the Central Bureau of Economic Affairs, Ministry of Economic Affairs. 5. Description of the invention (6 levels; therefore, the small sealed package hemisphere provides the same Increasing the area but forming a thinner thickness. In contrast, in the previous example of low nucleation density, there are fewer but larger particles with the same thickness of 30 nanometers as illustrated in Figure 3C, which are the same size as those in 囷 3a-b. h) Mask the crown with light and etch the hsg stone on the bit line dielectric to ensure separation between adjacent crowns. Alternatively, use an unmasked anisotropic silicon surname; this will reduce the crown The height of the β-crown and the substrate that maintains the surface roughness include polysilicon doped on it and undoped -HSG stone on the surface. After removing the photoresist, clean the wafer to remove natural oxides; Undoped HSG silicon does not oxidize as easily as polysilicon doped with phosphorus below. (I) The shape of the HSG silicon particles is added with phosphorus-doped particles. First, the wafer is baked at 850 ° C in a hydrogen (H2) environment for 30-60 minutes. This removes any residual natural oxides and adds multiple components from it. Silicon 丨 04/100 moved to the silicon atom on particle 102 and swelled the particles related to the polysilicon below it. The area enhancement (capacitor formed by electrical measurement) factor was increased from about 2.2% of the original particle to the bulging particle. Approximately 2.7. See Figures 5a-b before and after the shape strengthening, respectively. Then change from hydrogen environment to hydrogen phosphate (pjjy environment) minutes; hydrogen phosphate decomposes on the surface of silicon and diffuses phosphorus into the particles to cause a surface doped with phosphorus. The concentration is greater than 2xl02Vcm3. (J) Any free-surface phosphorus, such as the mime that may occur between particles, and highly reactive sites for oxidation provided by the highly doped particles in the previous step. Indeed, natural oxides rapidly move in large amounts Growth on doped sand's typical thickness is in the range of 3 nanometers; such oxides (dielectric constant of 2.5-5. 5) will reduce the actual ΔΛ scale of 6 nanometer * oxidized coin capacitors Applicable in China National standard (CNS M4 specification (210X297)) (Please read the precautions on the back before filling this page) Install 42693 3 A7 ---- ~~ ________ B7_ V. Description of the invention (7) Dielectric constant. (Medium Nitrogen nitrides with a dielectric constant of 6.8 and 4.5 nanometers are covered by thermal oxides with a dielectric constant of 2 nanometers and a dielectric constant of 3.9). In addition, the deposition of the nitride dielectric with the surface reaction of oxygen and oxygen has oxidation. The latency of nucleation but has the least latency on silicon; therefore, the nitride deposited on the surface of oxidized silicon is thinner than that on clean silicon. This thinner nitride (eg 2-2 · 5 nm and Non-4.5 nm) may be too thin to prevent oxidation of the underlying particles during the oxidation of the nitride. Therefore, immediately after the deposition of the phosphorous nitrogen phase of the particles, the redundant cavity was evacuated and cooled to 74 ° C. and flowed over to vaporize the silane and ammonia to deposit the silicon nitride dielectric to a thickness of 4 5 nm. Alternatively, the wafer can be moved from a vacuum phosphorus-doped chamber to a silicon nitride deposition chamber. The nitride is then oxidized in a vapor at 850 ° C to form an oxide of about 2 nm on the nitride plus Plug pinholes; this completes the dielectric. (K) Deposited in doped polysilicon and patterned to form the top capacitor electrode. (L) Forming an interlayer dielectric and applying bonding; this is also connected to a Peripheral circuits in DRAM. Printed by the Consumer Cooperatives of the Central Standards Bureau of the HSG Growth Economy Department-T ^ l ^ i-JII4i flu nn a eJ (Please read the precautions on the back before filling this page) When HSG particles grow and thin The particles become thicker and the particles begin to merge. The growth of the particles increases the area of the side walls of the inclined particles but the merger of the particles eliminates the side walls, so there is a maximum total surface area as described in Figure 6. In fact, the roughness is measured electrically during the gas phase Polysilicon as a low-electrode capacitor》 Area enhancement factor doping, Figure 6 shows the area enhancement factor after the shape of the particles is improved (total rough seam surface area to original plane area ratio). Figure 6 capacitor growth conditions and the low nucleation density HSG growth conditions described in the example in Figure 3c Same. The paper size applies to China National Standards (CNS) A4 (210X297) ΑΊ 42693 3 B7 V. Description of the invention (8) In fact, Figure 3c shows the lateral extension of the particles caused by the merger. Figure 3b Compared with the particles in Figure 3c, the lateral compact particles are smaller in thickness (for example, 30 nanometers thick) due to the lower merging. Large area progression factor. The revised preferred embodiment can be modified in different ways to have thin and rough polysilicon with particle enhancement (for example, 30 nm thickness), which remains high during gas phase doping and oxygen-free intermediate formation. Characteristics of area enhancement factor. — For example, processing conditions can be changed. Silicon nitride dielectric deposition can be formed by rapid thermal nitridation (NH3 at 1000 ° C) to form a thin nitride barrier. Then, an oxide-based dielectric (such as Ta205) is deposited. In addition, the rough polysilicon electrode capacitor can be a coupling capacitor in an EEPR0M between floating point and control gate, or a general linear circuit or other coupling Capacitor》 i ^ ii ^^^ 1 ^^^ 1 rl ^ if — I In \, «3.-• '(Please read the precautions on the back before filling out this page) Central Bureau of Standards, Ministry of Economic Affairs, Shellfish Consumption Printed by the cooperative -10- This paper size applies to the Chinese standard (CNS > A4 size (210X 297 mm)