.修正 ff年&月< 案號 88112304 曰 Λ26924· 五、發明說明（1) 發明背景 本發明提ώ 一種將組件安裝到積體電路封裝周側的方 法。更明確的來說，本發明提出一種將電容安裝到耦合於 印刷電路板或其他類似裝置上之積體電路封裝（例如處理 器）周側的方法。 積體電路（I c)封裝包含了數種常見的組態方法。積體電 路封裝的目的在於將晶粒耦合到電氣接腳上，如此這個積 體電路才能被連接到其他裝置上。舉例來說，所謂的晶粒 可以是其上形成許多電子組件（如電晶體，電阻，電容等） 以及連接導體的矽晶基板。在典型的積體電路封裝_，電 氣導體尖端實際上是被連接到給合片上，然後晶粒會被封 裝在塑膠中以保護這些連接。在成品時，露出塑膠封裝外 的只剩下導體尖端而已，這些接腳可以***到印刷電路板 或麵包板上的孔洞中。 較新的建立積體電路封裝的技術包括將晶粒拿起來並以 電氣的方式將其連接到組件上，此即為本說明中所提到的 受控折疊晶；i連接（CCC或4C)封裝。C4封裝在塑膠保護系 統内不包含金屬尖端。C4封裝的頂端被電氣的耦合到晶粒 的導通"隆點”上，而C4封裝的底端則包含了 一系列的接合 區，這些接合區經過C 4封裝電氣性的與晶粒耦合在一起。 由於C 4封裝的底部是用來連接到印刷電路板或其他類似裝 置的接合區所在的位置，因此C4封裝的底端也通常被稱為 周側1^ 圖1為典型的連接方式。晶粒1 1被電氣的連接到C4封裝Amend ff year & month < case number 88112304, Λ26924 · V. Description of the invention (1) Background of the invention The present invention provides a method for mounting a component on the peripheral side of a package circuit. More specifically, the present invention proposes a method for mounting a capacitor on the periphery of a integrated circuit package (such as a processor) coupled to a printed circuit board or other similar device. The integrated circuit (I c) package contains several common configuration methods. The purpose of the integrated circuit package is to couple the die to the electrical pins so that the integrated circuit can be connected to other devices. For example, the so-called die can be a silicon substrate on which many electronic components (such as transistors, resistors, capacitors, etc.) and conductors are formed. In a typical integrated circuit package, the tip of the electrical conductor is actually connected to the chip, and then the die is encapsulated in plastic to protect these connections. When finished, only the tip of the conductor is exposed outside the plastic package. These pins can be inserted into holes on the printed circuit board or breadboard. Newer techniques for building integrated circuit packages include picking up the die and electrically connecting it to the component, which is the controlled folded die mentioned in this description; i connection (CCC or 4C) Package. The C4 package does not contain metal tips in a plastic protection system. The top end of the C4 package is electrically coupled to the conduction " bumps of the die ", while the bottom end of the C4 package contains a series of bonding areas which are electrically coupled to the die through the C4 package. Since the bottom of the C 4 package is where the bonding area for connecting to a printed circuit board or other similar device is located, the bottom end of the C 4 package is also commonly referred to as the peripheral side. Figure 1 shows a typical connection. Die 1 1 is electrically connected to the C4 package
59556.ptc 第5頁 2000.12. 04.005 426924 ‘案號 88112304 歹年, > 月f a ίΊ __ (2) 'Mtj / 1 3上。如前所述，C4封裝1 3的周側包含可電氣式的連接到 印刷電路板上的陣列式結合區域（如接合區或鲜球）。此類 的陣列包括地柵陣列（1 a n d - g r丨d - a r r a y， L G A )或球柵陣列 (ball-grid-array，BGA)。C4封裝可使用連接頭15電氣式 的耦合到印刷電路板1 7上。 一般來說’電氣式的耦合一個或多個電容到晶粒上以提 供晶粒電路的解耦合電容是有必要的〇此類電容的電容值 〆般來說是相當大的（也就是說，大約在10pF的等級）。 為了減低$連在電容器上的寄生電感，去耦合電容必須越 靠近晶粒越好。圖1畫出數種可以將電容轉合到晶粒上的 方法。首先，電容20a與20b電氣性的被耦合到C4封裝的頂 端（die side)’由於晶粒11的中心或核心離電容20a與20b 的距離相當大，因此晶粒1 1上會出現一個相當大的串聯電 感。同時，由於C 4封裝1 3的大小必須變大以容納電容2 0 a 與2 0 b ’因此用這種方法將電容耗合到晶粒1 1的成本也會 相對的提高（C4封裝的面積越大成本越高）。位於印刷電路 板頂端（或前端）的電容2 2 a與2 2 b與晶粒1 1的中心或核心距 離更大’因此其產生的串聯電感值更高。 如果印刷電路板在底部提供C 4封裝1 3的電氣接頭的話， 電谷2 4 a，2 4 b可以被連接到印刷電路板1 7的底部（背部）。 當印刷電路板是Ibiden USA Corp.所販賣的内建多層板 (或高密度多層板）或者WurthElektronik GmbtURot am See，德國）的DYCOstrate或TWINflex時，此方法將可 適用。第二種例子則是一個或多個的μ F R 4 η板。ρ R 4板包含 包含一個環氧基樹脂，此一樹脂經由玻璃編織纖維加以強59556.ptc page 5 2000.12. 04.005 426924 ‘case number 88112304 leap year, > month f a ί a __ (2) 'Mtj / 13 on. As mentioned earlier, the peripheral side of the C4 package 1 3 contains an array of bonding areas (such as land or fresh balls) that can be electrically connected to the printed circuit board. This type of array includes a ground grid array (1 a n d-g r d-a r r a y, L G A) or a ball grid array (BGA). The C4 package can be electrically coupled to the printed circuit board 17 using the connector 15. Generally, it is necessary to electrically couple one or more capacitors to the die to provide a decoupling capacitor for the die circuit. The capacitance of such capacitors is generally quite large (that is, On the order of 10 pF). In order to reduce the parasitic inductance connected to the capacitor, the decoupling capacitor must be as close to the die as possible. Figure 1 shows several ways to transfer capacitance to the die. First, the capacitors 20a and 20b are electrically coupled to the die side of the C4 package. Since the center or core of the die 11 is quite far from the capacitors 20a and 20b, a large size will appear on the die 11 Series inductance. At the same time, because the size of the C 4 package 13 must be larger to accommodate the capacitors 20 a and 20 b ', the cost of dissipating the capacitor to the die 1 1 in this way will also increase the relative cost (the area of the C4 package). The bigger the cost, the higher). The capacitors 2 2 a and 2 2 b located at the top (or front end) of the printed circuit board are more distanced from the center or core of the die 1 1 ', so they generate a higher series inductance value. If the printed circuit board is provided with a C 4 package 13 electrical connector at the bottom, the valleys 2 4 a, 2 4 b can be connected to the bottom (back) of the printed circuit board 17. This method is applicable when the printed circuit board is a built-in multilayer board (or high-density multilayer board) sold by Ibiden USA Corp. or DYCOstrate or TWINflex of Wurth Elektronik GmbtURot am See, Germany). The second example is one or more μ F R 4 η plates. ρ R 4 plate contains an epoxy-based resin, which is reinforced with glass braid
4269 24 案號 88112304 Η 年月 a :爹λ 五、發明說明 化，可增 的導通路 徑相連接 部所需花 低，然而 況在使用 耦合電容 的問題。 另外一 路板1 7間 的空間限 刷電路板 效果。 為了解 所產生的 封裝之組 發明總結 根據本 隙，此空 的周側也 路板空隙 用來與電 圖式說明 (3) 補充 加其抗火性。每個F R 4板在板的兩側包含了許多 徑，這些路徑通過加有焊錫的灌孔與另一側的路 。雖然將電容2 4 a，2 4 b連接到印刷電路板1 7的底 費的成本較將電容20a，20b連接到C4封裝13為 印刷電路板1 7上會出現可觀的寄生電感，這種情 FR4板時特別嚴重。總括來說，上述的這些加上 的方法都有會增加成本以及/或寄生阻抗量太大 種方法則是在連接頭1 5間以及C4封裝1 3與印刷電 加上非常小的耦合電容器。由於這些區域的嚴重 制，所耦合的電容將會很小，因此C4封裝1 3與印 1 7間必須加上額外的電容器以達到相同的去耦合 決前述之將諸如去耦合電容器等組件連接到晶粒 價格或電氣上的問題，提出一種可改善積體電路 件周側式安裝的方法或裝置是有其必要的。 發明的第一種實現方法，電路板上包含一個空 隙周圍包含了 一周邊區域。同時積體電路的封裝 提供了相對應的周邊區域，此一區域可用來與電 周圍的周邊區域相連結。積體電路封裝的周側被 子组件相連接。4269 24 Case No. 88112304 Η Year a: Da λ V. Description of the invention, the increase in the diameter of the conductive path required for the connection part is low, but the problem of using a coupling capacitor is the case. The space of the other circuit board 17 is limited to the effect of brushing the circuit board. In order to understand the resulting package group, the invention is summarized. According to this gap, this empty peripheral side is also a circuit board gap. It is used to explain with the electrical diagram (3) and adds its fire resistance. Each F R 4 board contains a number of paths on both sides of the board. These paths pass through soldered vias to the other side. Although the cost of connecting the capacitors 2 4 a and 2 4 b to the printed circuit board 17 is lower than that of connecting the capacitors 20 a and 20 b to the C4 package 13, considerable parasitic inductance will appear on the printed circuit board 17. FR4 board is particularly severe. To sum up, all of the methods mentioned above will increase the cost and / or the amount of parasitic resistance is too large. One way is to add very small coupling capacitors between the connector 15 and the C4 package 13 and the printed circuit. Due to the severe restrictions in these areas, the capacitance to be coupled will be small, so additional capacitors must be added between C4 package 13 and India 17 to achieve the same decoupling. It is necessary to propose a method or device for improving the peripheral side mounting of integrated circuit components due to the price of grains or electrical problems. The first implementation method of the invention includes a space on the circuit board and a peripheral area around it. At the same time, the package of the integrated circuit provides a corresponding peripheral area, and this area can be used to connect with the peripheral area around the power. The peripheral sides of the integrated circuit package are connected by subassemblies.
59550.ptc 第7頁 2000.12. 04. 007 426924 五、發明說明（4) '—丨-— — 圖1為連接到印刷電路板的C4封裝之側面圖， 採用常見的方式連接到這些裝置上。 圖2為使用本發明所提出之某種實現方法連接 路板上的C 4封裝之切面侧視圖。 圖2A為圖2中所示之印刷電路板，C4封裝以及s 迴流電流流經這些裝置時的切面側視圖。 阳^ 圖3為本發明所提出之另一種實現方法之切面側視圖， ::隔器或類似物放置在“封裝與印刷電路板間 以將C 4封裝與印刷電路板連接在一起。 圖4為本發明所提出之第二種實現方法之切面侧視圖， 此方法將印刷電路板薄片放置在u封裝與印刷電路板間以 將C4封裝與印刷電路板連接在一起。 圖5為本發明所提出之第三種實現方法之切面側視圖， 此方法將類似插座的接頭放置在C4封裝與印刷電路板間以 將C4封裝與印刷電路板連接在一起β 詳細說明 參考圖2，圖2為使用本發明所提出將耦合電氣組件（如 電容器）連接到積體電路封裝（如C4封裝）之一種實現方 法。晶粒31以常見的方式被連接到諸如C4封裝33之類的封 裝上。舉例來說’封裝33可使用LGA或BGA模式經過連接頭 3 5被耦合到印刷電路板3 7上。在本發明的這種實現方法 中’印刷電路板3 7上加上了空隙3 9。 封裝33的周邊區域被連接到空隙39周圍的周邊區域 上。因此，諸如輕合電容38之類的電氣組件便可在封裝3359550.ptc Page 7 2000.12. 04. 007 426924 V. Description of the invention (4) '— 丨 -— — Figure 1 is a side view of a C4 package connected to a printed circuit board, which is connected to these devices in a common way. Fig. 2 is a cut-away side view of a C4 package connected to a circuit board using one of the implementation methods proposed by the present invention. FIG. 2A is a cut-away side view of the printed circuit board, C4 package, and s-reflow current shown in FIG. 2 when these devices are flowing. Figure 3 is a cutaway side view of another implementation method proposed by the present invention, with a :: spacer or the like placed between the "package and the printed circuit board to connect the C 4 package to the printed circuit board. Figure 4 This is a cutaway side view of the second implementation method proposed by the present invention, which places a printed circuit board sheet between a u package and a printed circuit board to connect the C4 package and the printed circuit board together. Figure 5 A cross-sectional side view of the third implementation method is proposed. This method places a socket-like connector between the C4 package and the printed circuit board to connect the C4 package and the printed circuit board. An implementation method for connecting a coupled electrical component (such as a capacitor) to an integrated circuit package (such as a C4 package). The die 31 is connected to a package such as a C4 package 33 in a common manner. For example It is said that the package 33 can be coupled to the printed circuit board 37 via the connector 35 using the LGA or BGA mode. In this implementation method of the present invention, a gap 39 is added to the printed circuit board 37. The peripheral area of the package 33 is connected to the peripheral area around the gap 39. Therefore, electrical components such as the light-weight capacitor 38 can be connected to the package 33.
第8頁 426924 五、發明說明（5) 連接到印刷電路板37之前或經過連接頭35連接到印刷電路 板3 7之後直接連接到封裝3 3的周側上。空隙3 9可在封穿3 3 的底=>卩k供足夠的空間以將足夠大小的去耗合電容器（例 如’電容器3 8 )***到封裝3 3的周側上。 連接到封裝3 3周侧的耦合電容器可減低晶粒3丨與電容器 38之間的寄生電感值。如圖2A中所示，由晶粒3丨流經封裝 33與電容器3 9然後流回晶粒3 1的電流所形成的迴圈比較小 同時迴圈兩側所產生的電感值會互相抵消。在以圖2與圖 2A中所示的方式測試pentiu砻u處理器（intei公司）時， 其總電感值大約是20 0微微亨。當將去耦合電容器放置在 典型FR4印刷電路板的底側時（如圖i中所示的電容器 b)，電容器本身所產生的寄生電感可高達45〇微微. 亨’同時晶粒u ，封裂13 ’印刷電路板17，電容器24a再 回到Ba粒11這個迴圈上的寄生電感量高達35⑽微微亨。因 此，使+用圖2中所示之實現方法可將寄生電感的數量降低 90% ,這是因為耦合電容直接被接到封裝33的周側而不是 被接到印刷電路板背面的原因。 ί:圖3一5 ’本發明的另一種實現方法將-間隔器或類 似物放置在封裝33與印刷電路板3?的周邊區域間。此一間 用來將封裝33的周側空出一片區域，此一區域可用 ΪΐΪΪ裝33與印刷電路板37 °舉例來說，對圖3所示的 一棚5 t f而S ，晶粒31以電氣的方式輕合到封裝33 m:: ΐ:!電容器38則被連接到封裝33的周侧。間隔 衣破用來替代印刷電路板37上空隙的功能，它被用來增Page 8 426924 V. Description of the invention (5) Connect directly to the peripheral side of the package 33 before connecting to the printed circuit board 37 or after connecting to the printed circuit board 37 via the connector 35. The gap 3 9 can provide enough space at the bottom of the seal 3 3 = > 卩 k to insert a sufficient size de-consumption capacitor (e.g., 'capacitor 3 8') on the peripheral side of the package 3 3. A coupling capacitor connected to the peripheral side of the package 3 can reduce the parasitic inductance value between the die 3 and the capacitor 38. As shown in FIG. 2A, the loop formed by the current flowing from the die 3 through the package 33 and the capacitor 39 and then back to the die 31 is smaller, and the inductance values generated on both sides of the loop will cancel each other. When the pentiu 砻 u processor (intei company) was tested in the manner shown in FIG. 2 and FIG. 2A, the total inductance value was about 200 picohenry. When a decoupling capacitor is placed on the bottom side of a typical FR4 printed circuit board (capacitor b shown in Figure i), the parasitic inductance generated by the capacitor itself can be as high as 45 pico. 13 'printed circuit board 17, capacitor 24a returns to Ba particle 11 and the parasitic inductance on the loop is as high as 35⑽ picohenry. Therefore, using the implementation shown in Figure 2 can reduce the amount of parasitic inductance by 90%, because the coupling capacitor is directly connected to the peripheral side of the package 33 instead of the back of the printed circuit board. ί: Figures 3-5 'Another implementation method of the present invention places a spacer or the like between the package 33 and the peripheral area of the printed circuit board 3 ?. This area is used to free an area around the peripheral side of the package 33. This area can be used for mounting 33 and a printed circuit board 37 °. For example, for a shed 5 tf and S shown in FIG. Electrically closed to package 33 m :: ΐ :! Capacitor 38 is connected to the peripheral side of package 33. The spacer is used to replace the function of the gap on the printed circuit board 37. It is used to increase the
案號 88112304 426924Case No. 88112304 426924
HX 五、發明說明（6) 加封裝3 3的周側與印刷電路板頂端間的距離，此間隔環是 當硬度的材質所製成的。在本範例中，間隔環4丨被置 封裝33的周邊區域周圍並提供連接頭35與連接頭42間 =氣連接功㊣。在本例中’連接頭42可以是連接到印刷 電路板37的LGA或BGA連接頭。 圖4為本發明所提出之第-接^ 帝处上 弟一種實現方法，此方法將印刷 44 裝33的周邊區域周圍。印刷電路板環 』ί m = 這些灌孔可提供封裝33的電氣焊 f區域與連接頭45間的電氣連接。如圖3所示 例一 I ^ ΐ ^ 7对裝3 3與印刷電路板3 7隔開並提 供解耗合電容器之類的裝置—個足夠的介 圖5為本發明所提出之第三種奢 1 ^ ^ ^ 1.47 ^ ^ ίί ^33 ^ Μ JV ^ 板37的頂端與封裝33的周側連接在°°二周$以將Ρ刷電路 P〇g〇接腳或者其他的插座型以U腳47可：是 „ „ J导體’這些接腳可放在封奘 3』與：刷電路板37的凹處。如圖3與 合電容器之類的裝置一個足；二:頂端隔開並提供解輕 雖然本說明提出並詳細說明了數種實現的方法，缺而 他與本發明創作精神相類似或未恃離本發明所提之^圍之 Ξ的L有1 ί Ϊ的？f 1 變形均屬於本發明所得涵蓋之範 的積體電路㈣合到-個小型此處理巧其他 板以單端的連接器連接到主式此-盒式基 调1板上。使用本發明所提出的HX V. Description of the invention (6) Add the distance between the peripheral side of the package 3 3 and the top of the printed circuit board. This spacer ring is made of a material of hardness. In this example, the spacer ring 4 is placed around the peripheral area of the package 33 and provided between the connector 35 and the connector 42 = pneumatic connection function. The 'connector 42 in this example may be an LGA or BGA connector connected to the printed circuit board 37. FIG. 4 is a method for realizing the first-division brother of the present invention. This method will print 44 and 33 around the peripheral area. Printed circuit board ring 』ί m = These vias provide electrical connection between the electrical soldering f area of the package 33 and the connector 45. As shown in Figure 3, Example 1 I ^ ΐ ^ 7 pairs of mounting 3 3 are separated from the printed circuit board 37 and provide a device such as a depletion capacitor and a sufficient medium. FIG. 5 is a third luxury proposed by the present invention. 1 ^ ^ ^ 1.47 ^ ^ ί 33 ^ Μ JV ^ The top of the board 37 is connected to the peripheral side of the package 33 at two degrees for two weeks to connect the P brush circuit P0g0 pin or other socket type with U pin 47 may: Yes "J conductor" These pins can be placed in the seal 3 "and: the recess of the circuit board 37 is brushed. Figure 3 is sufficient for a device such as a capacitor; two: the top is separated and provides a solution. Although this description proposes and describes several implementation methods in detail, it is similar to or does not depart from the spirit of the invention. In the present invention, there are 1 L ^ Ξ Ξ Ξ? The f 1 variants are integrated circuits that are covered by the scope of the present invention and are combined into a small-sized processing board. The other board is connected to the main-type-box-type tone board 1 with a single-ended connector. Use the proposed
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