TW425657B - Method for fabricating a semiconductor device - Google Patents

Method for fabricating a semiconductor device Download PDF

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Publication number
TW425657B
TW425657B TW088113790A TW88113790A TW425657B TW 425657 B TW425657 B TW 425657B TW 088113790 A TW088113790 A TW 088113790A TW 88113790 A TW88113790 A TW 88113790A TW 425657 B TW425657 B TW 425657B
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TW088113790A
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Chul-Ju Hwang
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Hwang Chul Ju
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02183—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing tantalum, e.g. Ta2O5
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02301—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment in-situ cleaning

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Chemical & Material Sciences (AREA)
  • Semiconductor Memories (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

A method for fabricating a semiconductor device is provided, in which a tantalum oxynitride film is used as a high-permittivity capacitor dielectric film. In the method of the present invention, all or some of the process steps required for the formation of the capacitor are conducted in situ in a same reactor, thereby the growth of a native oxide layer and the generation of contaminants can be effectively prevented. According to the present invention, the performance of the capacitor is greatly enhanced.

Description

425^57- 五、發明說明（1) 本發明係有 用以製造一種電 钽（TaON)，並有 電容之效能。 隨半導體裝 之需求亦顯增加 荷容量之需求仍 容為例，其所佈 低。為了使元件 積，且亦能符合 中一直不斷地在 具高介電常數之 BST((Ba, Sr)TiO； 當採用此類 能獲得大幅提昇 理與化學特性。 質衰減以及漏電 電極之複晶矽層 固定應力狀態下 利用習知方 低電極、介電質 基底於數個反應 會於其上形成原 污染物會破半導 關於一種製造半導體裝置的方法，特別是 谷’其介電層係採用高介電常數之氮氧化 效地隔離製程時相關之污染以大幅地增加 置之尺寸日漸縮小’對具大電荷儲存裝置 。既使單元元件之尺寸曰趨減小，對大電 舊持續不變。就元件之表面積而言，以電 佔面積被縮減而使其儲電能力相對地降 如電晶體、電容等同時具較小的佈佔面 維持高電荷儲存準位的表現，在製程領域 寻找新的材質。目前發現可連到此目的、 材質為包括如五氧化二组（Ta2〇5)、 |)、或？2丁（卩13(2]"1-乂1'1)〇〇3)。 鐵電（ferroelectric)材質於電荷儲存效 時，在M0S積體電路的發展卻受限於其物 例如五氧化二坦常因缺少氧而發生介電性 流的特性·'再者，五氧化二纽層與作為上 或氮化金屬層之介面特性較差，且其在高 ’所以尚存需多問題需要解決。 法形成一電容結構時’如表面預淨、形成 、以及上電極等製程時，通常會將半導體 爐中移動。而且半導體基底暴露於空氣中 生氧化層或污染物。此類原生氧化層或是 體裝置之電性’而降低單元之電容量或增425 ^ 57- V. Description of the invention (1) The present invention is used to manufacture an electric tantalum (TaON) and has the performance of a capacitor. As the demand for semiconductor devices also increases significantly, the demand for load capacity is still an example, which is low. In order to make the element product, and also to comply with the BST ((Ba, Sr) TiO) with a high dielectric constant, when using this type can greatly improve the physical and chemical properties. Mass attenuation and complex crystal of the leakage electrode The silicon layer uses a conventional low electrode and a dielectric substrate under a fixed stress state. Several reactions will form the original contamination thereon, which will break the semiconductivity. A method for manufacturing semiconductor devices, especially Gu's dielectric layer system High dielectric constant nitrogen oxidation is used to effectively isolate the related pollution during the process to greatly increase the size of the device and gradually reduce the size of the device. With large charge storage devices, even if the size of the unit elements tends to decrease, it will not continue In terms of the surface area of the components, the reduction of the electricity occupied area has relatively reduced its power storage capacity, such as transistors, capacitors, etc., and has a smaller footprint to maintain a high charge storage level. In the process field Looking for new materials. It is currently found that materials that can be connected to this purpose include materials such as pentoxide (Ta205), |), or? 2 丁 (卩 13 (2) " 1- 乂 1'1) 〇〇3). When ferroelectric materials are used for charge storage, the development of integrated circuit in M0S is limited by its properties. For example, dipentapentoxide often has a dielectric flow due to lack of oxygen. The interface characteristics between the button layer and the upper or nitrided metal layer are poor, and they are high, so there are still many problems to be solved. When forming a capacitor structure, such as surface pre-cleaning, forming, and upper electrode processes, the semiconductor furnace is usually moved. Moreover, semiconductor substrates are exposed to air to generate oxide layers or pollutants. This kind of native oxide layer is the electrical property of the bulk device.

r-^425657 _____ 一^^ - - __________^一 五、發明說明（2) 加漏電流的機會。此外，複雜的製程程序會延遲整個製轾 步驟並且降低良率。 為能更清楚地瞭解本發明之背景，以下將簡述習知形 成半導體裝置之電容的方法。首先，蝕刻於半導體基底上 之絕緣層形成一接觸結構’並於其中形成一下電極。接 著’將基底浸入稀釋HF溶劑中將原生氧化層自下電極移 除’緊接著在兩個小時内形成一電容介電質層以防土原生 氧化層的生長。假若此介電質為氧化物形式，則基底需在 低氧環境下進行熱處理產生以改善介電質的品質。為形成 此低氧環境因而必須採用包括02、Ν20或〇钓氣體。熱處理 基本上會利用到鍋爐（furnace)或是快速熱製程設備。 接著，利用CVP或是濺鍍方式在介電層上形成上電極。此 上電極為金屬氮化物或是複晶；6夕。之後以微影触刻方式完 成半導體裝置之電容結構。 然而習知技術中仍存在一些缺點。第一，採用濕蝕刻 方式並無法完全地移除原生氧化層或是造成基底被再次污 染。一般而言，原生氣化層、雜質、微粒對電容或基底的 效能會造成負面的影響。根據習知技術所採用的方法，當 半導體基底在反應室間移動時常會暴露於空氣中，使得表 面形成厚度約10A的原生氧化層。此原生氧化層會破壞半 導體裝置之電性與物性。但是此原生氧化層並無法利用濕 式化學清洗方式如HF溶劑將之去除。再者，半導體裝置亦 會被濕式清洗帶來之雜質所污染。第二，在利用五氧化二 鈕作為電容介電層的實例中，氧在化學劑量上的短缺造成r- ^ 425657 _____ One ^^--__________ ^ One 5. Description of the invention (2) Opportunity to add leakage current. In addition, complex manufacturing processes can delay the entire manufacturing process and reduce yield. In order to understand the background of the present invention more clearly, a conventional method for forming a capacitor of a semiconductor device will be briefly described below. First, an insulating layer etched on a semiconductor substrate forms a contact structure 'and a lower electrode is formed therein. Next, the substrate was immersed in a dilute HF solvent to remove the native oxide layer from the lower electrode, and then a capacitive dielectric layer was formed within two hours to prevent the growth of the native oxide layer of the soil. If the dielectric is in the form of an oxide, the substrate needs to be heat-treated in a low-oxygen environment to improve the quality of the dielectric. To form this hypoxic environment it is necessary to use 02, N20 or 0 fishing gas. Heat treatment basically uses a furnace or a rapid thermal process equipment. Next, an upper electrode is formed on the dielectric layer by CVP or sputtering. The upper electrode is a metal nitride or a multiple crystal; After that, the capacitor structure of the semiconductor device is completed by lithography. However, there are still some disadvantages in the conventional technology. First, the wet etching method cannot completely remove the native oxide layer or cause the substrate to be contaminated again. Generally speaking, the primary gasification layer, impurities, and particles have a negative impact on the performance of the capacitor or substrate. According to the method adopted in the conventional technology, when the semiconductor substrate is moved between the reaction chambers, it is often exposed to the air, so that a primary oxide layer having a thickness of about 10A is formed on the surface. This primary oxide layer will destroy the electrical and physical properties of the semiconductor device. However, this primary oxide layer cannot be removed by wet chemical cleaning methods such as HF solvents. Furthermore, semiconductor devices are also contaminated by impurities brought about by wet cleaning. Second, in the case of using the pentoxide as the dielectric layer of the capacitor, the chemical shortage of oxygen caused

第5頁 425657 五、發明說明（3) 不預期地增加漏 後熱處理後，氣 圓柱結構。此時 發作為下電極之 氣化二鈕層之間 負面影響。第四 用於銷爐中尺裡 作為上電極，其 較差的接合能力 之製程步驟必須 假若兩製程步驟 設備分派待機時 因此’本發 置的方法，既使 層與污染。 本發明之另 方法’簡化製程 本發明之又一目 法，採用新的電 性。 本發明之再 方法，使上電極 造成漏電流之情 根據本發明 電流。第 體溢出， ，氧快速 實例中， 。此對具 ，習知方 較大尺寸 與五氡化 會破壞電 在不同的 間不存在 間（i d 1 e 明之一目 需執行數 五氧化二 會以非晶 緣擴散， 形成於複 五氧化二 步驟較複 五，利用 觸介面會 第六，因 ’相當費 遲，不可 種製造報導體裝置的 性（uniformity) 0 造報導體裝置的方 容介電質改進習知技術中介電特性與穩定 三’在形成 五氧化二组 地沿晶格邊 氮氧化矽層 高電容質之 法所採取之 的基底。第 二钽間之接 容之電性。 設備中進行 時間上的延 time) ° 的，在於提 個單元製程 目的’在於提供一 以改進晶圓間之一致 的’在於提供一種製 —目的，在於提供一 與下電極之介面異質 況亦可獲得改善。 钽層並進行 格型態形成 在採用複晶 晶石夕層與五 短層會產生 雜，並不適 金屬氮化物 發生反應， 為製造電容 時。此外* 避免地需對 供一種製造報導體裝 亦不會造成原生氧化 種製造報導體裝置的 性減小，因缺乏氧而 特徵，係提供一種製造一半導體裝置Page 5 425657 V. Description of the invention (3) Unexpected increase of post-leakage heat treatment, gas cylinder structure. At this time, a negative influence is caused between the two layers of the gasification two buttons as the lower electrode. Fourth, the process steps used for the pinhole of the furnace as the upper electrode, and its poor bonding ability must be provided if the two process steps are in standby when the equipment is dispatched, so the method of the present invention, even the layer and pollution. Another method of the present invention simplifies the manufacturing process. Another method of the present invention uses a new electrical property. According to another method of the present invention, the upper electrode causes a leakage current according to the present invention. The body overflows, in the case of oxygen fast,. For this pair, the larger size and pentification of the known side will destroy the electricity between different existences (id 1 e), one of the two items needs to be performed. The second pentoxide will diffuse with an amorphous edge, and it is formed in the second pentoxide step. Compared with the fifth, the use of the touch interface will be sixth, because 'quite too late, can not be used to produce the uniformity of the conductor device (uniformity) The substrate adopted by the method of high capacitance of the silicon oxynitride layer along the lattice edge of the second group of pentoxide. The electrical conductivity of the second tantalum capacitor. The time delay in the device is to mention a The purpose of the unit manufacturing process is to provide a method to improve wafer-to-wafer consistency. The purpose is to provide a manufacturing method that aims to provide an interface with the lower electrode which can also be improved. The tantalum layer is formed in a lattice pattern. When the polycrystalline spar layer and the five short layers are used, impurities are generated, and the metal nitride does not react, which is used to manufacture capacitors. In addition, it is necessary to avoid the need to provide a device for manufacturing a report conductor, which does not cause a reduction in the performance of a primary oxide device for manufacturing a report conductor device. It is characterized by a lack of oxygen, and provides a method for manufacturing a semiconductor device.

425657 五、發明說明（4) 的方法’於一半導體製成設備中進行，該半導體製程設備 至少具一反應室，包括：形成一第一導電層於/半導體基 底上；圖案化並蝕刻該第一導電層以定義出一第一電極； 於該半導體製程設備之一反應室中進行化學氣相沈積形成 一氮氧化钽層，作為該第一電極上之一電容介電質；以及 形成一第二電極覆蓋該氮氧化钽層。 在形成該氮氧化鉅層前，還包括於形成該氮氧化钽層 相同之反應室中對該半導體基底施以電漿清洗。 該電漿清洗步驟係採用一含鹵化物之電槳。 該電漿清洗步驟係採用一含齒化物與一惰性氣體之混合電 漿。 該電漿清洗步驟係採用一含i化物與一含氫氣體之混 合電槳。 該第一電極包括選自一摻雜導電雜質之矽晶層、一金 屬氮化層、一重金屬層、一财性（refract〇ry)金屬層、 一類重金屬層、以及一導電氧化層之一薄層所組成。 該第一電極為一複晶矽層，其具作為電漿摻雜之複數傘狀 突起。 上述方法還包括對氮氧化鉅層施以電漿處理，以改善 介面特性與層面品質，其中該電漿處理步驟係在形成該氮 氧化组層相同的反應室進行，或是將該半導體基底在真空 或低氧的環境下移至另一反應室. 該電漿處理步驟所採用氣體組成包括一含氧混合氣 體、一含氮混合氣體、以及一含氫混合氣體。425657 V. Method (4) of the invention is performed in a semiconductor manufacturing equipment. The semiconductor processing equipment has at least one reaction chamber, which includes: forming a first conductive layer on a semiconductor substrate; patterning and etching the first semiconductor layer; A conductive layer to define a first electrode; chemical vapor deposition in a reaction chamber of the semiconductor process equipment to form a tantalum oxynitride layer as a capacitor dielectric on the first electrode; and forming a first Two electrodes cover the tantalum oxynitride layer. Before forming the giant oxynitride layer, the semiconductor substrate is further subjected to plasma cleaning in the same reaction chamber in which the tantalum oxynitride layer is formed. The plasma cleaning step uses a halide-containing electric paddle. The plasma cleaning step uses a mixed plasma containing a dentate and an inert gas. The plasma cleaning step uses a mixture of an i-containing compound and a hydrogen-containing gas. The first electrode includes a thin layer selected from a silicon crystal layer doped with conductive impurities, a metal nitride layer, a heavy metal layer, a refractor metal layer, a type of heavy metal layer, and a conductive oxide layer. Made up of layers. The first electrode is a polycrystalline silicon layer having a plurality of umbrella-shaped protrusions doped as a plasma. The above method further includes applying plasma treatment to the giant oxynitride layer to improve the interface characteristics and layer quality. The plasma treatment step is performed in the same reaction chamber in which the oxynitride layer is formed, or the semiconductor substrate is placed in Move to another reaction chamber under vacuum or low oxygen environment. The gas composition used in the plasma treatment step includes an oxygen-containing mixed gas, a nitrogen-containing mixed gas, and a hydrogen-containing mixed gas.

第7頁 4 2 5 6 5 7 五、發明說明（5) 該第二電極包括選自一掺雜導電雜質之矽晶層、一金 屬氮化層、一重金屬層、一耐性（refractory)金屬唐 一類重金屬層、以及一導電氧化層之一薄層所組成。 該化學氣相沈積該氮氧化钽層步驟所採用钽的氣體源 係選自包括由 TPE[Ta(OC2H5)5]、PDNAT[Ta[N(CH3)2h]、 PDEAT[Ta[N(C2H5)2]5]、Ta(OC2H5)5_n(OCH2CH2OCH3)n、以及 TaC 1所組成，n為整數且1S nS 4 ° 該化學氣相沈積該氮氧化钽層步驟所採用溫度則設定 於100C至900C間’壓力則設定於lmTorr至1 00mT〇rr間， 加入該反應室之該含钽氣體流率為〇. 〇 1 s c⑶至]s 1 m。 該化學氣相沈積該氮氧化担層步驟係採用TaC 15、一 含氧氣體、一含氮氣體作為形成該氮氡化组層之氣體源。 該化學氣相沈積該氮氧化鈕層步驟係採用一含氧氣體與 TPE[Ta(〇C2H5)5M PDMT[Ta[N(CH3)2] 5]作為形成該氮氧化 鈕層之氣體源。 該化學氣相沈積該氛氧化组層步驟係採用選自巴枯— 含氮氣體、一惰性氣體、以及一含惰性氣體成分之氣體， 將其加入形成該氮氧化短層之該氣體源中。 該化學氣相沈積該氮氧化紐層步驟係採用電装能量 (plasma power)離子化該氣體源。 根據本發明之另一特徵’係提供—種製造一半導體裝 置的方法’於一半導體製成sS:備中進行，該半導體製程設 備至少具-反應t ’包括：利用含鹵素成分氣體之電漿清 洗一半導體基底，用以移除一原生氧化層以及其他附著之Page 7 4 2 5 6 5 7 V. Description of the invention (5) The second electrode includes a silicon crystal layer doped with a conductive impurity, a metal nitride layer, a heavy metal layer, and a refractory metal layer. A heavy metal layer and a thin layer of a conductive oxide layer. The tantalum gas source used in the step of chemical vapor deposition of the tantalum oxynitride layer is selected from the group consisting of TPE [Ta (OC2H5) 5], PDNAT [Ta [N (CH3) 2h], PDEAT [Ta [N (C2H5) 2] 5], Ta (OC2H5) 5_n (OCH2CH2OCH3) n, and TaC 1, where n is an integer and 1S nS 4 ° The temperature used in the step of chemical vapor deposition of the tantalum oxynitride layer is set between 100C and 900C 'The pressure is set between lmTorr and 100 mT0rr, and the tantalum-containing gas flow rate added to the reaction chamber is 0.01 s c⑶ to] s 1 m. The step of chemical vapor deposition of the oxynitride support layer uses TaC 15, an oxygen-containing gas, and a nitrogen-containing gas as a gas source for forming the nitrogenated trioxide layer. The chemical vapor deposition of the oxynitride button layer uses an oxygen-containing gas and TPE [Ta (〇C2H5) 5M PDMT [Ta [N (CH3) 2] 5] as a gas source for forming the oxynitride button layer. The step of chemically vapor-depositing the atmospheric oxidation group layer is to use a gas selected from the group consisting of Baku-a nitrogen-containing gas, an inert gas, and an inert gas component, and add it to the gas source forming the short nitrogen oxide layer. The step of chemical vapor deposition of the oxynitride layer uses plasma power to ionize the gas source. According to another feature of the present invention, 'a method is provided for manufacturing a semiconductor device', which is performed in a semiconductor fabrication process. The semiconductor process equipment has at least a reaction t ', including: plasma cleaning using a halogen-containing gas. A semiconductor substrate for removing a native oxide layer and other attached

第8頁 “ —w u W 小 A -r 五、發明說明（6) -- 污染物；形成一第一導電層於該半導體基底上；圖案化並 银刻該弟一導電層以定義出一第一電極；於該半導體製^ 設備之一反應室中進行化學氣相沈積形成一氮氧化组層， 作為該第一電極上之一電容介電質；形成一第二電極覆蓋 該氮氧化组層；其中，上述所有處理步驟係在形成該氮^ 化组層相同的反應室進行，或是將該半導體基底在真空或 低氧的環境下移至另一反應室進行。 為讓本發明之上述和其他目的、特徵、和優點能更明顯易 懂’下文特舉一較佳實施例，並配合所附圓式，作詳 細說明如下： 圖式簡單說明： 第1A至1D圖係顯示本發明中製程電容步驟之剖面：以 及 第2圖係顯示完成本發明之半導體裝置之結構剖面 圖。 符號說明： 200、5〜半導體基底；210〜絕緣圖案層；220〜接觸 洞；230〜下電極；240〜介電層，·250~上電極；10〜中央 搶；20 、 30 、 40 、 50〜反應室。 實施例： 半導體裝置之電容製程為本發明最佳實 以下將以一 例：配:圖，詳述於下文。執行形成電容之製程所採用之 半導體製程設，包括數個反應室（react〇r)。 百先，將半導體基底200送入反應是中，半導體基底Page 8 "—wu W 小 A -r 5. Explanation of the invention (6)-Contaminants; forming a first conductive layer on the semiconductor substrate; patterning and silver engraving the conductive layer to define a first conductive layer An electrode; performing chemical vapor deposition in a reaction chamber of one of the semiconductor manufacturing equipment to form an oxynitride group layer as a capacitor dielectric on the first electrode; forming a second electrode to cover the oxynitride group layer Wherein all the above processing steps are performed in the same reaction chamber forming the nitrogen group layer, or the semiconductor substrate is moved to another reaction chamber under a vacuum or a low oxygen environment. And other objects, features, and advantages can be more clearly understood. The following is a detailed description of a preferred embodiment, in conjunction with the attached round form, as follows: Brief description of the drawings: Figures 1A to 1D show the present invention The cross section of the capacitor step: and FIG. 2 is a cross-sectional view showing the structure of the semiconductor device of the present invention. Symbol description: 200, 5 ~ semiconductor substrate; 210 ~ insulating pattern layer; 220 ~ contact hole; 230 ~ lower electrode; 240 ~ Dielectric layer, 250 ~ upper electrode; 10 ~ central grabbing; 20, 30, 40, 50 ~ reaction chamber. Example: The capacitor manufacturing process of the semiconductor device is the best of the present invention. The following will take an example: with: Figure, details It is described below. The semiconductor process equipment used to execute the capacitor formation process includes several reaction chambers. Baixian, the semiconductor substrate 200 is sent into the reaction process, and the semiconductor substrate

425657 五、發明說明（7) 2,括絕緣層严案21〇與接觸洞。接著，在形成下電極 蚰，在將形成氮氧化鉅層之原反應室中對基底2 〇 〇進行電 ，清，。在此實施例中，電漿氣體係混合SF6與虹。電漿 清洗氣體，選自氟化物、惰性氣體、或是氫化物等混合氣 體成分。氟化物氣體可選自包括氟碳化物、氟氮化物、氟 f化物、氟矽化物、氟溴化物、氟磷化物、以及氟砷化物 等。惰性氣體可選自氬、氖、氪等。氫化物可選自比、s 土 2H6、SiH4、BH3、AsH3、PH3、GeH4、SiH2Cl2 以及NH3 的混合 物。 然後形成第一導電層，接著經圖案化以及蝕刻製程形 成下電極’如第1B圖所示。 上述各步驟係在一反應室中進行，或是在低氧狀態下 移動基底至另一反應室中以防止基底表面受到污染。下電 極可由薄導電層群組成，其可包括摻雜導電雜質之矽晶 層、金屬氮化層、重金屬層、耐性（refract〇ry)金屬 層、類重金屬層、以及導電氧化層。此導電氧化層包括 Ru〇2層或Ir〇2層。在此實施例中，形成具傘狀（raushr〇〇m shaped )突起之複晶矽層，並利用含Ph3之電漿氣體進行 離子佈植、清洗並補強此類突起。接著利用圖案化與蝕刻 製程形成下電極230。欲進行電漿清洗之氣體成分可隨植 入雜質不同而改變’但通常含摻雜雜質與氫之混合物已可 滿足一般需求。因此當摻入雜質為硼或砷時以BHa與AsH3即 可。在上述實例中氫化合物可同時清洗表面並補強突起。425657 V. Description of the invention (7) 2, Including severe insulation layer 21 and contact holes. Next, after forming the lower electrode 蚰, the substrate 2000 is electrically cleaned in the original reaction chamber where the oxynitride layer will be formed. In this embodiment, the plasma gas system mixes SF6 and rainbow. Plasma cleaning gas is selected from the group consisting of fluoride, inert gas, or mixed gas such as hydride. The fluoride gas may be selected from the group consisting of fluorocarbon, fluoronitride, fluorofide, fluorosilicide, fluorobromide, fluorophosphide, and fluoroarsenide. The inert gas may be selected from argon, neon, krypton, and the like. The hydride may be selected from a mixture of ratio, s 2 2H6, SiH4, BH3, AsH3, PH3, GeH4, SiH2Cl2, and NH3. Then a first conductive layer is formed, and then a lower electrode 'is formed through a patterning and etching process as shown in FIG. 1B. The above steps are performed in a reaction chamber, or the substrate is moved to another reaction chamber under a low oxygen condition to prevent the substrate surface from being contaminated. The lower electrode may be composed of a thin conductive layer group, which may include a silicon layer doped with a conductive impurity, a metal nitride layer, a heavy metal layer, a refractory metal layer, a heavy metal-like layer, and a conductive oxide layer. The conductive oxide layer includes a Ru02 layer or an Ir02 layer. In this embodiment, a polycrystalline silicon layer with raushrm shaped protrusions is formed, and a plasma gas containing Ph3 is used for ion implantation, cleaning, and reinforcing such protrusions. Then, a patterning and etching process is used to form the lower electrode 230. The composition of the gas to be cleaned by plasma can be changed according to the implanted impurities', but usually a mixture containing doped impurities and hydrogen can meet the general requirements. Therefore, when the impurity is boron or arsenic, BHa and AsH3 are sufficient. In the above example, the hydrogen compound can simultaneously clean the surface and reinforce the protrusions.

第10頁 425657 五、發明說明（8) 氣體源係包括由 TPE[Ta(OC2H5)5]、PMAT[Ta[N(CH3)2]5]、 PDEAT[Ta[N(C2H5)2]5]、Ta(OC2H5)5—n(OCH2CH2OCH3)n、以及 TaCl5等所組成。Page 10 425657 V. Description of the invention (8) The gas source system includes TPE [Ta (OC2H5) 5], PMAT [Ta [N (CH3) 2] 5], PDEAT [Ta [N (C2H5) 2] 5] , Ta (OC2H5) 5-n (OCH2CH2OCH3) n, and TaCl5.

Ta(0et)5—n(0R)n，其中Oet 為OC2H5，0R 為OCH2CH2OCH3， 隨n值會改變其化學特性。Ta (0et) 5-n (0R) n, where Oet is OC2H5, and 0R is OCH2CH2OCH3, which will change its chemical characteristics with the value of n.

Ta(0et)5_n(0R)或TaCOetUORh (n=l，2)因較 Ta(0et )5具相同或更高的蒸汽壓（vapor pressure)，而 易於使用於化學沈積設備中。再者，Ta(0et)5_n(0R)n化學 穩定性較高，且與Ta (Oe t )5之鎔點約為室溫（2 1 °C )相較 有較低的鎔點（-2 0 °C )。 在此實施例中係採用评£[丁&(0(：2115)5]作為钽的來源， 並一起混合含氣的氣體。 此沈積製程係操作在溫度l〇〇°c至900。(：間，壓力在 lmTorr至1 OOmTorr間’供應TPE與含氮氣體，其流率分別 為O.Olsccm至lslm與lsccm至lOslm。此時含氫化合物之氣 體可一起供應，流率為O.Olsccm至lslm。氫化物可選自η 2、Si2H6、SiH4、BH3、AsH3、PH3、GeH4、SiH2Cl2 以及ΝΗ3 的 混合物。 氣體源經電漿能量被離子化。在較佳實施例中，電装 能量設定於1 0W至3KW間，含氮氣體或含氫化物氣體之流率 設定於10seem至lOslm間。沈積溫度則設定於100 ι至9〇〇 °C間，壓力則設定於lmTorr至1 OOmTorr間。 在另一實施例中’利用PDMAT或PDEAT作為鈕氣體源， 以含氣之氣體做為反應氣體’其流率分別為〇.〇lSCCm至Ta (0et) 5_n (0R) or TaCOetUORh (n = 1, 2) is easier to use in chemical deposition equipment because it has the same or higher vapor pressure than Ta (0et) 5. In addition, Ta (0et) 5_n (0R) n has high chemical stability, and has a lower pupal point (-2 1 ° C) than that of Ta (Oe t) 5 (-2 1 ° C). 0 ° C). In this embodiment, [Ding & (0 (: 2115) 5] is used as the source of tantalum, and a gas containing gas is mixed together. This deposition process is operated at a temperature of 100 ° C to 900. : At a pressure of lmTorr to 100 mTorr, TPE and nitrogen-containing gas are supplied, and the flow rates thereof are 0.01sccm to lslm and lsccm to lslm. At this time, the gas containing hydrogen compounds can be supplied together, and the flow rate is 0.1sccm Up to lslm. The hydride may be selected from a mixture of η2, Si2H6, SiH4, BH3, AsH3, PH3, GeH4, SiH2Cl2, and NΗ3. The gas source is ionized by plasma energy. In a preferred embodiment, the energy of the electrical device is set at Between 10W and 3KW, the flow rate of nitrogen-containing gas or hydride-containing gas is set between 10seem and 10slm. The deposition temperature is set between 100 ι and 900 ° C, and the pressure is set between lmTorr and 100mTorr. In another embodiment, 'using PDMAT or PDEAT as a button gas source, and using a gas containing gas as a reaction gas', the flow rates are 0.001 SCCm to

第11頁 卜425657 五、發明說明（9) lslm與lsccm至lOslm。在較佳的狀況下，沈積溫度設定於 100 °C至9 0 0 °C間，壓力則設定於lmTorr至lOOmTorr間。此 時含氫化合物之氣體可加入反應氣體中，流率為0. 01 seem 至 1 s 1 m。 與前述實施例相同地，氣體源經電漿能量被離子化。 在較佳實施例中，電漿能量設定於1 0W至3KW間，含氧氣體 或含氫化物氣體之流率設定於10 sccm至l〇s lm間。沈積溫 度則設定於100 °C至9 0 0 t間，壓力則設定於lmTorr至 lOOmTorr^。 在另一實施例中係採用TaC 15作為钽的來源，並一起 混合含氧與氮氧化物的氣體。此沈積製程係操作在溫度 100 °C至900 °c間’壓力在lmTorr至lOOmTorr間，供應Page 11 BU 425657 V. Description of the invention (9) lslm and lsccm to lOslm. Under better conditions, the deposition temperature is set between 100 ° C and 900 ° C, and the pressure is set between lmTorr and 100mTorr. At this time, a gas containing hydrogen compounds can be added to the reaction gas at a flow rate of 0.01 seem to 1 s 1 m. As in the previous embodiment, the gas source is ionized by plasma energy. In a preferred embodiment, the plasma energy is set between 10W and 3KW, and the flow rate of the oxygen-containing gas or hydride-containing gas is set between 10 sccm and 10 slm. The deposition temperature is set between 100 ° C and 900 t, and the pressure is set between lmTorr and 100mTorr ^. In another embodiment, TaC 15 is used as the source of tantalum, and a gas containing oxygen and nitrogen oxides is mixed together. This deposition process operates at a temperature between 100 ° C and 900 ° c. The pressure is between lmTorr and 100mTorr.

TaCl5與含氮與氮氧化物的氣體，其流率分別為〇. 〇1 sccm 至lslm與lsccm至lOslm。此時含氫化合物之氣體可一起供 應’流率為0. 01 seem至1 slm。氫化物可選自H2、Si2He、 SiH4、BH3、AsHs、PHa、GeH4、SiH2Cl2 以及NH3 的混合物。 亂體源經電紫能董被離子化。在較佳實施例中，電漿能量 設定於1 0W至3KW間，含氧或氫氮氣體化物氣體之流率設定 於1 0 sc cm至1 〇 s 1 m間。在較佳的情況下，沈積溫度則設定 於100 C至90 0 °C間’壓力則設定於lmT〇rr至1〇〇111了〇1^間。 在形成上述氣氧化钽層後，於同一反應室中形成第1D 圖所示之上電極250，完成電容之基本結構。亦可將半導 體基底在真空或低氧的環境下移至另一反應室形成上電極 25 0。此上電極可包括摻雜導電雜質之矽晶層、金屬氮化TaCl5 and nitrogen and nitrogen oxide-containing gases have flow rates of 0.01 sccm to lslm and lsccm to lOslm, respectively. 01 seem 至 1 slm。 Gases containing hydrogen compounds can be supplied together at this time. The hydride may be selected from a mixture of H2, Si2He, SiH4, BH3, AsHs, PHa, GeH4, SiH2Cl2, and NH3. The source of the disorder was ionized by the electric purple energy. In a preferred embodiment, the plasma energy is set between 10 W and 3 KW, and the flow rate of the oxygenated or hydrogen-nitrogen-containing gas is set between 10 sc cm and 10 s 1 m. In a better case, the deposition temperature is set between 100 C and 90 0 ° C, and the pressure is set between lmTorr and 1001 ^. After the gas tantalum oxide layer is formed, the upper electrode 250 shown in FIG. 1D is formed in the same reaction chamber to complete the basic structure of the capacitor. The semiconductor substrate can also be moved to another reaction chamber under vacuum or low oxygen to form the upper electrode 250. The upper electrode may include a silicon crystal layer doped with conductive impurities, metal nitride

第12頁 五、發明說明（9) lslm與lsccm至l〇sim。在較佳的狀況下，沈積溫度設定於 100C至900C間，壓力則設定於lmTorr至lOOmTorr間。此 時含氫化合物之氣體可加入反應氣體中，流率為〇.〇lsccm 至 1 s 1 m。 與前述實施例相同地，氣體源經電漿能量被離子化。 在較佳實施例中’電漿能量設定於丨〇W至3KW間，含氧氣體 或含氫化物氣體之流率設定於1 〇 s C c m至1 〇 s丨m間。沈積溫 度則設定於1 00 t：至900 °c間’壓力則設定於lmTorr至 lOOmTorr 間。 在另一實施例中係採用TaC 15作為钽的來源，並一起 混合含氧與氮氧化物的氣體。此沈積製程係操作在溫度 100C至900 C間’壓力在lmTorr至lOOmTorr間，供應 TaCls與含氮與氮氧化物的氣體’其流率分別為〇 . 〇1 sccffi 至lslm與lsccm至lOslm。此時含氫化合物之氣體可一起供 應，流率為O.Olsccm至lslm。氫化物可選自比、si2H6、 SiH4、BH3、AsH3、PH3、GeH4、SiH2Cl2 以及NH3 的混合物。 氣體源經電漿能量被離子化。在較佳實施例中電聚能量 設定於10W至3KW間，含氧或氩氤氣體化物氣體之流率設定 於lOsccm至1〇31瓜間。在較佳的情況下’沈積溫度則設定 於100t至90(TC間，壓力則設定於lmT〇rri1〇〇mT〇rr間。 在形成上述氮氧化组層後’於同一反應室中形成第11} 圖所示之上電極25 0，完成電容之基本結構。亦可將半導 體基底在真空或低氧的環境下移至另一反應室形成上電極 250。此上電極可包括摻雜導電雜質之矽晶層、金屬氮化Page 12 5. Description of the invention (9) lslm and lsccm to 10sim. Under better conditions, the deposition temperature is set between 100C and 900C, and the pressure is set between lmTorr and 100mTorr. At this time, a gas containing a hydrogen compound can be added to the reaction gas at a flow rate of 0.01 scm to 1 s 1 m. As in the previous embodiment, the gas source is ionized by plasma energy. In a preferred embodiment, the 'plasma energy is set between 0 W and 3 KW, and the flow rate of an oxygen-containing gas or a hydride-containing gas is set between 10 s C cm and 10 s m. The deposition temperature is set between 100 t: to 900 ° c and the pressure is set between lmTorr and 100 mTorr. In another embodiment, TaC 15 is used as the source of tantalum, and a gas containing oxygen and nitrogen oxides is mixed together. This deposition process is operated at a temperature between 100C and 900 C and a pressure between lmTorr and 100mTorr. TaCls and nitrogen and nitrogen oxide-containing gases are supplied at flow rates of 0.01 sccffi to lslm and lsccm to lslm. At this time, the gas containing hydrogen compounds can be supplied together at a flow rate of 0.01 sccm to lslm. The hydride may be selected from a mixture of ratio, si2H6, SiH4, BH3, AsH3, PH3, GeH4, SiH2Cl2, and NH3. The gas source is ionized by plasma energy. In a preferred embodiment, the electro-energetic energy is set between 10W and 3KW, and the flow rate of the oxygen or argon-containing gaseous gas is set between 10 sccm and 1031 melon. In the best case, the 'deposition temperature is set between 100t and 90 ° C, and the pressure is set between lmTorri100mTorr. After the formation of the above-mentioned nitrogen oxide group layer', the 11th is formed in the same reaction chamber. } The upper electrode 250 as shown in the figure completes the basic structure of the capacitor. The semiconductor substrate can also be moved to another reaction chamber in a vacuum or low oxygen environment to form an upper electrode 250. This upper electrode may include a conductive impurity doped Silicon layer, metal nitride

2 5 6 5 7 五、發明說明（10) -------_____ 2:°。此上電極可包括摻雜導電雜質之矽晶層、金屬氮化 2、重金屬層、耐性（refractory)金屬層、類重金氮化 勺二以及導電乳化層。與下電極相同土也’此導電氧化層可 包括Ru02層或Ir〇2層。 第2圖係顯示完成本發明之半導體裝置之結構剖面 圖’包括富庶個反應室20、30、40、50。所有上述製程步 驟可在相同的反應室進行，或是將半導體基底在真空或= 氧的環境下移至另一反應室，以防止產生原生氧化層或是 遭受污染。利用中央艙10之傳送裝置（未示於圖令）傳送 基底5於相對應之反應室。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者’在不脫離本發明之精神 和範圍内，當可作更動與潤飾’因此本發明之保護範圍當 視後附之申請專利範圍所界定者為準。2 5 6 5 7 V. Description of the invention (10) -------_____ 2: °. The upper electrode may include a silicon crystal layer doped with conductive impurities, a metal nitride, a heavy metal layer, a refractory metal layer, a heavy gold-like nitride, and a conductive emulsified layer. The same as the lower electrode, the conductive oxide layer may include a Ru02 layer or an Ir02 layer. Fig. 2 is a sectional view showing the structure of a semiconductor device according to the present invention, including a plurality of reaction chambers 20, 30, 40, and 50. All of the above process steps can be performed in the same reaction chamber, or the semiconductor substrate can be moved to another reaction chamber under a vacuum or oxygen environment to prevent the generation of native oxide layers or contamination. The substrate 5 is transferred to the corresponding reaction chamber by a transfer device (not shown in the drawing) of the center cabin 10. Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Any person skilled in the art can change and retouch without departing from the spirit and scope of the present invention. Therefore, the protection of the present invention The scope shall be determined by the scope of the attached patent application.

第13頁Page 13

Claims (1)

425657 六、申請專利範圍 1. 一種製造一半導體裝置的方法，於一半導體製成設 備中進行’該半導體製程設備至少具一反應室，包括： 形成一第一導電層於一半導體基底上； 圖案化並蝕刻該第一導電層以定義出一第一電極； 於該半導體製程設備之一反應室中進行化學氣相沈積 形成一氮氧化钽層，作為該第一電極上之一電容介電質； 以及 形成一第二電極覆蓋該氮氧化钽層。 2. 如申請專利範圍第1項所述之方法，其中在形成該 氮氡化紐層前，還包括於形成該氮氧化钽層相同之反應室 中對該半導體基底施以電漿清洗。 3. 如申請專利範圍第2項所述之方法，其中該電装清 洗步驟係採用一含南化物之電衆。 4. 如申請專利範圍第2項所述之方法，其中該電渡清 洗步驟係採用一含齒化物與一惰性氣體之混合電漿。 5如申請專利範圍第2項所述之方法，其中該電漿清洗 步驟係採用一含豳化物與一含氫氣體之混合電聚。 6. 如申請專利範圍第1項所述之方法，其中該第一電 極包括選自一摻雜導電雜質之矽晶層、一金屬氣化層、一 重金屬層、—耐性（refractory)金屬層、一類重金屬 層、以及一導電氧化層之一薄層所組成。 7. 如申請專利範圍第1項所述之方法’其中該第— 極為一複晶珍層，其具作為電漿摻雜之複數傘狀突起。 8·如申請專利範圍第1項所述之方法’還包括對氣氣425657 6. Scope of patent application 1. A method for manufacturing a semiconductor device, which is performed in a semiconductor manufacturing equipment, the semiconductor processing equipment has at least one reaction chamber, including: forming a first conductive layer on a semiconductor substrate; pattern Forming and etching the first conductive layer to define a first electrode; and performing chemical vapor deposition in a reaction chamber of the semiconductor process equipment to form a tantalum oxynitride layer as a capacitor dielectric on the first electrode And forming a second electrode to cover the tantalum oxynitride layer. 2. The method according to item 1 of the scope of patent application, wherein before forming the azanitride layer, the method further includes performing plasma cleaning on the semiconductor substrate in the same reaction chamber in which the tantalum oxynitride layer is formed. 3. The method as described in item 2 of the scope of the patent application, wherein the cleaning step of the electric device uses an electric compound containing a south chemical. 4. The method as described in item 2 of the scope of the patent application, wherein the electric washing step uses a mixed plasma containing a dentate and an inert gas. 5. The method according to item 2 of the scope of patent application, wherein the plasma cleaning step uses a mixed electropolymerization of a halide-containing compound and a hydrogen-containing gas. 6. The method according to item 1 of the scope of patent application, wherein the first electrode comprises a silicon crystal layer doped with a conductive impurity, a metal vaporization layer, a heavy metal layer, a refractory metal layer, A heavy metal layer and a thin layer of a conductive oxide layer. 7. The method according to item 1 of the scope of the patent application, wherein the first electrode is a complex crystal layer having a plurality of umbrella-shaped protrusions doped as a plasma. 8. The method described in item 1 of the scope of patent application 'further includes 4 2 5 B B - 六 、申請專利範圍 =麵層施以電漿處理，以改善介面特性與層面品質’其中 g^處理步驟係在形成該氮氧化鈕層相同的反應室進 二’或是將該半導體基底在真空或低氧的環境下移至另一 反應室。 9.如申請專利範圍第8項所述之方法，其中該電漿處 XW -1-1- ,、 1 广’鄉所採用氣體組成包括一含氧混合氣體、一含氮混合 氣體、以》 . ^ 乂及―含氫混合氣體。 1 0，如申請專利範圍第1項所述之方法，其中該第二電 極包括A ^自—摻雜導電雜質之矽晶層、一金屬氮化層'一 重金屈思 、嘴、—耐性（refractory)金屬層、一類重金屬 曰以及一導電氧化層之—薄層所組成。 、U.如申請專利範圍第1項所述之方法，其中該化學氣 相'尤積該氮氧化鈕層步驟所採用钽的氣體源係選自包括由 TPE[Ta(〇C2H5)5] ' PDNAT[Ta[N(CH3)2]5] ' PDEAT [ Ta [ N (C2 Η 5)2]5]、Ta(〇c2H5)5_n(〇CH2CH2〇CH3)n、以及TaCl5K 組成，n 為整數且1芸。 12·如_申請專利範圍第1項所述之方法，其中該化學氣 相沈積該氛氧化纽層步驟所採用溫度則設定於1〇〇〇c至 9〇〇〇C間，壓力則設定於ImTorr至lOOmTorr間，加入該反 應室之該含钽氣體流率為〇. 01 seem至lslm。 .1 3 如申請專利範圍第1項所述之方法，其令該化學氣 相，積該氮氧化组層步羯係採用Ta(^、—含氧氣體、一 含氣氣體作為形成該氤氧化钽層之氣體源。 1 4_如申請專利範圍第丨項所述之方法其中該化學氣4 2 5 BB-VI. Scope of patent application = Plasma treatment on the surface layer to improve the interface characteristics and layer quality 'where g ^ the processing step is performed in the same reaction chamber forming the nitrogen oxide button layer' or the The semiconductor substrate is moved to another reaction chamber under a vacuum or a low oxygen environment. 9. The method as described in item 8 of the scope of the patent application, wherein the plasma composition XW -1-1-, 1 and the gas composition used in Guang'xiang includes an oxygen-containing mixed gas, a nitrogen-containing mixed gas, and ^ 乂 and ―Hydrogen-containing gas mixture. 10, The method as described in item 1 of the scope of the patent application, wherein the second electrode includes a silicon self-doped silicon impurity layer, a metal nitride layer, a heavy gold qusi, a mouth, and a resistance ( refractory) metal layer, a type of heavy metal, and a conductive oxide layer-a thin layer. U. The method according to item 1 of the scope of patent application, wherein the chemical vapor phase 'especially the tantalum gas source used in the step of accumulating the oxynitride button layer is selected from the group consisting of TPE [Ta (〇C2H5) 5] PDNAT [Ta [N (CH3) 2] 5] 'PDEAT [Ta [N (C2 Η 5) 2] 5], Ta (〇c2H5) 5_n (〇CH2CH2〇CH3) n, and TaCl5K, n is an integer and 1 Yun. 12. The method as described in item 1 of the scope of patent application, wherein the temperature used in the step of chemical vapor deposition of the atmospheric oxidation button is set between 1000c and 9000c, and the pressure is set at 01 seem 到 lslm。 ImTorr to lOOmTorr, the tantalum-containing gas flow rate added to the reaction chamber is 0.01 seem to lslm. .1 3 The method as described in item 1 of the scope of the patent application, which causes the chemical vapor phase to accumulate the nitrogen oxide group step by using Ta (^,-oxygen-containing gas, a gas-containing gas as the oxidant Gas source for tantalum layer. 1 4_ The method as described in item 丨 of the patent application, wherein the chemical gas 第15頁 425657 六、申請專利範圍 相沈積該氮氧化钽層步驟係採用一含氧氣體與TPE[Ta(〇c 2 H5 )5 ]或P D N A T [ Ta [ N (CH3 )2 ]5 ]作為形成該氣氧化组層之氣 體源。 1 5.如申請專利範圍第1項所述之方法，其中該化學氣 相沈積該氮氧化钽層步驟係採用選自包括一含氫氣體、一 惰性氣體、以及一含惰性氣體成分之氣體，將其加入形成 該氮氡化鈕層之該氣體源中。 1 6.如申請專利範圍第1項所述之方法，其中該化學氣 相沈積該氮氧化鈕層步驟係採用電漿能量（pUsma p〇wer )離子化該氣體源。 17. —種製造一半導體裝置的方法，於一半導體製成 設備中進行’該半導體製程設備至少具一反應室，包括： 利用含齒素成分氣體之電漿清洗一半導體基底，用以 移除一原生氧化層以及其他附著之污染物； 形成一第一導電層於該半導體基底上； 圖案化並蝕刻該第一導電層以定義出一第一電極； 於該半導體製程設備之一反應室中進行化學氣相沈積 形成一氮氧化钽層，作為該第一電極上之一電容介電質； 以及 形成一第二電極覆蓋該氮氧化钽層； 其中，上述所有處理步驟係在形成該氮氧化叙層相同 的反應室進行，或是將該半導體基底在真空或低氧的環境 下移至另一反應室進行。Page 15 425657 VI. Patent application phase phase deposition The tantalum oxynitride layer is formed by using an oxygen-containing gas and TPE [Ta (〇c 2 H5) 5] or PDNAT [Ta [N (CH3) 2] 5] as the formation The gas source of the gas oxidation layer. 15. The method according to item 1 of the scope of patent application, wherein the step of chemical vapor depositing the tantalum oxynitride layer is a gas selected from the group consisting of a hydrogen-containing gas, an inert gas, and an inert gas component, It is added to the gas source forming the nitrogenated button layer. 16. The method according to item 1 of the scope of patent application, wherein the step of chemically vapor-depositing the oxynitride button layer uses plasma energy (pUsma power) to ionize the gas source. 17. A method of manufacturing a semiconductor device, which is performed in a semiconductor fabrication equipment. The semiconductor processing equipment has at least one reaction chamber, including: cleaning a semiconductor substrate with a plasma containing a tooth element gas for removing A native oxide layer and other attached pollutants; forming a first conductive layer on the semiconductor substrate; patterning and etching the first conductive layer to define a first electrode; in a reaction chamber of the semiconductor process equipment Performing chemical vapor deposition to form a tantalum oxynitride layer as a capacitor dielectric on the first electrode; and forming a second electrode to cover the tantalum oxynitride layer; wherein all the above-mentioned processing steps are in forming the oxynitride Perform the reaction in the same reaction chamber, or move the semiconductor substrate to another reaction chamber in a vacuum or low oxygen environment.
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