TW425545B - Coding error correction detection device - Google Patents

Abstract

The present invention provides a coding error correction detection device that speeds up data coding error correction and detection processes. The data is taken into the first error detection circuit 12 at the same time when the input interface 11 writes the input data into buffer RAM 20 in blocks. Data determined to have no coding error in the first error detection circuit 12 may be output from buffer RAM 20 via input interface 15 by omitting coding error correction process in the error correction circuit 13 and coding error detection process in the second error detection circuit 14.

Description

五、發明說明（1) '— [發明之所屬技術領域] 本發明係為有關一種由CD(compact disc)或 DVD(Digital Video Disc)等的大容量記憶媒體所讀取的 數位資料，依含於資料的錯誤修正碼及錯誤檢測碼實施' 理之錯誤碼更正檢測裝置。 處 [習知技術] 作為數位音頻CD之數位資料的讀取專屬記憶體^⑽ 而活用的CD-ROM系統中，為了提昇讀取光碟資料的可靠 性，對讀出的數位數據實施雙重的碼錯誤修正處理。此種 修正處理構成係在與音頻系統共通的數位訊號處理部實施 第1次’而在設於CD-ROM系統之專屬CD-ROM解碼器實施第2 次。 第4圖為表示CD-ROM系統之構成方塊圖，第5圖為在今 系統的各部處理資料構成圖。 / 由拾訊部（pick up)l承受照射於光碟2的光的反射 光’將該光的強弱作為電壓值之變化予以取出e拾訊控制 部3係為控制CD拾訊部1之相對於光碟2的讀取位置，以能 使拾訊部1依正確順序讀取記憶於光碟2的數據。光碟2的 再生為維持拾訊部1讀取軌道的線速度於一定，配合拾訊 控制部3對拾訊部1位置之控制’使光碟2以預定速度旋轉 驅動地進行伺服控制（CLV控制）。或以進行伺服控制（cAV 控制）以便光碟2的旋轉角速度保持於一定。 類比訊號處理部4係讀取拾訊部1輸出的電壓變化的 值，產生以588位元為1幀式（frame)的EFM(Eigh1; toV. Description of the invention (1) '— [Technical field to which the invention belongs] The present invention relates to a digital data read by a large-capacity memory medium such as a CD (compact disc) or DVD (Digital Video Disc). Implement error correction code detection device for data error correction code and error detection code. [Known technology] As a read-only memory for digital data of digital audio CDs ^ 活 In the CD-ROM system in use, in order to improve the reliability of reading the data of the disc, the read digital data is implemented with double codes Error correction processing. This type of correction processing is performed for the first time 'in a digital signal processing section common to the audio system, and for the second time in a dedicated CD-ROM decoder provided in the CD-ROM system. Fig. 4 is a block diagram showing the structure of the CD-ROM system, and Fig. 5 is a diagram showing the structure of data processed by each part of the system. / The pick-up unit 1 receives the reflected light of the light irradiated to the optical disc 2 and takes out the intensity of the light as a change in the voltage value. The pick-up control unit 3 is used to control the The reading position of the optical disc 2 enables the pickup unit 1 to read the data stored in the optical disc 2 in the correct order. The reproduction of the optical disc 2 is to maintain a constant linear speed of the reading track of the pickup unit 1. In conjunction with the control of the position of the pickup unit 1 by the pickup control unit 3, the servo control of the optical disc 2 is driven at a predetermined speed (CLV control). . Or, servo control (cAV control) is performed so that the rotational angular velocity of the disc 2 is kept constant. The analog signal processing unit 4 reads the value of the voltage change output by the pickup unit 1 and generates an EFM (Eigh1; to

C:\Program Files\Patent\3l〇562.ptd 第 4 頁 Δ255 在5 五、發明說明（2)C: \ Program Files \ Patent \ 3l〇562.ptd page 4 Δ255 in 5 V. Description of the invention (2)

Fourteen Modulation)訊號。該EF Μ訊號係如第5圖所示， 各幀的開始24位元分配為同步訊號，其後每間隔3位元的 連接位元以14位元是重覆分配為數據位元。數位訊號處理 部5對由類比訊號處理部4輸入的EFM訊號施以EFM解調，以 變換14位元為8位元。在此種EFM解調時，由連接於同步訊 號的最初數據位元產生8位元的副碼數據（subc〇de data)，且由剩餘32個的數據位元產生32位元組符號數據 (Symbol data)。進而對32位元組的符號數據實施 CIRC(Cross -Inter leave Reed-So 1 〇m〇n code)解碼以產生 1幀由24位元組構成的CD-ROM數據。由此circ解碼完成最 初之瑪錯誤修正處理。 此CD-ROM數據係以24位元組X 98幀之合計2352位元組 為1區塊。而對此1區塊數據，通常（模式1時）係如第6圖所 示，分別分配為同步訊號[12位元組]、標頭[4位元 組](header )、使用者數據[ 2048位元組]、錯誤檢測瑪 EDC(Eri:or Detection Code)[4位元組]及錯誤修正瑪 ECC(Error Correction Code)[276 位元組]。此外，對此 CD-ROM數據’係在1區塊中’除同步訊號12位元組以外的 2340位元組皆施以暗碼（Scramble)處理，並於再生時則實 施解暗碼（descramble)處理而回復原先狀態。 CD-ROM解碼器6係對由數位訊號處理部5輪入的CD-ROM 數據，依錯誤修正碼（ECC)及錯誤檢測碼（EDC)進行錯誤碼 修正處理及檢測處理後，將完成處理之CD-ROM數據輸於主 電腦（host computer)。在此種CD-ROM解碼器6的處理中，Fourteen Modulation) signal. The EF MU signal is shown in FIG. 5. The first 24 bits of each frame are allocated as synchronization signals, and the connection bits of every 3 bits thereafter are repeatedly allocated as data bits with 14 bits. The digital signal processing section 5 applies EFM demodulation to the EFM signal input from the analog signal processing section 4 to convert 14 bits into 8 bits. In this EFM demodulation, 8-bit subcode data is generated from the first data bit connected to the synchronization signal, and 32-bit symbol data is generated from the remaining 32 data bits ( Symbol data). Furthermore, the 32-byte symbol data is subjected to CIRC (Cross-Inter leave Reed-So 100m code) decoding to generate 1 frame of CD-ROM data composed of 24 bytes. This circ decoding completes the initial Mar error correction processing. This CD-ROM data is based on a total of 2352 bytes of 24 bytes x 98 frames as one block. For this block of data, usually (in mode 1), as shown in Fig. 6, they are respectively allocated as a synchronization signal [12 bytes], a header [4 bytes] (header), and user data [ 2048 bytes], error detection code EDC (Eri: or Detection Code) [4 bytes] and error correction code ECC (Error Correction Code) [276 bytes]. In addition, this CD-ROM data is "in block 1", except that the 2340 bytes of the synchronization signal are subjected to Scramble processing, and the decryption processing is performed during reproduction. And return to the original state. The CD-ROM decoder 6 performs error code correction processing and detection processing on the CD-ROM data input by the digital signal processing unit 5 according to the error correction code (ECC) and error detection code (EDC). CD-ROM data is input to the host computer. In the processing of such a CD-ROM decoder 6,

—III C:\ProgramFiles\Patent\310562.ptd 第 5 頁 425545 五、發明說明（3) 通常係依ECC更正數據之錯誤崎後，以edc確認是否已將錯 誤碼正岑更正。若殘留有錯誤碼時，再度以ECC實施錯誤 碼的修正處理，或以附加錯誤旗標（flag)K態將含有錯誤 碼狀態的CD-ROM數據輪於主電腦。 緩衝RAM7接於CD-ROM解碼器6，是以1幀單位將自數位 訊號處理部5輸至CD-ROM解碼器6的CD-ROM數據予以暫時記 憶《>ECC及EDC係附加於1幀CD-ROM數據，故在CD-ROM解碼 器6的處理上至少須有1幀CD-ROM數據。因此，為能記憶各 個處理所須的1幀CD-ROM數據而設置緩衝RAM7。控制微電 腦8係以内藏有記憶控制程式的記憶體的所謂單晶片微電 腦構成’依該控制程式可控制CD-ROM解碼器6的動作。同 時’控制微電滕8亦將由主電腦輸入的指令（c〇mmanc[)數據 或由數位訊號處理部5輸入的副碼數據予以暫時記憶在内 藏記憶體。據此’控制微電腦8可對應於主電腦的指示控 制各部動作，並自CD-ROM解碼器6輸出預期的CD-ROM數據 至主電腦。 [本發明欲解決之課題] CD-ROM解碼器6則除CD-ROM數據的錯誤碼更正檢測的 處理之外，亦將數位訊號處理部5的CD-ROM數據的輸入及 對主電腦的CD-ROM數據的輸出予以同時處理。因而，配合 各處理，重覆對緩衝RAM 7的CD-ROM數據的寫入及讀出的動 作。 因CD-ROM解碼器6的各動作，係依控制微電腦8的指示 而控制，故當CD-ROM系統為多功能化時，控制微電腦8的—III C: \ ProgramFiles \ Patent \ 310562.ptd Page 5 425545 V. Description of the invention (3) After the error of the data is usually corrected according to ECC, confirm with edc whether the error code has been corrected. If an error code is left, the error code is corrected again by ECC, or the CD-ROM data containing the error code status is rounded to the host computer by adding an error flag (K). The buffer RAM 7 is connected to the CD-ROM decoder 6, and temporarily stores the CD-ROM data from the digital signal processing unit 5 to the CD-ROM decoder 6 in a unit of one frame. ≫ ECC and EDC are added to one frame CD-ROM data, so there must be at least one frame of CD-ROM data in the processing of the CD-ROM decoder 6. Therefore, a buffer RAM 7 is provided so that one frame of CD-ROM data necessary for each process can be stored. The control microcomputer 8 is a so-called single-chip microcomputer having a memory with a memory control program incorporated therein. The operation of the CD-ROM decoder 6 can be controlled by the control program. At the same time, the 'control micro-electric Teng 8' also temporarily stores the command (commmanc [) data input from the host computer or the sub-code data input from the digital signal processing section 5 into the built-in memory. Based on this, the control microcomputer 8 can control the operation of each unit in response to the instruction from the host computer, and output the expected CD-ROM data from the CD-ROM decoder 6 to the host computer. [Problems to be Solved by the Present Invention] In addition to the process of detecting the error code correction of the CD-ROM data, the CD-ROM decoder 6 also inputs the CD-ROM data of the digital signal processing unit 5 and the CD to the host computer. -ROM data output is processed simultaneously. Therefore, in accordance with each process, the operation of writing and reading the CD-ROM data in the buffer RAM 7 is repeated. Each operation of the CD-ROM decoder 6 is controlled according to the instructions of the control microcomputer 8. Therefore, when the CD-ROM system is multifunctional, the control of the microcomputer 8 is controlled.

C:\ProgramFiles\Patent\310562.ptd 第 6 頁 五、發明說明（4) 負擔加大’亦即’隨著多功能化，於取入數位訊號處理部 5的副碼數據或主電腦的指令數據等於控制微電腦8時，控 制微電腦8則除了各部的動作控制之外，亦須進行副碼數 據或指令數據等的處理。因此，控制微電腦8的控制動作 缺少空餘部份’對再生速度高速化造成障礙。 因此’本發明係以減輕控制微電腦的負擔，以對應於 再生速度之高速化為目的。 [解決課題之手段] 本發明係為解決上述之課題而創作，其特徵係在於對 含有自記錄媒體讀取的錯誤修正碼及錯誤檢測碼的數位數 據，進行錯誤修正碼的修正處理及錯誤檢測碼的檢出處 理’對電腦機器傳送已處理完畢的數位數據的錯誤碼更正 檢測裝置’其中’具備以預定的位元組構成的幀單位輸入 的數位數據記憶於緩衝記憶體的輸入介面（interface); 對輸至上述輸入介面體的上述數位數據依上述錯誤檢測碼 實施第1檢測處理的第1錯誤檢測電路；對記憶於上述缓衝 記憶體的上述數位數據，依上述錯誤修正碼實施修正處 理’並改寫上述數位數據錯誤的錯誤修正電路；對經上述 錯誤修正電路改寫錯誤而記憶於上述緩衝記憶體的上述數 位數據’依上述錯誤檢測碼實施第2檢測處理，並對應於 該檢測結果設定錯誤旗標（error f lag)的第2錯誤檢測電 路’以及對外部電腦機器輸出記憶於上述緩衝記憶趙的上 述數位數據的輸出介面等，而對上述第1錯誤檢測電路無 法檢測錯誤的上述數位數據’省略上述錯誤修正電路及上C: \ ProgramFiles \ Patent \ 310562.ptd Page 6 V. Explanation of the invention (4) Increased burden 'ie' With multifunctionalization, the subcode data of the digital signal processing unit 5 or the instruction of the host computer are taken in When the data is equal to controlling the microcomputer 8, in addition to controlling the operations of each part, the controlling microcomputer 8 must also perform processing such as sub-code data or command data. Therefore, the lack of a spare portion in the control operation of the control microcomputer 8 hinders an increase in the reproduction speed. Therefore, the present invention aims to reduce the burden of controlling the microcomputer and to increase the speed corresponding to the reproduction speed. [Means for Solving the Problem] The present invention was created to solve the above-mentioned problems, and is characterized by performing error correction code correction processing and error detection on digital data including error correction codes and error detection codes read from a recording medium. Code detection processing 'error code correction detection device for computer equipment that has transmitted processed digital data', among which 'equipped with digital data input in a frame unit composed of predetermined bytes is stored in an input interface of the buffer memory (interface ); A first error detection circuit that performs a first detection process on the digital data input to the input interface body according to the error detection code; and corrects the digital data stored in the buffer memory according to the error correction code Process 'and rewrite the above-mentioned digital data error error correction circuit; for the above-mentioned digital data stored in the buffer memory by the above-mentioned error correction circuit rewriting error', a second detection process is performed according to the above-mentioned error detection code, and corresponding to the detection result A second error detection circuit that sets an error flag (error f lag) and The external computer outputs the digital data output interface and the like stored in the buffer memory, and the digital data that cannot be detected by the first error detection circuit cannot be detected.

Mil li^w C:\Program Files\Patent\310562.ptd 第 7 頁 '一" -4-25545 ; 五、發明說明（5) 述第2錯誤檢測電路的處理過程。 根據本發明，在第1錯誤檢測電路中無法檢出碼錯誤 時’因係省略錯誤修正電路及第2錯誤檢測電路的處理， 故不含碼錯誤的數據係由輪入介面記憶於緩衝RAM，並依 原狀被讀於介面而輸出至外部因此，控制各部動作的控 制微電腦則無須進行對錯誤修正電路及第2錯誤檢測電路 的動作控制。 [發明之實施形態] 第1圖為表示本發明之錯誤碼更正檢測裝置的第1實施 形態方塊圖，第2圖為說明在此動作中各部數據流向的時 序圖。 錯誤碼更正檢測裝置10為相當於第4圖所示之CD —ROM 解碼器6 ’係連接於緩衝RAM20及控制微電腦30 »本發明之 錯誤碼更正檢測裝置1 〇係由輸入介面11，第1錯誤檢測電 路12、錯誤修正電路13，第2錯誤檢測電路14，輸出介面 15，指令暫存器16及記憶體控制電路ι7所構成。通常，錯 誤碼更正檢測裝置1〇的各部係集積在一個半導體基板上形 成。 輸入介面11係構成1區塊為235 2位元組形成的 CD-ROM(第6圖）與數位訊號處理部間的介面，且承受 CD-ROM數據供應至第1錯誤檢測電路1 1及記憶體控制電路 17。此輸入介面11係為對應於除12位元組同步訊號以外的 2340位元組CD-ROM數據實施的暗碼處理，在輸入階段實施 解暗碼處理。同時，由CD-ROM數據取出同步訊號，產生顯 mm mail C:\Program Files\Patent\310562.ptd 第 8 頁 4255 45 .Mil li ^ w C: \ Program Files \ Patent \ 310562.ptd Page 7 '一 "-4-25545; V. Description of the invention (5) The process of the second error detection circuit is described. According to the present invention, when a code error cannot be detected in the first error detection circuit, since the processing of the error correction circuit and the second error detection circuit is omitted, the data that does not contain a code error is stored in the buffer RAM by the turn-in interface. It is read in the interface as it is and output to the outside. Therefore, the control microcomputer that controls the operation of each part does not need to control the operation of the error correction circuit and the second error detection circuit. [Embodiment of the invention] Fig. 1 is a block diagram showing the first embodiment of the error code correction detection device of the present invention, and Fig. 2 is a timing chart illustrating the data flow of each part in this operation. The error code correction detection device 10 is equivalent to the CD-ROM decoder 6 ′ shown in FIG. 4 and is connected to the buffer RAM 20 and the control microcomputer 30. The error code correction detection device 1 of the present invention is provided by the input interface 11, the first The error detection circuit 12, the error correction circuit 13, the second error detection circuit 14, the output interface 15, the instruction register 16 and the memory control circuit ι7 are configured. Generally, each part of the error correction detection device 10 is formed by being integrated on a single semiconductor substrate. The input interface 11 constitutes an interface between a CD-ROM (Figure 6) formed by a block of 235 2-bytes and a digital signal processing unit, and the CD-ROM data is supplied to the first error detection circuit 11 and memory.体 控制 电路 17。 Body control circuit 17. This input interface 11 is a cryptographic process performed on the 2340-byte CD-ROM data other than the 12-byte sync signal, and a decryption process is performed during the input stage. At the same time, the synchronization signal is taken from the CD-ROM data, and the display is generated. Mm mail C: \ Program Files \ Patent \ 310562.ptd Page 8 4255 45.

示於各區塊前端以表示時序的區塊同步訊號。此區塊同步 訊號供應於錯誤碼更正檢測裝置1〇各部，用於各動作時序 的同步。 第1錯誤檢測電路12係依序取入自輸入介面η輸入的 CD-ROM數據於各區塊’藉由錯誤檢測碼（EDC)的演算處 理，檢測碼錯誤的有無。以碼錯誤檢出結果供至控制微電 腦30。 錯誤修正電路13係將記憶於緩衝RAM2〇的CD-ROM數據 以1區塊單位取入，依各個區塊的錯誤修正碼（ECC)檢測碼 錯誤的同時’修正檢出的碼錯誤。例如，對2種碼語，藉 由對應於各個碼順序（sequence)的症候群（syndr〇me)演 算’而算出碼錯誤位置及由錯誤而產生的誤差。然後，依 s亥算出結果’將誤差加算於對應該誤差位置的數據，以修 正瑪錯誤。 第2錯誤檢測電路14，依序將各區塊經錯誤修正電路 13修正碼錯誤的CD-ROM數據（除ECC)取入，藉由錯誤檢測 碼（EDC)實施演算處理，以檢測碼錯誤的有無。此第2錯誤 檢測電路14具有與第1錯誤檢測電路12相同的功能。此 時’因EDC不具有修正碼錯誤之功能，若在錯誤檢測電路 1 3中檢出碼錯誤時’係在cd-ROM數據附加錯誤旗標。 輸出介面電路15構成與主電腦間的介面，對應於主電 腦側的指示，以區塊單位輸出完成預定處理的CD_R〇M數 據。如有必要，可承受主電腦侧的控制資訊供予控制各 部動作的控制微電腦3 〇。A block synchronization signal shown at the front of each block to indicate timing. This block synchronization signal is supplied to each part of the error code correction detection device 10, and is used to synchronize the timing of each operation. The first error detection circuit 12 sequentially takes in the CD-ROM data inputted from the input interface η in each block ', and performs calculation by an error detection code (EDC) to detect the presence or absence of an error in the code. The code error detection result is supplied to the control microcomputer 30. The error correction circuit 13 fetches the CD-ROM data stored in the buffer RAM 20 in units of one block, and corrects the detected code errors according to the error correction code (ECC) detection code error of each block. For example, for two types of code words, the position of the code error and the error due to the error are calculated by performing a 'syndrome' calculation corresponding to each code sequence. Then, the calculation result according to s' is added to the data corresponding to the error position to correct the ma error. The second error detection circuit 14 sequentially takes in the CD-ROM data (except ECC) for which the blocks have been corrected by the error correction circuit 13 in order, and performs arithmetic processing with the error detection code (EDC) to detect the error Yes or no. This second error detection circuit 14 has the same function as the first error detection circuit 12. At this time, 'because EDC does not have the function of correcting the code error, if a code error is detected in the error detection circuit 13', an error flag is added to the cd-ROM data. The output interface circuit 15 constitutes an interface with the host computer, and outputs the CD_ROM data which completes the predetermined processing in block units in response to an instruction from the host computer side. If necessary, the control information on the host computer side can be supplied to the control microcomputer that controls the operation of each part.

指令暫存器16連接於輸入介面11、第1錯誤檢測電路 12、 錯誤修正電路13、第2錯誤修正電路14及輸出介面 1 5 ’對應於控制微電腦3〇的指示設定各電路的動作條件。 亦即於第1錯誤檢測電路12、錯誤修正電路13及第2錯誤檢 2電路14構成可選擇各別處理精度或是否執行處理的機 ，’而在指示暫存器16承受並貯藏控制微電腦3 〇提供之決 定條件的控制指令。另外，對輸入介面體丨丨及輸出介面15 則供應用以決定輸出入之數據格式（format)或傳送率 (rate)的控制指令。而這些控制指令亦由控制微電腦3〇供 應。 記憶趙控制電路17連接於輸入介面π、錯誤修正電路 13、 第2錯誤修正電路14及輸出介面15等各部與緩衝RAM2〇 間’對應於控制微電腦的指示以時分割方式控制各部與緩 衝RAM20間的數據輸出入。亦即，對緩衝1^旧〇不能以相同 的時序讀取並寫入複數的數據，故由記憶體控制電路17配 合各部之動作時序分配緩衝RAM2〇的存取。 緩衝RAM20係由具有代表性的dRAm、SRSM等可讀取及 寫入之記錄媒體形成’介由記憶體控制電路17記憶由輸入 介面體11輪入的數據。該緩衝RAM2〇具有至少可記憶2區塊 CD-ROM數據的容量，於錯誤修正電路13的修正處理及第2 錯誤檢測電路14的檢測處理中暫時保持由輸入介面n輸入 的CD-ROM數據。然後，在完成對主電腦侧的傳送記憶的 CD-ROM數據後，即能寫入接著輸入的CD_R〇M數據於該記憶 領域。此外’若以緩衝RAM20之記憶容量的充裕範圍來積The command register 16 is connected to the input interface 11, the first error detection circuit 12, the error correction circuit 13, the second error correction circuit 14, and the output interface 1 5 'to set the operating conditions of each circuit in accordance with the instructions of the control microcomputer 30. That is, the first error detection circuit 12, the error correction circuit 13, and the second error detection 2 circuit 14 constitute a machine that can select individual processing accuracy or whether to execute processing, and the control register 16 is received and stored in the instruction register 16 〇 Provide control instructions for determining conditions. In addition, the input interface body 丨 丨 and the output interface 15 are provided with control instructions for determining the format or rate of data input and output. These control instructions are also supplied by the control microcomputer 30. The memory control circuit 17 is connected between the input interface π, the error correction circuit 13, the second error correction circuit 14 and the output interface 15 and the buffer RAM 20 ′ corresponding to the instructions for controlling the microcomputer in a time division manner to control the sections and the buffer RAM 20 Data input and output. That is, the buffer 1 ^ old0 cannot read and write plural data at the same timing, so the memory control circuit 17 allocates the access of the buffer RAM2 in accordance with the operation timing of each part. The buffer RAM 20 is formed of a representative readable and writable recording medium such as dRAm, SRSM, and the like. The data input by the input interface body 11 is memorized by the memory control circuit 17. The buffer RAM 20 has a capacity capable of storing at least two blocks of CD-ROM data, and temporarily holds the CD-ROM data inputted from the input interface n during the correction processing by the error correction circuit 13 and the detection processing by the second error detection circuit 14. Then, after completing the transfer of the stored CD-ROM data to the host computer side, the CD_ROM data that is input next can be written into this memory area. In addition, if the storage range of the buffer memory 20 is sufficient,

C:\Program Files\Patent\310562.ptdC: \ Program Files \ Patent \ 310562.ptd

存CD-ROM數據’則亦可重覆相同的CI>_R0M數據傳送至主電 腦側。這些動作條件的選擇，係於控制微電腦由指令暫 存器16的設定決定》 控制微電腦30係對應於預定控制程式，將錯誤碼更正 檢測裝置10的動作與該連接於前段的裝置之動作同時予以 控制，為此，將控制指令設定在指令暫存器1 6。亦即，控 制微電腦30係將設定各個之動作條件的指令設定於指令暫 存器16 ’以便於對錯誤碼更正檢測裝置1〇無須繼續供應控 制指示。據此，對錯誤碼更正檢測裝置1 〇以外的各種裝 置’能以時分割方式進行動.作的控制。而且，以此控斜镟 電腦30對應於第1錯誤檢測電路12的檢出結果，設定錯誤 修正電路13及第2錯誤檢測電路14停止動作的控制旗標。 亦即，在第1錯誤檢測電路1 2判定取入於输入介面11的數 據為無錯誤碼際，即能省略全部錯誤修正電路13内的錯誤 修正處理及第2錯誤檢測電路14的錯誤檢測處理，而由控 制微電腦30對指令暫存器16設定控制旗標。 茲將參照第2圖說明有Μ上述之錯誤碼更正檢測裝置 的動作如下：圖中，係表示缓衝RAM20記憶2區塊資料S (η) 情形。 自前段的裝置輸入於1區塊的數據S(n)，首先輸入輸 入介面11，再由該輸入介面11介由記憶體控制電路17寫入 緩衝RAM20，同時，亦取入第1錯誤檢測電路12。而後於 第1錯誤檢測電路12在每區塊進行碼錯誤的檢測處理 > 將 該區塊數據S( η)是否含有碼錯誤的訊息傳至控制微電膘Storing CD-ROM data ’can also be transmitted to the main computer side by repeating the same CI> _R0M data. The selection of these operating conditions is determined by the setting of the control register 16 by the control microcomputer. The control microcomputer 30 corresponds to a predetermined control program, and simultaneously performs the operation of the error code correction detection device 10 and the operation of the device connected to the previous stage. For control, the control instruction is set in the instruction register 16. That is, the control microcomputer 30 sets the instructions for setting the respective operating conditions in the instruction register 16 'so that the error code correction detection device 10 need not continue to supply control instructions. Accordingly, various devices' other than the error code correction detection device 10 can be operated in a time division manner. In addition, the computer 30 sets a control flag for stopping the operation of the error correction circuit 13 and the second error detection circuit 14 in accordance with the detection result of the first error detection circuit 12 under this tilt control. That is, when the first error detection circuit 12 determines that the data taken into the input interface 11 is error-free, the error correction processing in all the error correction circuits 13 and the error detection processing in the second error detection circuit 14 can be omitted. The control microcomputer 30 sets a control flag to the instruction register 16. The operation of the above-mentioned error code correction detection device will be described with reference to FIG. 2. The figure shows the situation where the buffer RAM 20 stores 2 blocks of data S (η). The data S (n) in block 1 is input from the device in the previous section. The input interface 11 is input first, and then the input interface 11 is written into the buffer RAM 20 through the memory control circuit 17, and the first error detection circuit is also taken. 12. Then, the first error detection circuit 12 performs a code error detection process in each block > sends a message whether the block data S (η) contains a code error to the control microelectronics 膘

A:V3ia562,ptd 第頁 ^ 425545 五、發明說明（9) 30 °此時若在資料S(n)含有碼錯誤（例如n=i時），首先， 由緩衝RAM20將資料S (η)取入錯誤修正電路13實施預定的 修正處理’並重寫記憶於緩衝RAM20的數據s(n)的碼錯誤 的部份。繼之’將碼錯誤已重寫（已修正）的數據s(n)，自 緩衝RAM20取入於第2錯誤檢測電路14實施第2次錯誤檢測 處理。然後對應於主電腦側的指示，將記憶於緩衝Mm20 的數據S(n)由輸出介面15輸至主電腦側。另一方面，若在 數據S(n)不含有瑪錯誤時（例如n = 2時），並不將數據g(n) 取入錯誤修正電路13及第2錯誤檢測電路14，而將數據 S(n)以原狀自緩衝RAM 20介由輸出介面體15輸至主電腦 側。 在如上述的處理當令對於在第1錯誤修正電路12判定 為無碼錯誤的數據S(n)，即不須錯誤修正電路13及第2錯 誤檢測電路1 4的動作控制。故能減輕在此期間之控制微電 腦30負擔，得能容易對應於再生速度的高速化或多功能 化。 又因’由錯誤修正電路13及第2錯誤檢測電路14對緩 衝RAM20的存取動作的變少，故分配於由緩衝RAM20對主電 腦側的CD-ROM數據傳送的時間變長。是故，能提昇CD-ROM ， 數據的傳送速度。特別是在緩衝RA M2 0記憶1 〇區塊以上的 广 CD-ROM數據、集匯複數個區塊的CD-ROM數據傳送至主電腦 侧時，別具功效。 第3圖為表示本發明之錯誤碼更正檢測裝置的第2實施 形態方塊圖。A: V3ia562, ptd Page ^ 425545 V. Description of the invention (9) 30 ° If the data S (n) contains a code error (for example, n = i), first, the data S (η) is fetched by the buffer RAM20. The input error correction circuit 13 performs a predetermined correction process and rewrites a code error portion of the data s (n) stored in the buffer RAM 20. Then, the data s (n) whose code error has been rewritten (corrected) is fetched from the buffer RAM 20 into the second error detection circuit 14 to perform the second error detection process. Then, in response to the instruction from the host computer side, the data S (n) stored in the buffer Mm20 is output from the output interface 15 to the host computer side. On the other hand, if the data S (n) does not contain a ma error (for example, when n = 2), the data g (n) is not taken into the error correction circuit 13 and the second error detection circuit 14 and the data S (n) It is output from the buffer RAM 20 to the host computer side via the output interface 15 as it is. The above-mentioned processing should be performed on the data S (n) which is determined to be a codeless error by the first error correction circuit 12, that is, the operation control of the error correction circuit 13 and the second error detection circuit 14 is not required. Therefore, it is possible to reduce the burden on the control microcomputer 30 during this period, and it is possible to easily cope with the high-speed or multifunctional reproduction speed. Further, since the access operation of the buffer RAM 20 by the error correction circuit 13 and the second error detection circuit 14 is reduced, the time allocated to transfer the CD-ROM data from the buffer RAM 20 to the host computer becomes longer. Therefore, CD-ROM and data transfer speed can be improved. It is particularly effective when buffering the wide-ranging CD-ROM data of RAM 10 or more and storing the CD-ROM data of multiple blocks, and transferring it to the host computer. Fig. 3 is a block diagram showing a second embodiment of the error code correction detection device according to the present invention.

五、發明說明（10) 在此實施形態中，係因應於第1錯誤檢測電路12的檢 出結果’直接設定指令暫存器丨6’的控制旗標。亦即，錯 誤碼更正檢測裝置10,和僅有指令暫存器16，表示於第1圖 之錯誤瑪更正檢測裝置10不同。係直接取入第1錯誤檢測 電路12的檢出結果，設定錯誤修正電路13及第2錯誤檢測 電路14的動作停止的控制旗標。因此，控制微電腦3〇，不 須對應於第1錯誤檢測電路12的檢出結果，在指令暫存器 16設定控制旗標’其負擔則更為減輕。 " 上述實施例中，雖係以使用CD作為記錄媒體的⑶^⑽ 系統為例子’但記錄媒體可採用DVD或肌等的其他媒體 系統。 ^ [發明之功效] 根據本發明，在輸入數據 碼錯誤的修正處理及為修正處 處理。因此，能減輕用以控制 負擔而有利於動作的高速化或 略各個的處理可將空出來的時 電腦側的傳送，故能提昇數據 傳送速度。 中不含碼錯誤時，得能省略 ^之確認用的碼錯誤的檢測 現些處理動作的控制微電腦 多功能化。而且，由於能省 間，分配於CD-ROM數據對主 的傳送效率，該結果可加迷 [圖面的簡單說明] 更正檢測裝置的第i實施 第1圖為表示本發明之錯誤碼 形態方塊圖。 第2圖為說明資料流程的時序 第3圖為表示本發明之錯誤碼 圖。 更正檢測裝置的第2實施5. Description of the invention (10) In this embodiment, the control flag of the instruction register 6 is set directly according to the detection result of the first error detection circuit 12. That is, the error code correction detection device 10 is different from the error register correction detection device 10 shown in Fig. 1 only in the instruction register 16. The detection results of the first error detection circuit 12 are directly taken in, and the control flags for stopping the operation of the error correction circuit 13 and the second error detection circuit 14 are set. Therefore, the control microcomputer 30 need not correspond to the detection result of the first error detection circuit 12, and the burden of setting the control flag 'in the instruction register 16 is further reduced. " In the above embodiment, although the CD ^ ⑽ system using a CD as a recording medium is taken as an example ', the recording medium may be other media systems such as a DVD or a muscle. ^ [Effect of the invention] According to the present invention, correction processing and correction processing are performed for input data code errors. Therefore, it is possible to reduce the control load, which is beneficial to speeding up the operation, or it is possible to transfer the free time to the computer side when the processing is omitted. Therefore, the data transmission speed can be increased. If a code error is not included, it may be possible to omit the detection of the code error for the ^ confirmation. The microcomputer that controls the processing operations is now multifunctional. In addition, since the transmission efficiency of the CD-ROM data allocated to the host can be saved between provinces, the result can be fascinated. [Simplified description of the drawing] The i-th implementation of the correction detection device. Illustration. Fig. 2 is a timing chart for explaining the data flow. Fig. 3 is a diagram showing an error code of the present invention. Second implementation of correction detection device

d 2 55 4 5 五、發明說明（π) 形態方塊圖。 第4圖為表示CD-ROM系統之構成方塊圖 第5圖自光碟片讀出的數據格式圖。 第6圖CD-ROM數據的格式圖。 [符號之說明] 1 拾訊部 2 光碟 3 拾訊控制部 4 類比訊號處理部 5 數位訊號處理部 6 CD-ROM解碼器 7 緩衝RAM 8 控制微電腦 10 ' 1 0 ’ 錯誤碼更正檢測裝置 11 輸入介面 12 第1錯誤檢測電路 13 錯誤修正電路 14 第2錯誤檢測電路 15 輸出介面 16、 16’指令暫存器 17 記憶體控制電路 20 緩衝RAM 30 、30’控制微電腦d 2 55 4 5 V. Description of the invention (π) Form block diagram. Fig. 4 is a block diagram showing the structure of a CD-ROM system. Fig. 5 is a data format diagram read from an optical disc. Fig. 6 is a format diagram of CD-ROM data. [Explanation of symbols] 1 pickup unit 2 optical disc 3 pickup control unit 4 analog signal processing unit 5 digital signal processing unit 6 CD-ROM decoder 7 buffer RAM 8 control microcomputer 10 '1 0' error code correction detection device 11 input Interface 12 First error detection circuit 13 Error correction circuit 14 Second error detection circuit 15 Output interface 16, 16 'instruction register 17 Memory control circuit 20 Buffer RAM 30, 30' control microcomputer

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Claims (1)

-425545 六、申請專利範圍 1. 一種錯誤碼更正檢測裝置，係於對含有由記錄媒體讀出 的錯誤修正碼及錯誤檢測碼數位數據，實施依錯誤修正 碼的修正處理及依錯誤檢測碼的檢測處理，並傳送處理 完成後的數位數據至電腦機器侧的碼錯誤修正檢測裝置 中，具備： 將以預定位元組數構成的區塊單位輸入的數位數據 記憶於緩衝記憶體的輸入介面； 對輸於上述輸入介面的上述數位數據，依上述錯誤 檢測碼實施第1檢測處理的第1錯誤檢測電路； 對記憶於上述缓衝記憶體的上述數位數據，實施依 上述錯誤修正碼的修正處理，改寫上述數位數據錯誤部 位的錯誤修正電路； 對上述錯誤修正電路改寫錯誤處所而記憶於上述緩 衝記憶體的上述數位數據’實施依上述錯誤檢測碼的第 2檢測處理，且對應於檢出結果設定錯誤旗標的第2錯誤 檢測電路；及 將記憶於上述緩衝記憶體的上述數位數據輸出至外 部電腦機器的輸出介面等； 而對上述第1錯誤檢測電路若無檢出錯誤的上述數 位數據，省略在上述錯誤修正電路及上述第2錯誤檢測 電路的處理者。 2. 如申請專利範圍第1項記載之錯誤碼更正檢測裝置，該 裝置係具備有對應於上述第2錯誤檢測電路的檢測結果 ’設定指示上述錯誤修正電路及上述第2錯誤檢測電路-425545 6. Scope of patent application 1. An error code correction detection device for correcting the error correction code and error detection code digital data that is read from a recording medium, and performing correction processing according to the error correction code and error detection code. Detection processing, and transmitting the processed digital data to the code error correction detection device on the computer side, including: storing digital data input in a block unit composed of a predetermined number of bytes in an input interface of a buffer memory; A first error detection circuit that performs first detection processing on the digital data input to the input interface according to the error detection code; and performs correction processing on the digital data stored in the buffer memory according to the error correction code. To rewrite the error correction circuit of the above-mentioned digital data error part; to perform the second detection processing according to the above-mentioned error detection code on the above-mentioned digital data that is stored in the buffer memory by the above-mentioned error correction circuit overwriting the wrong place, and corresponding to the detection result A second error detection circuit for setting an error flag; and The digital data of the buffer memory is output to an output interface of an external computer, etc .; if the digital data of the first error detection circuit does not detect an error, the digital data in the error correction circuit and the second error detection circuit are omitted. Processor. 2. For example, the error code correction detection device described in item 1 of the scope of patent application, the device is provided with a detection result corresponding to the above-mentioned second error detection circuit ′, and the setting instruction indicates the above-mentioned error correction circuit and the above-mentioned second error detection circuit C:\Programnies\Patem\310562.ptd 第 15 頁 4 255 4 5 六、申請專利範圍 的動作停止的控制旗標的暫存器者。C: \ Programnies \ Patem \ 310562.ptd Page 15 4 255 4 5 VI. Patent register Register register of the stop flag of action C:\Program Files\Patent\310562.ptd 第 16 頁C: \ Program Files \ Patent \ 310562.ptd page 16