TW424325B

TW424325B - DRAM cells and method for making the same

Info

Publication number: TW424325B
Application number: TW88119399A
Authority: TW
Inventors: Jenn-Ming Huang
Original assignee: Taiwan Semiconductor Mfg
Priority date: 1999-11-06
Filing date: 1999-11-06
Publication date: 2001-03-01

Abstract

The present invention provides a novel DRAM cell of the giga bit generation and a method for making the same. The method comprises forming a conductive plug, forming an isolated insulating layer, in which a self-aligned technique is used to enable the internal structure of the element can be scaled so that the memory cells have a consistent electric property, and other isolation layer will not be damaged when performing the production process of the self-aligned contact. When the isolation layer is damaged, the isolation effect will be affected and a leakage current may occur. The void formed due to an excessive aspect ratio during the deposition of the insulating layer can be used as a best isolation, and the insulating material used by the insulator can greatly reduce the parasitic capacitance in the wordlines and bitlines of the memory cells.

Description

424325 五、發明說明（1) 未發明係有關於一種半導體記憶裝置（semiCQnductor memory device)的製造方法’特別是有關於一種於十億位元世代（Giga Bit Generation)之新穎的動態隨機存取記憶體（dynamic random access memory ; DRAM)細胞元及其製造方法。目前，由於積體電路的製程朝向ULSI發展因此内部的. 電路密度愈來愈增加，隨著積體電路的積集度日益增加，ί 現今DRAM細胞元的設計及製程尚有些技術障礙有待突破。以下將簡述傳統的DRAM製程及其技術缺失。首先’請參照第1圖，其顯示半〜導體基底4 〇形成有複數個淺溝槽隔離元件STI ’在半導體基底10上形成有包含閘極Gl、G2、G3、G4，以及n型離子源極/汲極i2a、12b 12c的電晶體’接著形成一氮化珍襯底層η。其中，上述閘極Gl、G2、G3、以及G4是由複晶矽層ί 6、石夕化鶴層 (WSix)18、氮化矽遮蔽層20、氮化矽側壁層14所構^。源極/沒極12b與12c上方分別形成有：！型離子摻雜複晶石夕 2 2 b、2 2 c ’以利後續接觸孔的形成。再者，摻雜複晶石夕 2 2 b、2 2 c上方分別形成有複晶矽層2 6與矽化鎢2 8構成之元線，以及下電極34、介電質層36、與上電極38所構成電容器C。而且’第1圖顯示半導體基底1〇上係形吏有三絕緣層24、33、40。 / X — 當上述傳統的DRAM細胞元製程’在自行對準接觸步驟而敍刻氮化矽襯底層Π時亦會蝕刻到氮化矽遮蔽化矽側壁層14影響隔離效果，基底亦受損宝佶，、。K付漏電流產424325 V. Description of the invention (1) The uninvented method relates to a method of manufacturing a semiconductor memory device (semiCQnductor memory device), particularly to a novel dynamic random access memory in the Giga Bit Generation Body (dynamic random access memory; DRAM) cell and its manufacturing method. At present, because the integrated circuit process is developing towards ULSI, the internal circuit density is increasing. With the increasing degree of integrated circuit integration, there are still some technical obstacles in the design and process of DRAM cells to be broken. The following will briefly describe the traditional DRAM process and its technical shortcomings. First, please refer to FIG. 1, which shows a semi-conductor substrate 4. A plurality of shallow trench isolation elements STI are formed. A semiconductor substrate 10 is formed with gate electrodes G1, G2, G3, G4, and an n-type ion source. The transistors of the electrode / drain i2a, 12b, 12c 'then form a nitride substrate layer n. The above-mentioned gates G1, G2, G3, and G4 are composed of a polycrystalline silicon layer 6, a lithographic chemical crane layer (WSix) 18, a silicon nitride shielding layer 20, and a silicon nitride sidewall layer 14. The source / non-poles 12b and 12c are formed above :! Type ions doped with polycrystalline spar 2 2 b, 2 2 c ′ to facilitate the subsequent formation of contact holes. In addition, a doped polycrystalline stone 2 2 b and 2 2 c are respectively formed with a polycrystalline silicon layer 26 and a tungsten silicide 28 wire, and a lower electrode 34, a dielectric layer 36, and an upper electrode, respectively. 38。 Capacitor C is formed. Furthermore, the first figure shows that the semiconductor substrate 10 has three insulating layers 24, 33, and 40 on it. / X — When the above-mentioned traditional DRAM cell manufacturing process is used to scribe the silicon nitride substrate layer in the self-aligning contact step, the silicon nitride masking silicon sidewall layer 14 is also etched to affect the isolation effect, and the substrate is also damaged.佶,,. K pay leakage current production

424325 五、發明說明（2) 生，且以氮化矽作為遮蔽層會形成大的寄生電容。而在沉積絕緣層2 4時，因深寬比過大會形成孔洞2 6而造成隨後形成的複晶石夕插塞短路。前述之缺點使得元件要再更縮小尺度顯得困難，尤其是在深次微米的世代中只允許更小尺寸的線寬及高深寬比，若無新製程技術的突破，將使得良率難以提昇，且無法達到經濟規模的量產。本發明的目的在於提供一種於十億位元世代（Giga Bi t Generation)之新穎的動態隨機存取記憶體（dynamic random access memory ; DR AM)細胞元及其製造方法，該方法係先形成導電插塞，再形成隔離之絕緣層，其中應用自行對準技術使得元件的内部構造可以尺度化以消除源極區角落的不對準效應’且可使該記憶體細胞元具有一致的電特性。本發明之另一目的在於提供一新穎的動態隨機存取記憶體細胞元及其製造方法，該方法於施行自行對準接觸製程步驟時不會損害到其他隔離層’而影響隔離效果使得漏電流產生。本發明尚有另一目的在於提供~新穎的動態隨機存取記憶體細胞7G及其製造方法’該方法於沉積絕緣層時因深寬比過大而形成之孔洞恰可利用為最佳的隔離與絕绫枋。本發明胃有另-目的在於提供-新賴的動態隨機存取記憶體細胞元及其製造方法，該方法採用的絕緣材料可大幅減低記憶體細胞凡之字元線及位元線中的寄生電容。424325 V. Description of the invention (2) The use of silicon nitride as a shielding layer will form a large parasitic capacitance. However, when the insulating layer 24 is deposited, the subsequent formation of the polycrystalline spar plug is short-circuited due to the excessive aspect ratio forming the holes 26. The aforementioned disadvantages make it difficult to reduce the size of the device, especially in the deep sub-micron generation. Only smaller line widths and high aspect ratios are allowed. Without breakthroughs in new process technologies, it will be difficult to improve yield. And it cannot reach mass production on an economic scale. An object of the present invention is to provide a novel dynamic random access memory (DR AM) cell in a Giga Bit Generation and a manufacturing method thereof. The method is to first form a conductive material. The plugs are then formed into an isolated insulating layer. The self-alignment technology is used to enable the internal structure of the component to be scaled to eliminate the misalignment effect at the corners of the source region and to make the memory cell have consistent electrical characteristics. Another object of the present invention is to provide a novel dynamic random access memory cell cell and a manufacturing method thereof. The method does not damage other isolation layers when performing a self-aligned contact process step, and affects the isolation effect and causes leakage current. produce. Another object of the present invention is to provide a novel dynamic random access memory cell 7G and a method for manufacturing the same. This method can be used for the best isolation and isolation of holes formed due to excessively large aspect ratios when depositing an insulating layer. Definitely. The stomach of the present invention has another object, which is to provide Xinlai's dynamic random access memory cell element and its manufacturing method. The insulating material used in the method can greatly reduce parasitics in word lines and bit lines of memory cells. capacitance.

_ 4243 2 5 五、發明說明（3) 簡-單說，本發明揭露一新穎的動態隨胞元及其製造方法’適用於—半導體基底，己概驟：在半導體基底上形成包含至少一被絕緣，、，構、源極/汲極的電晶體；全面性形成一第磨第一導電層，使露出該被絕緣隔離之問才蛋社辱電層；^ 面，夂義第一導電層以形成電性連接汲極之^攝夂上線接觸插塞’ Α電性連接源極之第一階段電二1, 全面性形成一第一絕緣層；形成一被絕緣隅ς镇啕插塞π 其穿過第一絕緣層而與第一階段位元線接祛之仇元，接；全面性形成-第二導電層，其穿過第〜Ϊ寒電性連， Ρ白奴電容接觸插塞電性連接；研磨第二導，層而與該被絕緣隔離之位元線之上表面；定義第二缘㊉，使露出成電性連接第一階段電容接觸插塞之第二階段二^，以形塞二全面性形成一第二絕緣層；及形成—電^哭容接觸插第二絕緣層而與第二階段電容接觸插塞電性連&，其穿過以下配合圖式以及較佳實施例以說明本發明: 明【圖式簡單說第1圖為根據習知技術之動態隨機存取記憶流程剖面圖體的製造態隨機第2 Α圖至第2G圖為根據本發明較佳實施例之存取記憶體的製造流程剖面圖。〜〜 [符號說明]_ 4243 2 5 V. Description of the invention (3) Jane-simply, the present invention discloses a novel dynamic satellite cell and its manufacturing method 'applicable to—semiconductor substrates, which has been summarized by forming at least one semiconductor substrate on a semiconductor substrate. Insulation, structure, source / drain transistor; comprehensively form a first conductive layer, so that the insulation layer is exposed; ^ surface, meaning the first conductive layer In order to form an electrical connection to the drain electrode, a photo-contact on-line contact plug is formed. The first phase of the electrical connection to the source electrode is to form a first insulating layer comprehensively; to form an insulated plug. It passes through the first insulation layer and is connected to the bit line of the first stage. It is fully formed-the second conductive layer is passed through the first to the third electrical layer, and the PB white capacitor contacts the plug. Electrical connection; grinding the second conductor and layer to isolate the upper surface of the bit line that is isolated from the insulation; defining the second edge 使, so that the exposure is electrically connected to the second stage of the first stage capacitor contact plug ^, Forming a second insulating layer with a plug in an all-round way; and forming a second insulating plug Layer and is electrically connected to the second-stage capacitive contact plug, which passes through the following cooperative drawings and preferred embodiments to illustrate the present invention: [Scheme Briefly, Figure 1 is a dynamic random according to the conventional technology Figures 2A to 2G of the manufacturing state of the sectional view of the access memory process are randomly generated, which are sectional views of the manufacturing process of the access memory according to the preferred embodiment of the present invention. ~~ [Symbol Description]

第6頁五、發明說明（4) 100〜早導體基底， 102〜二氧化矽襯底層； 112a至112c〜源極/ί及極（η型或ρ型離子）； Π 4〜氮化矽側壁層； I 1 6〜複晶矽層； II 8〜矽化鎢層； 1 1 9〜複晶矽層； 1 2 0〜氧化矽遮蔽層； G1-G4〜閘極結構； 122a至l-22c〜第一階段複晶矽插塞； 1 3 0〜絕緣層； 1 3 1、1 4 4〜孔洞； 1 3 2〜複晶矽層； 1 3 3〜矽化鎢層； 134〜氮化矽遮蔽層； 1 3 5〜氮化矽或氮氧化矽側壁層； 136〜介層窗； BL~位元線； 1 4 0〜複晶矽層； 1 41 a、1 41 c…第二階段複晶矽插塞； 142〜絕緣層144a、144c〜下電極； 146a、146c〜介電質層； 148a、148c〜上電極：Page 6 V. Description of the invention (4) 100 ~ early conductor substrate, 102 ~ silicon dioxide substrate layer; 112a to 112c ~ source / ί and pole (n-type or p-type ion); Π 4 ~ silicon nitride sidewall Layers; I 1 6 ~ multicrystalline silicon layer; II 8 ~ tungsten silicide layer; 1 19 ~ multicrystalline silicon layer; 12 0 ~ silicon oxide shielding layer; G1-G4 ~ gate structure; 122a to l-22c ~ The first stage of the polycrystalline silicon plug; 1 3 0 ~ insulating layer; 1 3 1, 1 4 4 ~ holes; 1 2 2 ~ polycrystalline silicon layer; 1 3 3 ~ tungsten silicide layer; 134 ~ silicon nitride shielding layer 1 3 5 ~ Silicon nitride or silicon oxynitride sidewall layer; 136 ~ Interlayer window; BL ~ Bit line; 1 40 ~ Multicrystalline silicon layer; 1 41a, 1 41c ... Second stage polycrystalline silicon Plug; 142 ~ insulating layers 144a, 144c ~ lower electrode; 146a, 146c ~ dielectric layer; 148a, 148c ~ upper electrode:

Cl、C2〜電容。Cl, C2 ~ Capacitor.

4243 2 5 五、發明說明（5) 實施例 *以下利用第2A至第2G圖說明本發明實施例，第2A圖至第2F圖為根據本發明較佳實施例之動態隨機存取記憶體製造流程剖面圖。百先’請參照第2A圖’顯示半導體基底丨〇〇形成有複數個淺溝槽隔離元件STI( trench is〇iati〇n)。依據第2A圖’首先係在半導體基底1〇〇上形成包含至少一被絕緣隔離之閘極結構G1〜G4、源極/汲極n2a~112c 的電晶體’其中閘極結構是由複晶矽層丨丨6、矽化鎢層 11 8、氧化碎遮蔽層丨2 〇及氧化矽側壁層丨〗4所構成。其次全面成長氧化矽Si02襯底層1〇2，經微影製程定義及濕蝕刻4刀氧化矽層1 〇 2以露出源/汲極。其中由於以濕银刻取代傳統的乾餘刻，故不會損傷基底及氧化矽侧壁層丨i 4。然後全面性形成一第一導電層119以覆蓋整個半導體基底’例如利用化學氣相沈積法形成複晶矽層。接著，請參照第2B圖，研磨複晶矽層11 9，使露出被絕緣隔離之閘極結構G1〜G 4之上表面，如藉由化學機械研磨’調整製程參數中的轉盤速度，下壓力，研磨墊類型和研磨劑種類以控制製程中的移除率’均勻性和選擇性，以開極結構G1~G4上之氧化矽遮蔽層120當做停止層，而研磨複晶矽層11 9至閘極結構G1 -G4之上表面。再者’請參照第2C圖，微影及蝕刻複晶矽層以形成電性連接沒極之第一階段位元線接觸插塞i 22b，及電性連接4243 2 5 V. Description of the Invention (5) Embodiment * The following describes the embodiment of the present invention by using FIGS. 2A to 2G, and FIGS. 2A to 2F show the manufacturing of dynamic random access memory according to the preferred embodiment of the present invention. Process sectional view. Baixian ', please refer to FIG. 2A, shows that a plurality of shallow trench isolation elements (STI) are formed on a semiconductor substrate. According to FIG. 2A, first, a transistor including at least one gate structure G1 to G4 and source / drain n2a to 112c is formed on a semiconductor substrate 100. The gate structure is made of polycrystalline silicon. Layer 丨丨 6, tungsten silicide layer 118, oxidized debris shielding layer 丨 20, and silicon oxide sidewall layer 丨〖4. Secondly, the silicon oxide Si02 substrate layer 102 is fully grown, and the 4-layer silicon oxide layer 102 is etched by the lithography process definition and wet etching to expose the source / drain. Among them, the wet dry engraving is used instead of the traditional dry etch, so it will not damage the substrate and the silicon oxide sidewall layer. Then, a first conductive layer 119 is formed comprehensively to cover the entire semiconductor substrate ', for example, a polycrystalline silicon layer is formed by a chemical vapor deposition method. Next, referring to Figure 2B, grind the polycrystalline silicon layer 119 to expose the upper surface of the gate structures G1 ~ G 4 which are insulated and isolated. If the mechanical disk is used to adjust the speed of the turntable in the process parameters, the down force In order to control the removal rate in the process of polishing pad type and polishing agent type, uniformity and selectivity, the silicon oxide shielding layer 120 on the open electrode structure G1 to G4 is used as a stop layer, and the polycrystalline silicon layer is polished. The upper surfaces of the gate structures G1-G4. Furthermore, please refer to FIG. 2C, lithography and etching the polycrystalline silicon layer to form the first stage bit line contact plug i 22b of the electrical connection electrode, and the electrical connection

第8頁五、發明說明（6) 源極之第一階段電容接觸插塞122a與122(：。然後全面性形成第一絕緣層1 3 0 ’以覆蓋複晶矽層丨丨9和閘極結構 G1〜G4，例如利用化學氣相沈積法形成二氧化矽層’而在沈積的同時，於狹窄的導線層間的凹陷處將難以被填滿，而形成孔洞1 3 1，其中由於接觸插塞已經形成，故不會因孔洞1 3 1的形成而發生短路的現象，此類孔洞正是最佳的隔離與絕緣材。然後’請參照第2 D圖，形成一穿過絕緣層1 3 〇而與第一階段位元線接觸插塞1 22b電性連接的位元線BL ^其中位凡線BL是由複晶矽層1 32、矽化鎢層1 33、氮化矽遮蔽層 1 34及氮化矽或氮氧化矽側壁層1 35所構成。再者，請參照第2 E圖’以微影製程及蝕刻步騾定義第一絕緣層1 3 0，形成一露出第一階段電容接觸插塞1 2 2 a與 122c之介層窗136，其次，全面性形成一第二導電層“ο以覆蓋個位元線’如利用化學氣相沈積法形成複晶石夕層。接著研磨複晶矽層1 4 0，使露出被絕緣隔離之位元線 BL之上表面，如藉由化學機械研磨，調整製程參數中的轉盤速度’下壓力，研磨塾類型和研磨劑種類以控制製程中的移除率，均勻性和選擇性，以位元線BL上之氮化妙遮蔽層1 34當做停止層’而研磨複晶矽層1 4 0至位元線bl之上表面。 ’ 而後，請參照第2F圖，微影及蝕刻複晶矽層1 40以形成電性連接第一階段電容接觸插塞122a、122c之第二階段電谷接觸插塞1 41 a與1 4 1 c °然後全面性形成第二絕緣層 4243 2 5 五、發明說明（7) 1 4 2 ’ _以覆蓋複晶€夕層1 4 〇和位元線B L，例如利闬化學氣相沈積法形成二氧化矽層，而在沈積的同時，於狹窄的導線層間的凹陷處將難以被填滿，而形成孔洞1 44，其中由於接觸插塞已經形成，故不會因孔洞1 3 1的形成而發生短路的現象’此類孔洞正是最佳的隔離與絕緣材。最後，請參照第2G圖，形成一穿過第二絕緣層1 42而與第二階段電容接觸插塞電性連接的電容器C1-C2。其中’電容器C 一般係包括複晶矽構成的下電極1 44a、 144c ;二氧化矽層/氮化矽層/二氧化矽層（ΟΝΟ)所構成的介電質層146a、146c :以及複晶矽層所構成的上電極 148a 、 148c 。本發明之一優點在於提供一種於十億位元世代之新顆的動態隨機存取記憶體細跑元及其製造方法，該方法係先形成導電插塞’再形成隔離之絕緣層’其中應用自行對準技術使得元件的内部構造可以尺度化以消除源極區角落的不對準效應，五可使該記憶體細胞元具有一致的電特性。本發明之另一優點在於提供一新穎的動態隨機存取記憶體細胞元及其製造方法’該方法於施行自行對準接觸製程步驟時不會損害到其他隔離層’而影響隔離效果使得漏電流產生。本發明尚有另一優點在於提供一新穎的動態隨機存取記憶體細胞元及其製造方法，該方法於沉積絕緣層時因深寬比過大而形成之孔洞可利用為最佳的隔離與絕緣材。本發明還有另一優點在於提供一新穎的動態隨機存取Page 8 V. Description of the invention (6) The first-stage capacitive contact plugs 122a and 122 (: of the source electrode. Then, a first insulating layer 1 3 0 'is formed comprehensively to cover the polycrystalline silicon layer 丨 9 and the gate electrode. The structures G1 to G4, for example, use a chemical vapor deposition method to form a silicon dioxide layer, and at the same time as the deposition, the depressions between the narrow wiring layers will be difficult to be filled, and holes 1 3 1 are formed. It has been formed, so there will not be a short circuit due to the formation of holes 1 31. Such holes are the best insulation and insulation materials. Then, please refer to Figure 2D to form a through-insulating layer 1 3 〇 The bit line BL electrically connected to the first-stage bit line contact plug 1 22b ^ wherein the bit line BL is composed of a polycrystalline silicon layer 132, a tungsten silicide layer 1 33, a silicon nitride shielding layer 1 34, and It is composed of silicon nitride or silicon oxynitride sidewall layer 1 35. Furthermore, please refer to FIG. 2E 'to define the first insulating layer 1 3 0 by the lithography process and the etching steps to form a first-stage capacitive contact plug. Plug the interlayer window 136 of 1 2 2 a and 122 c, and secondly, form a second conductive layer “ο to cover each The bit line is formed by using a chemical vapor deposition method, and then the polycrystalline silicon layer 14 is ground, so that the upper surface of the bit line BL which is isolated by insulation is exposed, and adjusted by chemical mechanical polishing, for example. The turntable speed in the process parameters 'down pressure, grinding type and abrasive type to control the removal rate, uniformity and selectivity in the process, using the nitrided masking layer 1 34 on the bit line BL as the stop layer' And polish the polycrystalline silicon layer 140 to the upper surface of the bit line bl. Then, please refer to FIG. 2F, lithography and etching the polycrystalline silicon layer 140 to form a first-stage capacitor contact plug 122a for electrical connection. The second stage of the 122c electric valley contact plug 1 41 a and 1 4 1 c ° and then comprehensively form a second insulating layer 4243 2 5 V. Description of the invention (7) 1 4 2 '_ to cover the polycrystalline layer 1 40 and bit lines BL, such as the Lithium Chemical Vapor Deposition method, form a silicon dioxide layer. At the same time as the deposition, the depressions between the narrow wire layers will be difficult to fill, forming holes 1 44, of which Since the contact plug has been formed, it will not be short due to the formation of the holes 1 3 1 This kind of hole is the best insulation and insulation material. Finally, please refer to Figure 2G to form a capacitor C1 that passes through the second insulating layer 142 and is electrically connected to the second-stage capacitor contact plug. -C2. 'Capacitor C generally includes lower electrodes 1 44a, 144c composed of polycrystalline silicon; dielectric layers 146a, 146c composed of silicon dioxide layer / silicon nitride layer / silicon dioxide layer (NONO): And upper electrodes 148a, 148c made of a polycrystalline silicon layer. One of the advantages of the present invention is to provide a dynamic random access memory sprinter with a new generation in the billion-bit generation and a manufacturing method thereof. Forming conductive plugs, and then forming an isolated insulating layer, in which self-alignment technology is applied so that the internal structure of the component can be scaled to eliminate the misalignment effect at the corners of the source region, and the memory cell can have consistent electrical characteristics. . Another advantage of the present invention is to provide a novel dynamic random access memory cell cell and a method for manufacturing the same. The method does not damage other isolation layers when performing self-aligned contact process steps, and affects the isolation effect and causes leakage current. produce. Another advantage of the present invention is to provide a novel dynamic random access memory cell and a method for manufacturing the same. The method can be used for optimal isolation and insulation when depositing an insulating layer due to an excessively large aspect ratio. material. Another advantage of the present invention is to provide a novel dynamic random access

〜43 2 5 五、發明說明（8) 記憶體細胞元及其製造方法，該方法採用的絕緣材料可大幅減低記憶體細胞元之字元線及位元線中的寄生電容。雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此項技藝者，在不脫離本發明之精神和範圍内，當可作更動與潤飾，因此本發明之保護範園當視後附之申請專利範圍所界定者為準。~ 43 2 5 V. Description of the invention (8) Memory cell and its manufacturing method. The insulating material used in this method can greatly reduce the parasitic capacitance in the word line and bit line of the memory cell. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make changes and retouching without departing from the spirit and scope of the present invention. The protection of Fan Yuan shall be determined by the scope of the attached patent application.

Claims

8S1u ο,, 424325 六、申請專利範圍 I 一種動態隨機存取記憶體的製造方法，適用於一半導體基底，包括下列步驟：在該半導體基底上形成包含至少一被絕緣隔離之閘極結構、源極/汲極的電晶體；全面性形成一第一導電層；研磨該第一導電層，使露出該被絕緣隔離之閘極結構之上表面；定義該第一導電層以形成電性連接該汲極之第一階段位元線接觸插塞，及電性連接該源極之第一階段電容接觸插塞；全面性形成一第一絕緣層；形成一被絕緣隔離之位元線，其穿過該第一絕緣層而與該第一階段位元線接觸插塞電性連接；全面性形成一第二導電層，其穿過該第一絕緣層而與該第一階段電容接觸插塞電性連接；研磨該第二導電層，使露出該被絕緣隔離之位元線之上表面；定義該第二導電層，以形成電性連接該第一階段電容接觸插塞之第二階段電容接觸插塞；全面性形成一第二絕緣層；及形成一電容器，其穿過該第二絕緣層而與該第二階段電容接觸插塞電性連接。 2.如申請專利範圍第1項所述之動態隨機存取記憶體的製造方法，其中更包括於該半導體基底上全面性成長氧 4 243 2 r _________ 六、申請專利' ' 一化矽襯底層。 ,3.如申請專利範圍第1項所述之動態隨機存取記憶體的製造方法’其中該閘極結構是由複晶矽層、矽化鎢層、氧化矽遮蔽層及氧化矽側壁層所構成。 4. 如申請專利範圍第1項所述之動態隨機存取記憶體的製造方法’其中研磨該第一和第二導電層係施行化學機械研磨製程。 5. 如申請專利範圍第1項所述之動態隨機存取記憶體的製造方法，其中該第一和第二絕緣層係二氧化矽層。 6. 如申請專利範圍第1項所述之動態隨機存取記憶體的製造方法，其中該導電層結構是由複晶矽層、矽化鎢層及氮化矽遮蔽層。 7. 如申請專利範圍第1項所述之動態隨機存取記憶體的製造方法，其中該導電層絕緣間隔層係氮化矽層或氮氧化矽層。8S1u ο, 424325 VI. Scope of patent application I. A method for manufacturing a dynamic random access memory is suitable for a semiconductor substrate, and includes the following steps: forming a gate structure and a source including at least one insulation layer on the semiconductor substrate; Electrode / drain transistor; comprehensively forming a first conductive layer; grinding the first conductive layer to expose the upper surface of the insulated gate structure; defining the first conductive layer to form an electrical connection with the The first-stage bit line contact plug of the drain electrode and the first-stage capacitor contact plug electrically connected to the source; comprehensively forming a first insulating layer; forming a bit line isolated by insulation, which penetrates It is electrically connected with the first-stage bit line contact plug through the first insulation layer; a second conductive layer is formed comprehensively, which passes through the first insulation layer and is in contact with the first-stage capacitor contact plug. Ground the second conductive layer to expose the upper surface of the bit line that is insulated and isolated; define the second conductive layer to form the first connection of the first-stage capacitive contact plug electrically Stage capacitor contact plug; comprehensiveness forming a second insulating layer; and forming a capacitor through the second insulating layer interposed capacitive contact with the second stage of the plug is electrically connected. 2. The method for manufacturing a dynamic random access memory as described in item 1 of the scope of patent application, which further includes comprehensively growing oxygen on the semiconductor substrate 4 243 2 r _________ 6. Applying for a patent '' Silicon substrate . 3. The method for manufacturing a dynamic random access memory according to item 1 of the scope of the patent application, wherein the gate structure is composed of a polycrystalline silicon layer, a tungsten silicide layer, a silicon oxide shielding layer, and a silicon oxide sidewall layer. . 4. The method for manufacturing a dynamic random access memory according to item 1 of the scope of the patent application, wherein the first and second conductive layers are polished by a chemical mechanical polishing process. 5. The method for manufacturing a dynamic random access memory according to item 1 of the scope of the patent application, wherein the first and second insulating layers are silicon dioxide layers. 6. The method for manufacturing a dynamic random access memory according to item 1 of the scope of the patent application, wherein the conductive layer structure is a polycrystalline silicon layer, a tungsten silicide layer, and a silicon nitride shielding layer. 7. The method for manufacturing a dynamic random access memory according to item 1 of the scope of the patent application, wherein the conductive insulating layer is a silicon nitride layer or a silicon nitride oxide layer.

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