TW424319B - System and method for limiting charge-pump internal node voltage - Google Patents
System and method for limiting charge-pump internal node voltage Download PDFInfo
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424319 五、發明說明(1) 發明領域 本發明是關於一種積體電路充電泵,特別關於一種具 有可限制其内部節點電位之電路的積體電路充電泵。 發明背景 某些積體電路(意指晶片)需要不同電位之供應電壓, 這些供應電壓可以藉由將電壓產生器合併於晶片之中而直 接在晶片内產生。對高於外接供應電壓之晶片内產生的供 應電壓來說,通常是使用一充電泵做為電壓產生器。圖1 是舊式積體電路充電泵10的方塊圖,此充電泵被用來產生 一高於外接供應電壓之供應電壓vh。充電泵10包括了一主 幫浦級ll(main pump stage, MPS) ' —井幫浦級13(well pump stage, WPS)及兩個做為通道閘之P通道電晶體pi4和 P15 〇MPS 11及WPS 13分別被連接至一VDD供應匯流排及一 接地匯流排以從一提供供應電壓VDD之外接電源接收電 力。此外,MPS 11及WPS 13經由一控制線16連接接收n個 (η代表一大於零之整數)幫浦控制信號^ Mps丨丨及肝$ a 之輸出端分別連接至ρ通道電晶體Ρ14和?15之源極。 Ρ通道電晶體Ρ14和Ρ15之閘極連接至一連線18以接收 一幫浦拉升控制信號PMPBST。當PMPBST被觸發時(在此實 施例中意指一邏輯低電位)會具有一拉升電位(意指一高於 正常VDD電位之電位)並用以控制從Mps n&wps 13之輸 端傳送出之電荷。 p通道電晶體P14之汲極連接至輸出端19*P通道電晶 體P15之汲極連接至P通道電晶體p14之井區。在此例中,p424319 V. Description of the invention (1) Field of the invention The present invention relates to an integrated circuit charge pump, in particular to an integrated circuit charge pump having a circuit that can limit the potential of its internal node. BACKGROUND OF THE INVENTION Certain integrated circuits (meaning wafers) require different potential supply voltages. These supply voltages can be generated directly in the wafer by incorporating a voltage generator into the wafer. For a supply voltage generated in a chip that is higher than the external supply voltage, a charge pump is usually used as the voltage generator. Figure 1 is a block diagram of a conventional integrated circuit charge pump 10, which is used to generate a supply voltage vh which is higher than the external supply voltage. The charge pump 10 includes a main pump stage (MPS) '-a well pump stage (WPS) 13 and two P-channel transistors pi4 and P15 as channel gates MPS 11 And WPS 13 are respectively connected to a VDD supply bus and a ground bus to receive power from an external power supply providing a supply voltage VDD. In addition, MPS 11 and WPS 13 are connected via a control line 16 to receive n (η represents an integer greater than zero) pump control signals ^ Mps 丨 丨 and liver $ a. The output terminals are connected to the p-channel transistor P14 and? Source of 15. The gates of the P-channel transistors P14 and P15 are connected to a connection 18 to receive a pump-up control signal PMPBST. When PMPBST is triggered (meaning a logic low potential in this embodiment), it has a pull-up potential (meaning a potential higher than the normal VDD potential) and is used to control the transmission from the Mps n & wps 13 output terminal Charge. The drain of the p-channel transistor P14 is connected to the output terminal 19 * The drain of the P-channel transistor P15 is connected to the well region of the p-channel transistor p14. In this example, p
第5頁 4243ί§P. 5 4243
通道電晶體Ρ14建構於—Ν_井區内β如同在半導體技術中 所熟知的,井區必需維持一電位(hen)高於或等於ρ通道電 晶體之源極或汲極中最高的電位,以使電晶體正常運作。 但疋,由於負載電流的波動,在輸出端丨9 (即ρ通道電晶體 Ρ14之汲極)之%的電位有時會高於Mps η之輸出端(即ρ通 道電晶體Ρ1 4之源極)的電位。此外,電晶體ρ〗4之源極的 電位有時也會咼於Vh的電位。所以,只是將井區連接至ρ 通道電晶體P14的源極或沒極是無助益的。 為了處理此問題,充電泵10使用WPS 13將\川的電位 保持在一大於P通道電晶體P14之源極或汲極中最高電位之 預設電位。熟悉此技術的人熟知P通道電晶體P1 5之井區的 電容值及漏電流通常都很小’因此,p通道電晶體p 1 5之源 極的電位將一直大於或等於井區的電位。於是,將p通道 電晶體P15之汲極連接一井區能有效地將井區的電位維持 於或高於P通道電晶體P1 5之源極及汲極的電位。 為了將供應電壓Vh維持在所希望的電位上,傳統上, 一控制電路(圖未顯示)提供在連線16上之幫浦電路信號以 使MPS11及WPS13分別將電荷傳送至p通道電晶體P14及 P15。幫浦拉升信號PMPBST做為控制P通道電晶體P14及?15 之狀態之用,以分別將電荷從MPS11及WPS13傳送至輪出端 19及P通道電晶體14之井區。更具體的說,當連接至p通道 電晶體P14及P15之源極的MPS11及WPS13在對他們的幫浦電 容充電時,P通道電晶體P14及P15是關閉的。尤其,Mpsil 及WPS13將其相對應之輸出端電壓上升至一明顯大於外接The channel transistor P14 is constructed in the β-well region. As is well known in semiconductor technology, the well region must maintain a potential (hen) higher than or equal to the highest potential of the source or drain of the p-channel transistor. In order to make the transistor work normally. However, due to the fluctuation of the load current, the potential at% of the output terminal 9 (ie, the drain of the p-channel transistor P14) is sometimes higher than the output of Mps η (the source of the p-channel transistor P1 4). ) Potential. In addition, the potential of the source of the transistor p4 may also be lower than the potential of Vh. Therefore, it is not helpful to simply connect the well region to the source or non-pole of the p-channel transistor P14. To deal with this problem, the charge pump 10 uses WPS 13 to maintain the potential of the transistor at a preset potential greater than the highest potential in the source or sink of the P-channel transistor P14. Those who are familiar with this technology are familiar with the capacitance value and leakage current of the well region of the P-channel transistor P1 5 are usually small '. Therefore, the potential of the source of the p-channel transistor p 1 5 will always be greater than or equal to the potential of the well region. Therefore, connecting the drain of the p-channel transistor P15 to a well region can effectively maintain the potential of the well region at or higher than the potential of the source and the drain of the p-channel transistor P15. In order to maintain the supply voltage Vh at the desired potential, traditionally, a control circuit (not shown) provides a pump circuit signal on the connection 16 so that MPS11 and WPS13 transfer the charge to the p-channel transistor P14, respectively. And P15. Pump up the signal PMPBST as a control P channel transistor P14 and? 15 to transfer the charge from the MPS11 and WPS13 to the well 19 of the wheel outlet 19 and the P-channel transistor 14 respectively. More specifically, when MPS11 and WPS13 connected to the sources of p-channel transistors P14 and P15 are charging their pump capacitors, P-channel transistors P14 and P15 are turned off. In particular, Mpsil and WPS13 increase their corresponding output voltage to
五、發明說明(3) 供應電壓之電位。這通常是經由對一在幫浦級内之電容 電而做到的並使得第一端是在零電位點而第二端是在外 供應電壓電位。之後幫浦級將第一端之電位提高,於是, 最少是開始,將第二端之電位提高至一高於外接供應電_ 之電位。 ’ ' t 一 一 ^ 々似 % ^ rh jui ^ 之電位與P14及P15之源極及没極之電位相同或更高V. Description of the invention (3) Supply potential. This is usually done by charging a capacitor in the pump stage such that the first terminal is at the zero potential point and the second terminal is externally supplied with the voltage potential. After that, the pumping stage raises the potential of the first terminal, so at least, at the beginning, the potential of the second terminal is increased to a potential higher than that of the external power supply. ’'T one one ^ 々 像 %% ^ rh jui ^ The potential is the same as or higher than the potentials of the source and non-poles of P14 and P15
V 當MPS11及WPS13已將P通道電晶體pi4及P15之源極電 位提高時,PMPBST信號使P通道電晶體P14及pi5開啟讓 電荷能從MPSU及WPS1 3之幫浦電容分別重新分配至p通道 電aa體P14及P15之源極,及分別至輪出端19及p通道曰 之井區。利用此法,充電泵10產生供應電壓、並維持 well 〇但如果P通道電晶體P14之井區電位過高時,連接至井 裝置中接合面崩潰之機率會增加。在一外接供應電壓 作電M還大的-項燒人測試令,這個問題 壓之充電泵。因此,需要有一種可以控制其内部節點電 發明目的 電果依,i ϊ明',冑供了—種可控制其内部節點電壓之充 路 第 徵是兮第電路及一第二鉗制電路。本發明其-之特 界電路藉由在丼區之電位到達-第-預設臨 電仇。本發明另出:之電流通路而限制井區之 特徵疋第一鉗制電路在一第一節點之電 本發明於降低充電泵中接合面的崩潰機率。 發月中實施例包括了一第一幫浦電路;一第二幫浦電 ^^88111980 五、發明說明(4) 位到達一第二預执辟w ^ ------" 之導電通路來限制— 弟知點至輸出端 重新分配至井[ ·電位而電荷是由該第一節點 开區。限制井區及 卑即點 接至井區之裝置中 卩點之電位可以降低連 本發明之Π匕:潰之機率。 之幫浦電路及一電容暫充f泵包括一具有邏輯電路 輯電路根據外接月其一之特徵是該邏 中之電容節點之電懕 艾电备幫浦電路 岸電壓相备大^ 升速率。這項特徵適用於在外接供 速心低: 之電壓上升速率以外,電容節點與外;供 相當大時了 Li I 這項特徵適用於在外接供應電壓 成為另丄降低接人外ί供應電壓有關之電容節點之電位而 成為另降低接合面朋潰機率之機制。 圖示簡單說明 亡贲J1係使用ρ通道電晶體之導通閘極的舊式積體電路 充電系方塊圖。 圖2係一本發明實施例中之具有内部節點電壓控制之 積體電路充電泵方塊圖。 圖 圖3係一完成圖2中方塊圖之積體電路充電泵之電路 圖4係圖3中之積體電路充電泵之操作時序圖。 詳細說明 圖2是一方塊圖,描繪了一積體電路充電泵2〇。依據V When MPS11 and WPS13 have increased the source potentials of the P-channel transistors pi4 and P15, the PMPBST signal turns on the P-channel transistors P14 and pi5 so that the charge can be redistributed from the pump capacitors of MPSU and WPS1 3 to the p-channel, respectively. The source of the electric aa body P14 and P15, and the well area to the channel exit 19 and p channel, respectively. With this method, the charge pump 10 generates a supply voltage and maintains well. However, if the potential of the well region of the P-channel transistor P14 is too high, the chance of the joint surface in the well device to collapse will increase. The external power supply voltage is still large for the M-test test order. This problem is caused by the charge pump. Therefore, there is a need to control the internal node power of the invention. The purpose of the invention is to provide a charging circuit that can control the internal node voltage. The characteristics are a first circuit and a second clamping circuit. According to the present invention, its special circuit is reached by the potential in the 丼 region, and the preset electric circuit is set. The present invention has the following features: the current path restricts the well area. The first clamping circuit is at a first node. The invention reduces the probability of collapse of the joint surface in the charge pump. The embodiment in the middle of the month includes a first pump circuit; a second pump power ^^ 88111980 V. Description of the invention (4) The bit reaches a second pre-execution w ^ ------ " conductive Path to limit — the point to the output is redistributed to the well [potential and the charge is opened by the first node. Restricting the well area and the point where the point is connected to the device in the well area can reduce the potential of the joints of the present invention. The pump circuit and a capacitor temporary charge pump include a logic circuit. The circuit is based on external characteristics. One of the characteristics is that the capacitor node in the logic is powered by a pump circuit. The shore voltage is relatively high. This feature is suitable for low-speed external power supply: outside the voltage rise rate, the capacitor node is external; when the supply is quite large, Li I. This feature is suitable for reducing the external supply voltage when the external supply voltage becomes another. The potential of the capacitive node becomes another mechanism to reduce the probability of rupture at the joint. The diagram shows the block diagram of the charging circuit of the old integrated circuit using the conduction gate of the p-channel transistor. FIG. 2 is a block diagram of an integrated circuit charge pump with internal node voltage control in an embodiment of the present invention. Fig. 3 is a circuit diagram of the integrated circuit charge pump for completing the block diagram in Fig. 2. Fig. 4 is an operation timing chart of the integrated circuit charge pump in Fig. 3. DETAILED DESCRIPTION FIG. 2 is a block diagram depicting an integrated circuit charge pump 20. in accordance with
05ib-4535TW?2-pic 第8頁 42>43f 9 _ 五、發明說明(5) ' ~ 本發明之一實施例,充電泵20含有内部節點電壓限定控 制。為了更清楚明瞭’在每一圖中具有相同或類似功能或 結構之元件使用相同的參考數字。除了含有—具有主燒入 控制電路(MBC) 22之主幫浦級(MPS) 21及一具有井區燒入控 制電路(WBC)24之井幫浦級(WPS)23不同於MPS1 1 (圖1 )及 WPS13C圖1)外,充電泵20與充電泵1〇(圖1)是相似的。此 外’此實施例之充電泵2 0包括了一鉗制電路2 5及一鉗制電 路2 6 〇 充電果20的組接如下。MPS21經由連線16連接接收一 幫浦控制信號’如同充電泵1〇(圖1)。在此實施例中, 1^〔22及*^321經由連線2 7連接接收一燒入幫浦控制信號 BPMP。MPS21之輸出端經由一即點N20連接至P通道電晶體 P1 4之源極。p通道電晶體p 1 4之閘極連接接收幫浦拉升信 號PMPBST 通道電晶體P14之之汲極(也就是輸出端19)連 接至鉗制電路25之一端。鉗制電路25之另一端連接至電晶 體P14之N-井區及電晶體P15之汲極。 WPS23亦如同充電泵1〇(圖1)經由連線16連接接收幫浦 控制信號。在此實施例中,WPS23之WBC24經由連線28連接 接收一井幫浦燒入控制信號WBIC。WPS23之輸出端經由一 節點N22連接至P通道電晶體pi5之源極。p通道電晶體P15 之閘極經由連接接收幫浦拉升信號PMPBST。P通道電晶體 P15之汲極連接至電晶體p 14之N-井區及電晶體P15之汲 極。鉗制電路26連接於節點N22及輸出端19之間。 充電泵20之操作如下。在正常模式之操作下,BPMP及05ib-4535TW? 2-pic Page 8 42 > 43f 9 _ V. Description of the invention (5) '~ In one embodiment of the present invention, the charge pump 20 includes an internal node voltage limiting control. For the sake of clarity, elements having the same or similar functions or structures in each figure are given the same reference numerals. Except that-the main pump stage (MPS) 21 with the main burn control circuit (MBC) 22 and the well pump stage (WPS) 23 with the well burn control circuit (WBC) 24 are different from the MPS1 1 (Figure 1) and WPS13C (Figure 1), the charge pump 20 is similar to the charge pump 10 (Figure 1). In addition, the charging pump 20 of this embodiment includes a clamping circuit 25 and a clamping circuit 26. The charging fruit 20 is assembled as follows. The MPS21 receives a pump control signal 'via the connection 16 like the charge pump 10 (Fig. 1). In this embodiment, 1 ^ [22 and * ^ 321 receive a burn-in pump control signal BPMP via the connection 27. The output of MPS21 is connected to the source of P-channel transistor P1 4 via a point N20. The gate connection of the p-channel transistor p 1 4 receives the pump-up signal PMPBST. The drain (ie, output terminal 19) of the channel transistor P14 is connected to one end of the clamp circuit 25. The other end of the clamp circuit 25 is connected to the N-well region of the transistor P14 and the drain of the transistor P15. WPS23 is also connected to charge pump 10 (Figure 1) to receive the pump control signal through connection 16. In this embodiment, WBC24 of WPS23 is connected via a connection 28 to receive a well pumping control signal WBIC. The output of WPS23 is connected to the source of P-channel transistor pi5 via a node N22. The gate of the p-channel transistor P15 receives the pump-up signal PMPBST via a connection. The drain of the P-channel transistor P15 is connected to the N-well region of the transistor p14 and the drain of the transistor P15. The clamp circuit 26 is connected between the node N22 and the output terminal 19. The operation of the charge pump 20 is as follows. In normal mode operation, BPMP and
4243 1 9 五、發明說明(6) WBIC信號使MBC22及WBC24進入正常模式。當mbC22在正常 模式時’與MPS21其餘之電路執行内部操作以利用如同 MPS11(圖1)之方法’使MPS21將節點N20之電位上升來回應 接收自連線16之幫浦控制信號。當MPS21將節點N20之電位 上升時’P通道電晶體P14讓電荷從節點N20重新分配至輸 出端19以回應PMPBST信號。藉由適當地觸發控制信號’ ^ 的電位維持在一所需之電位上。 h 同樣地,在正常模式中,WBC24與WPS23其餘之電路執 行内部操作以利用如ffMPS13(圖1)之方法,使WBC23將節點 N22之電位上升來回應接收自連線丨6之幫浦控制信號。當 W^S24將節點N22之電位上升時,p通道電晶體pi5讓電荷從4243 1 9 V. Description of the invention (6) WBIC signal makes MBC22 and WBC24 enter normal mode. When the mbC22 is in the normal mode, it performs internal operations with the remaining circuits of the MPS21 to use the method like MPS11 (Figure 1) to cause the MPS21 to raise the potential of the node N20 in response to the pump control signal received from the connection 16. When MPS21 raises the potential of node N20, the 'P-channel transistor P14 allows the charge to be redistributed from node N20 to output terminal 19 in response to the PMPBST signal. The potential of the control signal ′ ^ is maintained at a desired potential by appropriately triggering the control signal. h Similarly, in normal mode, the remaining circuits of WBC24 and WPS23 perform internal operations to use methods such as ffMPS13 (Figure 1) to make WBC23 raise the potential of node N22 in response to the pump control signal received from the connection 6 . When W ^ S24 raises the potential of node N22, the p-channel transistor pi5 allows the charge from
節點N22重新分配至p通道電晶體pi4之井區以回應pMpBST 信號。藉由此法,VweI1之電位維持在一等於或大於v 點N 2 0之電位。 1 依據本發明,鉗制電路25及26是分別用以限制¥及 知點N22之電▲位以阻止連接至p通道電晶體pi4井區之裝置 中之接合面崩冑。鉗制電路25被設計成在Vweil電位到達― 預叹臨界電壓時’藉由提供一條從P通道電晶體P14至輪出 二19之:電:路以限制U電位。舉例來說 出 2』可以用-其正極電接至p通道 電路 v古一個-搞躲Γ來元成。因 Vwen之電位被限制在較 t㈤-極體臨界電壓值之電位,而阻止了連接至 、電:^ 4井區之裝置中之接合面崩潰D 同樣地,细击,丨φ 。λ , 甜刺電路26被設計成在節點Ν22電位到達—Node N22 is reassigned to the well area of p-channel transistor pi4 in response to the pMpBST signal. By this method, the potential of VweI1 is maintained at a potential equal to or greater than the v-point N 2 0. 1 According to the present invention, the clamp circuits 25 and 26 are used to limit the electric potential of the ¥ and the knowledge point N22 to prevent the joints in the device connected to the p-channel transistor pi4 well area from collapsing. The clamping circuit 25 is designed to limit the U potential by providing a path from the P-channel transistor P14 to the wheel-out when the Vweil potential reaches the ―predicted critical voltage‖. For example, "2" can be used-its positive electrode is electrically connected to the p-channel circuit v-one-to avoid Γ. Because the potential of Vwen is limited to a potential that is higher than the threshold voltage of the t 极 -pole body, the junction surface in the device connected to the well: ^ 4 well zone is prevented from collapsing. Similarly, fine tap,, φ. λ, the sweet thorn circuit 26 is designed to reach the potential at the node N22—
Α9ά1^ί 五、發明說明(7) --------- 預設臨界電壓時,藉由提 一 妨雪怿從知點N22至輸出端19之 = 限制節點N22之電位。舉例來說,鉗制電路26 之二;6 I接至卽點N22且其負極電接至輸出端19 ^ 。因此,節點N22之電位被限制在較v高 一個一極體臨界電壓值之雷仿 ί Ρ Ί -¾ Φ a 值之電位,而错由限制用以將電荷傳 送至P通道電日日體P 1 4 I Γ5" + 4* jtL Λ- rsr ^ a Λ 14井£之拉升電壓,阻止了連接至ρ通 道電aafP14井區之裝置中之接合面崩潰。 ,在燒入模式中,此實施例之外接供應電壓VDD在燒入 測試中被提高約4. 5伏特,但如熟知此技術的人所知悉 的,燒入電壓是與技術有關的。由於Mps21及肝§23在 N2 0及N22所提供之拉升量通常是與外接供應電壓v⑽有關 的,在燒入模式中,節點N20及N22的上升通常會大於在正 常模式。因此,雖然鉗制電路25及26有且助於限制v之 電位丄這些鉗制電路在燒入模式時,無法阻止外接應電 壓之高電位使MPS21及WPS23將節點N20及N22之電位提高至 這些相當高的電位。由於將電荷從節點N2〇及N22傳送至輪 出端19及P通道電晶體p 14之井區需要一定的時間,如果節 點N20及N22上升的速率高於電荷經由電晶體pi4&pi5重新 分配的速率’與電晶體P14&P15之源極比較下,在節點 N20及N22高電壓成長會導致連接至p通道電晶體pi4井區之 裝置中之接合面崩潰。 依據本發明’ MBC22及WBC24被設計成可在燒入模式時 降低節點N20及N22之上升速率。在燒入模式中,MpS2l及 WPS23拉升_點N20及N22時,降低上升速率有助於提供電Α9ά1 ^ ί V. Description of the invention (7) --------- When presetting the threshold voltage, by referring to the potential of the limit node N22 from the knowledge point N22 to the output terminal 19 For example, the clamp circuit 26 bis; 6 I is connected to the point N22 and its negative electrode is electrically connected to the output terminal 19 ^. Therefore, the potential of the node N22 is limited to a potential of a value of ρ Ί -¾ Φ a, which is higher than the threshold voltage of a polar body, which is used to transfer the charge to the electric channel P of the P channel. 1 4 I Γ5 " + 4 * jtL Λ- rsr ^ a Λ The pull-up voltage of well 14 prevents the joint in the device connected to the channel aafP14 well area from collapsing. In the burn-in mode, the external supply voltage VDD of this embodiment is increased by about 4.5 volts during the burn-in test, but as known to those skilled in the art, the burn-in voltage is technology-related. Because Mps21 and liver §23 provide the pull-up amounts at N2 0 and N22, which are usually related to the external supply voltage v⑽, in the burn-in mode, the rise of nodes N20 and N22 will usually be greater than in normal mode. Therefore, although the clamp circuits 25 and 26 help and limit the potential of v, these clamp circuits cannot prevent the high potential of the external voltage when the burn-in mode is enabled. MPS21 and WPS23 increase the potential of nodes N20 and N22 to these fairly high The potential. Since it takes a certain amount of time to transfer charges from nodes N20 and N22 to the well area of wheel 19 and P channel transistor p14, if nodes N20 and N22 rise faster than the charge is redistributed through transistor pi4 & pi5 Compared with the source of the transistor P14 & P15, the high voltage growth at the nodes N20 and N22 will cause the junction in the device connected to the p-channel transistor pi4 well area to collapse. According to the present invention 'MBC22 and WBC24 are designed to reduce the ascent rate of nodes N20 and N22 during the burn-in mode. In the burn-in mode, when MpS2l and WPS23 are pulled up_points N20 and N22, reducing the rising rate helps to provide electricity
第11頁 4243 1 8 五'發明說明(8) ' ----— --- 何更多的時間從這些節點重新分配至輸出端及P通道電晶 ^P14之井區。於是,節點N20及N22之最高電位被降低而 減小了連接至節點N20及N22之裝置中之接合面崩潰機率。 更精緻的疋’WBC24不但降低了上升速率,還可被設計成 在燒入模式時限制節點N22之拉升電位。MBC22及ffBC24的 只把例配合圖3做以下之說明。 圖3是—示意圖,描繪了充電泵2〇(圖2)。在此實施例 中,MPS21是以n通道電晶體關20、MN21、MN24及P通道電 晶體P20、P21及一電容。。來完成。p通道電晶體pH也做 為MBC22之用。 MPS21的組接如下。N通道電晶體MN2〇的源極、閘極及 沒極分別連接至VDD供應匯流排、連線16]及節點N20。連 線1 61是連線1 6 (圖1)之一單元線,用以傳送幫浦控制信 號。在此實施例中,連線^,傳送一前置拉升(pre_boost) fs破PREBST。在對節點N20前置充電(precharge)時, PREBST信號選擇性地被觸發或閒置,此處將會在下文詳細 說明。當信號PREBST被觸發時,會具有一高於外接供應電 壓VDD之電位。 N通道電晶體MN21被連接成二極體,其正極連接至vdd 供應匯流排而負極速接至節點N20。電容C20連接在節點 N2 0及N21之間。P通道電晶體P20之源極、閘極及汲極分別 連接至VDD供應匯流排、連線162及節點N21。連線162是連 線1 6 (圖1 )之一單元線,用以傳送幫浦控制信號。在此實 施例中’連線162傳送一幫浦信號PMP。在拉升節點N20Page 11 4243 1 8 Five 'Explanation of the invention (8)' -------- --- How much time is redistributed from these nodes to the output end and the P-channel transistor ^ P14 well area. As a result, the highest potentials of the nodes N20 and N22 are lowered, which reduces the probability of a joint collapse in a device connected to the nodes N20 and N22. The more refined 疋 'WBC24 not only reduces the rise rate, it can also be designed to limit the pull-up potential of node N22 during the burn-in mode. MBC22 and ffBC24 are described below with reference to Figure 3 only. Fig. 3 is a schematic diagram depicting the charge pump 20 (Fig. 2). In this embodiment, MPS21 uses n-channel transistors 20, MN21, MN24, and P-channel transistors P20, P21, and a capacitor. . To be done. The p-channel transistor pH is also used as MBC22. The connection of MPS21 is as follows. The source, gate, and end of the N-channel transistor MN20 are connected to the VDD supply bus, connection 16], and node N20, respectively. The connection line 61 is a unit line for connection line 16 (Fig. 1) for transmitting the pump control signal. In this embodiment, ^ is connected to transmit a pre-boost fs to break PREBST. When the node N20 is precharged, the PREBST signal is selectively triggered or idled, which will be described in detail below. When the signal PREBST is triggered, it will have a potential higher than the external supply voltage VDD. The N-channel transistor MN21 is connected as a diode, with the positive pole connected to the vdd supply bus and the negative pole fast connected to the node N20. Capacitor C20 is connected between nodes N2 0 and N21. The source, gate, and drain of the P-channel transistor P20 are connected to the VDD supply bus, connection 162, and node N21. The connection 162 is a unit line of connection 16 (Fig. 1), and is used for transmitting the pump control signal. In this embodiment, the 'connection 162 transmits a pump signal PMP. Lifting node N20
第12頁 4243 1 9 五、發明說明(9) 時,PMP信號選擇性地被觸發至一邏輯高電位,此處將會 在下文詳細說明。 P通道電晶體P2 1之源極、閘極及汲極分別連接至VDD 供應匯流排、連線27及節點N21。連線27連接接收燒入幫 浦信號BPMP且信號BPMP在節點N20上升時選擇性地觸發或 閒置’而在燒入模式時是閒置的,將在下文中詳細說明。 N通道電晶體MN24之源極、閘極及汲極分別連接至接地匯 流排、連線163及節點N21。連線163是連線16之一單元線, 用以傳送幫浦控制信號。在此實施例中,連線1 傳送一 前置電容(pre-capac i tor )信號PRECAP。PRECAP信號在節 點N20上升時選擇性地觸發或閒置,將在下文中詳細說 明。 WPS23 包括一N 通道電晶體MN25、MN26、MN28、MN29 及Page 12 4243 1 9 V. In the description of the invention (9), the PMP signal is selectively triggered to a logic high level, which will be described in detail below. The source, gate, and drain of the P-channel transistor P2 1 are connected to the VDD supply bus, connection 27, and node N21. The connection 27 is connected to receive the burn-in pump signal BPMP and the signal BPMP is selectively triggered or idled when the node N20 rises, and is idle in the burn-in mode, which will be described in detail below. The source, gate, and drain of the N-channel transistor MN24 are connected to the ground bus, the connection 163, and the node N21. The connection 163 is a unit line of the connection 16 for transmitting a pump control signal. In this embodiment, the connection 1 transmits a pre-capaci tor signal PRECAP. The PRECAP signal is selectively triggered or idled when the node N20 rises, as will be explained in detail below. WPS23 includes an N-channel transistor MN25, MN26, MN28, MN29 and
P通道電晶體P23、P25及一電容C21。WPS23的組接如下。N 通道電晶體MN25之極、閘極及汲極分別連接至VDD供應匯 流排、連線16!及節點N22。N通道電晶體MN26被連接成二 極體’其正極連接至VDD供應匯流排而負極連接至節點 N22。電C21連接在節點N22及N24之間。P通道電晶體P23 之源極、閘極及汲極分別連接至VDD供應匯流排、連線i 6 及節點N23。 2 P通道電晶體p 2 5之源極 '閘極及汲極分別連接至節没 N23、連線28丨及節點N24。連線28,是連線28之一單元線, 用以傳送井區燒入控制信號◊在此實施例中,連線28ι連 接接收一燒入控制信號TBURN且信號TBURN在正常模式時是P-channel transistors P23, P25 and a capacitor C21. The connection of WPS23 is as follows. The N-channel transistor MN25 has its pole, gate, and drain connected to the VDD supply bus, connection 16 !, and node N22, respectively. The N-channel transistor MN26 is connected as a diode ', whose positive terminal is connected to the VDD supply bus and the negative terminal is connected to the node N22. Electricity C21 is connected between nodes N22 and N24. The source, gate and drain of the P-channel transistor P23 are connected to the VDD supply bus, connection i 6 and node N23, respectively. The source and gate of the 2 P-channel transistor p 2 5 are connected to node N23, connection 28, and node N24, respectively. Connection 28 is a unit line of connection 28, which is used to transmit the burn-in control signal in the well area. In this embodiment, connection 28m is connected to receive a burn-in control signal TBURN and the signal TBURN is in normal mode.
4243ί^ 五、發明說明(ίο) 閒置的’而在燒入模式時被觸發,將在下文詳細說明。Ν 通道電晶體ΜΝ28之源極、閘極及没極分別連接至接地匯流 排、連線16a及節點Ν24。Ν通道電晶體ΜΝ29之源極、閘極 及汲極分別連接至點Ν24、連線282及點Ν23。連線282是連 線28之一單元線且連接傳送一正常模式幫浦信號抑㈣。 ΡΜΡΝ信號在燒入模式時被觸發而在正常模式時是閒置的, 將在下文細詳說明。在另一實施例中’ TBURN及ΡΜΡΝ信號 是同一信號。另外,ΡΜΡΝ信號也可以是ΡΜΡ信號之反向信 號。 此外’充電泵20包括一Ρ通道電晶體Ρ26及Ν通道電晶 體ΜΝ23、ΜΝ27及ΜΝ30 通道電晶體Ρ26被連接成二極體, 其正極連接至Ρ通道電晶體Ρ14之井區,而負極連接至輸出 端19。因此’二極體式連接之ρ通道電晶體ρ26將^川之電 位限制在一約高於一個Vh電位之臨界電壓(即約、+ )。ν 通道電晶體MN23、MN27及MN30也都被連接成二極體。尤 其’二極體式連接之N通道電晶趙MN23之正極連接至VDD供 應匯流排而其負極連接至輸出端19。因此,二極體式連接 之N通道電晶體MN23使輸出端19之電位Vh上升至一較VDD外 接供應電壓低一個臨界電壓值之電位(即VDI)_Vtn)。二極體 式連接之N通道電晶體MN27之正極連接至VDD供應匯流排而 其負極連接至P通道電晶體P14之丼區。因此,ν通道電晶 體MN27是用以將veell上升至一較外接供應電壓vdd低一個臨 界電壓值之電位(即VDD-Vtn)。二極體式連接之電晶體題23 及MN2 7在電源啟動時使其源極電壓上升有助於確保正確之4243ί ^ V. Description of the Invention (ίο) Idle ’which is triggered during the burn-in mode, will be described in detail below. The source, gate, and non-poles of the N-channel transistor MN28 are connected to the ground bus, connection 16a, and node N24, respectively. The source, gate, and drain of the N-channel transistor MN29 are connected to point N24, line 282, and point N23, respectively. The connection 282 is a unit line of the connection 28 and is connected to transmit a normal mode pump signal. The PMPN signal is triggered in the burn-in mode and idle in the normal mode, which will be described in detail below. In another embodiment, the 'TBURN and PMPN signals are the same signal. In addition, the PMPN signal may also be a reverse signal of the PMP signal. In addition, the charge pump 20 includes a P-channel transistor P26 and N-channel transistor MN23, MN27, and MN30. The channel transistor P26 is connected as a diode, the positive electrode of which is connected to the well region of the P-channel transistor P14, and the negative electrode is connected to Output terminal 19. Therefore, the 'diode-connected' ρ channel transistor ρ26 limits the potential of ^ chuan to a threshold voltage (ie, about, +) above a Vh potential. The ν channel transistors MN23, MN27, and MN30 are also connected as diodes. In particular, the anode of the 'diode-connected N-channel transistor Zhao MN23 is connected to the VDD supply bus and the anode is connected to the output terminal 19. Therefore, the diode-connected N-channel transistor MN23 causes the potential Vh of the output terminal 19 to rise to a potential (ie, VDI) _Vtn) which is lower than the VDD external supply voltage by a critical voltage value. The anode of the diode-connected N-channel transistor MN27 is connected to the VDD supply bus and its anode is connected to the region of the P-channel transistor P14. Therefore, the ν-channel transistor MN27 is used to raise the veell to a potential lower than the external supply voltage vdd by a critical voltage value (ie, VDD-Vtn). Diode-connected transistor questions 23 and MN2 7 increase the source voltage at power-on to help ensure correct
第14頁 424319 五、發明說明(11) 啟動。二極體式連接之N通道電晶體)^3〇之正極連接至節 點N22而其負極連接至輸出端19。因此,N通道電晶體MN3〇 將節點N22之電位限制在一較vh電位高一個臨界電壓值之 電位。 圖4是一時序圖,描繪了充電泵2〇之操作。pmpbsT信 號之電位由波形40來表示。如波形40所示’ PMPBST信號事 實上是一其高電位等於拉升電位之時衝脈波信號(cl〇ck signal)。PREBST信號之電位由波形41來表示,其亦為一 高電位為拉升電位之週期信號^ PREBST信號之高電位狀態 被微微延遲發生而較PMPBST信號之高電位狀態短,這使得 PMPBST信號的高電位狀態完全覆蓋了 PREBST信號之高電位 狀態。PRECAP信號之電位由波形42來表示,除了 PRECAP信 號在之高電位等於正常電位(即大致與外接供應電壓相同) 外’大致與PREBST信號相同。 PMP信號由波形43來表示’為一非具拉升電位之週期 信號。波形43之高電位狀態之時間是較波形41及42之高電 位狀態來得長。此外,波形43之高電位狀態約與PMPBST信 號之高電位狀態同時開始,但較PMPBST信號為短。因此, 波形40之高電位狀態完全覆蓋了波形43之高電位狀態,同 樣也完全覆蓋了波形41及42之高電位狀態。Page 14 424319 V. Description of the invention (11) Start. The diode-connected N-channel transistor) has a positive pole connected to node N22 and a negative pole connected to output terminal 19. Therefore, the N-channel transistor MN30 limits the potential of the node N22 to a potential higher than the vh potential by a threshold voltage value. FIG. 4 is a timing diagram illustrating the operation of the charge pump 20. The potential of the pmpbsT signal is represented by a waveform 40. As shown in waveform 40, the PMPBST signal is actually a clock signal when its high potential is equal to the pull-up potential. The potential of the PREBST signal is represented by waveform 41, which is also a periodic signal with a high potential being a pull-up potential ^ The high potential state of the PREBST signal is slightly delayed and is shorter than the high potential state of the PMPBST signal. The potential state completely covers the high potential state of the PREBST signal. The potential of the PRECAP signal is represented by waveform 42, except that the high potential of the PRECAP signal is equal to the normal potential (that is, approximately the same as the external supply voltage) ', which is approximately the same as the PREBST signal. The PMP signal is represented by waveform 43 'as a periodic signal with no pull-up potential. The time of the high potential state of the waveform 43 is longer than the time of the high potential state of the waveforms 41 and 42. In addition, the high-potential state of waveform 43 starts at about the same time as the high-potential state of the PMPBST signal, but is shorter than the PMPBST signal. Therefore, the high-potential state of waveform 40 completely covers the high-potential state of waveform 43, as well as the high-potential state of waveforms 41 and 42.
第15頁 在節點N20至N22及N24之電位分別是由波形45、44、 47及46來表示。波形44至47在充電泵20 (圖3)操作期間的 變化如下所述。BPMP由波形48來表示且在正常模式中大致 等於PMP信號。但是’在燒入模式時BPMP信號是閒置的, 五、發明說明(12) 因此波形48在圖中顯示出於燒入模式時有一低電位D pmpn 及TBURN信號由波形49及50來表示。在正常模式時,波形 49及50保持在高電位。相反地,在燒入模式時,波形49及 5 0保持在低電位。另外,PMpN信號可以是pmp信號之反向 信號。如前述’波形4〇至43及48至50是由一控制電路(圖 未顯示)提供的。熟知積體電路技術之人在閲讀本發明之 說明後可以不需額外之研究而做出這種控制電路。 請參閱圖3及圖4,充電泵20之此實施例之操作如下。 在正常啟動模式時,N通道電晶體MN21、MN23 ' MN26及 MN27對節點N20、輸出端19、節點N22及P通道電晶體P14之 井區前置充電至一較外接供應電壓VDD低一個臨界電壓值 之電位。此外’ PMPN及TBURN信號是在低電位,因此關閉 了 N通道電晶體MN29並啟動p通道電晶體p25。至於節sN2{) 及N22 ’最初之前置充電顯示在波形45及47之上升邊緣45! 及4 7,。然後隨著pjjpBSTj·!號在拉升電位,pREBST信號被 推升至一拉升電位,如上升邊緣41〗所示。結果,p通道電 晶想P14及P15被關閉且N通道電晶體MN20及MN25分別將節 點N20及N22之電位拉升至外接供應電壓之電位。節點mo 及N22電位之「完整拉升」(fuU_rail puu_up)顯示在上 升邊緣線段452及472。 PRECAPk號在上升邊緣41被觸發,如波形42之上升 邊緣42】所示。為了回應PRECAp信號之高電位,n通道電晶 體MN24及MN28是開啟的’因此分別拉降了節點Ν2ι及㈣彳之 電位。然後PREBST及PRECAP信號是閒置的,如下降邊緣 ^资_ 五、發明說明(13) 412及4 22所示。PREBST及PRECAP信號之低電位關閉了n通道 電晶體MN20、MN24、MN25 及MN28 〇 之後,控制電路(圖未顯示)將PMP及BPMP閒置,如下 降邊緣43t 所示。如前述,PMP及BPMP信號在正常模式 時是相同的。PMP及BPMP信號之低電位開啟了 p通道電晶體 P2 0、P23及P21 ’因此拉升了節點N21及N23之電位,如上 升邊緣44]及46!所示。此外,由於pjjPN及TBURN信號是在低 電位’ N通道電晶體MN29是關閉的且p通道電晶體p25是開 啟的。結果’卽點N 2 0及N 2 2之電位分別經由電容c 2 〇及c 2 1 被拉升’如上升邊緣線段453及4 73所示。P通道電晶體P2〇 及P21提供了二個平行上升路徑來直接拉升節點N2i之電 位。由於P通道電晶體是做為拉升裝置使用,節點N2〇之電 位可以被拉升至一電容亦被充電至此之電位再加上。 在PMP信號閒置時,節點N22之電位以一稍有不同的方法拉 升°P通道電晶體P23及P25提供單一個上升路徑來拉升節 點N24之電位。再者,由於p通道電晶體是故為上升裝置使 用’節點N22之電位可以拉升至前述電位再加上VDI)。 然後’ PMPBST信號是間置的’如下降邊緣4〇ι所示。 PJiPBST信號之低電位開啟了 p通道電晶體pi4及?15以讓電 何成即點N20及N22分別重新分配至輸出端〗9及p通道電晶 體P14之井區。接著PMPBST、PMP及BPMP信號轉換至高電 位’如上升邊緣402、432及482所示。PMPBST、PMP及BPMP 1吕號關閉了P通道電晶體P14、P15、P20、P23及P21。之後 隨著PREBST及PRECAP信號接下來的上升邊緣此循環—直重 第17頁 五、發明說明(⑷ * - 複著。 相對的’在燒入模式時,控制電路(圖未顯示)提供了 f持在高電位之BPMP信號。結果,p通道 曰體P21及P25是關閉的,而N通道電晶體_29是開啟的。 2的信號也以在正常模式★同樣的方式提供,因此 泵20(圖4)在燒人模式時的操作方式舆在正f模式時_ 樣’除了以下的說明。 由於P通道電晶體P21在燒入模式時是關閉的,只 通道電晶體P20是用來拉升節點N21之電位。因此 C20在與正常模式之操作比較下是以—較低的速率來拉 在正f模式之操作中’p通道電晶體P20及 P21之操作拉升了電容C2〇,而在燒入模式時只 電晶體P20是用來拉升電容C2〇的。 、 =於N通道電晶體觀9是開啟的且?通道電晶體m是 ’電,!經由P通道電晶體Ρ23·通道電晶體_ 來拉升。但疋,在與Ρ通道電晶體Ρ23及ρ25於正常 = 拉升之比較下’Ν通道電晶體簡將節點Ν24 之拉升限制在一較外接供應電壓VDD低一個臨界電壓值之 5 ΓΛ 在節點N 2 4上被減低的拉升不只減低了節點 N22忐夠上升的電位,也減低了電容C2l的上升速率。如 Ϊ彼Ϊί入模式時’電容⑽及⑶上升速率的降低有效地 ^低連接至Ρ通道電晶體Ρ14井區之襄置中接合面崩潰之機 以上所述之充電栗内部電壓限定控制機制之實施例僅 第18頁 ----- 五 '發明說明(15) ' --- 為本發明主要原則之說明,非以限制本發明 ^ 來說,熟知積體電路技術之人在閱讀本發明$ $,二舉例 做出不同的MBC22、〇C24及鉗制電路25、26。^ ^後可以 M^C22、WBC24及鉗制電路%、26也可以被設計成可提供不 二,I界點及上升速率。於是,雖然本發明已以—較佳實 ^列揭露如上,但在不背離本發明之精神與範圍之情況下 备可做些許的改變與潤飾。The potentials at nodes N20 to N22 and N24 are represented by waveforms 45, 44, 47, and 46, respectively. The waveforms 44 to 47 during the operation of the charge pump 20 (Fig. 3) are as follows. BPMP is represented by waveform 48 and is approximately equal to the PMP signal in the normal mode. However, the BPMP signal is idle in the burn-in mode. V. Explanation of the invention (12) Therefore, the waveform 48 in the figure shows that there is a low potential D pmpn and TBURN signal in the burn-in mode by the waveforms 49 and 50. In normal mode, waveforms 49 and 50 remain high. On the contrary, in the burn-in mode, the waveforms 49 and 50 remain at a low level. In addition, the PMpN signal may be a reverse signal of the pmp signal. As mentioned earlier, the waveforms 40 to 43 and 48 to 50 are provided by a control circuit (not shown). Those skilled in the art of integrated circuit technology can make such a control circuit without additional research after reading the description of the present invention. Please refer to FIG. 3 and FIG. 4. The operation of this embodiment of the charge pump 20 is as follows. In the normal startup mode, the N-channel transistors MN21, MN23, MN26 and MN27 pre-charge the well area of node N20, output 19, node N22, and P-channel transistor P14 to a threshold voltage lower than the external supply voltage VDD Value of potential. In addition, the PMPN and TBURN signals are at a low potential, so the N-channel transistor MN29 is turned off and the p-channel transistor p25 is turned on. As for the sections sN2 {) and N22 ′, the initial pre-charging is displayed on the rising edges 45! And 47 of the waveforms 45 and 47. Then as pjjpBSTj ·! Is at the pull-up potential, the pREBST signal is pushed up to a pull-up potential, as shown by rising edge 41. As a result, the p-channel transistors P14 and P15 are turned off and the N-channel transistors MN20 and MN25 pull the potentials of the nodes N20 and N22 to the potentials of the external supply voltage, respectively. The “full pull” (fuU_rail puu_up) of the potentials of nodes mo and N22 is shown on the rising edge segments 452 and 472. The PRECAPk number is triggered at the rising edge 41, as shown by the rising edge 42 of the waveform 42]. In response to the high potential of the PRECAp signal, the n-channel transistors MN24 and MN28 are turned on ', thus pulling down the potentials of the nodes N2m and ㈣ 彳, respectively. Then the PREBST and PRECAP signals are idle, as shown in the falling edge. V. Invention Description (13) 412 and 4 22. After the low potentials of the PREBST and PRECAP signals turn off the n-channel transistors MN20, MN24, MN25, and MN28, the control circuit (not shown in the figure) idles the PMP and BPMP, as shown in the falling edge 43t below. As mentioned before, the PMP and BPMP signals are the same in normal mode. The low potential of the PMP and BPMP signals turns on the p-channel transistors P2 0, P23, and P21 ′, thus pulling up the potentials of nodes N21 and N23, as shown by rising edges 44] and 46 !. In addition, since the pjjPN and TBURN signals are at a low potential ', the N-channel transistor MN29 is turned off and the p-channel transistor p25 is turned on. As a result, the potentials of the “卽 points N 2 0 and N 2 2 are pulled up via the capacitors c 2 0 and c 2 1, respectively” as shown in the rising edge segments 453 and 4 73. P-channel transistors P20 and P21 provide two parallel rising paths to directly pull up the potential of node N2i. Since the P-channel transistor is used as a pull-up device, the potential of node N20 can be pulled up to a capacitor and charged to this potential plus. When the PMP signal is idle, the potential of node N22 is pulled up by a slightly different method. The P-channel transistors P23 and P25 provide a single rising path to pull up the potential of node N24. Furthermore, since the p-channel transistor is used as a rising device, the potential of the node N22 can be pulled up to the aforementioned potential plus VDI). Then the 'PMPBST signal is interlaced' as shown by the falling edge 40m. The low potential of the PJiPBST signal turns on the p-channel transistor pi4 and? 15 so that electricity can be immediately redistributed to points N20 and N22 to the output terminal 9 and the p-channel electric crystal P14 well area. Then the PMPBST, PMP and BPMP signals are switched to high potentials' as shown by rising edges 402, 432 and 482. PMPBST, PMP and BPMP 1 Lu closed the P-channel transistors P14, P15, P20, P23 and P21. This cycle follows the rising edge of the PREBST and PRECAP signals next-straight on page 17 V. Description of the invention (⑷ *-duplicate. Relatively, in the burn-in mode, the control circuit (not shown) provides f The BPMP signal held at a high potential. As a result, the p-channel body P21 and P25 are turned off, and the N-channel transistor _29 is turned on. The signal of 2 is also provided in the same manner as in the normal mode, so the pump 20 ( Figure 4) The operation mode in the burn mode is the same as in the positive f mode except for the following description. Because the P-channel transistor P21 is turned off in the burn-in mode, only the channel transistor P20 is used to pull up The potential of node N21. Therefore, compared with the normal mode operation, C20 is pulled at a lower rate in the positive f mode operation. The operation of the p-channel transistor P20 and P21 raises the capacitance C2. In the burn-in mode, only the transistor P20 is used to pull up the capacitor C20., = Is turned on at the N-channel transistor view 9 and? The channel transistor m is' electrical !! Via the P-channel transistor P23 Crystal_ to pull up. But 疋, in the P channel transistor P23 and 25 Under normal = pull-up comparison, the N-channel transistor simply limits the pull-up of node N24 to a threshold voltage value 5 which is lower than the external supply voltage VDD. ΓΛ The reduced pull-up on node N 2 4 is not only reduced. It can increase the potential of node N22, and also reduce the rise rate of capacitor C2l. For example, the decrease in the “capacitance” and ⑶ rise rate in the “entry mode” effectively reduces the connection to the P14 well in the P-channel transistor. The machine for the breakdown of the joint surface The above-mentioned embodiment of the internal voltage limiting control mechanism of the charging pump is only on page 18 --- 5 'Description of the Invention (15)' --- This is an explanation of the main principles of the present invention, not the Restricting the present invention ^ For those who are familiar with integrated circuit technology after reading the present invention, two examples are made of different MBC22, OC24 and clamp circuits 25, 26. ^ ^ can be M ^ C22, WBC24 and clamp circuits %, 26 can also be designed to provide unique, I boundary points and rising rates. Therefore, although the present invention has been disclosed as above with the preferred embodiment, it is prepared without departing from the spirit and scope of the present invention. Can be changed and retouched slightly.
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